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WO2018132458A1 - Jfet vertical à tranchées avec terminaison d'échelle - Google Patents

Jfet vertical à tranchées avec terminaison d'échelle Download PDF

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Publication number
WO2018132458A1
WO2018132458A1 PCT/US2018/013141 US2018013141W WO2018132458A1 WO 2018132458 A1 WO2018132458 A1 WO 2018132458A1 US 2018013141 W US2018013141 W US 2018013141W WO 2018132458 A1 WO2018132458 A1 WO 2018132458A1
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WIPO (PCT)
Prior art keywords
region
termination
trenches
regions
termination region
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Application number
PCT/US2018/013141
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English (en)
Inventor
Zhongda Li
Anup Bhalla
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United Silicon Carbide, Inc.
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Publication date
Priority claimed from US15/405,827 external-priority patent/US10050154B2/en
Application filed by United Silicon Carbide, Inc. filed Critical United Silicon Carbide, Inc.
Publication of WO2018132458A1 publication Critical patent/WO2018132458A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/83—FETs having PN junction gate electrodes
    • H10D30/831—Vertical FETs having PN junction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/051—Manufacture or treatment of FETs having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/051—Manufacture or treatment of FETs having PN junction gates
    • H10D30/0512—Manufacture or treatment of FETs having PN junction gates of FETs having PN homojunction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/328—Channel regions of field-effect devices of FETs having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/8303—Diamond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Definitions

  • JFETs Vertical junction field-effect transistors made from materials such as silicon carbide (SiC) are useful in power electronic circuits, such as power factor correction (PFC) circuits, DC-DC converters, DC-AC inverters, and motor drives.
  • PFC power factor correction
  • the performance of vertical SiC JFETs may be improved through the use of edge terminations.
  • a vertical FET with a ladder termination is made from semiconductor materials such as silicon carbide (SiC) by a process using a limited number of masks.
  • a first mask is used to form mesas and trenches in active cell and termination regions simultaneously.
  • a mask-less self-aligned process is used to form silicide source and gate contacts.
  • a second mask is used to open windows to the contacts.
  • a third mask is used to pattern overlay metallization.
  • An optional fourth mask is used to pattern passivation.
  • the channel may be doped via one or more angled implantations, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.
  • Figure 1 provides, for reference, a cross-sectional view of a prior art vertical JFET with planar floating guard-ring termination.
  • Figure 2 illustrates a cross-sectional view of a first illustrative embodiment of a vertical JFET with trench guard-ring terminations made using a set of four masks.
  • Figure 3 is a top view of an example layout for the JFET of the first embodiment.
  • Figure 4 is a cross-sectional view of the termination region of the JFET of the first embodiment.
  • FIGs. 5-11 are cross-sectional views of the JFET of the first embodiment as a work in process through various stages of manufacture.
  • Figure 5 is a cross-sectional view of the starting material for fabricating the JFET.
  • Figure 6 is a cross-sectional view of the JFET of the first embodiment in process after trench etching using a hard masking layer that is defined by a first mask.
  • Figure 7 is a cross-sectional view of the JFET of the first embodiment in process after vertical and tilted implantations of the first doping type with the hard masking layer in place.
  • Figure 8 is cross-sectional view of the JFET of the first embodiment in process after oxide spacer and silicide formation in the active cell region and the termination region.
  • Figure 9 is a cross-sectional view of the JFET of the first embodiment in process after trench filling and window opening for source and gate contacts using a second mask.
  • Figure 10 is a cross-sectional view of the JFET of the first embodiment in process after depositing and patterning the top metal using a third mask.
  • Figure 1 1 is cross-sectional view of the completed JFET after forming the passivation layer using a fourth mask.
  • Figure 12 is a cross-sectional view of a second illustrative embodiment of a JFET.
  • Figure 13 is a cross-sectional view of a third illustrative embodiment of a JFET.
  • Figure 14 is a cross-sectional view of a fourth illustrative embodiment of a JFET.
  • Figure 15 is a cross-sectional view of a fifth illustrative embodiment of a JFET.
  • Figure 16 is a cross-sectional view of a sixth illustrative embodiment of a JFET.
  • Figure 17 is a cross-sectional view of a seventh illustrative embodiment of a JFET.
  • Figure 18 is a cross-sectional view of an eighth illustrative embodiment of a JFET.
  • a vertical JFET may be made from semiconductor materials such as silicon carbide (SiC) by a process using a limited number of masks in a simplified process, thereby reducing costs.
  • semiconductor materials suitable for the creation of such JFETs include silicon (Si), gallium nitride (GaN), aluminum nitride (A1N), gallium oxide (Ga203), and diamond, for example.
  • a first mask is used to form mesas and trenches in active cell and termination regions simultaneously.
  • a mask-less self-aligned process is used to form silicide source and gate contacts.
  • a second mask is used to open windows to the contacts.
  • a third mask is used to pattern overlay metallization.
  • An optional fourth mask is used to pattern passivation.
  • the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.
  • Additional masks may be employed to implement a number of variations. For example, channel implant and silicide formation in the termination region may be blocked by additional masks, or additional masks may be employed to remove certain features from the termination region after they are formed across the wafer.
  • Figure 1 is a vertical cross-sectional view of a prior art SiC vertical channel JFET with planar guard ring termination.
  • a drain electrode 119 is at the bottom of the device.
  • a source electrode 108 is at the top.
  • a gate electrode 109 is connected by a gate silicide 105 to a gate region 106.
  • the gate region 106 is doped with a first doping type.
  • the gate silicide 105 is present at the bottoms of the trenches as well as beneath the gate electrode 109.
  • the gate silicide 105 is electrically contiguous, although the connections from the trench bottoms to the area beneath the gate electrode are not shown in Figure 1.
  • the source electrode 108 is connected by a source silicide 103 to a source region 104.
  • the source region 104 is heavily doped with a second doping type that is the opposite type of the first doping type.
  • the drain electrode 119 contacts a drain region 118 that is heavily doped with the second doping type.
  • the gate region 106 extends to the bottoms and side walls of the trenches, and is formed by implantations of the first doping type at zero degrees and at tilted angles.
  • the channel region 158 is doped with the second doping type and connects the source region 104 to the drift region 130, where current is then conducted to the drain region 118.
  • guard ringsl60 In the termination region 102 are guard ringsl60 that are heavily doped with the first doping type. There are gaps 159 between each of the guard rings 160. The gaps 159 are doped with the second doping type.
  • the potentials of the guard rings 160 are floating.
  • the termination region 102 and portions of the active cell region 101 are covered by an interlay er dielectric 140 and/or a passivation layer 110.
  • the interlayer dielectric 140 also fills the trenches in the active region 101.
  • FIG. 2 is a vertical cross-sectional view of an illustrative first embodiment of a vertical JFET with trench guard-ring terminations made using a set of four masks.
  • the drain electrode 219 contacts the drain region 218.
  • the drain region 218 is heavily doped with the second doping type.
  • a silicide may be used to connect a metal electrode to a heavily doped semiconductor region.
  • Above the drain region 218 is the drift region 230.
  • the drift is lightly doped with second doping type.
  • the trenches in both the active region 201 and termination region 202 may be created simultaneously, e.g., by etching.
  • the trenches are separated by mesas such as mesas 216A and 216B.
  • the width of the mesas in the termination region 202 may either be equal to, smaller than, or larger than the width of the mesas in the active cell region 201.
  • a vertical channel JFET in the active cell 201 includes a gate region 206 that may be formed, for example, by implantation of the first doping type.
  • the gate region 206 may implanted vertically to dope the trench bottom. Additionally, as shown in FIG 2, the gate region may extend to the sidewalls 226 of the trenches, e.g., by implantation at a tilted angle, to dope the sidewalls of the mesas.
  • the trenches are filled with an interlayer dielectric 240.
  • the JFET of Figure 2 is shown with a passivation layer 210.
  • the same implantations used to dope the bottom 206 and sidewalls 226 of the trenches in the active region 201 may be used to create faux-gate doped elements 236 at the bottoms of the trenches in the termination region 202.
  • the faux- gate regions 236 include a portion extending and sidewalls 246.
  • the faux-gate regions 236 are floating, being not connected to the gate regions 206 of the active region 201.
  • the faux-gate region in each trench in the termination area 202 is not connected to the faux- gate region in any other trench.
  • the faux-gate regions on the left and right of each mesa in the termination area 202 can float to different potentials.
  • the mesas in the termination region 202 have a heavily doped region faux-source 212 of the second doping type at the top. These regions 212 may be formed at the same time as the source region 204 atop the mesas in the active cell region 201. However the faux- source regions 212 are floating, being connected neither to each other nor to the source regions 204 of the active area 201.
  • a source silicide contact 203 sits on top of the mesa, above the source region 204.
  • the gate silicide contact 205 sits at the bottom of the trench above the gate region 206 in the active area 201 and beneath the gate electrode 209.
  • the source silicide contacts 203 in the active cell region are connected to the source electrode 208.
  • the gate silicide contacts 205 are connected to the gate electrode 209, e.g., through connections which are not in the plane of the vertical cross section of Figure 2.
  • the silicide contacts in the termination region 21 1 and 213 are floating.
  • the contacts 211 and 213 are ohmically isolated, having no conductive material path connecting them to each other each within each mesa or from mesa to mesa.
  • These silicides 211 and 213 are not connected to each other or to any electrode, such that the electrical potentials of such silicides in the trenches and mesas of the termination region 202 are independent.
  • the heavily doped regions of opposite doping types in the trenches and mesas of the termination region 202 are floating and have independent electrical potentials, such that, for example, the electrical potential of the silicide 213 in trench 217 is independent from that of the trench sidewall 246 of mesa 216B.
  • the doped elements 212 and 236 are neither connected to each other within the mesa, nor are like elements joined from mesa to mesa. Each doped element in each termination region mesa floats to its own potential. The doped elements are nonetheless adjacent, and thus form P-N junctions. Since the faux-gate regions on the left and right side of each mesa in the termination area 202 are floating, the mesas in the termination region form a back-to-back structure, e.g., a PNP structure.
  • drain contact 219 When a small potential is applied to the drain contact 219, the same potential is taken by drain 218, drift 203, and faux-source regions 212. A reverse bias appears at the junction between the faux-gate 236 and faux-source 212 regions in the leftmost mesa 216A in the termination area 202. As the voltage increases, the mesa 216A depletes until punch- through occurs to the faux-gate region of the trench to the right of mesa 216A. Punch- through may be described as the point where the depletion region reaches the outer faux-gate sidewall junction. The device is designed such that this punch-through occurs before the avalanche breakdown of the faux-source to faux-gate junction.
  • the second mesa 216B begins to deplete just as the first mesa 216A did.
  • the voltage is again supported between the faux-gate 236 and faux-source 212 of the second mesa 216B until, and a higher potential, the second mesa 216B depletes and punch-through to the faux-gate of the mesa to the right of mesa 216B occurs.
  • a potential ladder is created, with each mesa handling a potential difference set by the punch though between adjacent faux-gates.
  • the field can be spread to form a high voltage termination region 202, where a potential appears also at the faux-source to faux-gate junction within each mesa.
  • the key to the termination structure is to have an avalanche breakdown voltage between faux-gate and faux-source that is higher than the punch-through voltage between the left and right faux- gates in each mesa. With that, a ladder termination can be built, because the faux-gate to faux-source is shielded from breakdown by the punch-through action, and does not limit the overall blocking voltage of the device.
  • each termination mesa may be designed to punch though at 30V.
  • a total voltage of 900V may be supported, as long as the active cells are designed to reach that voltage as well before breakdown. Due to process variations, the punch-through voltage and faux-gate-source breakdown voltages may vary, but the design margin should always ensure that the punch-through voltage in each mesa is less than the faux-gate-source avalanche breakdown voltage.
  • This termination structure differs from standard guard ring terminations in that the adj acent faux-gate regions are separated by actual faux-source regions, which are not present in, for example, the termination 102 of Figure 1.
  • the voltage at each ring appears at the faux-gate-faux-source junction. This is different from the guard rings in region 102 of Figure 1 , where the voltage appears between the guard ring 160 and the lightly doped drift region 159.
  • Figure 3 is a top view of an example layout of a JFET such as the JFET of the first embodiment.
  • the mesas 371 are parallel to each other.
  • the mesas 377 are concentric.
  • the semiconductor such as SiC or GaN, is etched, leaving trenches in the active area such as trench 373, and trenches in the termination region such as trench 378.
  • silicide contacts are formed on the top of the mesas 371 and at the bottom of the active trenches 373, using a self- aligned process.
  • the self-aligned process uses an oxide spacer to ensure that the silicide at the top of the mesas 371 does not short to the silicide at the bottom of the trenches 373.
  • a source contact window 372 is opened in the inter-layer dielectric to make contact between the source silicide 371 and the source overlay metal 374.
  • the gate contact window 375 is opened in the inter-layer dielectric to make contact between the gate silicide contacts 373 to the gate overlay metal 376.
  • the mesas 377 and trenches 378 are formed at the same time as those in the active region, and silicide contacts may be formed on top of the mesas 377 and at the bottom of the trenches 378, during the same self-aligned silicide formation process in the active region. However, if any such contacts are formed in the termination region, they are not connected to the gate overlay metal 376 or the source overlay metal.
  • Figure 4 is an annotated cross-sectional view of the termination region 402 of the JFET of the first embodiment. A portion of the active area 401 is also shown. For purposes of the examples herein, it may assumed that this is an npn JFET, such that the first doping type is p-type and the second doping type is n-type. In practice, npn and pnp devices may be made by the processes described herein.
  • the p-n junction 450 between the heavily doped region of the second doping type 412 and the mesa sidewall 446, which is doped with the first type, is reverse biased, while the regions in the middle of the mesa doped with the second doping type 454 and 427 are being depleted.
  • the trench bottoms 436 and sidewalls 446 in termination region 402 are doped with the first doping type, e.g., with the same material used for the gate 406 in the active region. However, in the termination region 402, the trench bottoms 436 and sidewalls 446 are not connected to the gate voltage or to each other, and hence are floating.
  • the reverse voltage on the p-n junction 450 in the mesa stops increasing, and the further voltage will be supported in the next mesa.
  • each mesa supports the punch-through voltage of the mesa.
  • the punch-through voltage of the mesa needs to be less than the breakdown voltage of the p-n junction 450 in the mesa, and this determines the maximum mesa width that can be used.
  • the total voltage that can be supported by the termination can be increased by adding more and more trench-mesa pairs to create a potential ladder. Note that in the termination region 402, the silicides 411 and 413 are floating.
  • a drain contact 419 at the bottom that is connected to a drain region 418.
  • the drain region 418 is in turn connected to the drift region 430.
  • the trenches are filled with interlay er dielectric 440, and the device is topped with a passivation layer 410.
  • a gate silicide 405 connects a gate electrode 409 to a gate region 406.
  • the dashed boundary 456 illustrates the depletion layer edge when the first termination mesa is fully depleted, and the second is partially depleted.
  • the conductive silicide region atop each trench 411 will float to a potential that is different from the potential of the source and gate terminals, e.g., gate contact 409.
  • the structure of Figure 4 forms a stepped potential ladder to sustain the device off-state blocking voltage.
  • the termination features a P-N junction within each mesa that is shielded by the depletion of the mesas 454, such that the maximum voltage at the junction 450 stays below its breakdown voltage. This is in contrast, for example, to prior designs using a field plate contacted to mesas in the termination region.
  • mesas may vary in the range of 0.5 um to 2 um or more wide, and be 0.6 um to 3 um or more deep. Such mesas in the termination may support a standoff voltage of 10 to 40 V, for example.
  • the number of termination rings, e.g., concentric mesas in the termination region depends on the required support voltage. For example, to support 700 V in the blocking state with 20V/ring, at least 35 rings are required.
  • active region mesas and termination region mesas may be created at the same time using the same materials and masks, the active area mesa widths need not be the same as termination area mesa widths. The width of the termination region mesas may be adjusted according to the desired standoff voltage.
  • Figure 4 shows a few potential contours 452 at two mesas. These illustrate how this termination structure creates a potential ladder, where each of the floating silicide regions 4411 and 413 are at staggered potentials due to the voltages across the P-N junctions such as junction 450.
  • FIGs. 5 through 1 1 The basic methods for the various illustrative embodiments of the JFETs of the present invention are illustrated in FIGs. 5 through 1 1 with vertical cross-sectional views of a first illustrative embodiment of a JFET as a work in process.
  • Silicon or SiC JFETs for example, may be made using two dopant types, n-type and p-type.
  • the first dopant type refers to the gate implant type of the JFET
  • the “the second dopant” type refers to the dopant type used for the source and drain.
  • the descriptions of the structures and methods herein apply equally to n-channel and p-channel devices.
  • An n-channel device uses n-type regions for source and drain, and has a p-type gate region.
  • the starting material illustrated in Figure 5 is a wafer containing a heavily doped top layer 504 of the second doping type to be used for source contacts.
  • the top heavily doped region 504 can be formed either by epitaxy or by implantation, for example.
  • the layers 530 can could be formed by epitaxy.
  • the bottom layer of the starting wafer is a heavily doped substrate 518 of the second doping type which will be used for a drain.
  • Figure 6 illustrates a cross-sectional view of the JFET in process as seen after trench etching using a first mask.
  • a hard masking layer 680 is first deposited on top of the heavily doped region of the second type 606.
  • the hard masking layer 680 can be oxide, metal, or both, for example.
  • the hard masking layer 680 is patterned using the first mask, and etched.
  • the trenches 605 in both the active cell region 601 and the termination region 602 are etched simultaneously using the hard masking layer 680.
  • the trenches 617 extend into the drift region 630. Also shown in Figure 6 is the drain region 618.
  • Figure 7 illustrates a cross-sectional view of the JFET in process as seen after implantations of the first doping type.
  • the implantations are performed without removing the hard masking layer 780. No additional masks are needed for this step.
  • a vertical implantation of the first doping type forms the heavily doped regions 706 at the bottom of the trenches 717 in both the active cell region 701 and the termination region 702.
  • the hard masking layer 780 protects source region 704 from being counter-doped by the implantation.
  • a tilted implantation of the first doping type may be used to form the regions 726 on the side walls of the trenches 717. Sidewall regions 726 may optionally be less-heavily doped than the trench bottom regions 706.
  • the hard mask 780 is removed after the implantations are completed, and the wafer is annealed to activate the implanted dopants, for example. Also shown in Figure 7 are the drift region 730 and the drain region 718.
  • Figure 8 illustrates a cross-sectional view of the JFET in process as seen after a self- aligned silicide contact formation.
  • the silicide contacts 803 and 805 are formed
  • the oxide spacers 842 on the side walls of the trenches 817 are formed by depositing and/or growing oxide, followed by blanket etching back. Using an etching process that operates primarily vertically, the spacers 842 remain only on mesa sides.
  • an ohmic metal such as Ni
  • Ni is deposited and annealed using rapid thermal annealing to form the silicides. Because Ni does not react with oxide, the silicide only forms on top of the second- doping-type regions 804 and the first-doping-type regions 806. The unreacted Ni on the oxide spacers 803 is then removed, and thus there is no shorting path between the silicide 803 and the silicide 805.
  • the drift region 830 and the drain region 818 are also shown in Figure 818.
  • Figure 9 illustrates a cross-sectional view of the JFET in progress as seen after contact window opening using a second mask.
  • an interlayer dielectric 940 such as oxide
  • the second mask is used to pattem the contact windows to the source silicide 903 and a portion of the gate silicide 905.
  • the windows are then cleared by etching.
  • the active region 901 the source contact windows 904 are opened in each of the cells.
  • a shared gate contact window to the gate silicide 905 is opened outside the cells.
  • no contact window is opened, and thus all the silicide contacts are under the inter-layer dielectric 940.
  • Figure 10 illustrates a cross-sectional view of the JFET in progress as seen after an overlay metal is defined using a third mask.
  • a conductor such as a metal is deposited, patterned using the third mask, and etched, leaving source electrode 1008 and gate electrode 1009 separated by the interlayer dielectric 1040.
  • the source electrode 1008 makes contact to the source silicide contacts 1003 on top of each mesa, and thereby to the source region 1004.
  • the gate electrode 1009 makes contact to the gate silicide 1005 and thereby to the gate region 1006.
  • the silicide contacts 101 1 and 1013 are not connected to any overlay metal, and thus their potentials float separately from each other and from other voltages in the device. Also shown in Figure 10 are the drift region 1030, the drain region 1018, the termination region mesa top 1012, and the termination region trench side walls and bottom 1036, which are now distinct from the similarly formed structures in the active cell region 1001 by virtue of not being connected to the source or gate electrodes respectively.
  • FIG. 1 1 illustrates a cross-sectional view of the completed JFET as seen after forming a passivation layer using a fourth mask.
  • a passivation material such as benzo-cyclo-butene (BCB)
  • BCB benzo-cyclo-butene
  • the passivation layer 11 10 is patterned using the fourth mask to open the windows through the passivation material to the source electrode metal 1108 and to the gate electrode metal 1 109. No window through the passivation layer 11 10 is opened in the termination region 1102. It is, of course, possible to entirely skip this passivation step, e.g., if the oxide layer under the BCB were sufficient to ensure device reliability.
  • drain contact 1 1 19 is formed to complete the JFET process. Also shown in Figure 1 1 are drain region 1 118, drift region 1130, source silicide 1103, source region 1104, gate silicide 1 105, gate region 1 106, interlayer dielectric 1 140, termination region silicides 11 11 and 1 113, and termination doped regions 1112, and 1136.
  • Figure 12 illustrates a cross-sectional view of a second embodiment of a trench terminated JFET.
  • the second embodiment is similar to the first embodiment shown, e.g., in Figures 5-11.
  • the sidewalls 1207 of the channel region of the mesa 1216A have been doped by an implantation of the second doping type. This is done to lower the channel resistance and achieve better control of the threshold voltage by raising the doping level higher than that of the drift region 1230 from which the mesas are formed.
  • such implantation may be done after the vertical and tilted implantations of the first doping type discussed above in reference to Figure 7.
  • the channel implantation of the second doping type may be done without using any mask (e.g., after the removal of the hard masking layer 780 of Figure 7.)
  • the side wall 1227 of the mesa 1216B in the termination region 1202 is also doped by this implantation.
  • This doped region 1227 in the termination region 1202 does not substantially affect the functionality of the trench guard-ring termination. It is possible to compensate for the added charges by reducing the width of the mesas 1205 in the termination region 1202. This implantation is followed by activation annealing.
  • drain contact 1219 drain region 1218, drift region 1230, source silicide 1203, source region 1204, source electrode 1208, gate silicide 1205, gate region 1206, gate electrode 1209, interlayer dielectric 1240, passivation 1210, termination region silicides 1211 and 1213, and termination doped regions 1212 and 1226.
  • Figure 13 is a cross-sectional view of a third illustrative embodiment of a trench terminated JFET.
  • the third embodiment is similar to the second embodiment shown in Figure 12, but here in Figure 13, in the termination region 1302, the width of the trenches 1317 is narrower than the width of the trenches in the active cell region 1301.
  • the tilted implantation of the first doping type is done simultaneously for the active cell region 1301 and the termination region 1302 using the same tilt angle.
  • the tilt angle is chosen such that the side-wall first-doping-type region 1326 reaches the bottom of the first-doping-type region only in the active cell region 1301.
  • drain contact 1319 drain region 1318, drift region 1330, source silicide 1303, source region 1304, source electrode 1308, gate silicide 1305, gate region 1306, gate electrode 1309, optional channel implant region 1307, interlayer dielectric 1340, passivation 1310, termination region silicides 1311 and 1313, and termination region mesa top doped region 1312, in addition to the ILD 1340, passivation 1340, and optional additional channel doping 1307.
  • Figure 14 is a cross-sectional view of a fourth illustrative embodiment of a trench terminated JFET.
  • the fourth embodiment is similar to the second embodiment shown in Figure 12, but here in Figure 14 the width of the trenches 1417 in the termination region 1402 is wider than the width of the trenches in the active cell region 1401.
  • a fifth mask is used to separate the first-doping-type implantations for the active cell region 1401 and the termination region 1402. The additional mask is applied after the implantations of the first- doping-type described with reference to Figure 7. This mask blocks the active cells 1401 but is open in the termination region 1402.
  • the first-doping-type region on the side wall 1446 is implanted deeper towards the center of the mesa in the termination region 1402 as compared to the analogous structure 1426 in the active region 1401. This makes the mesas 1416 in the termination region 1402 easier to deplete and improves the termination.
  • drain contact 1419 drain region 1418, drift region 1430, source silicide 1403, source region 1404, optional channel implant 1407, source electrode 1408, gate silicide 1405, gate region 1406, gate electrode 1409, interlayer dielectric 1440, passivation 1410, termination region silicides 1411 and 1413, and termination doped regions 1412 and 1436, and optional doped region 1427.
  • Figure 15 is a cross-sectional view of a fifth illustrative embodiment of a trench terminated JFET.
  • the fifth embodiment is similar to the second embodiment shown in Figure 12, but here in Figure 15 a sixth mask is used so that no silicide will be formed in the termination region 1502.
  • This sixth mask brings the total mask count to five for the process: trench, Ni block, contact, metal, and passivation.
  • Silicide, including gate silicide 1505 and source silicide 1503 only forms in the active cell region 1501.
  • the sixth mask can work either by stopping Ni from being deposited in the termination region 1502, or by leaving oxide in the termination region 1502 so that Ni cannot react with the semiconductor. This would occur during the methods discussed in reference to Figure 8.
  • drain contact 1519 drain region 1518, drift region 1530, source region 1504, optional channel implant 1507, source electrode 1508, gate region 1506, gate electrode 1509, interlayer dielectric 1540, passivation 1510, and termination doped regions 1512 and 1536, and optional termination doped region 1527.
  • Figure 16 is a cross-sectional view of a sixth illustrative embodiment of a trench terminated JFET.
  • the sixth embodiment is similar to the second embodiment shown in Figure 12, but here in Figure 16 a seventh mask is used to prevent the optional channel implant of the second type from entering the termination region 1602.
  • the optional channel implant of the second doping type 1607 only forms in the active cell region 1601. This seventh mask brings the total mask count to five for the process: trench, channel implant block, contact, metal, and passivation.
  • drain contact 1619 drain region 1618, drift region 1630, source region 1604, source silicide 1603, source electrode 1608, gate region 1606, gate silicide 1605, gate electrode 1609, interlayer dielectric 1640, passivation 1610, and termination silicides 1611 and 1613, and termination doped regions 1612 and 1636.
  • FIG 17 is a cross-sectional view of a seventh illustrative embodiment of a trench terminated JFET.
  • a seventh mask is used to prevent the optional channel implant of the second doping type from getting into the termination region 1702.
  • the seventh mask is also used to prevent the growth of oxide spacers and formation of gate and source silicide in the termination region.
  • One method to achieve this structure is to deposit an oxide layer after the gate implants of the first doping type, then pattern the oxide layer to open only the active area 1701 before performing the further channel implants and silicide formation steps.
  • the channel implant only forms the second-doping-type region 1707 in the active cells 1701, and the gate silicide 1705 and source silicide 1703 only form in the active cells 1701.
  • This seventh mask brings the total mask count to five for the process: trench, channel implant and silicide block, contact, metal, and passivation.
  • drain contact 1719 drain region 1718, drift region 1730, source region 1704, source silicide 1703, source electrode 1708, gate region 1706, gate silicide 1705, gate electrode 1709, channel implant 1707, interlayer dielectric 1740, passivation 1710, and termination doped regions 1712 and 1736.
  • Figure 18 is a cross-sectional view of an eighth illustrative embodiment of a trench terminated JFET.
  • the eighth embodiment is similar to the fifth embodiment shown in Figure 15.
  • an eighth mask is used to keep the heavily doped wafer top layer, which is used to form the source regions 1804 in the active region 1801, from being formed in the termination region 1802.
  • the starting wafer is shown as having a layer 504 of a second doping typing that will become the source region 1804.
  • Layer 504 may be created by epitaxy or implantation, for example.
  • the JFET depicted in Figure 18 may be created by using such a starting wafer by using the eighth mask to control the etching away of the top heavily doped region of the second doping type in the termination region 1802, leaving the top heavily doped region of the second type only in the active region 1801.
  • This eighth mask brings the total mask count to five for the process: source partem, trench, contact, metal, and passivation.
  • the JFET depicted in Figure 18 may be created by using a starting wafer that does not have the top heavily doped region of the second doping type, and then using the eighth mask to control the implantation of a top heavily doped region of the second doping in the active region termination region 1802, leaving the top heavily doped region of the second type only in the active region.
  • an eighth mask may be used to control the selective removal of source regions in the termination region 1802 after the formation of the mesas.
  • drain contact 1819 drain region 1818, drift region 1830, source electrode 1808, source silicide 1803, gate region 1806, gate silicide 1805, gate electrode 1809, interlay er dielectric 1840, passivation 1810, optional channel doping 1807, and termination doped region 1846 and optional termination doped region 1827.
  • the options described herein are independent and may be combined in any number of ways to produce vertical JFET devices with ladder termination regions.
  • the termination regions may be made: (a) with or without silicides; (b) with or without vertical regions of the second doping type at a different doping concentration level than the center of the mesa; (c) mesas or trenches that are a different width than those in the active cell region; (d) with or without regions of heaving doping of the second type on the tops of the mesas; and (e) with trench vertical sidewall regions of doping of the first type that do or do not extend do to regions of doping of the first type at the bottom of the trench, or any combination therefore.
  • the active cell region may be made with or without vertical channel doping regions, whether or not analogous structures are found in the termination region.

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  • Electrodes Of Semiconductors (AREA)

Abstract

Un JFET vertical avec une terminaison d'échelle peut être fabriqué par un procédé faisant appel à un nombre limité de masques. Un premier masque est utilisé pour former des mesas et des tranchées simultanément dans des régions de cellule active et de terminaison. Un procédé d'auto-alignement sans masque est utilisé pour former des contacts de grille et de source en siliciure. Un deuxième masque est utilisé pour ouvrir des fenêtres vers les contacts. Un troisième masque est utilisé pour former des motifs de métallisation de recouvrement. Éventuellement, un quatrième masque est utilisé pour former des motifs de passivation. Le canal peut éventuellement être dopé par l'intermédiaire d'une implantation oblique, et la largeur des tranchées et des mesas dans la région de cellule active peut être amenée à varier par rapport à celle dans la région de terminaison.
PCT/US2018/013141 2017-01-13 2018-01-10 Jfet vertical à tranchées avec terminaison d'échelle WO2018132458A1 (fr)

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US15/405,827 US10050154B2 (en) 2015-07-14 2017-01-13 Trench vertical JFET with ladder termination
US15/405,827 2017-01-13

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US6855970B2 (en) * 2002-03-25 2005-02-15 Kabushiki Kaisha Toshiba High-breakdown-voltage semiconductor device
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