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WO2018131084A1 - Circuit pll - Google Patents

Circuit pll Download PDF

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Publication number
WO2018131084A1
WO2018131084A1 PCT/JP2017/000541 JP2017000541W WO2018131084A1 WO 2018131084 A1 WO2018131084 A1 WO 2018131084A1 JP 2017000541 W JP2017000541 W JP 2017000541W WO 2018131084 A1 WO2018131084 A1 WO 2018131084A1
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WO
WIPO (PCT)
Prior art keywords
frequency
signal
output
oscillation
outputs
Prior art date
Application number
PCT/JP2017/000541
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English (en)
Japanese (ja)
Inventor
裕貴 柳原
恒次 堤
下沢　充弘
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2017/000541 priority Critical patent/WO2018131084A1/fr
Priority to JP2018561128A priority patent/JP6556383B2/ja
Publication of WO2018131084A1 publication Critical patent/WO2018131084A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03C—MODULATION
    • H03C3/00—Angle modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division

Definitions

  • the present invention relates to a PLL (Phase Locked Loop) circuit.
  • This PLL connects the control terminal of the VCO (Voltage Controlled Oscillator) with a DAC (Digital-to-Analog-Converter) through a switch, turns on the switch at a point where the frequency changes sharply, and connects the DAC to the control terminal of the VCO. By applying this output, the time until the PLL outputs the correct frequency again is shortened.
  • VCO Voltage Controlled Oscillator
  • DAC Digital-to-Analog-Converter
  • the PLL circuit of the present invention compares a frequency divider that divides an oscillation signal whose frequency changes with time, a reference signal and an oscillation signal that is divided by the frequency divider, and outputs a signal corresponding to the difference.
  • the frequency comparator and the phase filter output the high-frequency component of the signal output from the phase filter, a loop filter that outputs the signal from which the high-frequency component is blocked, and the oscillation signal is changed according to the output signal of the loop filter.
  • An output oscillator a digital signal processor for obtaining the frequency of the oscillation signal, a parameter control circuit for obtaining a control parameter based on the frequency of the oscillation signal obtained by the digital signal processor, and an analog signal to the loop filter or the oscillator according to the control parameter And a digital-to-analog converter that corrects the time variation of the oscillation frequency of the oscillator.
  • an appropriate applied parameter can be obtained dynamically in accordance with a change in circuit characteristics due to a temperature change or aged deterioration.
  • FIG. 1 is a configuration diagram illustrating a configuration example of a PLL circuit according to a first embodiment of the present invention. It is a conceptual diagram showing the relationship between the applied voltage of DAC12 which concerns on Embodiment 1 of this invention, and convergence time. It is a block diagram which shows the modification of the PLL circuit of Embodiment 1 of this invention. It is a block diagram which shows one structural example of the PLL circuit which concerns on Embodiment 2 of this invention. It is a block diagram which shows the modification of the PLL circuit which concerns on Embodiment 2 of this invention.
  • FIG. 1 is a block diagram showing a configuration example of a PLL circuit according to Embodiment 1 of the present invention.
  • the PLL circuit includes a PFD (Phase Frequency Detector) 1, a CP (Charge Pump) 2, an LF (Loop Filter) 3, a VCO 4, a frequency divider 5, a ⁇ modulator 6, a chirp generation circuit 7, a parameter control circuit 8, a frequency A conversion circuit 9, an ADC (Analog to Digital Converter) 10, a DSP (Digital Signal Processor) 11, a DAC 12, and a switch 13 are provided.
  • PFD1 (an example of a phase frequency comparator) is a PFD that compares the phases of the reference signal and the output signal of the frequency divider 5 and outputs a signal corresponding to the phase difference to CP2.
  • the reference signal is supplied from a signal source such as a crystal oscillator.
  • CP2 is a charge pump circuit that converts the output signal of PFD1 into a current and outputs the converted current to LF3.
  • LF3 (an example of a loop filter) is an LF that blocks a high-frequency component included in the current converted by CP2, and outputs the blocked signal to the VCO 4.
  • VCO 4 (an example of an oscillator) is a VCO that changes the oscillation frequency in accordance with a signal output by LF 3.
  • the frequency divider 5 (an example of a frequency divider) divides the oscillation signal output from the VCO 4 in accordance with the frequency division ratio setting signal output from the ⁇ modulator 6 and supplies the divided signal to the PFD 1 and the ⁇ modulator 6. This is the output frequency divider.
  • the ⁇ modulator 6 (an example of the ⁇ modulator) operates using the output signal of the frequency divider 5 as a clock, generates a frequency division ratio setting signal according to the output signal of the chirp generation circuit 7, and generates the generated frequency division ratio This is a ⁇ modulator that outputs a setting signal to the frequency divider 5.
  • the chirp generation circuit 7 outputs a chirp signal linearly changing with respect to time to the ⁇ modulator 6 corresponding to the frequency division ratio of the PLL circuit, and at the timing when the frequency of the PLL circuit changes sharply.
  • This is a circuit that outputs a signal to the parameter control circuit 8.
  • the chirp generation circuit 7 is a digital circuit, and an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), a microcomputer, or the like is used.
  • the parameter control circuit 8 is a parameter control circuit 8 that generates control parameters for controlling the DAC 12 and the switch 13 and outputs the generated parameters to the DAC 12 and the switch 13.
  • the parameter control circuit 8 outputs a signal for controlling ON / OFF of the switch 13 in synchronization with a signal indicating a timing at which the frequency of the PLL circuit output from the chirp generation circuit 7 changes sharply.
  • the parameter control circuit 8 outputs a control signal indicating the output voltage of the DAC 12 to the DAC 12.
  • the parameter control circuit 8 is a digital circuit, and an ASIC, FPGA, microcomputer, or the like is used.
  • the frequency conversion circuit 9 is a frequency conversion circuit that converts the frequency of the output signal of the VCO 4 and outputs the frequency-converted signal to the ADC 10.
  • the frequency conversion circuit 9 includes a frequency divider 21 that divides the reference signal, a frequency divider 22 that divides the output signal of the VCO, a signal that the frequency divider 21 divides, and a signal that the frequency divider 22 divides. Is provided.
  • the frequency dividing ratio of the frequency divider 21 may be 1. In this case, the frequency divider 21 may be deleted and the reference signal may be input directly to the mixer 23.
  • the ADC 10 is an ADC that converts the analog signal frequency-converted by the frequency conversion circuit 9 into a digital signal and outputs the converted digital signal to the DSP 11.
  • the DSP 11 (an example of a digital signal processor) obtains the instantaneous frequency of the output signal of the VCO 4 from the digital signal converted by the ADC 10, and an error between the desired frequency and the obtained instantaneous frequency in the chirp signal (modulated wave) output from the VCO 4.
  • a method for obtaining the instantaneous frequency for example, there is a method of orthogonally demodulating an input signal, obtaining an instantaneous phase, and calculating the instantaneous frequency from the instantaneous phase.
  • the desired frequency is a frequency corresponding to the chirp signal generated by the chirp generation circuit 7, that is, a frequency obtained by multiplying the frequency of the reference signal by the frequency division ratio indicated by the chirp signal.
  • the convergence time is the time until the error between the desired frequency (desired chirp signal) and the actual frequency (actual chirp signal) falls within a predetermined value.
  • the DAC 12 (an example of a digital-analog converter) is a DAC that generates an analog signal in accordance with a control signal from the parameter control circuit 8 and outputs the generated analog signal to the switch 13.
  • the switch 13 (an example of a switch) is a switch that switches between ON and OFF according to the control signal of the parameter control circuit 8 and controls whether or not the output signal of the DAC 12 is transmitted to the VCO 4.
  • the chirp generation circuit 7 generates a signal proportional to a desired modulation wave and outputs it to the ⁇ modulator 6. For example, if the desired modulation wave is a sawtooth wave, the chirp generation circuit 7 generates a sawtooth wave.
  • the chirp generation circuit 7 outputs a pulse signal that rises at a timing when the output frequency of the PLL circuit changes sharply to the parameter control circuit 8. This pulse signal is called a frequency jump signal.
  • the frequency jump signal is a 1-bit digital signal, and the rising timing means the timing when the output frequency of the present PLL circuit changes sharply.
  • the ⁇ modulator 6 applies ⁇ modulation to a signal proportional to the desired modulation wave generated by the chirp generation circuit 7 and outputs the result to the frequency divider 5.
  • the signal proportional to the desired modulation wave generated by the chirp generation circuit 7 includes a decimal number, but the frequency divider 5 realizes a fractional division ratio by converting it into an integer with a ⁇ modulator and performing ⁇ modulation.
  • the frequency divider 5 divides the signal of the VCO 4 in accordance with the frequency division ratio signal output from the ⁇ modulator 6.
  • PFD 1 outputs a signal corresponding to the phase difference between the reference signal and the output of frequency divider 5 to CP 2.
  • CP2 outputs a current corresponding to the output of PFD1 to LF3.
  • LF3 cuts off the high frequency component of the signal output from CP2, and outputs the signal that cut off the high frequency component to VCO4.
  • the VCO 4 outputs an oscillation signal according to the applied control voltage.
  • the frequency conversion circuit 9 converts the frequency of the input VCO 4 signal and outputs it to the ADC 10.
  • the ADC 10 samples the input at regular intervals, converts it to a digital signal, and outputs it to the DSP 11.
  • the DSP 11 orthogonally demodulates the signal output from the ADC 10 to obtain an instantaneous phase, and calculates an instantaneous frequency from the instantaneous phase.
  • the DSP 11 calculates an error between a desired frequency and an actual frequency in the modulated wave.
  • the PLL circuit cannot follow the steep change in frequency at the point where the frequency of the modulation wave changes sharply, and an error between the desired frequency and the actual frequency becomes large.
  • the DSP 11 compares the time change of the detected actual frequency of the PLL with the time change of the desired frequency, calculates the convergence time until the error between the two becomes a predetermined value or less, and sets the convergence time to the parameter control circuit 8. Output to.
  • the DSP 11 stores parameters such as the slope and length of the chirp signal necessary for obtaining the desired frequency in an internal memory, calculates the desired frequency with reference to these parameters, and calculates the actual frequency. Used to calculate frequency error. Alternatively, the chirp signal itself may be stored.
  • the parameter control circuit 8 obtains the output voltage of the DAC 12 from the convergence time output from the DSP 11 and outputs the obtained output voltage to the DAC 12.
  • the parameter control circuit 8 turns on the switch 13 in synchronization with the frequency jump signal output from the chirp generation circuit 7 and turns off the switch 13 when the ON time of the switch 13 obtained from the convergence time elapses.
  • the ON time is a time during which the switch 13 is ON.
  • the signal output from the parameter control circuit 8 to the switch 13 is a 1-bit digital signal, which means “1” means switch ON and “0” means switch OFF.
  • the parameter control circuit 8 may calculate the set time of the DAC 12 and the ON time of the switch 13 from the convergence time, or a table showing the relationship between the convergence time, the set time of the DAC 12 and the ON time of the switch 13. May be stored in the memory, and the set time of the DAC 12 and the ON time of the switch 13 may be obtained from the table.
  • the DAC 12 sets the output voltage according to the control signal output from the parameter control circuit 8 and outputs the set voltage to the switch 13.
  • the switch 13 controls ON / OFF according to the control signal output from the parameter control circuit 8, and outputs the output voltage of the DAC 12 to the VCO 4 while the switch 13 is ON. When it is OFF, the output signal of the DAC 12 is blocked.
  • VCO 4 outputs an oscillation frequency according to a composite voltage of the output voltage of LF 4 and the output voltage of DAC 12 while switch 13 is ON.
  • the DSP 11 measures the convergence time until the error between the desired frequency and the actual frequency is equal to or less than a predetermined value, and converges to the parameter control circuit 8 in the same manner as described above. Output time.
  • the parameter control circuit 8 changes two parameters of the output voltage of the DAC 12 and the ON time of the switch 13 according to the convergence time.
  • the parameter control circuit 8 outputs the output voltage of the DAC 12 to the DAC 12 as needed.
  • the parameter control circuit 8 turns on the switch 13 in synchronization with the next frequency jump signal, and turns off the switch 13 when the ON time of the switch 13 elapses.
  • the convergence time is measured again by the DSP 11, and the parameter control circuit 8 changes two parameters of the output voltage of the DAC 12 and the ON time of the switch 13 according to the convergence time.
  • the parameter control circuit 8 searches for a parameter that minimizes the convergence time.
  • FIG. 2 is a conceptual diagram showing the relationship between the voltage applied to DAC 12 and the convergence time according to Embodiment 1 of the present invention.
  • FIG. 2 when the application amount from the DAC 12 is too large (see FIG. 2A) and too small (see FIG. 2C), the application amount by the DAC 12 is appropriate (FIG. 2).
  • the convergence time becomes longer. That is, by observing the convergence time and searching for a parameter that minimizes the convergence time, an appropriate application parameter can be obtained. For example, the following two methods can be used to search for a parameter that minimizes the convergence time.
  • the first method sweeps two parameters, the output voltage of the DAC 12 and the ON time of the switch 13, over the entire range, stores each convergence time, and creates a table of convergence times corresponding to the parameter values. It is a technique.
  • the parameter control circuit 8 employs a parameter value that minimizes the convergence time, and generates a modulated wave.
  • the second method is the gradient descent method, which is a minimization algorithm.
  • the parameter control circuit 8 calculates the gradient from the change in convergence time with respect to the change in each parameter, and reaches the minimum value by changing the parameter so as to decrease the gradient.
  • the parameter control circuit 8 employs the parameter value and generates a modulated wave.
  • the convergence time is fed back and the applied voltage and the applied time are adjusted, so that it is dynamically appropriate according to changes in circuit characteristics due to temperature changes and aging deterioration. There is an effect that the applied parameter can be obtained.
  • By performing feedback so as to minimize the convergence time it is possible to minimize the invalid time that deviates from the desired frequency and to increase the proportion of the time that is effective as a signal.
  • the PLL circuit of the first embodiment may be configured such that the output of the VCO 4 is input to the frequency divider and the output of the frequency divider is input to the frequency divider 5 and the frequency divider 22.
  • FIG. 3 is a configuration diagram showing a modification of the PLL circuit according to the first embodiment of the present invention.
  • the operating frequency of the frequency divider 5 and the frequency divider 22 is lowered, so that the frequency division ratio is also reduced. Since the frequency divider has a feature that the power consumption increases as it operates at a higher frequency, providing the frequency divider 31 (an example of a second frequency divider) reduces the overall power consumption. In addition, since the frequency dividing ratio of the frequency divider 5 and the frequency divider 22 is reduced, the overall circuit scale is reduced by providing the frequency divider 31.
  • the parameter control circuit 8 controls whether or not the output impedance of the DAC 12 is set to high impedance instead of the switch 13.
  • the parameter control circuit 8 controls the time waveform of the output voltage of the DAC 12. At this time, since the time waveform needs to be synchronized with the frequency jump signal output from the chirp generation circuit 7, the parameter control circuit 8 controls the output voltage of the DAC 12 in synchronization with the frequency jump signal.
  • FIG. 4 is a block diagram showing a configuration example of a PLL circuit according to Embodiment 2 of the present invention.
  • the DAC 12 and the switch 13 of the first embodiment are deleted, the newly added CP41 (an example of a charge pump circuit) is connected to the output terminal of CP2, and the parameter control circuit 8
  • the CP 41 is controlled.
  • the difference from the first embodiment is that, while the first embodiment uses the DAC 12 and the switch 13 to apply a voltage to the output terminal of the LF3, the second embodiment has the CP41 connected to the input terminal of the LF3. Applying current.
  • CP 41 is a charge pump circuit that applies a current to LF 3 in accordance with a control signal from parameter control circuit 8.
  • the parameter control circuit 8 obtains the set current of the CP 41 and the ON time of the CP 41 from the convergence time output from the DSP 11.
  • the parameter control circuit 8 outputs a set current to the CP 41 as needed, and outputs a control signal for turning on the CP 41 in synchronization with the frequency jump signal output from the chirp generation circuit 7. Then, the parameter control circuit 8 outputs a signal for turning off the CP 41 when the ON time of the CP 41 elapses.
  • the control signal output by the parameter control circuit 8 is a 1-bit digital signal. When “1”, it means ON, and when it is “0”, it means OFF.
  • the parameter control circuit 8 searches for the output current and ON time of the CP 41 so as to minimize the convergence time measured by the DSP 11 in the same manner as in the first embodiment, and operates using the parameters obtained thereafter. To do.
  • CP 41 applies a current to LF 3 for a predetermined time according to the control signal of parameter control circuit 8. In the point where the frequency changes sharply, the CP 41 injects an appropriate charge into the LF 3 to shorten the time until the correct frequency is output again.
  • LF3 cuts off the high frequency component of the output current of CP2 and the output current of CP41 and outputs it to VCO4 during the ON time.
  • VCO 4 controls the oscillation frequency according to the output signal of LF 3 and outputs an oscillation signal.
  • the convergence time is fed back and the applied current and the applied time of the CP 41 are adjusted. Therefore, according to the change in the circuit characteristics due to the temperature change and the aging deterioration, There is an effect that an appropriate applied parameter can be obtained.
  • an active filter is used as the loop filter, the output voltage of the loop filter cannot be directly applied from the outside to obtain a desired value, and the first embodiment cannot be used.
  • the loop filter Since charges are injected into the input, it can be used in an active filter.
  • the frequency divider 31 is loaded on the feedback path of the VCO 4, the oscillation signal of the VCO 4 is output to the frequency divider 31, and the signal divided by the frequency divider 31 is divided. 5 may be output.
  • FIG. 5 is a block diagram showing a modification of the PLL circuit according to Embodiment 2 of the present invention.

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Abstract

Au moyen d'un circuit PLL classique, des caractéristiques de circuit changent dynamiquement en raison de changements de température et de dégradation au cours du temps, et par conséquent, il était difficile de trouver des paramètres d'application appropriés pour un CAN. Ce circuit PLL comprend : des diviseurs de fréquence permettant de diviser des signaux d'oscillation ; un comparateur de fréquence de phase permettant de comparer un signal de référence avec des signaux d'oscillation divisés par les diviseurs de fréquence, et d'émettre des signaux en fonction de la différence correspondante ; un filtre à boucle qui bloque des composantes haute fréquence de signaux émis par le comparateur de fréquence de phase, et émet des signaux pour lesquels les composantes haute fréquence sont bloquées ; un oscillateur qui change la fréquence d'oscillation en fonction des signaux de sortie du filtre à boucle, et émet des signaux d'oscillation ; un processeur de signal numérique permettant de trouver la fréquence des signaux d'oscillation ; un circuit de commande de paramètres permettant de trouver des paramètres de commande sur la base de la fréquence du signal d'oscillation trouvée par le processeur de signal numérique ; et un convertisseur analogique-numérique qui émet des signaux analogiques vers le filtre à boucle ou l'oscillateur en fonction des paramètres de commande, et corrige le changement de temps de la fréquence d'oscillation.
PCT/JP2017/000541 2017-01-11 2017-01-11 Circuit pll WO2018131084A1 (fr)

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PCT/JP2017/000541 WO2018131084A1 (fr) 2017-01-11 2017-01-11 Circuit pll
JP2018561128A JP6556383B2 (ja) 2017-01-11 2017-01-11 Ｐｌｌ回路

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7015738B1 (en) * 2003-06-18 2006-03-21 Weixun Cao Direct modulation of a voltage-controlled oscillator (VCO) with adaptive gain control
JP2006136000A (ja) * 2004-11-08 2006-05-25 Samsung Electronics Co Ltd スプレッドスペクトルクロック生成器及びスプレッドスペクトルクロック信号を生成する方法
US8022782B2 (en) * 2008-09-16 2011-09-20 Samsung Electronics Co., Ltd. Two-point phase modulator and method of calibrating conversion gain of the same
JP2012165036A (ja) * 2011-02-03 2012-08-30 Toshiba Corp スペクトラム拡散クロックジェネレータ
JP2015115633A (ja) * 2013-12-09 2015-06-22 株式会社メガチップス クロック生成回路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7015738B1 (en) * 2003-06-18 2006-03-21 Weixun Cao Direct modulation of a voltage-controlled oscillator (VCO) with adaptive gain control
JP2006136000A (ja) * 2004-11-08 2006-05-25 Samsung Electronics Co Ltd スプレッドスペクトルクロック生成器及びスプレッドスペクトルクロック信号を生成する方法
US8022782B2 (en) * 2008-09-16 2011-09-20 Samsung Electronics Co., Ltd. Two-point phase modulator and method of calibrating conversion gain of the same
JP2012165036A (ja) * 2011-02-03 2012-08-30 Toshiba Corp スペクトラム拡散クロックジェネレータ
JP2015115633A (ja) * 2013-12-09 2015-06-22 株式会社メガチップス クロック生成回路

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