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WO2018125191A1 - Revêtement de sous-ailette pour dispositifs finfet (transistor à effet de champ à ailette) - Google Patents

Revêtement de sous-ailette pour dispositifs finfet (transistor à effet de champ à ailette) Download PDF

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Publication number
WO2018125191A1
WO2018125191A1 PCT/US2016/069415 US2016069415W WO2018125191A1 WO 2018125191 A1 WO2018125191 A1 WO 2018125191A1 US 2016069415 W US2016069415 W US 2016069415W WO 2018125191 A1 WO2018125191 A1 WO 2018125191A1
Authority
WO
WIPO (PCT)
Prior art keywords
fin
liner
over
node
gate
Prior art date
Application number
PCT/US2016/069415
Other languages
English (en)
Inventor
Benjamin Chu-Kung
Jack T. Kavalieros
Van H. Le
Ashish Agrawal
Seung Hoon Sung
Tahir Ghani
Glenn A. Glass
Anand S. Murthy
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2016/069415 priority Critical patent/WO2018125191A1/fr
Publication of WO2018125191A1 publication Critical patent/WO2018125191A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6219—Fin field-effect transistors [FinFET] characterised by the source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30—Devices controlled by electric currents or voltages

Definitions

  • the present description relates to the field of FinFET device fabrication for integrated circuit dies and, in particular to a device with a liner over the source and drain.
  • Fin Field Effect Transistors present improvements over complementary metal oxide semiconductor (CMOS) transistors for use in semiconductor chips.
  • CMOS transistors normally have a source, drain, and channel all formed on a flat silicon substrate.
  • FinFETs have the source, drain, and channel formed in a long rib of semiconductor material, referred to as the fin, which extends upward from the semiconductor substrate.
  • a raised source and drain are formed over the fin at each and of a region of the fin that becomes the channel.
  • a gate is then formed over and around the channel between the source and drain.
  • the gate In operation, the gate is turned on to put the channel in a highly conductive state that allows electrons or holes to easily move through the fin from source to drain.
  • the FinFET reduces leakage current from the channel into the substrate that is a problem with planar CMOS transistors.
  • the FinFET also has less leakage between the source and drain in the off state. This is all done in a device that can be made smaller.
  • Figure 1 is a simplified gate cut cross-sectional side view diagram of a FinFET transistor with a liner according to an embodiment.
  • Figures 2, 3, and 4 show a Ge/SiGe fin suitable for constructing a transistor according to an embodiment in a fin cut under the source, a gate cut and a fin cut under the gate, respectively.
  • Figures 5, 6, and 7 show a Ge/SiGe fin with an added gate oxide and gate metal according to an embodiment in a fin cut under the source, a gate cut and a fin cut under the gate, respectively.
  • Figures 8, 9, and 10 show a Ge/SiGe fin with excess gate oxide removed according to an embodiment in a fin cut under the source, a gate cut and a fin cut under the gate, respectively.
  • Figures 11, 12, and 13 show a Ge/SiGe fin with spacers and raised source and drain according to an embodiment in a fin cut under the source, a gate cut and a fin cut under the gate, respectively.
  • Figures 14, 15, and 16 show a Ge/SiGe fin with recessed shallow trench isolation according to an embodiment in a fin cut under the source, a gate cut and a fin cut under the gate, respectively.
  • Figures 17, 18, and 19 show a Ge/SiGe fin with a liner over the source, drain and gate according to an embodiment in a fin cut under the source, a gate cut and a fin cut under the gate, respectively.
  • Figures 20, 21, and 22 show a Ge/SiGe fin with a dielectric over the liner according to an embodiment in a fin cut under the source, a gate cut and a fin cut under the gate, respectively.
  • Figures 23, 24, and 25 show a Ge/SiGe fin with contacts through the dielectric and through the liner according to an embodiment in a fin cut under the source, a gate cut and a fin cut under the gate, respectively.
  • Figure 26 is a block diagram of a computing device incorporating a die with FinFET devices using a liner according to an embodiment.
  • a germanium (Ge) transistor in a FinFET device offers distinct benefits for some applications especially when structured with a SiGe subfin.
  • S1O 2 is used as a gate oxide
  • both SiGe and Ge show a poor interface to SiC based oxides. Accordingly, there are many different interface states at these interfaces. The different states provide a conduction path and which then contributes to leakage through the gate when the transistor is in an off-state.
  • This off-state leakage increases power consumption and increases the heat generated by the transistor as the leakage current is dissipated. In addition, the off-state leakage diminishes the difference between the on and the off state. This reduces the transistors effectiveness for many different circuit applications.
  • a liner is formed between the SiGe or Ge and S1O 2 interface.
  • the liner may be applied over a SiGe subfin.
  • the liner improves the interface and reduces the off- state leakage.
  • a conventional ILD such as S1O 2 may be used with improved current leakage.
  • the liner may be applied after a dummy gate has been formed or after a subtractive gate has been formed in a FinFET transistor structure.
  • the liner may also be formed after an RSD (Raised Source and Drain) has been formed. The liner remains in place and is not removed. In addition, by placing the liner over a dummy gate or subtractive gate, the liner does not affect the channels of the transistor.
  • RSD Raised Source and Drain
  • Figure 1 is a simplified gate cut cross-sectional side view diagram of a FinFET transistor with a liner.
  • the structure is built over a silicon substrate 102.
  • a SiGe fin 104 is formed over the substrate.
  • the substrate typically is referred to as having a front side and a back side.
  • the active components are formed on the front side and the back side provides structure and, in some cases, a mounting surface.
  • the fin extends from the front side and is shown in a transverse view extending across the page.
  • An additional Ge fin layer is formed over the SiGe portion of the fin for source, drain, or another structure.
  • a gate oxide 108 of e.g. S1O 2 is then deposited over the Ge.
  • a gate electrode 110 e.g. TiN or polysilicon is formed over the gate oxide. With gate electrode in place, an electrode liner 112 is applied over the gate metal.
  • the liner is a thin layer of a non-conducting and electrically inert material, such as a ceramic or oxide. Additional layers 114 of dielectric and other layers for connection, wiring, isolation and structure are formed over the liner. A contact 116 is formed through these layers to make an electrical contact with the gate electrode. While only a gate electrode is shown, additional electrodes may be added, depending on the particular device. A similar structure may be used for a source, drain, and any other nodes or contacts of the device.
  • n-type transistor there is a first n-well 122 for a source and a contact
  • n-well 124 coupled to the n-well.
  • n-well 126 for a drain and a contact 128 coupled to the well.
  • the liner extends over the source and drain just as for the gate with an opening for the contact. Additional structure such as shallow trench isolation, oxides, overlying dielectrics, and distribution and connection layers are not shown in order not to obscure the liner and other aspects.
  • the structure is referred to typically as a finFET, however, the fin-based structure may be used to form other devices in addition to transistors, including diodes, control gates, switches, connecting nodes, etc.
  • a transistor will be described with a source, drain, and gate, however, the same structure, principles, and techniques may be applied to other fin-based devices with other types of nodes.
  • the principles of the present invention may be applied to a variety of different fin materials instead of SiGe and GE.
  • the fin may be made of any semiconducting (e.g. III-V, II-V, C-containing), organic, or conducting dielectric (e.g. ZnO, NiO) materials.
  • Figures 2, 3, and 4 show a Ge/SiGe fin suitable for constructing a transistor as described herein.
  • Figure 3 is a side view diagram along the fin similar to that of Figure 1.
  • Figure 2 is an S/D fin cut cross-section of the same structure taken across the fin at the position of either the source or the drain.
  • Figure 4 is a gate fin cut cross-section of Figure 3 structure taken across the fin at the position of the gate which is in the center of Figure 3.
  • a SiGe subfin 204 is formed over a silicon substrate 202.
  • Ge fin 208 is formed over the subfin and a shallow trench isolation (STI) is formed over the substrate 202 on both sides of the fin.
  • STI shallow trench isolation
  • the silicon substrate 202 is a wafer with many parallel rows of fins.
  • the STI is formed between all of the rows.
  • the illustrated fin has a Ge fin over a SiGe subfin, the wafer and portions of each die may have other types of dies and areas that do not have fins.
  • the process described herein may be applied to a Ge-SiGe fin while other parts of the wafer are masked or at least masked for some parts of the process.
  • the substrate is described as silicon but may be formed of many other materials to suit different implementations.
  • the substrate may be a semiconductor substrate but may also be another type of material such as oxide in silicon-on-insulator (SOI), partial SOI substrate, polysilicon, amorphous silicon, ceramic, glass or organic materials, etc.
  • SOI silicon-on-insulator
  • the semiconductor substrate may have multiple wafers or dies which are stacked or otherwise deposited or grown.
  • the fin may be formed by removing material between the fins to create ridges from the substrate. Alternatively, the fin may be formed by applying or depositing material over the substrate
  • Figures 5, 6, and 7 show a second fabrication stage of the transistor of Figures 2, 3, and 4.
  • a gate oxide layer 210 is deposited over the entire surface of the transistor and any other similar neighboring transistors.
  • the gate oxide may be S1O 2 or any other suitable oxide, depending on the particular characteristics desired for the transistor. While referred to herein as a gate oxide, the layer may be formed of other dielectric materials that can be formed or patterned over the fin, such as high-k materials include hafnium silicate, zirconium silicate, hafnium dioxide and zirconium dioxide, etc.
  • the gate dielectric may be applied by any of a variety of different techniques including atomic layer deposition.
  • the gate oxide is followed by the selective deposition of a gate metal, such as Cu, Ti, or Al.
  • the gate 212 may be formed of polysilicon or another suitable non-metallic material.
  • the gate metal may be deposited using photolithography or in any other way. In photolithography, a photoresist is first applied and exposed over the planned transistor gates. The photoresist is removed over the portions for each gate. The gate metal is then deposited or plated and the photoresist is removed leaving the structure shown in the figures.
  • the gate fin cut of Figure 7 shows the gate metal deposited over the gate oxide on the fin and the S/D fin cut of Figure 5 shows only the liner. There is no gate metal over the source and drain.
  • Figures 8, 9, and 10 show the transistor after excess gate oxide has been removed.
  • the gate metal may be used as a mask over the gate oxide. All of the gate oxide that is not covered by the gate metal is removed. As shown in Figure 8 the source/drain and STI areas are exposed. The gates as shown in Figure 10 are covered in oxide.
  • the gate metal provides a convenient mask for etching techniques but other processes may be used including applying the oxide only over the gates initially.
  • Figures 11, 12, and 13 show the transistor after spacers and RSD (Raised Soure/Drain) formations have been applied.
  • the gate fin cut of Figure 13 shows that the gate is not directly affected, however
  • Figure 12 shows that spacers 216 are applied on each side of the gate along and around the fin.
  • the spacers serve to isolate the gate metal from layers that are applied later, such as the ILD (Inter- Layer Dielectric) layers.
  • a raised source and a raised drain 214 are applied over and around the fin.
  • the shape of the RSD 214 is shown also in the S/D fin cut view of Figure 11, although other shapes may also be used.
  • the RSD may be formed of doped Si, Ge, SiGe, or another suitable material. The particular shapes may be formed by epitaxial growth or by photolithography as discussed above or in any other suitable fashion.
  • the source and drain may be formed by doping the Ge fin
  • Figures 14, 15, and 16 are three views of the transistor after a process to recess the height of the STI 206.
  • the STI is etched away using any of a variety of suitable techniques after the gate, source, drain and any other appropriate structures are masked.
  • the etching leaves an exposed region 220 of the fin. This region is mostly the SiGe subfin, but depending on the particular configuration may also include some of the Ge fin. While there are many benefits to recessing the STI, the reduced STI layer leaves a part of the SiGe subfin exposed.
  • an ILD were to be applied directly over the structure, there would be a direct interface between the SiGe subfin and the ILD which typically includes a significant amount of silica (S1O 2 ). As mentioned above, there may be significant leakage from the SiGe subfin channel of this transistor and the ILD.
  • a liner may be used to stop at least some of the leakage.
  • the STI By etching the STI, the STI is prevented from being in contact with the P-N junction between the Ge and the n+Ge. This removes a potential source of current leakage from the P-N junction.
  • the STI may be etched before or after some of the other operations described here. The thickness of the STI may be configured to suit different purposes. In the described examples, the STI is etched sufficient to prevent the monolayer from being in contact with the Ge in order to avoid the leakage.
  • Figures 17, 18, and 19 are three views of depositing a liner 222 over the entire transistor structure and particularly in the exposed undercut regions 220 of the SiGe subfin.
  • the layer may be deposited or plated and covers the entire transistor in this example. However there are areas that do not need to be covered such as the source, drain, and gate locations for the attachment of contacts or electrodes. Accordingly, the application of the liner may be modified to only include exposed parts of the fin and the RSD.
  • the liner is selected as a non-conductive or low conductivity material that adheres well to the materials of the fin. This may be Si and Ge but may be other materials, depending on the particular implementation. A variety of electrically inert materials may also be used. Some suitable materials are ceramics and oxides. Some examples of such materials include AI2O 3 , Ti0 2 , SiN, Hf0 2 , TiON, Ge0 2 , GeN, Zr0 2 and others.
  • this non-conducting or dielectric liner material 222 forms an electrical conduction barrier around the fin on both sides as shown in both the S/D cut of Figure 17 and the gate cut of Figure 19. It also forms a barrier across the top of the fin including the gate electrode 212, the spacers 216 and the RSD 214. The ends of the fin 208 and the subfin 204 are also covered in the liner. The entire transistor is electrically isolated on the top. The only conduction path is therefore into the substrate 202 which is a very limited path for a FinFET structure.
  • Figures 20, 21, and 22 show the transistor structure after an ILD 230 has been applied over all or most of the wafer.
  • the ILD is applied over the liner 222 so that the liner is between the ILD and the fin 204, 208 and between the ILD and the source 214, drain 214, and gate 212.
  • the ILD may be formed of conventional materials including silica and there will be no or very little electrical conduction or leakage into the ILD 230 because of the liner 222.
  • the transistor is completed with the addition of source and drain contacts 232.
  • holes are etched through the ILD 230 and the liner 222 to reach the source 214 and drain 214. These holes are then filled with a suitable conductor such as copper or aluminum.
  • a gate contact 234 may also be a gate contact 234 through the liner 222 to the gate metal 212. The arrangement and configuration of the contact may be adapted to suit different devices.
  • the device is then finished with any additional operations as may be suitable for the intended device such as adding additional metal and dielectric layers, creating further contacts, conductive paths and connections, polishing and other finishing operations.
  • the wafer is diced to form individual chips which are packaged as appropriate for the intended application.
  • the liner is applied after the gate and the RSD has been deposited. This allows for a wide variety of different liners to be used because the liner does not need to later be removed in part. In addition a liner in this location has very little effect on the channel so that a greater variety of different liners may be used.
  • Comparing Figure 24 with Figure 1 shows that a transistor structure may be produced with or without the raised source and drain.
  • the liner may also be applied to other types of FinFET devices.
  • Figure 26 illustrates a computing device 11 in accordance with one implementation.
  • the computing device 11 houses a board 2.
  • the board 2 may include a number of components, including but not limited to a processor 4 and at least one communication chip 6.
  • the processor 4 is physically and electrically coupled to the board 2.
  • the at least one communication chip 6 is also physically and electrically coupled to the board 2.
  • the communication chip 6 is part of the processor 4.
  • computing device 11 may include other components that may or may not be physically and electrically coupled to the board 2.
  • these other components include, but are not limited to, volatile memory (e.g., DRAM) 8, non-volatile memory (e.g., ROM) 9, flash memory (not shown), a graphics processor 12, a digital signal processor (not shown), a crypto processor (not shown), a chipset 14, an antenna 16, a display 18 such as a touchscreen display, a touchscreen controller 20, a battery 22, an audio codec (not shown), a video codec (not shown), a power amplifier 24, a global positioning system (GPS) device 26, a compass 28, an accelerometer (not shown), a gyroscope (not shown), a speaker 30, a camera 32, and a mass storage device (such as hard disk drive) 10, compact disk (CD) (not shown), digital versatile disk (DVD) (not shown), and so forth).
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • the communication chip 6 enables wireless and/or wired communications for the transfer of data to and from the computing device 11.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 6 may implement any of a number of wireless or wired standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, Ethernet derivatives thereof, as well as any other wireless and wired protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 11 may include a plurality of communication chips 6. For instance, a first communication chip 6 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second
  • communication chip 6 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the integrated circuit die of the processor, memory devices, communication devices, or other components are fabricated to include two transistor, one resistor memory cells with an RRAM or other element as described herein.
  • the described memory cells may be embedded as memory for other components in a CMOS or other logic processing die or a standalone memory array may be made on its own die.
  • the term "processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the computing device 11 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 11 may be any other electronic device that processes data including a wearable device.
  • Embodiments may be implemented as a part of one or more memory chips, controllers, CPUs (Central Processing Unit), microchips or integrated circuits interconnected using a motherboard, an application specific integrated circuit (ASIC), and/or a field programmable gate array (FPGA).
  • CPUs Central Processing Unit
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • references to “one embodiment”, “an embodiment”, “example embodiment”, “various embodiments”, etc., indicate that the embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Further, some embodiments may have some, all, or none of the features described for other embodiments.
  • Coupled is used to indicate that two or more elements co-operate or interact with each other, but they may or may not have intervening physical or electrical components between them.
  • a FinFET device includes a semiconductor substrate having a front side surface, a fin extending from the front side surface, a node of the fin applied over the fin, a dielectric liner over the node, and inter-layer dielectric over the front side surface and the node.
  • the liner is also over the fin.
  • inventions include shallow trench isolation beside the fin and wherein the liner is also over the shallow trench isolation.
  • the device comprises a transistor, wherein the node comprises a gate, the transistor further comprising a raised source as a node and a raised drain as a node and wherein the liner is over the gate, the source and the drain.
  • the liner is formed of a ceramic.
  • the liner is formed a material selected from a group consisting of of A1203, Ti02, SiN, Hf02, TiON, Ge02, GeN, and Zr02
  • the inter-layer dielectric is formed of silica.
  • the fin comprises a silicon germanium sub fin and a germanium fin over the sub fin and wherein the liner covers a portion of the subfin.
  • the fin is formed from the semiconductor substrate.
  • the gate oxide is formed of silica and the liner is formed of a dielectric material other than silica.
  • Some embodiments pertain to a method of forming a fin-based device that includes forming a fin on a front side surface of a semiconductor substrate, forming a node over the fin; forming a dielectric liner over the node, and forming an inter-layer dielectric over the front side surface and the node.
  • forming a liner comprises forming the liner also over the fin. Further embodiments include forming a shallow trench isolation over the substrate beside the fin before forming the node and recessing the shallow trench isolation after forming the node and before forming the liner.
  • Further embodiments include forming spacers beside the node and wherein forming the liner comprises forming the liner over the spacers.
  • Further embodiments include etching a hole through the inter-layer dielectric and the liner to reach the node and forming a contact to the node in the hole.
  • the fin is formed of Ge and the liner is formed of silica.
  • Some embodiments pertain to a computing system that includes a memory having instructions stored thereon, and a processor coupled to the memory to execute the instructions, the processor having transistors formed over a silicon substrate having a front side surface, at least some of the transistors having a fin extending from the front side surface, a node of the fin applied over the fin, a dielectric liner over the node, and inter-layer dielectric over the front side surface and the node.
  • the transistors further comprise a raised source as a node and a raised drain as a node and wherein the liner is over the gate, the source and the drain.
  • the liner is formed of a ceramic.

Landscapes

  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un revêtement de sous-ailette pour une utilisation avec des dispositifs FinFET. Dans un exemple, un dispositif FinFET comprend un substrat semi-conducteur ayant une surface latérale avant, une ailette s'étendant à partir de la surface latérale avant, un noeud de l'ailette appliquée sur l'ailette, un revêtement diélectrique sur le noeud, et un diélectrique inter-couche sur la surface latérale avant et le noeud.
PCT/US2016/069415 2016-12-30 2016-12-30 Revêtement de sous-ailette pour dispositifs finfet (transistor à effet de champ à ailette) WO2018125191A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2016/069415 WO2018125191A1 (fr) 2016-12-30 2016-12-30 Revêtement de sous-ailette pour dispositifs finfet (transistor à effet de champ à ailette)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2016/069415 WO2018125191A1 (fr) 2016-12-30 2016-12-30 Revêtement de sous-ailette pour dispositifs finfet (transistor à effet de champ à ailette)

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WO2018125191A1 true WO2018125191A1 (fr) 2018-07-05

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130154005A1 (en) * 2011-12-20 2013-06-20 International Business Machines Corporation Soi finfet with recessed merged fins and liner for enhanced stress coupling
US20140138742A1 (en) * 2011-07-22 2014-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Device Having Source/Drain Regions Regrown from Un-Relaxed Silicon Layer
US20150035069A1 (en) * 2013-07-31 2015-02-05 United Microelectronics Corp. Finfet and method for fabricating the same
US20150179756A1 (en) * 2013-02-27 2015-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. Metal Gate and Gate Contact Structure for FinFET
US20160099342A1 (en) * 2014-10-02 2016-04-07 International Business Machines Corporation Structure and method to increase contact area in unmerged epi integration for cmos finfets

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140138742A1 (en) * 2011-07-22 2014-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Device Having Source/Drain Regions Regrown from Un-Relaxed Silicon Layer
US20130154005A1 (en) * 2011-12-20 2013-06-20 International Business Machines Corporation Soi finfet with recessed merged fins and liner for enhanced stress coupling
US20150179756A1 (en) * 2013-02-27 2015-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. Metal Gate and Gate Contact Structure for FinFET
US20150035069A1 (en) * 2013-07-31 2015-02-05 United Microelectronics Corp. Finfet and method for fabricating the same
US20160099342A1 (en) * 2014-10-02 2016-04-07 International Business Machines Corporation Structure and method to increase contact area in unmerged epi integration for cmos finfets

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