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WO2018125141A1 - Procédés d'incorporation de carbone stabilisé dans des films de nitrure de silicium - Google Patents

Procédés d'incorporation de carbone stabilisé dans des films de nitrure de silicium Download PDF

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Publication number
WO2018125141A1
WO2018125141A1 PCT/US2016/069218 US2016069218W WO2018125141A1 WO 2018125141 A1 WO2018125141 A1 WO 2018125141A1 US 2016069218 W US2016069218 W US 2016069218W WO 2018125141 A1 WO2018125141 A1 WO 2018125141A1
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Prior art keywords
silicon nitride
reactant
nitride precursor
precursor
reacting
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PCT/US2016/069218
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English (en)
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James M. Blackwell
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Intel Corporation
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Priority to PCT/US2016/069218 priority Critical patent/WO2018125141A1/fr
Publication of WO2018125141A1 publication Critical patent/WO2018125141A1/fr

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • C23C16/345—Silicon nitride
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • C23C16/45553—Atomic layer deposition [ALD] characterized by the use of precursors specially adapted for ALD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si

Definitions

  • Silicon nitride films for integrated circuits Silicon nitride films for integrated circuits.
  • Incorporation of carbon in stabilized form can be used to improve ash stability and etch selectivity of silicon nitride deposited via either plasma-enhanced atomic layer deposition (ALD) or flowable chemical vapor deposition (CVD) methods.
  • ALD plasma-enhanced atomic layer deposition
  • CVD flowable chemical vapor deposition
  • One technique for introducing carbon into a silicon nitride film is by introducing organic carbon species such as methyls, carbosilanes, etc. at the time of deposition. The organic carbon species introduced in this manner risks being removed thermally or through plasma processing.
  • Figure 1 shows a schematic of a representative deposition system.
  • Figure 2 illustrates a schematic representation of a method of depositing a silicon nitride film or layer on a substrate by an ALD process.
  • Figure 3 presents a symbolic representation of the chemical reactions occurring in the ALD process.
  • Figure 4 presents a symbolic representation of the chemical reactions occuring in a CVD process.
  • Figure 5 is an interposer implementing one or more embodiments.
  • Figure 6 illustrates an embodiment of a computing device.
  • a silicon nitride composition or film incorporating carbon that is bound to two or more nitrogen atoms is described as an integrated circuit device including a substrate incorporating such a silicon nitride film or composition. Methods for forming a silicon nitride film having carbon incorporated pre-bound to two or more nitrogen atoms are also described.
  • a method of forming a silicon nitride composition as a dielectric film includes depositing a silicon nitride precursor having a general formula of General Formula I: R
  • Ri is selected from a hydrogen atom, a substituted amine or nothing at all, wherein R 2 and R are independently selected from a C 1 -C 4 alkylsilyl, and
  • R4 is C x H m R 5 C y H n and x and y are independently is 0 or 1, m and n are independently 0, 1 or 2 and R 5 is a C 1 -C 4 alkylsilyl or nothing at all.
  • the deposited silicon nitride precursor is reacted with a co-reactant such as ammonia, an amine or a multifunctional nitrile (e.g., fumaronitrile, succinonitrile) to form a silicon nitride composition or film.
  • a co-reactant such as ammonia, an amine or a multifunctional nitrile (e.g., fumaronitrile, succinonitrile) to form a silicon nitride composition or film.
  • a co-reactant such as ammonia, an amine or a multifunctional nitrile (e.g., fumaronitrile, succinonitrile)
  • a silicon nitride precursor having the formula of General Formula I incorporates carbon atoms into the composition pre-bound to two or more nitrogen atoms.
  • the composition or film is referenced herein as a silicon nitride composition or film despite containing carbon atoms (a silicon nitride
  • a silicon nitride film derived from a silicon nitride precursor having the formula of General Formula I may be used, for example, as a passivation layer on semiconductor integrated circuits, as an etch mask or as a dielectric between plates in, for example, an analog chip.
  • the silicon nitride precuror having the formula of General Formula I is a carbodiimide, amidine, or guanidine containing reactive N-bis bonds.
  • Examples include, but are not limited to, N,N-bis(trimethylsilyl) carbodiimide, N,N- bis(trimethylsilyl) amidine and N,N-bis(trimethylsilyl) guanidine.
  • silicon nitride precursors having the general formula of General Formula I include heterocyclic complexes including, but are not limited to, N-silylated heterocylic complexes such as triazine and triazole.
  • FIG. 1 shows a schematic of a representative deposition system.
  • the system can representatively be used for a CVD or ALD process.
  • System 100 includes chamber 102 having an interior volume suitable to accommodate a substrate, such as a semiconductor wafer.
  • Chamber 102 includes stage 115 on which a substrate can be supported.
  • Figure 1 shows substrate 120 such as a wafer optionally having a plurality of transistor devices formed thereon on stage 115 in a device side up configuration.
  • gas source 104 of, for example, a silicon nitride precursor having the formula of General Formula I
  • gas source 106 of, for example, a first co-reactant
  • gas source 108 of, for example, a second co-reactant, a purge gas or other gas source.
  • Remote plasma activator 110 is separate from and communicates with chamber 102 while plasma activator 112 may be operated directly in chamber 102 (e.g., a capacitively coupled plasma electrode).
  • a plasma activator such as remote plasma generator 110 and/or plasma generator 112 includes a plasma or ionization source for activating gas source 114, such as a hydrogen or other gas source(s) for introduction of an activated species into chamber 102 (plasma source to include ions, electrons, protons and radicals of the activated gas).
  • gas source 114 such as a hydrogen or other gas source(s) for introduction of an activated species into chamber 102
  • plasma source to include ions, electrons, protons and radicals of the activated gas.
  • the plasma source may be described in terms of energy density related to factors such as an energy applied to the gas source at the plasma activator (e.g., to establish a concentration of activated species in the plasma source) and the distance of plasma activator from a substrate surface in chamber 102. Energy density is one variable associated with a plasma source.
  • Typical plasma densities can be in a range from 0.1 W/cm 2 to 1.0 W/cm 2 .
  • Other variables include the duration or exposure time of the substrate (or reactants) to the plasma source and when a plasma source is introduced.
  • the plasma source may be introduced during more than one of the pulses of an ALD process (e.g., during the purge pulse, co-reactant pulse or both) in a plasma-enhanced ALD (PEALD) process.
  • PEALD plasma-enhanced ALD
  • a plasma source may be introduced with the precursor and co-reactant(s) in a CVD process in plasma-enhanced CVD (PECVD) process.
  • PECVD plasma-enhanced CVD
  • System 100 also includes an example of a heat source (shown as heat source 116) that may be used to heat an interior of chamber 102 to a desired temperature for a reaction between a substrate and the precursor or precursor and co-reactant(s).
  • heat source 116 shows temperature source 116 disposed within chamber 102 (in this case, within a stage within the chamber). It is to be appreciated that a suitable reactor may include hotwall or coldwall chambers.
  • Figure 1 also shows evacuation source 118 connected to an interior chamber 102 to evacuate excess or non-reactive constituents or process gases (e.g., precursor, co-reactant) from the chamber. Evacuation source 118 may be connected to a vacuum pump or other source (not shown).
  • Figure 2 illustrates a schematic representation of a method of depositing a silicon nitride film or layer on a substrate by an ALD process.
  • Figure 3 presents a symbolic representation of the chemical reactions occurring in the ALD process using a silicon nitride precursor of General Formula I that is N,N-bis(trimethylsilyl) carbodiimide.
  • the method begins by placing a substrate in a chamber of an ALD system such as system 100 of Figure 1 (block 210, Figure 2).
  • the substrate may be a silicon wafer including a plurality of transistors formed thereon and, for example, at least one dielectric layer deposited on its surface.
  • the substrate may be heated within the reactor to a
  • a representative pressure within the reactor may range from 0.1 Torr to 10 Torn
  • a first co-reactant of a Lewis acidic chlorosilane co-reactant is introuced (e.g., pulsed) into the chamber and deposited on the substrate (block 215, Figure 2).
  • a Lewis acidic chlorosilane such as silicon tetrachloride, hexachlorodisilane, trichlorosilane and
  • dichlorosilane When used as a co-reactant with a silicon nitride precursor, the silicon nitride precursor is incorporated into a film in conjunction with the chlorosilane and a volatile less Lewis acidic by-product (e.g., a chloride) and an alkylsilyl chloride is removed as part of the process (see Figure 3).
  • a volatile less Lewis acidic by-product e.g., a chloride
  • an alkylsilyl chloride is removed as part of the process (see Figure 3).
  • the pulsing of the Lewis acidic chlorosilane e.g., silicon
  • tetrachloride, hexachlorodisilane, trichlorosilane and dichlorosilane can be between about 1 second to 20 seconds with a flow rate of up to 10 standard liters per minute (SLM).
  • SLM standard liters per minute
  • the chamber of the ALD system is then purged in preparation for introducing a silicon nitride precursor having the formula of General Formula I (block 220, Figure 2).
  • purge gases include, but are not limited to, nitrogen (N 2 ), helium (He) and Argon (Ar) or other non-reactive gases. Purging can be between about 0.5 seconds and 40 seconds.
  • a silicon nitride precursor having the formula of General Formula I is then introduced into the chamber (block 225, Figure 2).
  • the silicon nitride precursor is N,N-bis(trimethylsilyl) carbodiimide.
  • a representative deposition pulse for a silion nitride precursor includes, but are not limited to, a pulse duration of between around 0.5 seconds and 20 seconds, a flow rate of up to 10 SLM, a reactor pressure between around 0.05 Torr and 1000 Torr, a temperature between around 80°C and 200°C, a substrate temperature between around 100°C and around 400°C, and an RF energy source that may be applied at a power that ranges from 5 W to 200 W and at a frequency of 13.56 MHz, 27
  • the chamber of the system is then purged again in preparation for introducing second co-reactant (block 230, Figure 2).
  • the purging is performed with plasma.
  • Plasma purging can be between about 0.5 seconds and 10 seconds.
  • a second co- reactant of, for example, ammonia is then introduced into the chamber (block 235, Figure 2).
  • a representative deposition of ammonia in an ALD process is a pulse duration of 0.5 seconds to 20 seconds.
  • the chamber may then be purged for about 0.5 seconds to 10 seconds.
  • the sequence of first co-reactant pulse/purge/precursor pulse/purge/second co-reactant pulse/purge is repeated until a target silicon nitride film having bound carbon film thickness is achieved on the substrate (block 245, Figure 2).
  • the above method or process for forming a silicon nitride film is based on
  • Silicon nitride precursors having the formula of General Formula I can also be used as co-reactants in low temperature flowable CVD processes in conjunction with a first co-reactant of a silylamine such as trisilylamine ((HSi) N) where direct Si-N/Si-N metathesis or Si-N/Si-H metathesis occurs leading to incorporation of the reactive carbon bound nitrogen unit in the growing film.
  • a silylamine such as trisilylamine ((HSi) N) where direct Si-N/Si-N metathesis or Si-N/Si-H metathesis occurs leading to incorporation of the reactive carbon bound nitrogen unit in the growing film.
  • a plasma based on ammonia, oxygen, argon or other gases may be used as part of the flowable CVD process. In general, this type of process is carried out at substrate temperatures between 20°C and 100°C with continuous flow of coreactants in defined ratios.
  • the deposition is followed by a higher temperature bake and/or ultraviolet (UV), e-beam or other cure to convert initially deposited film into denser silicon-nitride like film.
  • Figure 4 presents a symbolic representation of the chemical reactions occuring in a CVD process.
  • Figure 5 illustrates interposer 300 that includes one or more embodiments.
  • First substrate 302 may be, for instance, an integrated circuit die.
  • Second substrate 304 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die.
  • interposer 300 may connect an integrated circuit die to ball grid array (BGA) 306 that can subsequently be connected to second substrate 304.
  • BGA ball grid array
  • first and second substrates 302/304 are attached to opposing sides of interposer 300.
  • first and second substrates 302/304 are attached to the same side of interposer 300.
  • three or more substrates are interconnected by way of interposer 300.
  • Interposer 300 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide.
  • the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
  • the interposer may include metal interconnects 308 and vias 310, including but not limited to through-silicon vias (TSVs) 312.
  • Interposer 300 may further include embedded devices 314, including both passive and active devices.
  • Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices.
  • More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on interposer 300.
  • RF radio- frequency
  • silicon nitride compositions and processes for their formation disclosed herein may be used in the fabrication of interposer 300.
  • Figure 6 illustrates computing device 400 in accordance with one embodiment.
  • Computing device 400 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a SoC die.
  • SoC system-on-a-chip
  • the components in computing device 400 include, but are not limited to, integrated circuit die 402 and at least one communication chip 408.
  • communication chip 408 is fabricated as part of integrated circuit die 402.
  • Integrated circuit die 402 may include CPU 404 as well as on-die memory 406, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STTM-RAM).
  • eDRAM embedded DRAM
  • STTM or STTM-RAM spin-transfer torque memory
  • Computing device 400 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die.
  • volatile memory 410 e.g., DRAM
  • non-volatile memory 412 e.g., ROM or flash memory
  • graphics processing unit 414 GPU
  • digital signal processor 416 crypto processor 442 (a specialized processor that executes cryptographic algorithms within hardware)
  • chipset 420 antenna 422, display or a touchscreen display 424, touchscreen controller 426, battery 428 or other power source, a power amplifier (not shown), global positioning system (GPS) device 444, compass 430, motion coprocessor or sensors 432 (that may include an accelerometer, a gyroscope, and a compass), speaker 434, camera 436, user input devices 438 (such as a keyboard, mouse, stylus, and touchpad), and mass storage device 440 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory 410 e.g., DRAM
  • non-volatile memory 412 e.g., ROM or flash memory
  • Communications chip 408 enables wireless communications for the transfer of data to and from computing device 400.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • Communication chip 408 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • Computing device 400 may include a plurality of communication chips 408. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second
  • communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • Processor 404 of computing device 400 includes one or more devices, such as transistors or metal interconnects, as well as silicon nitride passivation formed in accordance with embodiments presented above.
  • the term "processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • Communication chip 408 may also include one or more devices, such as transistors or metal interconnects, as well as silicon nitride passivation formed in accordance with embodiments presented above.
  • another component housed within computing device 400 may contain one or more devices, such as transistors or metal interconnects, as well as silicon nitride passivation formed in accordance with implementations presented above.
  • computing device 400 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • computing device 400 may be any other electronic device that processes data.
  • Example 1 is a method of forming a dielectric film including depositing a silicon nitride precursor having the general formula of General Formula I:
  • dashed lines individually represent an optional bond, wherein Ri is selected from a hydrogen atom, a substituted amine or nothing , wherein R 2 and R are independently selected from a C 1 -C 4 alkylsilyl, wherein R4 is C x H m R 5 C y H n and x and y are independently 0 or 1, m and n are independently 0, 1 or 2 and R 5 is a C 1 -C 4 alkylsilyl; and reacting the silicon nitride precursor with a co-reactant.
  • Example 2 the co-reactant in the method of Example 1 includes ammonia.
  • the silicon nitride precursor in the method of Example 2 is selected from a carbodiimide, an amidine and a guanidine.
  • the co-reactant in the method of Example 3 is ammonia and is a second co-reactant and before the silicon nitride precursor is reacted with the second co-reactant, the method includes reacting the silicon nitride precursor with a first co-reactant including a Lewis acidic chlorosilane.
  • the Lewis acidic chlorosilane in the method of Example 4 includes silicon tetrachloride, hexachlorodisilane, trichlorosilane and dichlorosilane.
  • Example 6 depositing the silicon nitride precursor and reacting the silicon nitride precursor with the first co-reactant and the second co-reactant in the method of Example 4 includes an atomic layer deposition process.
  • the silicon nitride precursor in the method of Example 3 includes N,N- bis(trimethylsilyl)carbodiimide.
  • the silicon nitride precursor in the method of Example 3 includes N,N- bis(trimethylsilyl)amidine.
  • the silicon nitride precursor in the method of Example 3 includes N,N- bis(trimethylsilyl)guanidine.
  • the silicon nitride precursor in the method of Example 1 is selected from a triazine and a triazole.
  • Example 11 depositing the silicon nitride precursor and reacting the silicon nitride precursor with the co-reactant in the method of any of Examples 6-10 includes a chemical vapor deposition process.
  • the co-reactant in the method of Example 11 is a second co-reactant and before the silicon nitride precursor is reacted with the second co-reactant, the method includes reacting the silicon nitride precursor with a first co-reactant including a silylamine.
  • Example 13 is a method of depositing a silicon nitride film including introducing a semiconductor substrate into a chamber; exposing the substrate to a silicon nitride precursor having the general formula of General Formula I: wherein dashed lines individually represent an optional bond, wherein Ri is selected from a hydrogen atom, a substituted amine or nothing, wherein R 2 and R 3 are independently selected from a C 1 -C4 alkylsilyl, wherein R 4 is C x H m R 5 C y H n and x and y are independently 0 or 1, m and n are independently 0, 1 or 2 and R 5 is a C 1 -C4 alkylsilyl; and reacting the silicon nitride precursor with a co-reactant to form a silicon nitride film.
  • a silicon nitride precursor having the general formula of General Formula I: wherein dashed lines individually represent an optional bond, wherein Ri is selected from a hydrogen atom, a substituted amine
  • Example 14 exposing the silicon nitride precursor to the substrate and reacting the silicon nitride precursor with the co-reactant in the method of Example 13 includes a chemical vapor deposition process.
  • Example 15 exposing the silicon nitride precursor to the substrate and reacting the silicon nitride precursor with the co-reactant in the method of Example 13 includes an atomic layer deposition process.
  • Example 16 the co-reactant in the method of Example 15 includes ammonia.
  • the silicon nitride precursor in the method of Example 16 is selected from a carbodiimide, an amidine and a guanidine.
  • the co-reactant in the method of Example 17 is a second co-reactant and before the silicon nitride precursor is reacted with the second co-reactant, the method includes reacting the silicon nitride precursor with a first co-reactant including a Lewis acidic chlorosilane.
  • the silicon nitride precursor in the method of Example 13 is selected from a triazine and a triazole.
  • the co-reactant in the method of Example 13 is a second co-reactant and before the silicon nitride precursor is reacted with the second co-reactant, the method includes reacting the silicon nitride precursor with a first co-reactant including a silylamine.
  • Example 21 is an integrated circuit device including a semiconductor substrate; and a silicon nitride film on the semiconductor substrate, the silicon nitride film including carbon atoms bound to more than one nitrogen atoms.
  • the silicon nitride film of the integrated circuit device of Example 21 includes a passivation layer on an integrated circuit.
  • Example 23 the silicon nitride film of the integrated circuit device of Example 21 includes an etch step.
  • Example 24 the silicon nitride film of the integrated circuit device of any of Examples 20-23 is derived from a silicon nitride precursor having the general formula of General Formula I:
  • dashed lines individually represent an optional bond, wherein Ri is selected from a hydrogen atom, a substituted amine or nothing , wherein R 2 and R are independently selected from a C1-C4 alkylsilyl, wherein R4 is C x H m R 5 C y H n and x and y are independently 0 or 1, m and n are independently 0, 1 or 2 and R 5 is a C1-C4 alkylsilyl; and reacting the silicon nitride precursor with a co-reactant.

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Abstract

L'invention porte sur un procédé de formation d'un film diélectrique qui consiste : à déposer un précurseur de nitrure de silicium ayant pour formule générale la formule (I), dans laquelle les lignes en pointillés représentent individuellement des liaisons facultatives, R1 sont choisi parmi un atome d'hydrogène, une amine substituée ou rien, R2 et R3 sont choisis indépendamment parmi un alkylsilyle en C1 à C4, R4 est CxHmNR5CyHn, x et y ayant indépendamment pour valeur 0 ou 1, m et n ayant indépendamment pour valeur 0, 1 ou 2 et R5 étant un alkylsilyle en C1 à C4; à faire réagir le précurseur de nitrure de silicium avec un co-réactif. L'invention concerne également un dispositif de circuit intégré qui comprend un substrat semi-conducteur; un film de nitrure de silicium sur le substrat semi-conducteur, le film de nitrure de silicium comprenant des atomes de carbone liés à plusieurs atomes d'azote.
PCT/US2016/069218 2016-12-29 2016-12-29 Procédés d'incorporation de carbone stabilisé dans des films de nitrure de silicium WO2018125141A1 (fr)

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US6455417B1 (en) * 2001-07-05 2002-09-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming damascene structure employing bi-layer carbon doped silicon nitride/carbon doped silicon oxide etch stop layer
US7893433B2 (en) * 2001-02-12 2011-02-22 Asm America, Inc. Thin films and methods of making them
US20130330482A1 (en) * 2012-06-06 2013-12-12 National Chiao Tung University Carbon-doped silicon nitride thin film and manufacturing method and device thereof
US20150024608A1 (en) * 2012-06-01 2015-01-22 Air Products And Chemicals, Inc. Organoaminodisilane Precursors and Methods for Depositing Films Comprising Same
US20160118621A1 (en) * 2013-06-21 2016-04-28 Universal Display Corporation Hybrid barrier layer for substrates and electronic devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7893433B2 (en) * 2001-02-12 2011-02-22 Asm America, Inc. Thin films and methods of making them
US6455417B1 (en) * 2001-07-05 2002-09-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming damascene structure employing bi-layer carbon doped silicon nitride/carbon doped silicon oxide etch stop layer
US20150024608A1 (en) * 2012-06-01 2015-01-22 Air Products And Chemicals, Inc. Organoaminodisilane Precursors and Methods for Depositing Films Comprising Same
US20130330482A1 (en) * 2012-06-06 2013-12-12 National Chiao Tung University Carbon-doped silicon nitride thin film and manufacturing method and device thereof
US20160118621A1 (en) * 2013-06-21 2016-04-28 Universal Display Corporation Hybrid barrier layer for substrates and electronic devices

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