WO2018125052A1 - Selective area deposition of metal layers from hetero-pentadienyl metal complex precursors - Google Patents

Abstract

Metal layers including a metal M are selectively deposited on metal surfaces via chemical vapor deposition or atomic layer deposition from a hetero-pentadienyl metal complex precursor of formula (I), wherein L is a ligand; n is 1, 2 or 3; X is NR¹, S(O)(O), S(O)(R¹)(R¹), S(R¹)(R¹), P(O)(R¹), P(R¹)(R¹)(R¹) or O; each R independently is hydrogen or a straight or branched chain C₁-C₆ alkyl; each R¹ independently is hydrogen or a straight or branched chain C₁-C₆ alkyl; and M is a first row late transition metal or a platinum group metal.

Description

SELECTIVE AREA DEPOSITION OF METAL LAYERS FROM HETERO-PENTADIENYL

METAL COMPLEX PRECURSORS

Background

[0001] In integrated circuit design, a via, or vertical interconnect access, is a small opening in an insulating layer that provides an electrical connection between different layers. Vias electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias.

Brief Description of the Drawings

[0002] The disclosure described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, features illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some features may be exaggerated relative to other features for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.

[0003] Fig. 1 is a diagram showing selectivity for metal-over-metal deposition vs. metal-over- interlayer dielectric (ILD) deposition from a hetero-pentadienyl metal complex precursor, in accordance with an implementation of the disclosure.

[0004] Fig. 2 is an interposer for use with one or more of the implementations of the disclosure.

[0005] Fig. 3 is a computing device built in accordance with implementations of the disclosure.

Detailed Description

[0006] In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

[0007] Scaling of features in integrated circuits is ever-decreasing as the drive for more capacity is ever-increasing. Integrated circuits contain electrically conductive structures, also referred to as vias, to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. Sizing and spacing of vias has progressively decreased and the trend is expected to continue. In some implementations, one measure of the size of vias is the dimension of the via opening. In implementations, one measure of the spacing of the vias is the via pitch. In implementations, via pitch represents the center-to-center distance between the closest adjacent vias.

[0008] Current methods of forming vias include lithographic processes. Lithographic methods face challenges regarding smaller features sizes. For example, extremely small via pitches are generally below the resolution capabilities of even extreme ultraviolet (EUV) lithographic scanners. Lithographic processes require the costly use of multiple masks. If via pitches continue to decrease, it may not be possible, even with the use of multiple masks, to print via openings for these extremely small pitches.

[0009] Aspects of the present disclosure address these and other deficiencies with selective area deposition of metal films or metal layers by atomic layer deposition (ALD) or chemical vapor deposition (CVD) from metal complex precursors with certain built-in structural features, such as metal complex precursor hetero-pentadienyl metal complexes of formula I, as described below. The metal complex precursor structural features enable ALD or CVD of late transition metals or platinum group metals on metallic surfaces while avoiding deposition on adjacent non- metal surfaces. Implementations described herein enable a more robust interconnect fabrication scheme, as well as enable the manufacture of other circuits or structures of an integrated circuit.

[0010] Some implementations described herein involve the fabrication of metal and via patterns based on the positions of an underlying layer. In some implementations, a metal interconnect process is effectively reversed from some top down patterning approaches and built from the previous layer up. For example, in some top down patterning approaches an interlayer dielectric (ILD) is first deposited, with a pattern for metal and via layers subsequently patterned therein. In some top down patterning approaches, alignment to a previous layer is performed using a lithography scanner alignment system followed by etching.

[0011] Implementations described herein may be used to enable electroless via bottom-up fill on non-catalytic metals and can also enable self-aligned bottom-up interconnect design.

Selective deposition of ruthenium (Ru) on tungsten (W) may be used for growth of a catalytic cap on W at the bottom of a via structure in a low-k ILD material. Selective deposition of a Ru cap on under-lying exposed W contacts through a via opening formed in a low-k ILD material using the hetero-pentadienyl metal complex precursors can be used to enable bottom-up electroless via fill.

[0012] The nature of one or more of the processes described herein (e.g., precursor type, surfaces and deposition schemes) render one or more of the approaches applicable for back end of line (BEOL) integration and self-aligned patterning schemes.

[0013] Implementations described herein enable fabrication, by selective metal deposition, of vias that are directly centered on underlying metal lines. For example, the vias may be wider than, narrower than or the same thickness as the underlying metal lines, e.g., due to non-perfect selective etch processing. In an implementation, the centers of the vias are directly aligned (match up) with the centers of the metal lines.

[0014] In implementations, approaches are provided for the deposition of various transition metals selectively on metal surfaces, while avoiding deposition on contiguous, hydrophilic and generic low-k dielectric surfaces. In one such implementation, selective metal deposition is accomplished by thermal ALD or CVD using a hetero-pentadienyl metal complex precursor optionally together with a suitable co-reactant such as a hydrogen, ammonia, hydrazine or oxygen. The selective deposition may be performed with or without pre-treatment of an adjacent or nearby low-k substrate. Pre-treatments include pre-cleaning, chemical passivation or mechanical pre-treatment.

[0015] In an implementation, the metal complex precursors are hetero-pentadienyl metal complexes of formula I:

(L)n

[0016] where

[0017] L is a ligand;

[0018] n is 1 , 2 or 3;

[0019] X is NR¹ , S(0)(0), S(0)(R¹)(R¹), S(R¹)(R¹), P(0)(R¹), P(R¹)(R¹)(R¹) or O;

[0020] each R independently is hydrogen or a straight or branched chain d-C₆ alkyl;

[0021] each R¹ independently is hydrogen or a straight or branched chain d-C₆ alkyl; and

[0022] M is a first row late transition metal atom or a platinum group metal atom.

[0023] In some implementations, first row late transition metals include manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni) or copper (Cu). In some implementations, platinum group metals include ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir) or platinum (Pt).

[0024] In an implementation, the hetero-pentadienyl metal complex may be heteroleptic, that is, where n is 1 and L is a hetero-pentadienyl ligand not identical to the hetero-pentadienyl ligand:

[0025] In another implementation, the metal complex may be homoleptic, that is, where L is an identical hetero-pentadienyl ligand and n is 1 . In an implementation, X is S(0)(0), S(0)(R¹)(R¹), S(R¹)(R¹), P(0)(R¹) or P(R¹)(R¹)(R¹) or X is NR¹.

[0026] In an implementation, ligand L may be trispyrazolyborate, ethylcyclopentadienyl, 2,4- dimethylpentadienyl, pyrrolyl, 2,2,6,6-tetramethyl-3,5-hepanedionato, cycloocta-1 ,3,5,7- tetraene, cyclohexadiene, N,N-di-t-butylacetamidinato, ethylene, hexene, cyclooctadiene, diethyl ether, tetrahydrofuran, acetonitrile, CO, NH₃ or PY₃ where each Y is independently phenyl or hydrogen or a straight or branched chain C C₆ alkyl.

[0027] In an implementation, M is Ru and X is NR¹ ; in an implementation, M is Ru and X is NR¹ where R¹ is t-butyl. This hetero-pentadienyl metal complex is of formula:

[0028] Fig. 1 illustrates a diagram 100 showing via preparation by selective metal deposition over a metal interconnect vs. over an interlayer dielectric (ILD) from a hetero-pentadienyl metal complex precursor 101 . The hetero-pentadienyl metal complex precursor 101 in this

implementation has two t-butylamino-pentadienyl ligands complexed with metal M. In one implementation, metal M is ruthenium. Hetero-pentadienyl metal complex precursor 101 encompasses the homoleptic ruthenium complex of Example 1 (described below) where each 3-position R group is methyl and other R groups are hydrogen. In implementations, the R groups of the two ligands of hetero-pentadienyl metal complex precursor 101 are not identical, providing a heteroleptic ruthenium complex. Referring to diagram 100, the top surface of integrated circuit substrate 102 is provided having exposed ILD portions 103 and an exposed interconnect metal portion 104. A hetero-pentadienyl metal complex precursor 101 is inhibited from depositing on the exposed ILD portions 103 and is encouraged to deposit on the exposed interconnect metal portion 104. In one implementation, the selective deposition is achieved without protecting or passivating either the exposed ILD portions 103 or the exposed

interconnect metal portion 104 and, as such, the deposition occurs selectively on the exposed interconnect metal portion 104 while the exposed ILD portions 103 are exposed to the metal complex precursors. In an implementation, the exposed interconnect metal portion 104 is a pure metal such as, but not limited to, copper, nickel, cobalt, manganese, ruthenium, molybdenum or tungsten, or a conductive metal containing such as, but not limited to, titanium nitride, vanadium nitride or tungsten nitride. In diagram 100, a via 105 comprising metal M, in this implementation ruthenium, is formed on the metal interconnect portion 104 as shown, to provide a surface of an integrated circuit with exposed ILD portions and a via comprising metal M formed on an exposed interconnect metal portion. In an implementation, circuit structure 106 is part of an integrated circuit. In implementations, the via 105 may contain some residual heteroatom nitrogen and/or carbon originating from the hetero-pentadienyl metal complex precursor 101. Implementations disclosed herein are applied to electrical vias for purposes of illustration, and not limitation. It may be noted that the implementations described herein may be applied to a wide variety of different types of integrated circuits, microelectronic devices, and other substrate surfaces, circuits, and circuit structures in the aforementioned.

[0029] In implementations, a method of depositing a metal M on a substrate surface, the method comprising providing a substrate surface and depositing the metal M from a hetero- pentadienyl metal complex of formula I is disclosed.

[0030] In an implementation, depositing the metal M forms a layer comprising metal M. In an implementation the layer comprising metal M is from about 1 nm to about 150 nm thick.

[0031] Bulky R¹ and/or R group substituents of the metal complex of formula I, such as t-butyl, may protect the metal center from direct undesirable reactions with an adjacent or nearby dielectric surface by providing an effective hydrophobic pocket. The selectivity for metal surfaces is achieved by direct interaction of the hetero-pentadienyl ligand with the conducting sea of electrons on the metal surface. Straight or branched chain alkyl includes methyl, ethyl, n- propyl, i-propyl, n-butyl, i-butyl, t-butyl, n-pentyl, t-pentyl, neopentyl, i-pentyl, sec-pentyl, 3- pentyl, n-hexyl, 2-methylpentyl, 3-methylpentyl, 2-ethylbutyl, 3-ethylbutyl, 2,3-dimethylbutyl or ethylpropyl.

[0032] In an implementation, as is also used throughout the present description, interconnect material, such as the material of metal lines, comprises one or more metals or other conductive structures. Copper lines or structures may or may not include barrier layers between the copper and surrounding ILD material. As used herein, the term metal includes alloys, stacks and other combinations of multiple metals. Metal interconnect lines may include barrier layers, stacks of different metals or alloys, etc. Interconnect lines are also sometimes referred to in the arts as traces, wires, lines, metal or simply interconnect.

[0033] In an implementation, the metal surface or interconnect (exposed metal surface) on which deposition occurs may comprise copper (Cu), nickel (Ni), cobalt (Co), manganese (Mn), ruthenium (Ru), molybdenum (Mb) or tungsten (W).

[0034] In an implementation, as used throughout the present description, interlayer dielectric (ILD) material, such as the material of interlayer dielectric lines, comprises a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (Si0₂)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, organosilicate glass or combinations thereof. The ILD layers may include pores or air gaps to further reduce their dielectric constant. The interlayer dielectric material may be formed by conventional techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or by other deposition methods.

[0035] In an implementation, depositing the metal M forms a layer comprising metal M and one or more nitrogen (N), oxygen (O), phosphorous (P) or sulfur (S) heteroatoms. In an

implementation, depositing the metal M forms a layer comprising metal M and one or more N, S or P heteroatoms.

[0036] Final via interconnect structures may comprise detectable discrete layers of the first row late transition metals or platinum group metals, such as chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), ruthenium (Ru), rhodium (Rh), platinum (Pt) or palladium (Pd). Standard microscopic or spectroscopic analysis techniques may be used to detect the layers (e.g. scanning electron microscopy (SEM), transmission electron microscopy (TEM), X-ray photoelectron spectroscopy (XPS), atomic emission spectroscopy (AES), energy dispersive spectroscopy (EDS), electron energy loss spectroscopy (EELS), etc.) at the bottom of an via interconnect structure along with their absence in an adjacent dielectric surface.

[0037] In some implementations, the present methods may result in low levels of carbon present in the deposited metal layers. In an implementation, the deposited metal layers comprise less than or equal to 9.7, less than or equal to 9.0, less than or equal to 8.0, less than or equal to 7.0, less than or equal to 6.0, less than or equal to 5.0, less than or equal to 4.0, less than or equal to 3.0, less than or equal to 2.0 or less than or equal to 1 .0 percent by weight carbon, based on the total weight of the deposited metal layer. The deposited metal layers may contain carbon from about 0.01 or from about 0.2 to about 9.7 weight percent, based on the total weight of the final deposited metal layer. Carbon present in the layer comprising metal M may originate from the hetero-pentadienyl ligand. [0038] In some implementations, the present methods may result in low levels of the presence of one or more nitrogen (N), oxygen (O), phosphorus (P) or sulfur (S) heteroatoms being present in the final deposited metal layer, which may originate from the hetero-pentadienyl ligand. The deposited metal layer may comprise from about 0.3, about 0.5, about 0.8, about 1 .0 or about 2.0 to about 3.0, about 4.0, about 5.0, about 6.0, about 7.0, about 8.0, about 9.0 or about 9.9 weight percent of one or more N, O, P and S atoms, based on the total weight of the deposited metal layer. In an implementation, depositing the metal M forms a layer which comprises greater than or equal to 90 weight percent metal M.

[0039] In implementations, metal layers may be formed on or above an underlying

semiconductor substrate or structure (not shown), such as underlying device layer(s) of an integrated circuit. A substrate, such as a semiconductor substrate, may be used to manufacture integrated circuits. The semiconductor substrate may include a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include single crystal silicon, polycrystalline silicon or silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The semiconductor substrate, depending on the stage of manufacture, often includes transistors, integrated circuitry and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants and other materials commonly found in semiconductor substrates. Furthermore, the structure may be fabricated on underlying lower level interconnect layers.

[0040] In an implementation, metal M is deposited from a hetero-pentadienyl metal complex of formula I where M is a first row late transition metal atom or a platinum group metal atom. In an implementation, metal M is Mn, Fe, Co, Ni or Cu or is Ru, Rh, Pd, Os, Ir or Pt.

[0041] In an implementation of the present methods, metal M in the hetero-pentadienyl metal complex precursor is Ru and X is NR¹. In an implementation, M is Ru and X is N(t-butyl). In an implementation, the hetero-pentadienyl metal complex precursor is homoleptic where each X is

N(t-butyl).

[0042] In an implementation, the deposition is performed at a temperature of from about 150°C (degree Celsius) to about 500 °C. In an implementation, the deposition is performed at a temperature of from about 200 °C to about 450 °C.

[0043] In an implementation, the substrate surface comprises one or more metal regions and one or more non-metal regions where the metal M is selectively deposited on the metal regions. In an implementation, the weight ratio of the metal M deposited on the metal regions to that of the metal M deposited on the non-metal regions is greater than or equal to 20. In an

implementation, the weight ratio of the metal M deposited on the metal regions to that of the metal M deposited on the non-metal regions is greater than or equal to 30. In an

implementation, the weight ratio of the metal M deposited on the metal regions to that of the metal M deposited on the non-metal regions is greater than or equal to 40. [0044] In an implementation, the present metal deposition methods comprise fabrication of a via interconnect structure of an integrated circuit. In an implementation, a method of fabricating a via interconnect structure for an integrated circuit comprises forming a plurality of metal contacts in a dielectric layer to provide exposed regions of the dielectric layer and exposed regions of the metal contacts. The method also comprises forming, using a selective metal atomic layer deposition (ALD) or chemical vapor deposition (CVD) process, a metal layer on the exposed regions of the metal contacts without forming the metal layer on the exposed regions of the dielectric layer. The metal contacts may include tungsten (W).

[0045] In an implementation, disclosed is an integrated circuit comprising a dielectric material; an interconnect disposed within the dielectric material; and a via over the interconnect; where the via comprises a metal M and one or more heteroatoms, where the metal M is a first row late transition metal or a platinum group metal and the one or more heteroatoms are at least one of nitrogen (N), oxygen (O), phosphorous (P) or sulfur (S) atoms. In an implementation, the via comprises one or more N, P or S heteroatoms. Presence of the heteroatoms in the via may originate from the hetero-pentadienyl metal complex precursor.

[0046] In an implementation, the interconnect comprises a metal such as copper (Cu), nickel (Ni), cobalt (Co), manganese (Mn), ruthenium (Ru), molybdenum (Mb) or tungsten (W). In an implementation, the metal M is manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir) or platinum (Pt).

[0047] In some implementations, the processes provide for deposition of metal layers containing high levels of the desired metal. In an implementation, the via comprises greater than or equal to 90 weight percent metal M. In an implementation, the via comprises from about 0.3 to about 9.9 weight percent of the heteroatoms or from about 0.5 to about 6.0 weight percent of the heteroatoms.

[0048] In an implementation, the via comprises metal M, the one or more heteroatoms and carbon. In an implementation, the via comprises from about 0.01 to about 9.7 weight percent carbon. In an implementation, the via comprises from about 0.01 to about 7.0 weight percent carbon. Presence of carbon in the via may originate from the hetero-pentadienyl metal complex precursor.

[0049] In an implementation, the dielectric material comprises silicon dioxide or a low-k dielectric material. The weight ratio of metal M over the interconnect to that of metal M over the dielectric material may be greater than or equal to 20. In an implementation, the weight ratio of metal M over the interconnect to that of metal M over the dielectric is greater than or equal to 30. In an implementation, the weight ratio of metal M over the interconnect to that of metal M over the dielectric is greater than or equal to 40.

[0050] In an implementation, the metal M is Ru. In an implementation, the metal M is Ru and the heteroatom is N. In an implementation, the via is from about 1 nm to about 150 nm thick. [0051] In an implementation, disclosed is a method for the preparation of a hetero-pentadienyl metal complex of formula I:

(L)n where L is a ligand; n is 1 , 2 or 3; X is NR¹ , S(0)(0), S(0)(R¹)(R¹), S(R¹)(R¹), P(0)(R¹), P(R¹)(R¹)(R¹) or O; each R independently is hydrogen or a straight or branched chain C C₆ alkyi; each R¹ independently is hydrogen or a straight or branched chain C C₆ alkyi; and M is a first row late transition metal or a platinum group metal; the method comprising preparing a hetero-pentadienyl ligand of formula la:

forming a salt of the hetero-pentadienyl ligand; reacting a metal-halogen compound with the hetero-pentadienyl ligand salt to form a hetero-pentadienyl metal complex and purifying the hetero-pentadienyl metal complex. Purification comprises removal of complexed organics. Removal of organics may be performed under reduced pressure. Purification comprises sublimation.

[0052] Fig. 2 illustrates an interposer device 200 according to implementations. In an implementation, device 200 is an integrated circuit comprising a via 105 over an interconnect 208 disposed within a dielectric material. It may be noted that one or more vias of interposer device 200 may be formed using one or more implementations of the present disclosure, Device 200 is an intervening substrate used to bridge a first substrate 202 to a second substrate 204. The first substrate 202 may be an integrated circuit die. The second substrate 204 may be a memory module, a computer motherboard or another integrated circuit die. Generally, the purpose of interposer device 200 is to spread a connection to a wider pitch or to reroute a connection to a different connection. Device 200 may couple an integrated circuit die 202 to a ball grid array (BGA) 206 that can subsequently be coupled to the second substrate 204. In some implementations, the first and second substrates 202/204 are attached to opposing sides of the interposer 200. In other implementations, the first and second substrates 202/204 are attached to the same side of interposer device 200. And in further implementations, three or more substrates are interconnected by way of device 200.

[0053] The interposer device 200 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material or a polymer material such as polyimide. In further

implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium and other group lll-V and group IV materials.

[0054] Interposer device 200 may include metal interconnects 208 and vias 105, including but not limited to through-silicon vias (TSVs) 212. The interposer device 200 may further include embedded devices 214, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors and MEMS devices may also be formed on the interposer device 200.

[0055] In accordance with implementations of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of the interposer device 200 and/or may be interfaced directly with device 200.

[0056] Fig. 3 illustrates a computing device 300 built in accordance with implementations of the disclosure. The computing device 300 may include a number of components. In one implementation, these components are attached to one or more motherboards. In an alternate implementation, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as an SoC used for mobile devices. The components in the computing device 300 include, but are not limited to, an integrated circuit 302 according to an implementation and at least one communications logic unit 308. In some implementations the communications logic unit 308 is fabricated within the integrated circuit 302 while in other implementations the communications logic unit 308 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit 302. The integrated circuit 302 may include a processor 304 (e.g., central processing unit (CPU)) as well as on-die memory 306, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM), SRAM or spin-transfer torque memory (STT-MRAM). It may be noted that, in certain implementations, the integrated circuit 302 may include fewer elements (e.g., without the processor 304 and/or on-die memory 306) or additional elements other than the processor 304 and on-die memory 306. In one

implementation, integrated circuit 302 may include one or more micro light emitting diode (LED) arrays 305 with or without the processor 304 and/or on-die memory 306. In another implementation, integrated circuit 302 may be a part of a micro LED-based display device with multiple micro LED arrays 305 and a thin film transistor (TFT) backplane, with or without the processor 304 and/or on-die memory 306. In another example, the integrated circuit 302 may include some or all the elements described herein, as well as include additional elements. It may be noted that in implementations, that some or all the elements (e.g., LED 305, processor 304, or memory 306) of integrated circuit 302 may include circuit structure 106, as described herein.

[0057] Computing device 300 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 310 (e.g., DRAM), non-volatile memory 312 (e.g., ROM or flash memory), a graphics processing unit 314 (GPU), a digital signal processor 316, a crypto processor 342 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 320, an antenna 322 (in some

implementations two or more antenna may be used), a display or a touchscreen display 324 (e.g., incorporating one more arrays of the micro LEDs disclosed herein), a touchscreen controller 326, a battery 330 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 328 (which may further include a compass), a motion coprocessor or sensors 332 (that may include an accelerometer, a gyroscope and a compass), a microphone (not shown), a speaker 334, a camera 336, user input devices 338 (such as a keyboard, mouse, stylus and touchpad) and a mass storage device 340 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD) and so forth). The computing device 300 may incorporate further transmission, telecommunication or radio functionality not already described herein. In some implementations, the computing device 300 includes a radio that is used to communicate over a distance by modulating and

radiating electromagnetic waves in air or space. In further implementations, the computing device 300 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.

[0058] The communications logic unit 308 enables wireless communications for the transfer of data to and from the computing device 300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some implementations they might not. The communications logic unit 308 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.1 1 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G and beyond. The computing device 300 may include a plurality of communications logic units 308. A first communications logic unit 308 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC and Bluetooth and a second communications logic unit 308 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and others.

[0059] The processor 304 (also referred to "processing device" herein) of the computing device 300 includes one or more devices, such as transistors, RF filters, or LEDs, that are formed in accordance with implementations of the present disclosure. The term "processor" or

"processing device" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. Processor 304 represents one or more general- purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processor 304 may be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processor 304 may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like.

[0060] The communications logic unit 308 may also include one or more devices, such as transistors, RF filters, or LEDs, that are formed in accordance with implementations of the present disclosure.

[0061] In further implementations, another component housed within the computing device 300 may contain one or more devices, such as transistors, RF filters, or LEDs, that are formed in accordance with implementations of the present disclosure.

[0062] In various implementations, the computing device 300 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 300 may be any other electronic device that processes data.

[0063] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

[0064] Various operations are described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

[0065] Implementations disclosed herein may be used in the manufacture of a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers and the like. In other implementations, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. A processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory and the chipset, may potentially be manufactured using the approaches disclosed herein.

[0066] Any ranges cited herein are inclusive. The term "about" used throughout is used to describe and account for small fluctuations. The term "about" may mean the numeric value may be modified by ±5%, ±4%, ±3%, ±2%, ±1 %, ±0.5%, ±0.4%, ±0.3%, ±0.2%, ±0.1 % or ±0.05%. All numeric values are modified by the term "about" whether or not explicitly indicated. Numeric values modified by the term "about" include the identified value; that is "about 5.0" includes 5.0. Measureable levels of atoms, elements or molecules may depend on the method of detection. In part, the term "about" is intended to provide for this.

[0067] The terms "over," "above" "under," "between," and "on" as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed above or over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

[0068] The words "example" or "exemplary" are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "example' or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the words "example" or "exemplary" is intended to present concepts in a concrete fashion. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless specified otherwise, or clear from context, "X includes A or B" is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then "X includes A or B" is satisfied under any of the foregoing instances. In addition, the articles "a" and "an" as used in this application and the appended claims may generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. Moreover, use of the term "an

implementation" or "one implementation" or "an implementation" or "one implementation" throughout is not intended to mean the same implementation or implementation unless described as such. The terms "first," "second," "third," "fourth," etc. as used herein are meant as labels to distinguish among different elements and may not necessarily have an ordinal meaning according to their numerical designation.

[0069] Unless otherwise indicated, all parts and percentages are by weight.

[0070] Implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V or group IV materials.

Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure.

[0071] A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the disclosure, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the disclosure may also be carried out using nonplanar transistors.

[0072] Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (Si0₂) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some implementations, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

[0073] The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

[0074] For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

[0075] In some implementations, when viewed as a cross-section of the transistor along the source-channel-drain direction, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[0076] In some implementations of the disclosure, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0077] In implementations, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions may be formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion- implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further implementations, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy. In further implementations, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

[0078] In other implementations, one or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (Si0₂), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

Examples

[0079] Example 1 Preparation of Ru(t-butyl-N-pentadienyl)₂

[0080] A 3-4 g mixture of MgS0₄ and 3-methylcrotonaldehyde (1 eq.; -10 g) in 200 mL dry methylene chloride is cooled to 0°C under a N₂ atmosphere. To the flask, t-butylamine (1 .1 eq.) is added dropwise over 20 minutes using a syringe. The reaction is left in the ice bath and allowed to slowly warm up to room temperature overnight (16 h). The reaction mixture is filtered through a frit in a glovebox and the solvent and all volatiles are removed under vacuum (4 h). The ligand is not volatile under vacuum at room temperature. The product is collected as a viscous yellow oil and stored over molecular sieves (4 A) overnight; yield of t- butylazapentadiene is 95%.

[0081] ¹ H NMR (400 MHz, 293 K, CD₂CI₂): δ 8.20 (d, 1 H, ³J_HH = 8.2 Hz, N=CH); 6.27 (d, 1 H, ³JHH = 8.2 Hz, C=CH), 1 .59 (s, 3H, CH₃); 1 .53 (s, 3H, CH₃); 1 .22 (s, 9H, t-bu).

[0082] A 2-3 g sample of t-butylazapentadiene is dissolved in THF (150 mL) and cooled to minus 78°C under N₂. In a separate Schlenk flask, potassium bis(trimethylsilyl)amide (KHMDS) is dissolved in THF (150 mL) is stirred at room temperature and transferred dropwise via cannula (over 20 min) to the cold t-butylazapentadiene flask. The reaction mixture gradually becomes orange and a precipitate is observed. After complete addition of KHMDS, the reaction mixture is allowed to stir at minus 78°C for 2 h. The cold bath is then removed and the flask is allowed to warm up slowly to room temperature and stir for another 2 h upon which all precipitate goes into solution. The solution color becomes red. The solvent is removed under vacuum and the crude solid is washed with hexane giving a dark yellow-orange solid; yield 65%.

[0083] ¹ H NMR (400 MHz, 293 K, THF-d₈): δ 7.74 (d, 1 H, J_HH = 12.3 Hz, N=CH); 4.84 (d, 1 , J_HH = 12.3 Hz, C=CH); 3.95 (br s, 1 H, =CH₂); 3.56 (br s, 1 H, =CH₂); 1 .96 (s, 3H, CH₃), 1 .29 (s, 9H, t- bu).

2 eq.

[0084] Two equivalents of the deprotonated ligand (2.2 eq.; 2 - 3 g) are dissolved in THF (150 mL) and stirred at room temperature on a Schlenk line. In a separate flask, mixture of dichloro(1 ,5-cyclooctadiene)ruthenium(ll), polymer (Ru(COD)CI₂ polymer) in THF (100 mL) is cooled to -78°C under N₂. A THF solution of the deprotonated ligand is transferred dropwise over 20 minutes via cannula to the Ru flask. The reaction is left in the -78^ cold bath and allowed to warm up to room temperature overnight without removing the cold bath. The solvent is removed to provide a brown oil. The product is extracted with hexane and filtered giving a pale yellow solid Ru(COD)(t-butyl-A/-pentadienyl)₂; yield 54%.

[0085] ¹ H NMR (400 MHz, 293 K, C₆D₆): 5 7.83 (d, 1 H, ³J_HH = 9.10 Hz, N=CH); 3.99 (d, 1 H, ³J_Hh = 9.10 Hz, C=CH); 3.64 (m, 1 H, COD), 3.35 (m, 1 H, COD), 2.50 (m, 1 H, COD), 2.01 (m, 1 H, COD), 1 .74 (s, 1 H, =CH₂), 1 .66 (s, 3H, CH₃), 1 .34 (s, 9H, t-bu), 0.27 (s, 1 H, =CH₂).

[0086] The pale yellow Ru(COD)(t-butyl-N-pentadienyl)₂ solid is loaded into a sublimator and heated at 70 °C under dynamic vacuum for 16 h. An orange solid is collected on the cold finger and characterized as Ru(t-butyl-A/-pentadienyl)₂. A mixture of isomers is collected; yield = 52%.

[0087] ¹ H NMR is reported for major isomer of the complex: (400 MHz, 293 K, C₆D₆): δ 6.21 (d, 1 H, JHH = 3.81 Hz, N=CH); 2.99 (br s, 1 H, C=CH₂); 2.84 (br s, 1 H, C=CH); 2.19 (br s, 1 H, C=CH₂); 1 .57 (s, 3H, CH₃); 1 .37 (s, 9H, t-bu).

[0088] ¹³C{¹ H} NMR (100 MHz, 293 K, C₆D₆): δ 1 19.4 (N=CH); 102.2 (C=CH); 69.3 (C=CH); 55.8 (t-bu); 50.5 (C=CH₂); 31 .3 (t-bu), 25.9 (CH₃).

[0089] Example 2 Chemical Vapor Deposition The Ru(t-butyl-N-pentadienyl)₂ complex prepared according to Example 1 is placed in a stainless steel ampoule and heated at 200 °C using a reactive carrier gas facilitating vaporization of the metal complex and combustion of the ligand. Ruthenium is deposited on patterned substrates consisting of metal and ILD at growth rate of greater than or equal to 90nm/h, yielding 95% and higher pure Ru metal films on the metal surface with deposition selectivity of 40:1 on the metal vs. ILD surface.

Claims

CLAIMS What is claimed is:

1. An integrated circuit comprising:

a dielectric material;

an interconnect disposed within the dielectric material; and

a via over the interconnect, wherein

the via comprises a metal M and one or more heteroatoms, wherein

the metal M is a first row late transition metal or a platinum group metal, and wherein the one or more heteroatoms are at least one of nitrogen (N), oxygen (O), phosphorous (P) or sulfur

(S) atoms.

2. The integrated circuit of claim 1 , wherein the interconnect comprises copper (Cu), nickel (Ni), cobalt (Co), manganese (Mn), ruthenium (Ru), molybdenum (Mb) or tungsten (W).

3. The integrated circuit of claim 1 , wherein the via comprises one or more heteroatoms comprising at least one of N, P or S.

4. The integrated circuit of claim 1 , wherein the metal M is manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir) or platinum (Pt).

5. The integrated circuit of claim 1 , wherein the via comprises greater than or equal to 90 weight percent metal M.

6. The integrated circuit of any of claims 1 to 5, wherein the via comprises from about 0.3 to about 9.9 weight percent of the one or more heteroatoms.

7. The integrated circuit of any of claims 1 to 5, wherein the via comprises from about 0.01 to about 9.7 weight percent carbon.

8. The integrated circuit of any of claims 1 to 5, wherein the via comprises the metal M, the one or more heteroatoms and carbon.

9. The integrated circuit of any of claims 1 to 5, wherein the dielectric material comprises silicon dioxide or a low-k dielectric material.

10. The integrated circuit of any of claims 1 to 5, wherein the weight ratio of the metal M over the interconnect to that of the metal M over the dielectric material is greater than or equal to 20.

11. The integrated circuit of any of claims 1 to 5, wherein the weight ratio of the metal M over the interconnect to that of the metal M over the dielectric material is greater than or equal to 30.

12. The integrated circuit of any of claims 1 to 5, wherein the metal M is Ru.

13. The integrated circuit of any of claims 1 to 5, wherein the metal M is Ru and the heteroatom is N.

14. The integrated circuit of any of claims 1 to 5, wherein the via is from about 1 nm to about 150 nm thick.

15. A method of depositing a metal M on a substrate surface comprising:

providing a substrate surface; and

depositing the metal M from a hetero-pentadienyl metal complex of formula I:

(L)n wherein

L is a ligand;

n is 1 , 2 or 3;

X is NR¹ , S(0)(0), S(0)(R¹)(R¹), S(R¹)(R¹), P(0)(R¹), P(R¹)(R¹)(R¹) or O;

each R independently is hydrogen or a straight or branched chain C C₆ alkyl;

each R¹ independently is hydrogen or a straight or branched chain C C₆ alkyl; and

M is a first row late transition metal or a platinum group metal; to form a layer comprising metal M on the substrate surface.

16. The method of claim 15, wherein the substrate surface comprises a metal region and a non-metal region and wherein the metal M is selectively deposited on the metal region rather than the non-metal region by using the hetero-pentadienyl metal complex, such that the weight ratio of the metal M deposited on the metal region to that of the metal M deposited on the non- metal region is greater than or equal to 20.

17. The method of claim 16, wherein the non-metal region comprises silicon dioxide or a low-k dielectric material.

18. The method of any of claims 15 to 17, wherein the substrate surface comprises copper, nickel, cobalt, manganese, ruthenium, molybdenum or tungsten.

19. The method of any of claims 15 to 17, wherein depositing the metal M comprises chemical vapor deposition or atomic layer deposition.

20. The method of any of claims 15 to 17, wherein the deposition is performed at a temperature of from about 150°C to about 500 °C.

21. The method of any of claims 15 to 17, wherein the deposition is performed using a hydrogen, ammonia, hydrazine or oxygen co-reactant.

22. The method of any of claims 15 to 17, wherein the substrate surface is not pre-treated prior to depositing the metal M.

23. A hetero-pentadienyl metal complex of formula I:

(L) n wherein

L is a ligand; n is 1 , 2 or 3;

X is NR¹ , S(0)(0), S(0)(R¹)(R¹), S(R¹)(R¹), P(0)(R¹), P(R¹)(R¹)(R¹) or O;

each R independently is hydrogen or a straight or branched chain C C₆ alkyl;

each R¹ independently is hydrogen or a straight or branched chain C C₆ alkyl; and

M is a first row late transition metal or platinum group metal.

24. The hetero-pentadienyl metal complex of claim 23, wherein M is Mn, Fe, Co, Ni, Cu, Ru, Rh, Pd, Os, Ir or Pt.

25. The hetero-pentadienyl metal complex of claims 23 or 24, wherein M is Ru and X is NR¹.