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WO2018103045A1 - Système, dispositif et procédé de création de point de contrôle - Google Patents

Système, dispositif et procédé de création de point de contrôle Download PDF

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Publication number
WO2018103045A1
WO2018103045A1 PCT/CN2016/109053 CN2016109053W WO2018103045A1 WO 2018103045 A1 WO2018103045 A1 WO 2018103045A1 CN 2016109053 W CN2016109053 W CN 2016109053W WO 2018103045 A1 WO2018103045 A1 WO 2018103045A1
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Prior art keywords
process number
test program
simulator
manager
test
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PCT/CN2016/109053
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English (en)
Chinese (zh)
Inventor
张传德
王金堂
张海勇
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华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201680080529.6A priority Critical patent/CN108604205B/zh
Priority to PCT/CN2016/109053 priority patent/WO2018103045A1/fr
Publication of WO2018103045A1 publication Critical patent/WO2018103045A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment

Definitions

  • the embodiments of the present invention relate to the field of computers, and in particular, to a method, an apparatus, and a system for creating a test point.
  • An emulator is a program that simulates the functions of a hardware processor and the instruction system through software to obtain a predicted output based on a specific input.
  • the simulator typically includes a functional simulator and a performance simulator.
  • the function simulator is used to achieve the correctness of the processor function, and the performance simulator is used to achieve test data output for performance and efficiency.
  • the simulator performance test is a method of running a standard checker on the simulator and getting test results to measure the performance of the simulator itself and whether the hardware parameter settings are reasonable.
  • the function simulator test is generally performed first, and then the performance simulator test is performed. After running a basic block on the function simulator, the instruction block is sent to the performance simulator for running.
  • a checkpoint is generally created to create a checkpoint at a fixed time or instruction execution interval.
  • the function simulator warms up with the performance simulator for a period of time to fill in the data in the performance simulator, and then performs the checkpoint creation process to generate the checkpoint data. This only needs to run the benchmark test program completely and create a series of checkpoints.
  • the performance simulator and function simulator can use the checkpoint data to restore the running state and execute some instruction block instructions. You can implement the benchmark test. Checkpoint can greatly shorten the test time and improve the test speed.
  • the present invention discloses a method and apparatus for creating a test point, ensuring that the created checkpoint is related to the benchmark, thereby improving the accuracy of the test result.
  • the present application provides a method for creating a test point.
  • the simulator includes a function simulator, a performance simulator, and a manager.
  • the method includes: the manager reads the T1 process number recorded in the process number register at the first time. And determining that the process indicated by the T1 process number is used to execute the test program, wherein the process number register holds the process number of the running process of the function simulator, and the manager sends at least one instruction block after the function simulator is run to the performance
  • the simulator executes, the manager reads the T2 process number recorded in the process number register at the second time, and determines that the process indicated by the T2 process number is used to execute the test program, and then the manager creates the test point and records the test point data, wherein
  • the test point data contains the snapshot of the function simulator and status information of the performance simulator.
  • the manager confirms that the process running by the function simulator is the test program process, and then the test points are created, thus ensuring that the test point data is related to the test program, ensuring the accuracy of subsequent tests. Sex.
  • the method before the first time, further includes: the manager reads and records the process number register when the function simulator is first detected to execute the test program.
  • the root process number of the record, the process executing the test program is the root process indicated by the root process number or the descendant process of the root process; the manager determines the process indicated by the T1 process number according to the root process number and the interprocess relationship maintained by the function simulator
  • the test program is executed, and according to the root process number and the interprocess relationship maintained by the function simulator, it is determined that the process indicated by the T2 process number is used to execute the test program.
  • the manager can determine whether a process is a test program process according to the inter-process relationship maintained by the function simulator and the root process of the test program, thereby verifying whether the process running by the function simulator is related to the test program, and creating a checkpoint under relevant circumstances. .
  • the method further includes: the inter-process relationship maintained by the manager according to the root process number and the function simulator Determining a test program process number set, the test program process number set containing the process number of the process for executing the test program; the manager determining that the process indicated by the T1 process number is used to execute the test program includes: the manager determines the T1 process number or the T1 process The parent process number of the number belongs to the test program process number set; the manager determines that the process indicated by the T2 process number is used to execute the test program includes: the manager determines that the parent process number of the T2 process number or the T2 process number belongs to the test program process number set.
  • the manager determines the test program process number set according to the inter-process relationship and the root process. When verifying whether a process belongs to the test program process, it only needs to see whether the process number of the process belongs to the test program.
  • the set of the program number, if it belongs, indicates that the test program process, if not, further determines whether the process is a test program process according to the interprocess relationship and the process number maintained by the function simulator, so that each verification process is not required Checking the interprocess relationship simplifies the verification process.
  • the method further includes: if the T1 process number does not belong to the test program process number set, the manager The T1 process number is added to the test program process number set; if the T2 process number does not belong to the test program process number set, the manager adds the T2 process number to the test program process number set.
  • the test program process number set is refreshed in real time. Further, if the parent process number of the T1 process number does not belong to the test program process number set, the manager also adds the parent process number of the T1 process number to the test program process. Number set; if the parent process number of the T2 process number does not belong to the test program process number set, the manager also adds the parent process number of the T2 process number to the test program process number set.
  • the test program includes the instruction instruction, and the manager detects the function simulator to execute the test program for the first time.
  • the root process number of the process number register record is read and recorded.
  • the manager reads the process number register after detecting the instruction instruction, and records the root process number recorded by the process number register.
  • the manager can monitor each instruction of the test program through the function simulator, and implement the test program by adding an instruction instruction to the test program.
  • the monitoring more specifically, the instruction instruction can be added at the beginning of the test program, at which time the process executing the test program is the root process, and the subsequent execution of the test program is the root process or the descendant process of the root process.
  • the inter-process relationship maintained by the function simulator is a proc in an operating system running on the function simulator Directory, the proc directory records the relationship between each thread and the parent process of each thread.
  • the parent process ID (PPID) of the parent process of the process is recorded in the /proc/pid/stat file of each process. According to the proc directory, you can get a process number tree with the root process number as the root node to describe the relationship between the test program processes.
  • the present application provides a readable medium, comprising: executing instructions, when the processor of the computing device executes the execution instruction, the computing device performs any of the first aspect or the first aspect The method in the implementation.
  • the present application provides a computing device, including: a processor, and a a memory and a bus; a memory for storing execution instructions, the processor and the memory being connected by a bus, and when the computing device is running, the processor executing the memory stored execution instructions to cause the computing device to perform the above first aspect or the first aspect A method in a possible implementation.
  • the application provides a device for creating a test point
  • the simulator includes a function simulator and a performance simulator
  • the device includes: a reading unit, configured to read the T1 process recorded by the process number register at the first time No., wherein the process number register holds the process number of the running process of the function simulator; the determining unit: the process for determining the T1 process number indication is used to execute the test program; and the scheduling unit is configured to run the function simulator At least one instruction block is sent to the performance simulator for execution; the reading unit is further configured to read the T2 process number recorded by the process number register at a second time; the determining unit is further configured to determine that the process indicated by the T2 process number is used to execute the test program Create a unit to create a test point and record test point data, where the test point data contains a snapshot of the function simulator and status information of the performance simulator.
  • the reading unit is further configured to: read and record the process number register record when the function simulator is first detected to execute the test program
  • the root process number, the process executing the test program is the root process indicated by the root process number or the descendant process of the root process
  • the determining unit is configured to determine the process indicated by the T1 process number according to the root process number and the interprocess relationship maintained by the function simulator Used to execute the test program and used to determine the process indicated by the T2 process number to execute the test program based on the root process number and the interprocess relationship maintained by the function simulator.
  • the determining unit is further configured to determine, according to the root process ID and the inter-process relationship maintained by the function simulator a test program process number set, the test program process number set includes a process number of a process for executing the test program; the determining unit is configured to determine a process indicated by the T1 process number for executing the test program, including: the determining unit is configured to determine the T1 process number or The parent process number of the T1 process number belongs to the test program process number set; the determining unit is configured to determine that the process indicated by the T2 process number is used to execute the test program, including: determining that the parent process number of the T2 process number or the T2 process number belongs to the test Program process number collection.
  • the determining unit is further configured to use the T1 process. The number is added to the test program process number set; if the T2 process number does not belong to the test program process number set, the determining unit is also used to add the T2 process number to the test program process number set.
  • the test program includes the instruction instruction, and the reading unit is configured to detect the function for the first time.
  • the simulation executes the test program, the root process number of the process number register record is read and recorded.
  • the read unit is configured to read the process number register after the instruction instruction is detected, and record the root process number recorded by the process number register.
  • the inter-process relationship maintained by the function simulator is a proc in an operating system running on the function simulator Directory, the proc directory records the relationship between each thread and the parent process of each thread.
  • the fourth aspect is the device implementation manner corresponding to the method of the first aspect, and the description in the first aspect or any possible implementation manner of the first aspect corresponds to the fourth aspect or any possible implementation manner of the fourth aspect, This will not be repeated here.
  • the present application provides a test point creation system including a function simulator, a manager and a performance simulator, a function simulator for functional simulation of the processor, and a performance simulator for performance simulation of the processor,
  • the manager is configured to read the T1 process number recorded by the process number register at the first time, and determine that the process indicated by the T1 process number is used to execute the test program, wherein the process number register holds the process number of the process that the function simulator is running.
  • the manager before the first time, is further configured to: when the function simulator is first detected to execute the test program, read and record the process number register record.
  • the root process number, the process executing the test program is the root process indicated by the root process number or the descendant process of the root process; the manager is used to determine the process indicated by the T1 process number according to the root process number and the interprocess relationship maintained by the function simulator.
  • the test program is executed; the manager is configured to determine the process indicated by the T2 process number to execute the test program according to the root process number and the interprocess relationship maintained by the function simulator.
  • the manager is further configured to determine, according to the root process number and the inter-process relationship maintained by the function simulator
  • the test program process number set, the test program process number set contains the process number of the process for executing the test program; the manager is used to determine the process indicated by the T1 process number for executing the test program, including: the manager is used to determine the T1 process number or the T1 process The parent process number of the number belongs to the test program process number set; the manager is used to determine the process indicated by the T2 process number for executing the test program including: the manager is used to confirm The parent process number of the T2 process number or T2 process number belongs to the test program process number set.
  • the manager is further configured to use the T1 process.
  • the number is added to the test program process number set; if the T2 process number does not belong to the test program process number set, the manager is also used to add the T2 process number to the test program process number set.
  • the test program includes the instruction instruction, and the manager is configured to read the process ID after detecting the instruction instruction. Register and record the root process number of the process number register record.
  • the inter-process relationship maintained by the function simulator is a proc in an operating system running on the function simulator Directory, the proc directory records the relationship between each thread and the parent process of each thread.
  • the fifth aspect is the apparatus implementation manner corresponding to the method of the first aspect, and the description in the first aspect or any possible implementation manner of the first aspect is applicable to any possible implementation manner of the fifth aspect or the fifth aspect, This will not be repeated here.
  • test program process runs on the function simulator at the beginning and the end of the warm-up phase, thereby ensuring that the created checkpoints are all related to the test program, and the other process pairs are reduced.
  • Checkpoint data interference which can improve the accuracy of the benchmark test.
  • FIG. 1 is a schematic diagram showing the logical structure of a simulator system according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a host computer according to an embodiment of the invention.
  • FIG. 3 is a scene diagram of a simulator warm-up phase according to an embodiment of the invention.
  • FIG. 4 is an exemplary flowchart of a test point creation method according to an embodiment of the invention.
  • FIG. 5 is a schematic diagram showing the logical structure of a test point creation apparatus according to an embodiment of the invention.
  • the function simulator when the checkpoint is created, since the function simulator can only perceive the simulated hardware data and the instruction flow of the translation execution, the operating system cannot be perceived, and if the checkpoint is not related to the benchmark, the function is not performed.
  • the simulator also performs checkpoint creation when running other user processes or kernel processes.
  • the checkpoint data obtained at this time has nothing to do with the benchmark test. It takes time and space to create and save checkpoint data, and subsequent performance tests are performed. It also wastes system resources and affects the accuracy of test results and even affects the design of the hardware architecture.
  • multi-level cache (cache) size For example, in the multi-core processor design process, various factors need to be considered: multi-level cache (cache) size, number of registers and bits, pipeline scheduling strategy, processor inter-core bus connections, floating-point modules, and so on.
  • cache multi-level cache
  • number of registers and bits For example, number of registers and bits, pipeline scheduling strategy, processor inter-core bus connections, floating-point modules, and so on.
  • FIG. 1 is a schematic diagram showing the logical structure of a simulator system according to an embodiment of the present invention.
  • the system includes a simulator 100 and a host 102.
  • the host machine 102 is used to provide an operating environment for the simulator, and the simulator 100 is used to simulate a computer architecture, including a function simulator 104, a manager 112, and a performance simulator 114.
  • the function simulator 104 is divided into two parts, the bottom layer being the processor simulator 106, and the virtual machine 108 running on the processor simulator 106.
  • the processor emulator 106 is a software module running on the host machine for simulating the function of the processor architecture.
  • the virtual machine 108 is a virtual machine running on the processor architecture simulated by the processor simulator 106, and runs thereon. There is a user operating system. When testing the performance of the simulator 100 using a performance tester, the first is to use the virtual machine 108 to run the benchmark code.
  • the relationship between the running processes is maintained on the virtual machine 108.
  • the /proc directory on the Linux operating system stores the file in the kernel running state
  • the /proc directory is a file system, that is, the proc file system, which can be viewed through the files therein.
  • Information about the system hardware and the currently running process is maintained.
  • /proc/pid/stat records the process ID (process id of the parent process, ppid), which describes the pid indication.
  • the parent process id value of the process so by scanning the proc directory, you can get the tree structure of all processes in the operating system, and you can get the relationship between all processes.
  • the function simulator 104 only requires the function to be correct, that is, the execution result is correct, so the internal working principle of the processor is not simulated in detail, and the performance simulator 114 is generally used to simulate the behavior of the processor hardware, so the performance simulator 114 needs to be detailed.
  • the various hardware components describing the processor architecture can obtain the operation of the various hardware simulated by the performance simulator 114 when the processor instructions are run.
  • the performance simulator 114 may include (or simulate) the following functions: an instruction decoder, the performance simulator 114 decodes the instruction when the instruction is executed, and the generator generates a plurality of microinstructions from the decoded instruction. Execute under the scheduling of the scheduler (sequential or out-of-order); various arithmetic unit modules; concurrent scheduler, so that the micro-instructions on each pipeline can run concurrently; interconnect and clock; the area where the processor stores data, such as each processing Registers, buffers, conversion monitor buffers (TLBs) on the core, and various coprocessor registers, etc.; debug modules for debugging functions on the processor's own hardware. It should be understood that the embodiments of the present invention are merely illustrative and do not limit the functional modules included in the performance simulator 114. In a specific implementation process, the performance simulator 114 may include more or fewer functional modules.
  • the manager 112 is a middleware that connects the function simulator 104 and the performance simulator 114 for instruction block forwarding and application program interface calls, and is also used to collect operational data of the performance simulator 114. After running an instruction block on the function simulator 104, the instruction block is sent to the performance simulator 114 through the manager 112, so that the function simulator 104 and the performance simulator 114 run the same instruction stream, and the function simulator 104 To achieve the correctness of the implementation of the function, the performance simulator 114 achieves test data output on performance and efficiency.
  • the performance simulator 114 and the function simulator 104 are run together, executing the same instruction block and interface calls, it takes a long time to run a set of benchmarkamrk test programs, which may take several days, or even tens of days, if there is still a pair If the parameters of the performance simulator 114 are modified multiple times, the entire test cycle is longer. In order to speed up the test, a form of creating a checkpoint may be taken, and at a fixed time or an instruction execution interval, the manager 112 performs a create checkpoint action.
  • the process of creating a checkpoint is: the function simulator 104 and the performance simulator 114 run together for a period of time, that is, a warm-up phase, during which the function simulator 104 runs through an instruction block and passes through the manager.
  • 112 sends the instruction block to the performance simulator 114 for operation, such that the function simulator 104 and the performance simulator 114 run the same instruction stream to populate the state information of the performance simulator 114 (including the cache, TLB, registers, Coprocessor registers, etc.), then create a checkpoint to generate checkpoint data, wherein the checkpoint data includes a function simulator 104
  • the snapshot and the status information of the performance simulator can be used to save and restore the state of the function of the function simulator 104 and the performance simulator 114.
  • the warm-up is executed after a certain period of time or after the execution of the instruction number interval, and a checkpoints action is created, so that a series of checkpoint data can be obtained.
  • Subsequent function simulator 104 and performance simulator 114 can use the checkpoint data to restore operational status and execute some instruction block instructions. This is the first time that the benchmark test program is completely run and a series of checkpoint data is created. After the performance simulator 114 modifies the parameter settings, the performance simulator and the function simulator only need to load the checkpoint data to implement the benchmark test. This can greatly increase the test speed and shorten the test time.
  • FIG. 1 is merely an exemplary illustration of a simulator system.
  • the simulator system may include more complicated components, and FIG. 1 does not impose any limitation on the specific implementation of the simulator system, for example, Some of the functionality of manager 112 may be nested within processor simulator 106 and/or processor simulator 116.
  • FIG. 2 is a schematic diagram showing the hardware structure of a host computer 102 according to an embodiment of the invention.
  • host machine 102 includes a processor 202, a memory 204, an input/output interface 206, a communication interface 208, and a bus 210.
  • the processor 202, the memory 204, the input/output interface 206, and the communication interface 208 implement a communication connection with each other through the bus 210.
  • the processor 202 is a control center of the host computer 102 for executing related programs to implement the technical solutions provided by the embodiments of the present invention.
  • the processor 202 can be a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits for executing related programs.
  • CPU central processing unit
  • ASIC application specific integrated circuit
  • the technical solution provided by the embodiment of the present invention is implemented.
  • the memory 204 can be a read only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM).
  • the memory 204 can store an operating system and other applications.
  • the program code for implementing the technical solution provided by the embodiment of the present invention is stored in the memory 204 and executed by the processor 202.
  • the memory 204 can be integrated with or integrated with the processor 202, or it can be one or more memory units independent of the processor 202.
  • Program code for execution by processor 202 may be stored in an external storage device or memory 204 coupled thereto.
  • the memory 204 is a RAM, and program code (eg, a function simulator module, a manager module or a performance simulator module, etc.) stored inside the external storage device is copied into the memory 204 for execution by the processor 202.
  • the memory 204 of the host 102 includes a function simulator module, a manager module, a performance simulator module, and the like, and the processor 202 executes a function simulator module, and the manager module and the performance simulator module implement test points.
  • the function simulator module is used to implement the functions of the function simulator
  • the manager module is used to implement the functions of the manager
  • the performance simulator module is used to implement the functions of the performance simulator.
  • a component for performing a specific function for example, the processor 202 or the memory 204, may be implemented by configuring a general-purpose component to perform a corresponding function, or may perform a specific function through a specific function.
  • the specific components are implemented, and this application does not limit this.
  • the input/output interface 206 is for receiving input data and information, and outputting data such as operation results.
  • Communication interface 208 implements communication between host device 102 and other devices or communication networks using transceivers such as, but not limited to, transceivers.
  • Bus 210 can include a path for communicating information between various components of host 102, such as processor 202, memory 204, input/output interface 206, and communication interface 208.
  • meter host 102 shown in FIG. 2 only shows the processor 202, the memory 204, the input/output interface 206, the communication interface 208, and the bus 210, in a specific implementation process, those skilled in the art should It is understood that host 102 also contains other devices necessary to achieve proper operation. At the same time, those skilled in the art will appreciate that host machine 102 may also include hardware devices that implement other additional functions, depending on the particular needs. Moreover, those skilled in the art will appreciate that host 102 may also only include the components necessary to implement embodiments of the present invention, and does not necessarily include all of the devices shown in FIG.
  • the hardware structure shown in FIG. 2 and the above description are applicable to various test point creation apparatuses provided by the embodiments of the present invention, and are applicable to performing various test point creation methods provided by the embodiments of the present invention.
  • the function simulator Before the checkpoint is created, the function simulator needs to warm up the performance simulator for a period of time, that is, the manager needs to send at least one basic block after the function simulator is executed to the performance simulator for execution. Used to fill in the various data in the performance simulator, and then perform the creation of a checkpoint action to generate checkpoint data. Because the simulator system is not only used to run the test program process, but also to run other processes that are not related to the test program. If the function simulator is not running the process for executing test instructions during the warm-up phase, the function simulator and The various data filled in the performance simulator is independent of the test program.
  • FIG. 3 is a scene diagram of a simulator warm-up phase according to an embodiment of the present invention, as shown in FIG. Show, there are four scenarios in the warm-up phase:
  • the simulator runs the test program process, that is, the W1 and W5 warm-up phases shown in Figure 3. Because the entire warm-up phase simulator runs the test program process, after the warm-up phase is over, the data filled in the function simulator and performance simulator is related to the test program. In this case, the checkpoint created is accurate. .
  • the simulator runs the test program process, and the process switch occurs during the warm-up phase. After the switch, the simulator runs other processes, that is, the W2 warm-up shown in Figure 3. stage. Because process switching occurs during the warm phase, the data filled in the function simulator and performance simulator is inaccurate after the end of the warm phase, and the checkpoint created is inaccurate.
  • the simulator runs other processes.
  • the process switch occurs.
  • the simulator runs the test program process, that is, the W4 pre-show shown in Figure 3. Hot stage. Because in the initial stage of the warm, the simulator runs other processes, but switches to the test program process in the warm process, which will cause insufficient warm-up, and will lead to functional simulator and performance simulation after the end of the warm phase.
  • the data filled in the device is not accurate, and the checkpoint created is also inaccurate.
  • FIG. 4 is a schematic flowchart of a method 400 for creating a test point according to an embodiment of the present invention. As shown in FIG. 4, the method 400 includes:
  • S402 The manager reads the T1 process number recorded in the process number (PID) register at the first time.
  • the process number of the process that the function simulator is running is stored in the PID register.
  • step S404 The manager determines whether the process indicated by the T1 process number is used to execute the test program. If the process indicated by the T1 process number is not used to execute the test program, the process returns to step S402. If the process indicated by the T1 process number is used to execute the test program, Then step S406 is performed.
  • the manager When the manager first detects that the function simulator executes the test program, it reads and records the root process number of the process number register record. The process that executes the test program is the root process or the root process indicated by the root process number. In the descendant process, the manager determines whether the process indicated by the T1 process number is used to execute the test program according to the root process number and the interprocess relationship maintained by the function simulator.
  • the operating system running on the function simulator is a Linux operating system
  • the inter-process relationship maintained by the function simulator is a proc directory in an operating system running on the function simulator, and the proc directory records each thread and each one. The relationship between the parent processes of a thread.
  • the proc directory can be exported by the operating system running on the function simulator through a shared directory for the manager to share.
  • the parent process ID (PPID) of the parent process of the process is recorded in the /proc/pid/stat file of each process. According to the proc directory, you can get a process number tree with the root process number as the root node to describe the relationship between the test program processes. If the T1 process number is the root process or the descendant process of the root process, the process indicated by the T1 process number is the process used to execute the test program.
  • the manager can determine the test program process number set according to the parent process number and the inter-process relationship maintained by the function simulator, and the test program process number set contains the process number of the process for executing the test program.
  • the manager determines whether the parent process number of the T1 process number or the T1 process number belongs to the test program process number set. If the T1 process number or the parent process number of the T1 process number belongs to the test program process number set, the process indicated by the T1 process number is The process used to execute the test program.
  • the manager determines whether the process indicated by the parent process number of the T1 process number is a test program process according to the inter-process relationship maintained by the function simulator.
  • the descendant process if the process indicated by the parent process number of the T1 process number is a descendant process of the test program process, it indicates that the process indicated by the T1 process number is a process for executing the test program; if the parent process number of the T1 process number indicates The process is not a descendant process of the root process, indicating that the process indicated by the T1 process number is not a program for executing the test program.
  • the manager also adds the T1 process number and its parent process number. Test program process number collection.
  • step S406 the warm-up phase may be started, that is, step S406 is performed, and if it is determined that the progress of the T1 process number indication is not for executing the test program, the manager may wait for a certain time, Or after the function simulator executes a certain instruction block, step S402 is re-executed.
  • S406 The manager sends at least one instruction block after the function simulator is executed to the performance simulator for execution.
  • the manager can enter the warm-up phase by the controller simulator, and send the instruction block after the function simulator is executed to the performance simulator to perform the filling of the performance simulator.
  • Various status data can be entered by the controller simulator, and send the instruction block after the function simulator is executed to the performance simulator to perform the filling of the performance simulator.
  • S408 The manager reads the T2 process number recorded in the PID register at the second time.
  • the manager reads the PID register again.
  • step S410 The manager determines whether the process indicated by the T2 process number is used to execute the test program. If the process indicated by the T2 process number is not used to execute the test program, the process returns to step S402. If the process indicated by the T1 process number is used to execute the test program, Then step S412 is performed.
  • the specific process for the manager to determine whether the process indicated by the T2 process number is used to execute the test program refers to the specific process of the manager for determining whether the process indicated by the T1 process number is used to execute the test program, and details are not described herein again.
  • the manager will also have the T2 process number and its parent. The process number is added to the test program process number set.
  • the duration of the warm-up phase is limited, there are very few cases where process switching occurs. If the process indicated by the T1 process number at the beginning of the warm-up phase and the process indicated by the T2 process number at the end of the warm-up phase are used to execute the test procedure. , it can be inferred that the entire warm-up phase simulator is running the test program process, the warm-up phase is valid, in this case, the checkpoint creation action can be performed; if the process indicated by the T2 process number is not used to perform the test The program indicates that the process switchover occurs during the warm-up phase, which will result in inaccurate data. The manager does not perform the checkpoint creation action, and can wait for a certain time, or wait for the function simulator to execute a certain instruction block and then re-execute. Step S402.
  • T1 process number and the T2 process number are only process numbers stored in the PID registers at two different time points, and the two may be the same or different.
  • test point data includes a snapshot of the function simulator and status information of the performance simulator.
  • the created test point data is saved for use in subsequent benchmark tests.
  • a series of accurate checkpoint data can be obtained, and the subsequent function simulator and performance simulator can use the checkpoint data to restore the running state and execute some instruction block instructions. This is only the first time you run the benchmark test program completely and create a series of checkpoint data. After the performance simulator changes the parameter settings, the performance simulator and function simulator only need to To load checkpoint data, you can implement the benchmark test.
  • test program process runs on the function simulator at the beginning and the end of the warm-up phase, thereby ensuring that the created checkpoints are all related to the test program, and the other process pairs are reduced.
  • Checkpoint data interference which can improve the accuracy of the benchmark test.
  • FIG. 5 is a schematic diagram showing the logical structure of a test point creation apparatus 500 according to an embodiment of the present invention. As shown in FIG. 5, the apparatus 500 includes a reading unit 502, a determining unit 504, a scheduling unit 506, and a creating unit 508.
  • the reading unit 502 is configured to read the T1 process number recorded by the process number register at the first time, wherein the process number register stores the process number of the process that the function simulator is running.
  • Determination unit 504 The process for determining the T1 process number indication is used to execute the test procedure.
  • the reading unit 502 is further configured to read and record the root process number of the process number register record when the function simulator is first detected to execute the test program, and the process of executing the test program is the root indicated by the root process number.
  • the test program includes an instruction instruction
  • the reading unit 502 is configured to read and record the root process number of the process number register record when the function simulator is first detected to execute the test program, where the reading unit 502 is configured to detect After the instruction is instructed, the process number register is read and the root process number recorded in the process number register is recorded.
  • the determining unit 504 is configured to determine that the process indicated by the T1 process number is used to execute the test program, and the determining unit 504 is configured to determine, according to the root process number and the inter-process relationship maintained by the function simulator, that the process indicated by the T1 process number is used to execute the test program. .
  • the inter-process relationship maintained by the function simulator may be a proc directory in an operating system running on the function simulator, and the proc directory records the relationship between each thread and the parent process of each thread.
  • the determining unit 504 is further configured to determine, according to the parent process ID and the inter-process relationship maintained by the function simulator, a test program process number set, where the test program process number set includes a process number of a process for executing the test program.
  • the determining unit 504 is configured to determine that the process indicated by the T1 process number is used to execute the test program.
  • the determining unit 504 is configured to determine that the T1 process number or the parent process number of the T1 process number belongs to the test program process number set.
  • the determining unit 504 is further configured to add the T1 process number to the test program process number set.
  • a scheduling unit 506, configured to send at least one instruction block after the function simulator is run to the performance mode The simulator is executed.
  • the reading unit 502 is further configured to read the T2 process number recorded by the process number register at the second time.
  • the determining unit 504 is further configured to determine that the process indicated by the T2 process number is used to execute the test program.
  • the determining unit 504 is configured to determine that the process indicated by the T2 process number is used to execute the test program, and the determining unit 504 is configured to determine, according to the root process number and the inter-process relationship maintained by the function simulator, that the process indicated by the T2 process number is used to execute the test program. .
  • the determining unit 504 is configured to determine that the process indicated by the T2 process number is used to execute the test program, and the determining unit 504 is configured to determine that the parent process number of the T2 process number or the T2 process number belongs to the test program process number set.
  • the determining unit 504 is further configured to add the T2 process number to the test program process number set.
  • a creation unit 508 is configured to create a test point and record test point data, wherein the test point data includes a snapshot of the function simulator and status information of the performance simulator.
  • the reading unit 502, the determining unit 504, the scheduling unit 506 and the creating unit 508 of the embodiment of the present invention may be implemented by the processor 202 and the memory 204 of the embodiment of FIG. 2, and more specifically, may be executed by the processor 202 in the memory 204.
  • the embodiment of the present invention is an apparatus embodiment of the manager, and the feature description of the embodiment of FIG. 4 is applicable to the embodiment of the present invention, and details are not described herein again.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the modules is only a logical function division, and may be implemented in another manner, for example, multiple modules or components may be combined or may be Integrate into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or module, and may be electrical, mechanical or otherwise.
  • the modules described as separate components may or may not be physically separated.
  • the components displayed as modules may or may not be physical modules, that is, may be located in one place, or may be distributed to multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. in.
  • the above integrated modules can be implemented in the form of hardware or in the form of hardware plus software function modules.
  • the above-described integrated modules implemented in the form of software function modules can be stored in a computer readable storage medium.
  • the software functional modules described above are stored in a storage medium and include instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform some of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a removable hard disk, a read only memory, a random access memory, a magnetic disk, or an optical disk, and the like, which can store program codes.

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  • Theoretical Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

Un mode de réalisation de la présente invention concerne un procédé, un dispositif et un système pour créer un point de contrôle, le procédé consistant : à lire un numéro de processus T1 enregistré par un registre de numéro de processus à un premier instant, à déterminer qu'un processus indiqué par le numéro de processus T1 est utilisé pour exécuter un programme de vérification, le registre de numéro de processus contenant un numéro de processus d'un processus actuellement exécuté par un simulateur de fonction, et au moins un bloc de base résultant après l'exécution du simulateur de fonction est envoyé à un simulateur de performance pour l'exécution ; à lire un numéro de traitement T2 enregistré par le registre de numéro de processus à un second instant, à déterminer qu'un processus indiqué par le numéro de traitement T2 est utilisé pour exécuter un programme de vérification ; à créer un point de contrôle et à enregistrer des données de point de contrôle, les données de point de contrôle comprenant un instantané du simulateur de fonction et des informations d'état du simulateur de performance. La solution technique décrite par le mode de réalisation de la présente invention peut augmenter la précision des données de point de contrôle, ce qui permet d'améliorer la précision de vérification du simulateur.
PCT/CN2016/109053 2016-12-08 2016-12-08 Système, dispositif et procédé de création de point de contrôle WO2018103045A1 (fr)

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