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WO2018196377A1 - 显示面板、像素驱动电路及其驱动方法 - Google Patents

显示面板、像素驱动电路及其驱动方法 Download PDF

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Publication number
WO2018196377A1
WO2018196377A1 PCT/CN2017/113909 CN2017113909W WO2018196377A1 WO 2018196377 A1 WO2018196377 A1 WO 2018196377A1 CN 2017113909 W CN2017113909 W CN 2017113909W WO 2018196377 A1 WO2018196377 A1 WO 2018196377A1
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WIPO (PCT)
Prior art keywords
switch
terminal
control
voltage signal
control signal
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Application number
PCT/CN2017/113909
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English (en)
French (fr)
Inventor
陈小龙
温亦谦
周明忠
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to KR1020197035197A priority Critical patent/KR102350681B1/ko
Priority to US15/744,079 priority patent/US10522079B2/en
Priority to JP2019558587A priority patent/JP6844034B2/ja
Priority to EP17907653.4A priority patent/EP3618045A4/en
Publication of WO2018196377A1 publication Critical patent/WO2018196377A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present application relates to the field of display technologies, and in particular, to a pixel driving circuit, a driving method of the pixel driving circuit, and a display panel including the pixel driving circuit.
  • the threshold voltage of the driving transistor of each pixel unit in the OLED display panel may be different, which will cause each pixel unit.
  • the currents of the middle light emitting diodes are inconsistent, causing uneven brightness of the OLED display panel.
  • the drive transistor material ages and mutates, causing problems such as drift of the threshold voltage of the drive transistor.
  • the degree of aging of the driving transistor materials is different, which causes the threshold voltage of each driving transistor in the OLED display panel to drift differently, which may also cause uneven display of the OLED display panel, and the display unevenness may follow the driving time.
  • the aging and aging of the drive transistor material becomes more severe.
  • an object of the present application is to provide a pixel driving circuit, a driving method thereof, and a display panel including the pixel driving circuit to improve brightness uniformity of the display panel.
  • the present application provides a pixel driving circuit including a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second capacitor, and an initial voltage signal.
  • the driving transistor is provided with a gate terminal, a source terminal and a drain terminal;
  • the first switch is disposed between the gate terminal and the drain terminal, and the gate terminal passes the a second switch is connected to the initial voltage signal end; the source terminal is respectively connected to the driving voltage signal end and the data voltage signal end through the third switch and the fourth switch;
  • the first capacitor is connected between the gate terminal and the ground terminal, and the second capacitor is connected between the gate terminal and the source terminal.
  • the pixel driving circuit further includes a first control signal end, and the first control signal end is connected to the control end of the first switch, the control end of the third switch, and the control end of the fourth switch And controlling on and off of the first switch, the third switch, and the fourth switch.
  • the pixel driving circuit further includes a second control signal end, and the second control signal end is connected to the control end of the second switch to control the on and off of the second switch.
  • the pixel driving circuit further includes a fifth switch, a light emitting diode and a negative voltage signal terminal, the light emitting diode has a positive terminal and a negative terminal, and the fifth switch is connected between the drain terminal and the positive terminal To control the on and off of the driving transistor and the light emitting diode, the negative terminal is connected to the negative voltage signal terminal.
  • the pixel driving circuit further includes a third control signal end, and the third control signal end is connected to the control end of the fifth switch to control on and off of the fifth switch.
  • the embodiment of the present application provides a display panel including the pixel driving circuit of any of the above embodiments.
  • Embodiments of the present application provide a pixel driving method, including
  • a pixel driving circuit includes a driving transistor, a first capacitor and a second capacitor, wherein the driving transistor is provided with a gate terminal, a source terminal and a drain terminal, and the first capacitor is connected between the gate terminal and the ground terminal The second capacitor is connected between the gate terminal and the source terminal;
  • a reset phase an initial voltage is applied to the gate terminal, and a driving voltage is applied to the source terminal to reset a potential of the gate terminal and a potential of the source terminal;
  • Vth is a threshold voltage of the driving transistor
  • the potential of the gate terminal is stored in the first capacitor
  • the Vth is stored in the second capacitor
  • the driving voltage is loaded at the source terminal, and the potential of the gate terminal is changed to stabilize the driving current of the driving transistor.
  • the pixel driving circuit further includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a light emitting diode, a first control signal end, a second control signal end, and a third control signal.
  • the first switch is disposed between the gate terminal and the drain terminal, and the gate terminal is connected to the initial through the second switch a voltage signal terminal;
  • the source terminal is respectively connected to the driving voltage signal terminal and the data voltage signal terminal through the third switch and the fourth switch, wherein the fifth switch is connected to the drain terminal and the
  • the first control signal end is connected to the control end of the first switch, the control end of the third switch, and the control end of the fourth switch;
  • the second control signal end is connected The control end of the second switch;
  • the third control signal end is connected to the control end of the fifth switch;
  • the first control signal end and the third control signal end are loaded with a high level signal, and the second control signal end is loaded with a low level signal, so that the second switch and The third switch is turned on, and the first switch, the fourth switch, and the fifth switch are turned off, the gate terminal loads the initial voltage through the second switch, and the source terminal passes The third switch loads the driving voltage.
  • the first control signal end is loaded with a low level signal
  • the second control signal end and the third control signal end are loaded with a high level signal, so that the first switch And the fourth switch is turned on, and the second switch, the third switch, and the fifth switch are turned off
  • the source terminal loads the data voltage through the fourth switch, the data voltage
  • the data voltage charges the gate terminal through the fourth switch, the driving transistor, and the first switch, and causes the potential of the gate terminal to be Vdata-Vth.
  • the pixel driving circuit further includes a light emitting diode and a negative voltage signal terminal, the light emitting diode has a positive terminal and a negative terminal, and the fifth switch is connected between the drain terminal and the positive terminal.
  • the negative terminal is connected to the negative voltage signal terminal;
  • the first control signal end and the second control signal end are loaded with a high level signal, and the third control signal end is loaded with a low level signal, so that the third switch and the The fifth switch is turned on, and the second switch, the first switch, and the fourth switch are turned off;
  • the C1 is a capacitance value of the first capacitor
  • the C2 is a capacitance of the second capacitor a value such that the driving current is independent of the threshold voltage
  • the third switch, the driving transistor, and the fifth switch are turned on such that the driving voltage signal terminal is electrically connected to the negative voltage signal terminal, In order to drive the LED to emit light, the driving
  • the pixel driving circuit provided by the present application includes a driving transistor, the driving transistor is provided with a gate terminal, a source terminal and a drain terminal; the first switch is disposed between the gate terminal and the drain terminal, and the gate is Extremely connected to the initial voltage signal end by the second switch; the source terminal is respectively connected to the driving voltage signal end and the data voltage signal end through the third switch and the fourth switch; The first capacitor is connected between the gate terminal and the ground terminal, and the second capacitor is connected between the gate terminal and the source terminal.
  • the data voltage signal terminal charges the gate terminal to a potential difference between the source terminal and the gate terminal to be a threshold voltage Vth of the driving transistor, and then charges the source terminal through the driving voltage signal terminal, so that the potential difference between the source terminal and the gate terminal is Vdd.
  • Vth a threshold voltage of the driving transistor
  • the driving current is independent of the threshold voltage Vth, thereby stabilizing the current flowing through the light emitting diode, and ensuring the light emitting brightness of the light emitting diode Evenly.
  • the pixel driving method provided by the present application resets the source terminal and the gate terminal by setting a reset phase.
  • the gate terminal is charged to a potential difference between the source terminal and the gate terminal through the data voltage signal terminal to be a threshold voltage of the driving transistor.
  • the threshold voltage Vth is independent, so that the current flowing through the light emitting diode is stabilized, and the light emitting luminance of the light emitting diode is ensured to be uniform.
  • the display panel provided by the present application includes the pixel driving circuit, and the driving current generated by the driving transistor is independent of the threshold voltage of the driving transistor, so that the driving current generated by the driving transistor is stabilized, and the pixel unit is eliminated. Due to the problem of threshold voltage drift caused by aging of the driving transistor or manufacturing process limitation, the current flowing through the light emitting diode is stabilized, the brightness of the light emitting diode is ensured to be uniform, and the display effect of the picture is improved.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit according to a first embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a pixel driving circuit according to a second embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • FIG. 4 is a timing diagram of a pixel driving circuit provided by an embodiment of the present application.
  • FIG. 5 is a flowchart of a pixel driving method provided by an embodiment of the present application.
  • FIG. 6 is a state diagram of a reset phase of a pixel driving circuit according to an embodiment of the present application.
  • FIG. 7 is a state diagram of a storage phase of a pixel driving circuit provided by an embodiment of the present application.
  • FIG. 8 is a state diagram of a light emitting phase of a pixel driving circuit according to an embodiment of the present application.
  • FIG. 1 is a pixel driving circuit according to a first embodiment of the present disclosure, including a driving transistor T0, a first switch T1, a second switch T2, a third switch T3, a fourth switch T4, and a first capacitor.
  • the driving transistor T0 is provided with a gate terminal g, a source terminal s and a drain terminal d.
  • the first switch T1 is disposed between the gate terminal g and the drain terminal d.
  • the gate terminal g is connected to the initial voltage signal terminal VINI through the second switch T2 to load an initial voltage Vini at the gate terminal g.
  • the source terminal s is respectively connected to the driving voltage signal terminal OVDD and the data voltage signal terminal VDATA through the third switch T3 and the fourth switch T4 to load the driving voltage Vdd or the source terminal s Data voltage Vdata.
  • the first capacitor C11 is connected between the gate terminal g and the ground terminal to store the potential of the gate terminal g.
  • a second capacitor C12 is connected between the gate terminal g and the source terminal s to store a potential difference between the gate terminal g and the source terminal s.
  • the switch described in this embodiment includes, but is not limited to, a switch circuit, a thin film transistor, and the like having a control circuit on/off function.
  • the pixel driving circuit further includes a first control signal end Scan1, and the first control signal end Scan1 is connected to the control end of the first switch T1 and the control end of the third switch T3. And a control end of the fourth switch T4 to control on and off of the first switch T1, the third switch T3, and the fourth switch T4.
  • the pixel driving circuit further includes a second control signal end Scan2, and the second control signal end Scan2 is connected to the control end of the second switch T2 to control the second switch T2. On and off.
  • the driving voltage signal terminal OVDD is turned on with the negative voltage signal terminal OVSS, and the driving of the driving transistor T0 is driven.
  • the current I drives the light-emitting diode L to emit light.
  • the driving current I is independent of the threshold voltage of the driving transistor T0, eliminating the problem of threshold voltage drift in the pixel unit due to aging of the driving transistor T0 or manufacturing process limitation, thereby flowing through the light emitting diode L.
  • the current is stable, ensuring uniform brightness of the light-emitting diode L, and improving the display effect of the screen.
  • the pixel driving circuit further includes a third control signal end Scan3, and the third control signal end Scan3 is connected to the control end of the fifth switch T5 to control the fifth switch T5. On and off.
  • the first switch T1, the driving transistor T0, the second switch T2, the fourth switch T4, and the fifth switch T5 are all P-type thin film transistors, when the switch is When the control terminal applies a low-level voltage, the switch is in an on state, and when the control terminal of the above switch applies a high-level voltage, the switch is in an off state.
  • the third switch T3 is an N-type thin film transistor. When a high-level voltage is applied to the control terminal of the switch, the third switch T3 is in an on state. When a control terminal of the switch applies a low-level voltage, the first The three switch T3 is in the off state.
  • the first switch T1, the driving transistor T0, the second switch T2, the third switch T3, the fourth switch T4, and the fifth switch T5 may also be other P-type or / and N-type thin film transistor combinations, this application is not limited.
  • control signal end when the pixel driving circuit is applied to a display panel or a display device, the control signal end may be connected to a scanning signal line in the display panel or the display device.
  • the embodiment of the present application further provides a display panel 100, including the pixel driving circuit provided by any of the above embodiments, and further includes an initial voltage signal line V1, a data voltage signal line V2, and a driving voltage signal line V3. And the negative voltage signal line V4.
  • the initial voltage signal terminal VINI is connected to the initial voltage signal line V1 to load the initial voltage Vini.
  • the data voltage signal terminal VDATA is connected to the data voltage signal line V2 to load the data voltage Vdata.
  • the driving voltage signal terminal OVDD is connected to the driving voltage signal line V3 to load the driving voltage Vdd.
  • the negative voltage signal terminal OVSS is connected to the negative voltage signal line V4 to load the negative voltage Vss.
  • the display panel may include a plurality of pixel arrays, each of which corresponds to any of the pixel driving circuits in the above-described exemplary embodiment. Since the pixel driving circuit eliminates the influence of the threshold voltage on the driving current I, the display of the LED L is stabilized, and the uniformity of the display brightness of the display panel is improved, so that the display quality can be greatly improved.
  • FIG. 4 is a timing diagram of a pixel driving circuit according to an embodiment of the present application.
  • FIG. 5 is a pixel driving method S100 according to an embodiment of the present disclosure, for driving the pixel driving circuit described in the above embodiment, including
  • S101 please refer to FIG. 2 and FIG. 3, providing a pixel driving circuit, including a driving transistor T0, A capacitor C11 and a second capacitor C12, the driving transistor T0 is provided with a gate terminal g, a source terminal s and a drain terminal d.
  • the first capacitor C11 is connected between the gate terminal g and the ground terminal
  • the second capacitor C12 is connected between the gate terminal g and the source terminal s.
  • the pixel driving circuit further includes an initial voltage signal terminal VINI, a data voltage signal terminal VDATA, and a driving voltage signal terminal OVDD.
  • the initial voltage signal terminal VINI is connected to the initial voltage signal line V1 for loading the initial voltage Vini.
  • the data voltage signal terminal VDATA is connected to the data voltage signal line V2 for loading the data voltage Vdata.
  • the driving voltage signal terminal OVDD is connected to the driving voltage signal line V3 for loading the driving voltage Vdd.
  • the pixel driving circuit further includes a first switch T1, a second switch T2, a third switch T3, a fourth switch T4, a fifth switch T5, a light emitting diode L, and a first control signal end Scan1, a second The control signal terminal Scan2, the third control signal terminal Scan3, the initial voltage signal terminal VINI, the data voltage signal terminal VDATA, and the driving voltage signal terminal OVDD.
  • the first switch T1 is disposed between the gate terminal g and the drain terminal d, and the gate g terminal is connected to the initial voltage signal terminal VINI through the second switch T2.
  • the source terminal s is connected to the driving voltage signal terminal OVDD and the data voltage signal terminal VDATA through the third switch T3 and the fourth switch T4, respectively.
  • the fifth switch T5 is connected between the drain terminal d and the light emitting diode L.
  • the first control signal end Scan1 is connected to the control end of the first switch T1, the control end of the third switch T3, and the control end of the fourth switch T4.
  • the second control signal end Scan2 is connected to the control end of the second switch T2.
  • the third control signal end Scan3 is connected to the control end of the fifth switch T5.
  • S102 enter a reset phase t1, load an initial voltage Vini at the gate terminal g, and load a driving voltage Vdd at the source terminal s to make the potential of the gate terminal g and The potential of the source terminal s is reset.
  • the first control signal end Scan1 and the third control signal end Scan3 are loaded with a high level signal, and the second control signal end Scan2 is loaded with a low level signal, so that the first The second switch T2 and the third switch T3 are turned on, and the first switch T1, the fourth switch T4, and the fifth switch T5 are turned off.
  • the gate terminal g loads the initial voltage Vini through the second switch T2.
  • the source terminal s loads the driving voltage Vdd through the third switch T3.
  • S103 enter the storage phase t2 at the source terminal s Loading a data voltage Vdata, and turning on the gate terminal g and the drain terminal d, so that the data voltage Vdata charges the gate terminal g until between the source terminal s and the gate terminal g
  • Vth which is the threshold voltage of the driving transistor T0.
  • the potential of the gate terminal g is stored in the first capacitor C11, and the Vth is stored in the second capacitor C12.
  • the first control signal end Scan1 is loaded with a low level signal
  • the second control signal end Scan2 and the third control signal end Scan3 are loaded with a high level signal, so that the first A switch T1 and the fourth switch T4 are turned on, and the second switch T2, the third switch T3, and the fifth switch T5 are turned off.
  • the source terminal s loads the data voltage Vdata through the fourth switch T4.
  • the data voltage Vdata charges the gate terminal g through the fourth switch T4, the driving transistor T0, and the first switch T1 until a potential difference between the source terminal s and the gate terminal g It is Vth, and the potential of the gate terminal g is Vdata-Vth.
  • the pixel driving circuit provided further includes a negative voltage signal terminal OVSS, and the light emitting diode L has a positive terminal and a negative terminal.
  • the fifth switch T5 is connected between the drain terminal d and the positive terminal.
  • the negative terminal is connected to the negative voltage signal terminal OVSS.
  • the first control signal end Scan1 and the second control signal end Scan2 are loaded with a high level signal
  • the third control signal end Scan3 is loaded with a low level signal, so that the first
  • the third switch T3 and the fifth switch T5 are turned on, and the second switch T2, the first switch T1, and the fourth switch T4 are turned off.
  • the third switch T3, the driving transistor T0 and the fifth switch T5 are turned on to turn on the driving voltage signal terminal OVDD and the negative voltage signal terminal OVSS to drive the LED L to emit light.
  • the source terminal s loads the driving voltage Vdd through the third switch T3.
  • the potential of the gate terminal g is Vdata-Vth+ ⁇ V
  • the difference between the potential of the source terminal s and the potential of the gate terminal g is Vdd-Vdata+Vth- ⁇ V
  • the ⁇ V ( Vdd-Vdata)*C2/(C1+C2)
  • the C1 is a capacitance value of the first capacitor C11
  • the C2 is a capacitance value of the second capacitor C12.
  • I k(Vsg-Vth) 2
  • the Vsg is the difference between the potential of the source terminal s and the potential of the gate terminal g
  • k is the intrinsic conduction factor of the driving transistor T0, which is determined by the characteristics of the driving transistor T0 itself. It can be seen that the drive current I is independent of the threshold voltage Vth of the drive transistor T0, and the drive current I is a current flowing through the light-emitting diode L. Therefore, the pixel driving circuit driven by the pixel driving method provided by the embodiment of the present application eliminates the influence of the threshold voltage Vth on the light emitting diode L, can improve the uniformity of the panel display, and improve the luminous efficiency.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种像素驱动电路、像素驱动方法(S100)和显示面板(100)，像素驱动电路包括驱动晶体管(T0)、第一开关(T1)、第二开关(T2)、第三开关(T3)、第四开关(T4)、第一电容(C11)、第二电容(C12)、初始电压信号端(VINI)、数据电压信号端(VDATA)和驱动电压信号端(OVDD)。驱动晶体管(T0)设有栅极端(g)、源极端(s)和漏极端(d)。栅极端(g)与漏极端(d)之间设置第一开关(T1)，且栅极端(g)通过第二开关(T2)连接于初始电压信号端(VINI)。源极端(s)通过第三开关(T3)和第四开关(T4)分别连接于驱动电压信号端(OVDD)和数据电压信号端(VDATA)。第一电容(C11)连接于栅极端(g)和接地端之间，第二电容(C12)连接于栅极端(g)和源极端(s)之间。

Description

显示面板、像素驱动电路及其驱动方法
本申请要求于2017年04月28日提交中国专利局、申请号为201710299022.6、申请名称为“显示面板、像素驱动电路及其驱动方法”的中国专利申请的优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本申请涉及显示技术领域，具体涉及一种像素驱动电路及该像素驱动电路的驱动方法和包括该像素驱动电路的显示面板。
背景技术
由于发光二极管(Organic Light Emitting Diode，OLED)显示面板制备过程不稳定性和技术受限等原因，OLED显示面板内每个像素单元的驱动晶体管的阈值电压会有差别，这样会造成每个像素单元中发光二极管的电流不一致，从而引起OLED显示面板的亮度不均匀。
另外，随着驱动晶体管驱动时间的推移，会造成驱动晶体管材料老化、变异，从而导致驱动晶体管的阈值电压发生漂移等问题。而且，驱动晶体管材料的老化程度不同，导致OLED显示面板内各个驱动晶体管的阈值电压的漂移量不同，也会造成OLED显示面板显示的不均匀现象，并且这种显示不均匀现象会随着驱动时间的推移和驱动晶体管材料的老化变得更严重。
发明内容
针对以上的问题，本申请的目的是提供一种像素驱动电路及其驱动方法和包括该像素驱动电路的显示面板，以提高显示面板的亮度均匀性。
为了解决背景技术中存在的问题，本申请提供了一种像素驱动电路，包括驱动晶体管、第一开关、第二开关、第三开关、第四开关、第一电容、第二电容、初始电压信号端、数据电压信号端和驱动电压信号端；所述驱动晶体管设有栅极端、源极端和漏极端；
所述栅极端与所述漏极端之间设置所述第一开关，且所述栅极端通过所述 第二开关连接于所述初始电压信号端；所述源极端通过所述第三开关和所述第四开关分别连接于所述驱动电压信号端和所述数据电压信号端；
所述第一电容连接于所述栅极端和接地端之间，所述第二电容连接于所述栅极端和所述源极端之间。
其中，所述像素驱动电路还包括第一控制信号端，所述第一控制信号端连接于所述第一开关的控制端、所述第三开关的控制端及所述第四开关的控制端，以控制所述第一开关、所述第三开关和所述第四开关的通断。
其中，所述像素驱动电路还包括第二控制信号端，所述第二控制信号端连接于所述第二开关的控制端，以控制所述第二开关的通断。
其中，所述像素驱动电路还包括第五开关、发光二极管及负极电压信号端，所述发光二极管具有正极端和负极端，所述第五开关连接于所述漏极端和所述正极端之间，以控制所述驱动晶体管与所述发光二极管的通断，所述负极端连接于所述负极电压信号端。
其中，所述像素驱动电路还包括第三控制信号端，所述第三控制信号端连接于所述第五开关的控制端，以控制所述第五开关的通断。
本申请实施例提供了一种显示面板，包括上述任一实施方式所述的像素驱动电路。
本申请实施例提供了一种像素驱动方法，包括
提供一种像素驱动电路，包括驱动晶体管、第一电容及第二电容，所述驱动晶体管设有栅极端、源极端及漏极端，所述第一电容连接于所述栅极端和接地端之间，所述第二电容连接于所述栅极端和所述源极端之间；
复位阶段，在所述栅极端加载初始电压，且在所述源极端加载驱动电压，以使所述栅极端的电位和所述源极端的电位复位；
存储阶段，在所述源极端加载数据电压，并导通所述栅极端和所述漏极端，以便于所述数据电压对所述栅极端充电，直到所述源极端和所述栅极端之间的电位差为Vth，所述Vth为所述驱动晶体管的阈值电压，并将所述栅极端的电位存储于所述第一电容中，及将所述Vth存储于所述第二电容中；
发光阶段，在所述源极端加载所述驱动电压，并改变所述栅极端的电位，以使所述驱动晶体管的驱动电流稳定。
其中，提供的所述像素驱动电路还包括第一开关、第二开关、第三开关、第四开关、第五开关、发光二极管、第一控制信号端、第二控制信号端、第三控制信号、初始电压信号端、数据电压信号端和驱动电压信号端；所述栅极端与所述漏极端之间设置所述第一开关，且所述栅极端通过所述第二开关连接于所述初始电压信号端；所述源极端通过所述第三开关和所述第四开关分别连接于所述驱动电压信号端和所述数据电压信号端，所述第五开关连接于所述漏极端和所述发光二极管之间；所述第一控制信号端连接于所述第一开关的控制端、所述第三开关的控制端及所述第四开关的控制端；所述第二控制信号端连接于所述第二开关的控制端；所述第三控制信号端连接于所述第五开关的控制端；
所述复位阶段中，设置所述第一控制信号端和所述第三控制信号端加载高电平信号，且所述第二控制信号端加载低电平信号，以使所述第二开关和所述第三开关导通，及所述第一开关、所述第四开关和所述第五开关关断，所述栅极端通过所述第二开关加载所述初始电压，所述源极端通过所述第三开关加载所述驱动电压。
其中，所述存储阶段，设置所述第一控制信号端加载低电平信号，且所述第二控制信号端和所述第三控制信号端加载高电平信号，以使所述第一开关和所述第四开关导通，及所述第二开关、所述第三开关和所述第五开关关断，所述源极端通过所述第四开关加载所述数据电压，所述数据电压为Vdata，所述数据电压通过所述第四开关、所述驱动晶体管及所述第一开关对所述栅极端充电，并使得所述栅极端的电位为Vdata-Vth。
其中，提供的所述像素驱动电路还包括发光二极管及负极电压信号端，所述发光二极管具有正极端和负极端，所述第五开关连接于所述漏极端和所述正极端之间，所述负极端连接于所述负极电压信号端；
所述发光阶段，设置所述第一控制信号端和所述第二控制信号端加载高电平信号，且所述第三控制信号端加载低电平信号，以使所述第三开关和所述第五开关导通，及所述第二开关、所述第一开关和所述第四开关关断；所述源极端通过所述第三开关加载所述驱动电压，所述驱动电压为Vdd，并使得所述栅极端电位为Vdata-Vth+δV，所述源极端的电位与所述栅极端的电位之差为 Vdd-Vdata+Vth-δV，所述δV＝(Vdd-Vdata)*C2/(C1+C2)，所述C1为所述第一电容的电容值，所述C2为所述第二电容的电容值，以使所述驱动电流与所述阈值电压无关；所述第三开关、所述驱动晶体管及所述第五开关导通使得所述驱动电压信号端与所述负极电压信号端导通，以便于所述驱动电流驱动所述发光二极管发光。
本申请提供的像素驱动电路，包括驱动晶体管，所述驱动晶体管设有栅极端、源极端和漏极端；在所述栅极端与所述漏极端之间设置所述第一开关，且所述栅极端通过所述第二开关连接于所述初始电压信号端；所述源极端通过所述第三开关和所述第四开关分别连接于所述驱动电压信号端和所述数据电压信号端；所述第一电容连接于所述栅极端和接地端之间，所述第二电容连接于所述栅极端和所述源极端之间。所述数据电压信号端给栅极端充电至源极端与栅极端的电位差为驱动晶体管的阈值电压Vth，再通过驱动电压信号端给源极端充电，以使源极端与栅极端的电位差为Vdd-Vdata+Vth-δV，使得驱动电流I＝k(Vdd-Vdata-δV)2，驱动电流与所述阈值电压Vth无关，从而使流过发光二极管的电流稳定，保证所述发光二极管的发光亮度均匀。
本申请提供的像素驱动方法，通过设置复位阶段对源极端和栅极端复位，在存储阶段，通过所述数据电压信号端给栅极端充电至源极端与栅极端的电位差为驱动晶体管的阈值电压Vth，再通过驱动电压信号端给源极端充电，以使源极端与栅极端的电位差为Vdd-Vdata+Vth-δV，使得驱动电流I＝k(Vdd-Vdata-δV)2，驱动电流与所述阈值电压Vth无关，从而使流过发光二极管的电流稳定，保证所述发光二极管的发光亮度均匀。
本申请提供的显示面板，包括上述像素驱动电路，可以使所述驱动晶体管产生的驱动电流与所述驱动晶体管的阈值电压无关，从而使所述驱动晶体管产生的驱动电流稳定，消除了像素单元中由于驱动晶体管老化或制作工艺限制造成的阈值电压漂移的问题，从而使流过发光二极管的电流稳定，保证所述发光二极管的发光亮度均匀，改善画面的显示效果。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例中所需要使 用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请第一实施例提供的像素驱动电路结构示意图。
图2是本申请第二实施例提供的像素驱动电路结构示意图。
图3是本申请实施例提供的一种显示面板的结构示意图。
图4是本申请实施例提供的像素驱动电路的时序图。
图5是本申请实施例提供的一种像素驱动方法流程图。
图6是本申请实施例提供的像素驱动电路的复位阶段的状态图。
图7是本申请实施例提供的像素驱动电路的存储阶段的状态图。
图8是本申请实施例提供的像素驱动电路的发光阶段的状态图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例的技术方案进行清楚、完整地描述。
请参阅图1，图1是本申请第一实施例提供的一种像素驱动电路，包括驱动晶体管T0、第一开关T1、第二开关T2、第三开关T3、第四开关T4、第一电容C11、第二电容C12、初始电压信号端VINI、数据电压信号端VDATA、驱动电压信号端OVDD。所述驱动晶体管T0设有栅极端g、源极端s和漏极端d。所述栅极端g与所述漏极端d之间设置所述第一开关T1。所述栅极端g通过所述第二开关T2连接于所述初始电压信号端VINI，以在所述栅极端g加载初始电压Vini。所述源极端s通过所述第三开关T3和所述第四开关T4分别连接于所述驱动电压信号端OVDD和所述数据电压信号端VDATA，以在所述源极端s加载驱动电压Vdd或数据电压Vdata。所述第一电容C11连接于所述栅极端g和接地端之间，以存储所述栅极端g的电位。第二电容C12连接于所述栅极端g和所述源极端s之间，以存储所述栅极端g和所述源极端s之间的电位差。本实施例所述的开关包括但不限于开关电路、薄膜晶体管等具有控制电路通断功能的模块。
本实施例提供的像素驱动电路通过驱动方法控制在复位阶段所述第二开 关T2、所述第三开关T3导通及所述第一开关T1、所述第四开关T4，使所述栅极端g加载所述初始电压Vini，所述源极端s加载所述驱动电压Vdd；在存储阶段所述第一开关T1、所述第四开关T4导通及所述第二开关T2、所述第三开关T3关断，使所述源极端s加载所述数据电压Vdata，且所述数据电压Vdata对所述栅极端g充电；在发光阶段所述第三开关T3导通及所述第二开关T2、所述第一开关T1、所述第四开关T4关断，所述源极端s加载所述驱动电压Vdd，并改变对所述栅极端g的电位,以使所述驱动晶体管T0产生的驱动电流I与所述驱动晶体管T0的阈值电压Vth无关，从而使所述驱动晶体管T0产生的驱动电流I稳定。
一种实施方式中，所述的像素驱动电路还包括第一控制信号端Scan1，所述第一控制信号端Scan1连接于所述第一开关T1的控制端、所述第三开关T3的控制端及所述第四开关T4的控制端，以控制所述第一开关T1、所述第三开关T3和所述第四开关T4的通断。
一种实施方式中，所述的像素驱动电路还包括第二控制信号端Scan2，所述第二控制信号端Scan2连接于所述第二开关T2的控制端，以控制所述第二开关T2的通断。
请参阅图2，图2是本申请第二实施例提供的一种像素驱动电路，包括第一实施例提供的像素驱动电路，使所述驱动晶体管T0产生的驱动电流I稳定。本实施例还包括发光二极管L、第五开关T5及负极电压信号端OVSS。所述发光二极管L可以是有机发光二极管等。所述发光二极管L具有正极端和负极端，所述第五开关T5连接于所述漏极端d和所述正极端之间，以控制所述驱动晶体管T0与所述发光二极管L的通断，所述负极端连接于所述负极电压信号端OVSS。当所述第三开关T3、所述驱动晶体管T0、所述第五开关T5导通时，所述驱动电压信号端OVDD与所述负极电压信号端OVSS导通，所述驱动晶体管T0产生的驱动电流I驱动所述发光二极管L发光。本实施例中所述驱动电流I与所述驱动晶体管T0的阈值电压无关，消除了像素单元中由于驱动晶体管T0老化或制作工艺限制造成的阈值电压漂移的问题，从而使流过发光二极管L的电流稳定，保证所述发光二极管L的发光亮度均匀，改善画面的显示效果。
一种实施方式中，所述的像素驱动电路还包括第三控制信号端Scan3，所述第三控制信号端Scan3连接于所述第五开关T5的控制端，以控制所述第五开关T5的通断。
一种实施方式中，所述第一开关T1、所述驱动晶体管T0、所述第二开关T2、所述第四开关T4、所述第五开关T5均为P型薄膜晶体管，当上述开关的控制端施加低电平电压时，开关处于导通状态，当上述开关的控制端施加高电平电压时，开关处于关断状态。所述第三开关T3为N型薄膜晶体管，当开关的控制端施加高电平电压时，所述第三开关T3处于导通状态，当开关的控制端施加低电平电压时，所述第三开关T3处于关断状态。在其他实施方式中，所述第一开关T1、所述驱动晶体管T0、所述第二开关T2、所述第三开关T3、所述第四开关T4、所述第五开关T5还可以为其他P型或/和N型薄膜晶体管组合，本申请不做限定。
本申请实施例中，像素驱动电路应用于显示面板或显示装置时，所述的控制信号端可以连接于显示面板或显示装置中的扫描信号线。
请参阅图3，本申请实施例还提供了一种显示面板100，包括上述任一种实施例提供的像素驱动电路，还包括初始电压信号线V1、数据电压信号线V2、驱动电压信号线V3及负极电压信号线V4。所述初始电压信号端VINI连接于所述初始电压信号线V1，以加载初始电压Vini。所述数据电压信号端VDATA连接于所述数据电压信号线V2，以加载数据电压Vdata。所述驱动电压信号端OVDD连接于所述驱动电压信号线V3，以加载驱动电压Vdd。所述负极电压信号端OVSS连接于所述负极电压信号线V4，以加载负极电压Vss。具体地，所述显示面板可以包括多个像素阵列，每个像素对应上述本示例实施方式中的任一像素驱动电路。由于所述像素驱动电路消除了阈值电压对驱动电流I的影响，使得发光二极管L显示稳定，改善了显示面板显示亮度的均匀性，因此可以极大的提升显示品质。
请参阅一并参阅图4～图8，图4是本申请实施例提供的像素驱动电路的时序图。图5是本申请实施例提供的像素驱动方法S100，用于驱动上述实施例所述的像素驱动电路，包括
S101、请参阅图2及图3，提供像素驱动电路，包括驱动晶体管T0、第 一电容C11及第二电容C12，所述驱动晶体管T0设有栅极端g、源极端s及漏极端d。所述第一电容C11连接于所述栅极端g和接地端之间，所述第二电容C12连接于所述栅极端g和所述源极端s之间。
进一步地，所述像素驱动电路还包括初始电压信号端VINI、数据电压信号端VDATA、驱动电压信号端OVDD。所述初始电压信号端VINI连接于初始电压信号线V1，用于加载初始电压Vini。所述数据电压信号端VDATA连接于数据电压信号线V2，用于加载数据电压Vdata。所述驱动电压信号端OVDD连接于驱动电压信号线V3，用于加载驱动电压Vdd。
进一步地，提供的所述像素驱动电路还包括第一开关T1、第二开关T2、第三开关T3、第四开关T4、第五开关T5、发光二极管L、第一控制信号端Scan1、第二控制信号端Scan2、第三控制信号端Scan3、初始电压信号端VINI、数据电压信号端VDATA和驱动电压信号端OVDD。所述栅极端g与所述漏极端d之间设置所述第一开关T1，且所述栅极g端通过所述第二开关T2连接于所述初始电压信号端VINI。所述源极端s通过所述第三开关T3和所述第四开关T4分别连接于所述驱动电压信号端OVDD和所述数据电压信号端VDATA。所述第五开关T5连接于所述漏极端d和所述发光二极管L之间。所述第一控制信号端Scan1连接于所述第一开关T1的控制端、所述第三开关T3的控制端及所述第四开关T4的控制端。所述第二控制信号端Scan2连接于所述第二开关T2的控制端。所述第三控制信号端Scan3连接于所述第五开关T5的控制端。
S102、请一并参阅图4至图6，进入复位阶段t1，在所述栅极端g加载初始电压Vini，且在所述源极端s加载驱动电压Vdd，以使所述栅极端g的电位和所述源极端s的电位复位。
一种实施方式中，设置所述第一控制信号端Scan1和所述第三控制信号端Scan3加载高电平信号，且所述第二控制信号端Scan2加载低电平信号，以使所述第二开关T2和所述第三开关T3导通，及所述第一开关T1、所述第四开关T4和所述第五开关T5关断。所述栅极端g通过所述第二开关T2加载所述初始电压Vini。所述源极端s通过所述第三开关T3加载所述驱动电压Vdd。
S103、请一并参阅图4、图5及图7，进入存储阶段t2，在所述源极端s 加载数据电压Vdata，并导通所述栅极端g和所述漏极端d，以便于所述数据电压Vdata对所述栅极端g充电，直到所述源极端s和所述栅极端g之间的电位差为Vth，所述Vth为所述驱动晶体管T0的阈值电压。将所述栅极端g的电位存储于所述第一电容C11中，及将所述Vth存储于所述第二电容C12中。
一种实施方式中，设置所述第一控制信号端Scan1加载低电平信号，且所述第二控制信号端Scan2和所述第三控制信号端Scan3加载高电平信号，以使所述第一开关T1和所述第四开关T4导通，及所述第二开关T2、所述第三开关T3和所述第五开关T5关断。所述源极端s通过所述第四开关T4加载所述数据电压Vdata。所述数据电压Vdata通过所述第四开关T4、所述驱动晶体管T0及所述第一开关T1对所述栅极端g充电，直到所述源极端s和所述栅极端g之间的电位差为Vth，并使得所述栅极端g的电位为Vdata-Vth。
S104、请一并参阅图4、图5及图8，进入发光阶段t3，在所述源极端s加载所述驱动电压Vdd，并改变所述栅极端g的电位，以使所述驱动晶体管T0的驱动电流I稳定。
进一步地，提供的所述像素驱动电路还包括负极电压信号端OVSS，所述发光二极管L具有正极端和负极端。所述第五开关T5连接于所述漏极端d和所述正极端之间。所述负极端连接于所述负极电压信号端OVSS。
一种实施方式中，设置所述第一控制信号端Scan1和所述第二控制信号端Scan2加载高电平信号，且所述第三控制信号端Scan3加载低电平信号，以使所述第三开关T3和所述第五开关T5导通，及所述第二开关T2、所述第一开关T1和所述第四开关T4关断。所述第三开关T3、所述驱动晶体管T0及所述第五开关T5导通使得所述驱动电压信号端OVDD与所述负极电压信号端OVSS导通，以驱动所述发光二极管L发光。所述源极端s通过所述第三开关T3加载所述驱动电压Vdd。由电荷分享原理可知，所述栅极端g电位为Vdata-Vth+δV，所述源极端s的电位与所述栅极端g的电位之差为Vdd-Vdata+Vth-δV，所述δV＝(Vdd-Vdata)*C2/(C1+C2)，所述C1为所述第一电容C11的电容值，所述C2为所述第二电容C12的电容值。根据晶体管I-V曲线方程I＝k(Vsg-Vth)2，所述Vsg为所述源极端s的电位与所述栅极端g的电位之差，可计算得到I＝k[(Vdd-Vdata)*C1/(C1+C2)]2,k为驱动晶体管T0 的本征导电因子，由驱动晶体管T0本身特性决定。可知，驱动电流I与驱动晶体管T0的阈值电压Vth无关，且该驱动电流I为流经所述发光二极管L的电流。因此，本申请实施例提供的像素驱动方法驱动的像素驱动电路消除了阈值电压Vth对发光二极管L的影响，可提高面板显示的均匀性，提高发光效率。
综上所述，虽然本申请已以较佳实施例揭露如上，但该较佳实施例并非用以限制本申请，该领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (14)

  1. 一种像素驱动电路，其中，包括驱动晶体管、第一开关、第二开关、第三开关、第四开关、第一电容、第二电容、初始电压信号端、数据电压信号端和驱动电压信号端；所述驱动晶体管设有栅极端、源极端和漏极端；
    所述栅极端与所述漏极端之间设置所述第一开关，且所述栅极端通过所述第二开关连接于所述初始电压信号端；所述源极端通过所述第三开关和所述第四开关分别连接于所述驱动电压信号端和所述数据电压信号端；
    所述第一电容连接于所述栅极端和接地端之间，所述第二电容连接于所述栅极端和所述源极端之间。
  2. 如权利要求1所述的像素驱动电路，其中，还包括第一控制信号端，所述第一控制信号端连接于所述第一开关的控制端、所述第三开关的控制端及所述第四开关的控制端，以控制所述第一开关、所述第三开关和所述第四开关的通断。
  3. 如权利要求2所述的像素驱动电路，其中，还包括第二控制信号端，所述第二控制信号端连接于所述第二开关的控制端，以控制所述第二开关的通断。
  4. 如权利要求3所述的像素驱动电路，其中，还包括第五开关、发光二极管及负极电压信号端，所述发光二极管具有正极端和负极端，所述第五开关连接于所述漏极端和所述正极端之间，以控制所述驱动晶体管与所述发光二极管的通断，所述负极端连接于所述负极电压信号端。
  5. 如权利要求4所述的像素驱动电路，其中，还包括第三控制信号端，所述第三控制信号端连接于所述第五开关的控制端，以控制所述第五开关的通断。
  6. 一种显示面板，其中，包括像素驱动电路，所述像素驱动电路包括驱动晶体管、第一开关、第二开关、第三开关、第四开关、第一电容、第二电容、初始电压信号端、数据电压信号端和驱动电压信号端；所述驱动晶体管设有栅极端、源极端和漏极端；
    所述栅极端与所述漏极端之间设置所述第一开关，且所述栅极端通过所述 第二开关连接于所述初始电压信号端；所述源极端通过所述第三开关和所述第四开关分别连接于所述驱动电压信号端和所述数据电压信号端；
    所述第一电容连接于所述栅极端和接地端之间，所述第二电容连接于所述栅极端和所述源极端之间。
  7. 如权利要求6所述的显示面板，其中，还包括第一控制信号端，所述第一控制信号端连接于所述第一开关的控制端、所述第三开关的控制端及所述第四开关的控制端，以控制所述第一开关、所述第三开关和所述第四开关的通断。
  8. 如权利要求7所述的显示面板，其中，还包括第二控制信号端，所述第二控制信号端连接于所述第二开关的控制端，以控制所述第二开关的通断。
  9. 如权利要求8所述的显示面板，其中，还包括第五开关、发光二极管及负极电压信号端，所述发光二极管具有正极端和负极端，所述第五开关连接于所述漏极端和所述正极端之间，以控制所述驱动晶体管与所述发光二极管的通断，所述负极端连接于所述负极电压信号端。
  10. 如权利要求9所述的显示面板，其中，还包括第三控制信号端，所述第三控制信号端连接于所述第五开关的控制端，以控制所述第五开关的通断。
  11. 一种像素驱动方法，其中，包括
    提供一种像素驱动电路，包括驱动晶体管、第一电容及第二电容，所述驱动晶体管设有栅极端、源极端及漏极端，所述第一电容连接于所述栅极端和接地端之间，所述第二电容连接于所述栅极端和所述源极端之间；
    复位阶段，在所述栅极端加载初始电压，且在所述源极端加载驱动电压，以使所述栅极端的电位和所述源极端的电位复位；
    存储阶段，在所述源极端加载数据电压，并导通所述栅极端和所述漏极端，以便于所述数据电压对所述栅极端充电，直到所述源极端和所述栅极端之间的电位差为Vth，所述Vth为所述驱动晶体管的阈值电压，并将所述栅极端的电位存储于所述第一电容中，及将所述Vth存储于所述第二电容中；
    发光阶段，在所述源极端加载所述驱动电压，并改变所述栅极端的电位，以使所述驱动晶体管的驱动电流稳定。
  12. 如权利要求11所述的像素驱动方法，其中，
    提供的所述像素驱动电路还包括第一开关、第二开关、第三开关、第四开 关、第五开关、发光二极管、第一控制信号端、第二控制信号端、第三控制信号、初始电压信号端、数据电压信号端和驱动电压信号端；所述栅极端与所述漏极端之间设置所述第一开关，且所述栅极端通过所述第二开关连接于所述初始电压信号端；所述源极端通过所述第三开关和所述第四开关分别连接于所述驱动电压信号端和所述数据电压信号端，所述第五开关连接于所述漏极端和所述发光二极管之间；所述第一控制信号端连接于所述第一开关的控制端、所述第三开关的控制端及所述第四开关的控制端；所述第二控制信号端连接于所述第二开关的控制端；所述第三控制信号端连接于所述第五开关的控制端；
    所述复位阶段中，设置所述第一控制信号端和所述第三控制信号端加载高电平信号，且所述第二控制信号端加载低电平信号，以使所述第二开关和所述第三开关导通，及所述第一开关、所述第四开关和所述第五开关关断，所述栅极端通过所述第二开关加载所述初始电压，所述源极端通过所述第三开关加载所述驱动电压。
  13. 如权利要求12所述的像素驱动方法，其中，所述存储阶段中，设置所述第一控制信号端加载低电平信号，且所述第二控制信号端和所述第三控制信号端加载高电平信号，以使所述第一开关和所述第四开关导通，及所述第二开关、所述第三开关和所述第五开关关断，所述源极端通过所述第四开关加载所述数据电压，所述数据电压为Vdata，所述数据电压通过所述第四开关、所述驱动晶体管及所述第一开关对所述栅极端充电，并使得所述栅极端的电位为Vdata-Vth。
  14. 如权利要求13所述的像素驱动方法，其中，
    提供的所述像素驱动电路还包括负极电压信号端，所述发光二极管具有正极端和负极端，所述第五开关连接于所述漏极端和所述正极端之间，所述负极端连接于所述负极电压信号端；
    所述发光阶段，设置所述第一控制信号端和所述第二控制信号端加载高电平信号，且所述第三控制信号端加载低电平信号，以使所述第三开关和所述第五开关导通，及所述第二开关、所述第一开关和所述第四开关关断；所述源极端通过所述第三开关加载所述驱动电压，所述驱动电压为Vdd，并使得所述栅极端电位为Vdata-Vth+δV，所述源极端的电位与所述栅极端的电位之差为 Vdd-Vdata+Vth-δV，所述δV＝(Vdd-Vdata)*C2/(C1+C2)，所述C1为所述第一电容的电容值，所述C2为所述第二电容的电容值，以使所述驱动电流与所述阈值电压无关；所述第三开关、所述驱动晶体管及所述第五开关导通使得所述驱动电压信号端与所述负极电压信号端导通，以便于所述驱动电流驱动所述发光二极管发光。
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JP6844034B2 (ja) 2021-03-17
EP3618045A1 (en) 2020-03-04
US10522079B2 (en) 2019-12-31
CN106960659B (zh) 2019-09-27
KR102350681B1 (ko) 2022-01-12
KR20190141755A (ko) 2019-12-24

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