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WO2018192523A1 - 一种显示基板及显示装置 - Google Patents

一种显示基板及显示装置 Download PDF

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Publication number
WO2018192523A1
WO2018192523A1 PCT/CN2018/083555 CN2018083555W WO2018192523A1 WO 2018192523 A1 WO2018192523 A1 WO 2018192523A1 CN 2018083555 W CN2018083555 W CN 2018083555W WO 2018192523 A1 WO2018192523 A1 WO 2018192523A1
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Prior art keywords
trace
fan
display substrate
data signal
fanout
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PCT/CN2018/083555
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English (en)
French (fr)
Inventor
尚建兴
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/303,310 priority Critical patent/US10983618B2/en
Publication of WO2018192523A1 publication Critical patent/WO2018192523A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display substrate and a display device.
  • a high definition Full In Cell (HD FIC) touch screen needs to be provided with a fanout (Fanout) area to lead the signal line of the display area through the trace, because the fan-out area is opposite to the display area. It is small, and the number of signal lines that need to be extracted is large. When the data signal line of the display area is taken out, the wiring needs to be inclined.
  • Fanout Fanout
  • the display substrate includes: a data signal line located in a display area of the display substrate; and
  • the data signal fanout trace further includes a second fanout trace disposed in the same layer as the source drain electrode of the display substrate and a third layer disposed in the same layer as the gate electrode of the display substrate. Fan out the line.
  • the display substrate further includes a bonding trace at the landing region, wherein the bonding region is located on a side of the fan-out region remote from the display region; the bonding traces are respectively associated with The data signal fanout traces are connected one by one.
  • the bonding trace includes a first bonding trace disposed in the same layer as the source drain electrode and a second bonding trace disposed in the same layer as the gate electrode;
  • first fanout trace is connected to at least one of: the first bond trace and the second bond trace.
  • the second fanout trace is connected to the first bond trace
  • the third fanout trace is connected to the second bond trace.
  • the number of the first fanout traces connected to the first bond trace is equal to the first of the second bond traces connected to the same layer as the gate electrode The number of fanouts.
  • the display substrate further includes a first insulating layer between the source drain electrode and the touch electrode;
  • the first fan-out trace is connected to the data signal line through the first connection hole and the second connection hole.
  • the display substrate further includes a third connection hole penetrating the first insulation layer and the second insulation layer;
  • the first fan-out trace is connected to the first bonding trace through the third connection hole and the fourth connection hole.
  • the display substrate further includes a third insulating layer between the source drain electrode and the gate electrode;
  • connection hole penetrating the first insulation layer, the second insulation layer, and the third insulation layer; and a sixth connection hole disposed in the second insulation layer
  • the first fan-out trace is connected to the second bonding trace through the fifth connection hole and the sixth connection hole.
  • the display substrate further includes a touch signal line disposed in the display area and disposed on the touch electrode through layer;
  • a touch signal fan-out route is located in the fan-out area and is respectively connected to the touch signal lines in one-to-one correspondence.
  • the data signal fanout trace and the touch signal fanout trace are spaced apart from each other.
  • an angle at which the first fan-out trace is inclined with respect to an extending direction of the data signal line is greater than a preset value, such that an interval between the first fan-out trace and an adjacent trace is greater than The aperture of the connection hole in the second insulating layer.
  • the touch signal line includes a virtual touch signal line
  • the first fan-out line includes a virtual touch signal fan-out line corresponding to the virtual touch signal line
  • a display device comprising the display substrate according to any of the above.
  • FIG. 1A is a schematic structural diagram of a display substrate according to an embodiment of the present invention.
  • FIG. 1B is a schematic structural diagram of a display substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a display substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a display substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a display substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a display substrate according to an embodiment of the present invention.
  • the spacing between the traces of the fan-out area is narrowed, and a short circuit is prone to occur.
  • the display area A total of 2,160 data signal lines.
  • the data signal fan-out traces on the same layer as the gate electrodes and the data signal fan-out traces on the same layer as the source-drain electrodes are 1080.
  • the data signal is transmitted.
  • the fan-out area of the fan-out area is in the same layer as the gate electrode, and the data signal fan-out line in the same layer as the source-drain electrode is densely arranged.
  • the thinning technique there is still a problem of short-circuiting between the respective layer data signal fan-out traces that are in the same layer as the gate electrode and in the same layer as the source-drain electrodes.
  • the inventors In order to reduce the set density of the data signal fanout traces disposed in the same layer as the source and drain electrodes and/or the data signal fanout traces disposed in the same layer as the gate electrodes, the inventors consider setting a portion of the data signal fanout traces to be provided in other In the process of implementing the present invention, the inventors have found that the traces disposed in the layer where the touch electrodes of the fan-out area in the in-cell touch panel are located (referred to as "touch electrode layers”) are relatively sparse, and A part of the trace is placed in the layer where the touch electrode is located to conduct the data signal.
  • touch electrode layers the traces disposed in the layer where the touch electrodes of the fan-out area in the in-cell touch panel are located
  • An embodiment of the present invention provides a display substrate, as shown in FIG. 1A, including a display area 001 and a fan-out area 002 adjacent to the display area.
  • the display area 001 includes a plurality of data set in the same layer as the source and drain electrodes SD.
  • the signal line 011; the fan-out area 002 includes a plurality of data signal fan-out traces 021 (see FIG. 1B) connected in one-to-one correspondence with the respective data signal lines.
  • the data signal fanout trace includes a first fanout trace 213 disposed in the same layer as the touch electrode T of the display substrate.
  • the data signal fanout traces of different layers are represented by different fills.
  • the data signal fanout trace 021 may further include a second fan-out trace 211 disposed in the same layer as the source drain electrode of the display substrate and a same layer as the gate electrode of the display substrate.
  • the third fan exit 212 may be included in Figure 1B.
  • the traces illustrated in the figure are inclined at a certain angle when the fan-out area is taken out, and tend to gather toward the middle.
  • the figure only shows the width and spacing of the traces and does not represent the true scale.
  • the area where the second fan-out trace 211 is located is overlapped with the area where the third fan-out trace 212 is located.
  • the area where the second fan-out trace 211 is located is overlapped with the area where the third fan-out trace 212 is located.
  • the layer where the touch electrode is located ie, the touch electrode layer
  • the layer where the gate electrode is located ie, the gate electrode layer
  • the layer where the source and drain electrodes are located ie, the source and drain electrodes
  • Electrode layer The three film layers are provided with data signal fanout traces (first fanout trace, second fanout trace, and third fanout trace), and the layer where the gate electrode is located and the source and drain electrodes are located. Compared with the data signal fan-out traces on the film layer (the second fan-out trace and the third fan-out trace), the data signal fan disposed in the same layer as the gate electrode and/or disposed in the same layer as the source-drain electrode can be reduced.
  • the number of traces (second fan traces and/or third fan traces), thereby reducing the data signal fanout trace of the gate electrode layer and/or source drain electrode layer (second fanout trace and/or The set density of the third fan exit line).
  • the distance between the obliquely arranged traces is increased, at least between the data signal fanout traces (especially between the second fanout trace and/or the third fanout trace). The risk of a short circuit.
  • the number of the first fanouts can be set according to actual needs, as long as the short circuit problem does not occur between the traces in the layer where the touch electrodes are located.
  • the number of data signal lines is constant, under certain conditions, the more the number of the first fan-out traces, the fewer the number of the second fan-out traces and the third fan-out traces, and the more favorable the reduction of the traces. The risk of short circuit between. As the number of third traces increases, it is necessary to appropriately reduce the width of the traces.
  • the display substrate further includes a bonding region on a side of the fan-out region remote from the display region, such as an integrated circuit (IC bonding) region.
  • IC bonding integrated circuit
  • the traces need to be separated according to different layers and signals, and the touch electrode layer integrated circuit (Touch IC) region (not shown) leads to the touch layer disposed on the same layer as the touch electrode.
  • the signal trace is drawn in the source-drain electrode layer integrated circuit (SD IC) region, and the data signal trace is set in the same layer of the source/drain electrode, and is extracted from the gate electrode layer integrated circuit (Gate IC) region. Layer data signal routing.
  • the first fanout trace (the data signal fanout trace provided in the same layer as the touch electrode) 213 to the bond trace disposed in the same layer as the source drain electrode (for example, data signal integrated circuit thermocompression bonding) Traces) or bond traces placed in the same layer as the gate electrode (eg, data signal integrated circuit thermobond traces).
  • the fan-out area includes a bonding area on a side of the fan-out area away from the display area (for example, a hot-stamped integrated circuit hot-welded area)
  • the joint area 003 includes a plurality of joint traces 031 which are respectively connected to the fan-out traces 021 in one-to-one correspondence.
  • the bonding trace 031 may include a first bonding trace 311 disposed in the same layer as the source drain electrode and a second bonding trace 312 disposed in the same layer as the gate electrode.
  • the second fanout trace 211 can be connected to the first bond trace 311; the third fanout trace 212 is connected to the second trace 312; the first fanout trace 213 is the first fanout trace 213 Connected to at least one of: a first bond trace 311 and a second bond trace 312. Illustrated in the figure is the case where the first fan-out traces 213 are connected to the first bond traces 311 and the second bond traces 312, respectively. In the implementation, the number of the first fanouts distributed to the first bonding wires and the number of the second bonding wires may also be set according to actual needs.
  • the number of first fan-out traces connected to the first bond trace is equal to the number of first fan-out traces connected to the second bond trace. In this way, the first fan-out trace is evenly distributed to the first bond trace and the second bond trace, which ensures that the number of wirings of the layer where the source drain electrode is located and the layer where the gate electrode is located is all the same when the fan-out region is obliquely wired. It may be reduced, and the short circuit problem is better improved.
  • the layer where the touch electrode is located is different from the layer where the source and drain electrodes are located and the layer where the gate electrode is located, in the specific implementation, it is necessary to provide a connection hole to realize the connection between the different film layers.
  • the following is exemplified by a specific structure.
  • the display substrate provided by the embodiment of the present invention further includes a first insulating layer between the source and drain electrodes and the touch electrode, and a second covering the touch electrode layer and the first insulating layer. Insulation;
  • the first fan-out trace 213 passes through the first connection hole 006 penetrating the first insulation layer 004 and the second insulation layer 005, and the second connection hole 007 and the first connection line disposed in the second insulation layer. 008 is connected to the data signal line 011.
  • the left side of the dotted line is the end of the first fan-out line 213 near the display area, and the right side is the end near the land.
  • the first fanout trace 213 passes through the third connection hole 009 penetrating the first insulation layer 004 and the second insulation layer 005, and is disposed on the second insulation layer 005.
  • the fourth connection hole 0010 and the second connection line 0011 are connected to the first bonding wire 311.
  • the display substrate provided by the embodiment of the present invention further includes a third insulating layer 0012 between the source and drain electrodes and the gate electrode;
  • the first fan exit line 213 passes through the fifth connection hole 0013 penetrating through the first insulating layer 004, the second insulating layer 005, the third insulating layer 0012, and the sixth connecting hole 0014 and the third hole disposed in the second insulating layer 005.
  • the connection line 0015 is connected to the second bonding trace 312.
  • the first fanout 213 is disposed in a plurality of manners.
  • the display substrate further includes a display substrate and is disposed in the same layer as the touch electrode.
  • the plurality of touch signal lines 012; the fan-out area further includes a plurality of touch signal fan-out traces 022 respectively connected to the touch signal lines; the first fan-out traces 213 and the touch signal fan-out traces 022 Set apart from each other.
  • a touch signal fanout trace 022 can be set every predetermined number of data signal fanout traces 021.
  • FIG. 5 an example is shown in which a touch signal fanout trace 022 is set every four fanout traces 021.
  • the touch signal line 012 may include a virtual touch signal line 013, and the first fan-out line 213 includes a virtual touch signal fan-out line 213a corresponding to the virtual touch signal line. .
  • the touch signal line 012 may include a virtual touch signal line 013
  • the first fan-out line 213 includes a virtual touch signal fan-out line 213a corresponding to the virtual touch signal line.
  • the number of the first fanout lines can be equal to the number of virtual touch signal lines.
  • the display area is provided with 2160 data signal lines, 576 touch signal lines, and 144 virtual touch signal lines.
  • one virtual touch signal line is set every four touch signal lines.
  • 2160 traces need to be arranged obliquely to extract 2160 data signal lines.
  • the layer where the touch electrodes are located in addition to the one-to-one connection with the 576 touch signal lines.
  • 144 data signal fanout traces are also set at positions corresponding to the extension lines of the fanout area of the 144 virtual touch signal lines, so that the data signal fan at the layer where the source and drain electrodes are located
  • the data signal fanout traces of the layer where the trace and the gate electrode are located can be set to only 1008, respectively, so that the wiring density can be reduced, the interval between the traces can be increased, and the risk of short circuit can be reduced.
  • the SD IC region is provided with 1080 first bonding traces disposed in the same layer as the source/drain electrodes, and the Gate IC region is provided with 1080 electrodes disposed in the same layer as the gate electrodes.
  • the second bonding trace has 576 touch signals to connect the traces in the Touch IC area.
  • 1008 second fan exit lines are directly connected with 1008 first joint traces
  • 1008 third fan exit lines are directly connected with 1008 second joint lines.
  • Lines can be connected one by one.
  • 72 odd-numbered first fan-out traces are connected in one-to-one correspondence with 72 first bond traces (or second bond traces), and 72 even-numbered first fans leave the first fan
  • the line is connected in one-to-one correspondence with 72 second bonding traces (or first bonding traces).
  • the SD IC area of the junction area leads to 1080 data signal integrated circuit bonding traces
  • the Gate IC area leads to 1080 data signal integrated circuit bonding traces
  • the Touch IC area leads to 576 touch signal integrated circuit bonding traces.
  • the trace density of the layer where the source drain electrode is located and the layer where the gate electrode is located can be reduced by more than 6.67%, and finally the occurrence rate of the short-circuit of the fan-out region can be reduced by about 0.5%.
  • the spacing between the traces is small, and the diameter of the connection hole is provided when the connection hole is provided on the fan-out line of the layer where the touch electrode is located (referred to as "touch electrode layer”)
  • the line width is larger than the line width of the trace.
  • the adjacent traces of the fan-out trace of the touch electrode layer may be covered. Therefore, it is necessary to appropriately increase the interval between the traces to ensure that there is enough space for the connection holes. Therefore, in other embodiments, as shown in FIG. 6, the data signal fanout trace of the touch electrode layer (the first fanout trace) is opposite to the data signal line.
  • the angle a of the extending direction tilt is greater than a preset value such that the interval between the data signal fanout trace and the adjacent trace is larger than the aperture of the connection hole in the second insulating layer.
  • the dotted elliptical area 214 in Fig. 6 illustrates the set area of the connection hole.
  • the solution of the embodiment of the present invention is applicable to an in-cell touch panel, such as an in-line Thin Film Transistor LCD (TFT-LCD), and the like.
  • TFT-LCD Thin Film Transistor LCD
  • an embodiment of the present invention further provides a display device, including the display substrate according to any of the above embodiments.
  • the data signal fan-out traces are disposed on the three layers of the touch electrode layer, the gate electrode layer and the source/drain electrode layer, thereby reducing the gate electrode layer and the source and drain electrodes.
  • the number of the data signal fan-out traces of the electrode layer (the second fan-out trace and the third fan-out trace) can be set, thereby reducing the setting density of the data signal fan-out trace of the gate electrode layer and the source-drain electrode layer, from the display
  • the distance between the obliquely arranged traces is increased, and the fan-out traces of the respective layers of the gate electrode layer and the source-drain electrode layer are reduced (the second fan-out trace and the third fan-out trace) The risk of short circuit between.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Human Computer Interaction (AREA)
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Abstract

一种显示基板及显示装置，显示基板包括：位于显示基板的显示区（001）的数据信号线（011）；和位于显示基板的邻近显示区（001）的扇出区（002）且与数据信号线（011）一一对应连接的扇出走线（021），其中，数据信号扇出走线（021）包括与显示基板的触控电极（T）同层设置的第一扇出走线（213）。

Description

一种显示基板及显示装置
相关申请的交叉引用
本申请要求于2017年4月21日递交的中国专利申请第201710264273.0号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本发明涉及显示技术领域，尤其涉及一种显示基板及显示装置。
背景技术
目前，高解析度内嵌式(High Definition Full In Cell，HD FIC)触控屏，需要设置扇出(Fanout)区将显示区的信号线通过走线引出，由于扇出区相对显示区的区域较小，而需要引出的信号线的数量较多，在将显示区的数据信号线引出时，走线需要倾斜布线。
发明内容
本发明的一方面提供了一种显示基板。所述显示基板包括：位于所述显示基板的显示区的数据信号线；和
位于所述显示基板的邻近所述显示区的扇出区且与所述数据信号线一一对应连接的数据信号扇出走线，其中，所述数据信号扇出走线包括与所述显示基板的触控电极同层设置的第一扇出走线。
在一个实施例中，所述数据信号扇出走线还包括与所述显示基板的源漏极电极同层设置的第二扇出走线以及与所述显示基板的栅极电极同层 设置的第三扇出走线。
在一个实施例中，所述显示基板还包括位于接合区的接合走线，其中，所述接合区位于所述扇出区的远离所述显示区的一侧，；所述接合走线分别与所述数据信号扇出走线一一对应连接。
在一个实施例中，所述接合走线包括与所述源漏极电极同层设置的第一接合走线和与栅极电极同层设置的第二结合走线；
其中，所述第一扇出走线线连接到下列二者中的至少一者：所述第一接合走线和所述第二接合走线。
在一个实施例中，所述第二扇出走线连接到所述第一接合走线；
其中，所述第三扇出走线连接到所述第二接合走线。
在一个实施例中，连接到所述第一接合走线的所述第一扇出走线的数量等于连接到与所述栅极电极位于同一层的所述第二接合走线的所述第一扇出走线的数量。
在一个实施例中，所述显示基板还包括位于所述源漏极电极与所述触控电极之间的第一绝缘层；
覆盖所述触控电极、所述第一绝缘层的第二绝缘层；
贯穿所述第一绝缘层、所述第二绝缘层的第一连接孔；
以及设置于所述第二绝缘层中的第二连接孔，
其中，所述第一扇出走线通过所述第一连接孔以及所述第二连接孔与所述数据信号线连接。
在一个实施例中，所述显示基板还包括贯穿所述第一绝缘层、所述第二绝缘层的第三连接孔；
以及设置于所述第二绝缘层中的第四连接孔，
其中所述第一扇出走线通过所述所述第三连接孔和所述第四连接孔 而连接到所述第一接合走线。
在一个实施例中，所述显示基板还包括位于所述源漏极电极与所述栅极电极之间的第三绝缘层；
贯穿所述第一绝缘层、第二绝缘层、所述第三绝缘层的第五连接孔；以及设置于所述第二绝缘层中的第六连接孔，
其中，所述第一扇出走线通过所述第五连接孔以及所述第六连接孔而连接到所述第二接合走线。
在一个实施例中，所述显示基板还包括位于所述显示区且与所述触控电极通层设置的触控信号线；
位于所述扇出区且分别与所述触控信号线一一对应连接的触控信号扇出走线。
在一个实施例中，所述所述数据信号扇出走线与所述触控信号扇出走线相互间隔设置。
在一个实施例中，所述第一扇出走线相对所述数据信号线的延伸方向倾斜的角度大于预设值，使得所述第一扇出走线与相邻的走线之间的间隔大于所述第二绝缘层中的连接孔的孔径。
在一个实施例中，所述触控信号线包括虚拟触控信号线，所述第一扇出走线包括对应于所述虚拟触控信号线的虚拟触控信号扇出走线。
一种显示装置，包括如以上任一项所述的显示基板。
附图说明
图1A为本发明实施例提供的显示基板的结构示意图；
图1B为本发明实施例提供的显示基板的结构示意图
图2为本发明实施例提供的一种显示基板的结构示意图；
图3为本发明实施例提供的一种显示基板的结构示意图；
图4为本发明实施例提供的一种显示基板的结构示意图；
图5为本发明实施例提供的一种显示基板的结构示意图；
图6为本发明实施例提供的一种显示基板的结构示意图。
具体实施方式
为了便于理解本发明的方案，下面首先对本发明的方案的基本思路进行介绍：扇出区的走线之间的间距就会变窄，容易发生短路，例如，在一种结构中，显示区内数据信号线共计2160根，目前方案中，在扇出区，与栅极电极位于同一层的数据信号扇出走线、与源漏极电极位于同一层的数据信号扇出走线分别为1080根，来传导数据信号，该方案中，扇出区的与栅极电极位于同一层的数据信号扇出走线、与源漏极电极位于同一层的数据信号扇出走线的设置较密集，实际生产过程中，在使用了细线化技术之后，仍一直伴随着与栅极电极位于同一层和与源漏极电极位于同一层的各自层数据信号扇出走线之间短路的问题。
为了减少与源漏极电极同层设置的数据信号扇出走线和/或与栅极电极同层设置的数据信号扇出走线的设置密度，发明人考虑将一部分数据信号扇出走线设置于其它的导电层，在实现本发明的过程中，发明人发现在内嵌式触摸屏中扇出区的触控电极所在的层(称为“触控电极层”)中设置的走线相对较稀疏，可以在触控电极所在的层中设置一部分走线来传导数据信号。下面结合附图和实施例对本发明提供的方案进行更详细地说明。
本发明实施例提供一种显示基板，如图1A所示，包括显示区001和邻近显示区的扇出区002；其中：显示区001包括与源漏极电极SD同层 设置的的多条数据信号线011；扇出区002包括多条与各数据信号线一一对应连接的数据信号扇出走线021(见图1B)。数据信号扇出走线包括与所述显示基板的触控电极T同层设置的第一扇出走线213。
图1B中通过不同的填充体现不同的膜层的数据信号扇出走线。如图1B所示，在一个实施例中，数据信号扇出走线021还可以包括与显示基板的源漏极电极同层设置的第二扇出走线211以及与显示基板的栅极电极同层设置的第三扇出走线212。
需要说明的是，由于扇出区相对显示区较窄，因而图中示意的走线在扇出区引出时倾斜一定的角度，有向中间聚拢的趋势。图中只是示意出了走线的宽度和间隔，并不代表真实的比例。
还需要说明的是，为了保证透过率，一般，第二扇出走线211所在区域与第三扇出走线212所在区域是重叠设置的，图1B的俯视图中为了体现出两个膜层，未体现这一点。
本发明实施例中，在触控电极所在的层(即，触控电极层)、栅极电极所在的层(即，栅极电极层)和源漏极电极所在的层(即，源漏极电极层)三个膜层设置数据信号扇出走线(第一扇出走线、第二扇出走线和第三扇出走线)，与在栅极电极所在的层和源漏极电极所在的层两个膜层上设置数据信号扇出走线(第二扇出走线和第三扇出走线)相比，可以降低与栅极电极同层设置和/或与源漏极电极同层设置的数据信号扇出走线(第二扇出走线和/或第三扇出走线)的数量，从而可以降低栅极电极层和/或源漏极电极层的数据信号扇出走线(第二扇出走线和/或第三扇出走线)的设置密度。从显示区引出数据信号时，倾斜布置的走线之间的距离增大，至少能够降低了数据信号扇出走线之间(尤其是第二扇出走线和/或第三扇出走线之间)的短路的风险。
具体实施时，第一扇出走线的数量可以根据实际需要进行设置，只要保证触控电极所在的层中的走线之间不会出现短路问题即可。当然，由于数据信号线的数量是一定的，在一定条件下，第一扇出走线的数量越多，第二扇出走线和第三扇出走线的数量就越少，越有利于降低走线之间短路的风险。随着第三走线的数量的增多，需要适当的降低走线的宽度。
一般，显示基板还包括位于所述扇出区的远离所述显示区的一侧的接合区，例如集成电路热压焊(IC bonding)区。在接合区，需要按照不同的膜层及信号分成几个区域将走线引出，触控电极层集成电路(Touch IC)区域(图中未示出)引出与触控电极同层设置的触控信号走线，在源漏极电极层集成电路(SD IC)区域引出于源漏极电极同层设置的数据信号走线，在栅极电极层集成电路(Gate IC)区域引出与栅极电极同层设置的数据信号走线。基于此，需要将第一扇出走线(与触控电极同层设置的数据信号扇出走线)213连接至与源漏极电极同层设置的接合走线(例如，数据信号集成电路热压焊走线)或者与栅极电极同层设置的接合走线(例如，数据信号集成电路热压焊走线)。
如图2所示，本发明实施例提供的显示基板中，扇出区包括位于所述扇出区的远离所述显示区的一侧的接合区(例如，热压焊集成电路热压焊区)003；接合区003包括多条分别与各扇出走线021一一对应连接的接合走线031。
进一步地，图2中，仍是以不同的填充体现不同的膜层的接合走线。例如，接合走线031可以包括与源漏极电极同层设置的第一接合走线311和与栅极电极同层设置的第二结合走线312。
在一个实施例中，所第二扇出走线211可以连接到第一接合走线311；第三扇出走线212连接到第二接走线312；第一扇出走线213第一扇出走 线213连接到下列二者中的至少一者：第一接合走线311和所述第二接合走线312。图中示例的是第一扇出走线213分别连接到第一接合走线311和第二接合走线312的情况。实施中，第一扇出走线分配至第一接合走线的数量以及分配至第二接合走线的数量，也可以根据实际需要进行设置。如果分配的数量越多，那么，相应的膜层在扇出区设置的数据信号扇出走线就越稀疏，在从显示区引出数据信号时，短路的风险就越小。具体实施时，在一个实施例中，连接到第一接合走线第一扇出走线的数量等于连接到第二接合走线第一扇出走线的数量。这样，将第一扇出走线均匀分配给第一接合走线和第二接合走线，保证了扇出区倾斜布线时源漏极电极所在层和栅极电极所在的层的布线的数量都尽可能减少，短路问题都得到较好的改善。
由于触控电极所在的层与源漏极电极所在的层、栅极电极所在的层是不同的膜层，具体实施时，需要设置连接孔实现不同膜层之间的走线的连接。下面通过具体的结构进行举例说明。
具体实施时，在一个实施例中，本发明实施例提供的显示基板还包括位于源漏极电极与触控电极之间的第一绝缘层、覆盖触控电极层、第一绝缘层的第二绝缘层；
如图3所示，第一扇出走线213通过贯穿第一绝缘层004、第二绝缘层005的第一连接孔006以及设置于第二绝缘层中的第二连接孔007以及第一连接线008而与数据信号线011连接。
图中，点划线左侧为第一扇出走线213靠近显示区的一端，右侧为靠近接合区的一端。
具体实施时，在一个实施例中，如图3所示，第一扇出走线213，通过贯穿第一绝缘层004、第二绝缘层005的第三连接孔009以及设置于第 二绝缘层005中的第四连接孔0010以及第二连接线0011，与第一接合走线311连接。
具体实施时，在一个实施例中，如图4所示，本发明实施例提供的显示基板还包括位于源漏极电极与栅极电极之间的第三绝缘层0012；
第一扇出走线213，通过贯穿第一绝缘层004、第二绝缘层005、第三绝缘层0012的第五连接孔0013以及设置于第二绝缘层005中的第六连接孔0014以及第三连接线0015，与第二接合走线312连接。
具体实施时，第一扇出走线213的具体设置方式有多种，具体实施时，如图5所示，在一个实施例中，显示基板还包括位于显示区且与触控电极同层设置的多条触控信号线012；扇出区还包括位于多条分别与触控信号线一一对应连接的触控信号扇出走线022；该第一扇出走线213与触控信号扇出走线022相互间隔设置。
具体的，可以每隔预设条数的数据信号扇出走线021设置一条触控信号扇出走线022。图5中是以每隔4条扇出走线021设置一条触控信号扇出走线022进行示例的。
具体实施时，如图5所示，触控信号线012可以包括虚拟触控信号线013，第一扇出走线213包括对应于虚拟触控信号线的虚拟触控信号扇出走线213a。。这样，基于原有的结构进行较小的改动，设计简单。
基于此，第一扇出走线的数量可以与虚拟触控信号线的数量相等。
例如，在一种HD FIC显示结构中，显示区设置数据信号线2160根，触控信号线576根，虚拟触控信号线144根。其中，每隔4根触控信号线设置一根虚拟触控信号线。在扇出区引出数据信号时，需要倾斜布置2160根走线来将2160根数据信号线引出，这时，在触控电极所在的层除了与576根触控信号线一一对应连接的触控信号扇出走线之外，还在144根虚 拟触控信号线在扇出区延伸线分别对应的位置处设置144根数据信号扇出走线，这样，在源漏极电极所在的层的数据信号扇出走线和栅极电极所在的层的数据信号扇出走线可以分别只设置1008根，这样，就可以降低布线密度，增加走线之间的间隔，降低短路风险。
在接合区(例如，集成电路热压焊区)中，SD IC区设置1080根与源漏极电极同层设置的第一接合走线，Gate IC区设置1080根与栅极电极同层设置的第二接合走线，Touch IC区设置576根触控信号接合走线。
当数据信号扇出走线到达接合区的时候，1008根第二扇出走线直接与1008根第一接合走线一一对应连接即可，1008根第三扇出走线直接与1008根第二接合走线一一对应连接即可。对于144根第一扇出走线中，72根第奇数根第一扇出走线与72根第一接合走线(或第二接合走线)一一对应连接，72根第偶数根第一扇出走线与72根第二接合走线(或第一接合走线)一一对应连接。最后，接合区的SD IC区引出1080根数据信号集成电路接合走线，Gate IC区引出1080根数据信号集成电路接合走线，Touch IC区引出576根触控信号集成电路接合走线。
本实施例的方案，源漏极电极所在的层、栅极电极所在的层的走线密度可以降低6.67％以上，最终可以降低0.5％左右的扇出区短路发生率。
考虑到扇出区倾斜布线时，走线之间的间距较小，而在触控电极所在的层(称为“触控电极层”)的扇出走线上设置连接孔时，连接孔的直径一般大于走线的线宽，触控电极层的扇出走线相邻的走线有可能会被覆盖，因而需要适当增大走线之间的间隔，以保证有足够的空间设置连接孔，而不会对其它的走线造成影响，基于此，具体实施时，在一个实施例中，如图6所示，触控电极层的数据信号扇出走线(第一扇出走线)相对数据信号线的延伸方向倾斜的角度a大于预设值，使得数据信号扇出走线与相 邻的走线之间的间隔大于第二绝缘层中的连接孔的孔径。图6中虚线椭圆区域214示意出了连接孔的设置区域。
本发明实施例的方案，适用于内嵌式触摸屏，如内嵌式薄膜晶体管液晶显示器(Thin Film Transistor LCD，TFT-LCD)，等等。
基于同样的发明构思，本发明实施例还提供一种显示装置，包括如以上任意实施例所述的显示基板。
本发明实施例提供的显示基板及显示装置中，在触控电极层、栅极电极层和源漏极电极层三个膜层设置数据信号扇出走线，可以降低栅极电极层和源漏极电极层的数据信号扇出走线(第二扇出走线和第三扇出走线)的设置数量，从而可以降低栅极电极层和源漏极电极层的数据信号扇出走线的设置密度，从显示区引出数据信号时，倾斜布置的走线之间的距离增大，降低了栅极电极层和源漏极电极层各自层数据信号扇出走线(第二扇出走线和第三扇出走线)之间短路的风险。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (14)

  1. 一种显示基板，包括：
    位于所述显示基板的显示区的数据信号线；和
    位于所述显示基板的邻近所述显示区的扇出区且与所述数据信号线一一对应连接的数据信号扇出走线，其中，所述数据信号扇出走线包括与所述显示基板的触控电极同层设置的第一扇出走线。
  2. 如权利要求1所述的显示基板，其中，所述数据信号扇出走线还包括与所述显示基板的源漏极电极同层设置的第二扇出走线以及与所述显示基板的栅极电极同层设置的第三扇出走线。
  3. 如权利要求2所述的显示基板，其中，所述显示基板还包括位于接合区的接合走线，其中，所述接合区位于所述扇出区的远离所述显示区的一侧，且所述接合走线分别与所述数据信号扇出走线一一对应连接。
  4. 如权利要求3所述的显示基板，其中，所述接合走线包括与所述源漏极电极同层设置的第一接合走线和与所述栅极电极同层设置的第二结合走线，
    其中，所述第一扇出走线连接到下列二者中的至少一者：所述第一接合走线和所述第二接合走线。
  5. 如权利要求4所述的显示基板，其中，所述第二扇出走线连接到所述第一接合走线；
    其中，所述第三扇出走线连接到所述第二接合走线。
  6. 如权利要求4所述的显示基板，其中，连接到所述第一接合走线的所述第一扇出走线的数量等于连接到所述第二接合走线的所述第一扇出 走线的数量。
  7. 如权利要求1～6任一项所述的显示基板，其中，还包括：位于所述源漏极电极与所述触控电极之间的第一绝缘层；
    覆盖所述触控电极和所述第一绝缘层的第二绝缘层；
    贯穿所述第一绝缘层、所述第二绝缘层的第一连接孔；
    设置于所述第二绝缘层中的第二连接孔，
    其中，所述第一扇出走线通过所述第一连接孔以及所述第二连接孔与所述数据信号线连接。
  8. 如权利要求7所述的显示基板，还包括：贯穿所述第一绝缘层、所述第二绝缘层的第三连接孔；
    设置于所述第二绝缘层中的第四连接孔，
    其中，所述第一扇出走线通过所述第三连接孔以及所述第四连接孔而连接到所述第一接合走线。
  9. 如权利要求8所述的显示基板，，还包括位于所述源漏极电极与所述栅极电极之间的第三绝缘层；
    贯穿所述第一绝缘层、第二绝缘层、所述第三绝缘层的第五连接孔；以及设置于所述第二绝缘层中的第六连接孔，
    其中，所述第一扇出走线通过所述第五连接孔以及所述第六连接孔而连接到所述第二接合走线。
  10. 如权利要求9所述显示基板，还包括位于所述显示区且与所述触控电极同层设置的触控信号线；
    位于所述扇出区且分别与所述触控信号线一一对应连接的触控信号 扇出走线。
  11. 如权利要求10所述的显示基板，其中，所述数据信号扇出走线与所述触控信号扇出走线相互间隔设置。
  12. 如权利要求11所述的显示基板，其中，所述第一扇出走线相对所述数据信号线的延伸方向倾斜的角度大于预设值，使得所述数据信号扇出走线与相邻的走线之间的间隔大于所述第二绝缘层中的连接孔的孔径。
  13. 如权利要求10所述的显示基板，所述触控信号线包括虚拟触控信号线，所述第一扇出走线包括对应于所述虚拟触控信号线的虚拟触控信号扇出走线。
  14. 一种显示装置，其中，包括如权利要求1～13任一项所述的显示基板。
PCT/CN2018/083555 2017-04-21 2018-04-18 一种显示基板及显示装置 WO2018192523A1 (zh)

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