WO2018185587A1 - Imaging device and electronic apparatus - Google Patents

Abstract

Provided is an imaging device that is capable of wide dynamic range imaging. An imaging device that has pixels that have a capacitive element that has an MIS structure, wherein the semiconductor layer of the capacitive elements is a metal oxide. The capacity values of the capacitive elements can be made to vary between two or more values depending on the voltage that is applied to the capacitive elements. As a result, pixels that detect low-intensity light become high sensitivity, and pixels that detect high-intensity light become low sensitivity, which makes it possible to perform wide dynamic range imaging without any special external control.

Description

Imaging apparatus and electronic apparatus

One embodiment of the present invention relates to an imaging device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, the technical field of one embodiment of the present invention disclosed in this specification more specifically includes a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, A driving method or a manufacturing method thereof can be given as an example.

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. In addition, a memory device, a display device, an imaging device, and an electronic device may include a semiconductor device.

A technique for forming a transistor using an oxide semiconductor thin film formed over a substrate has attracted attention. For example, Patent Document 1 discloses an imaging device having a structure in which a transistor including an oxide semiconductor and having extremely low off-state current is used for a pixel circuit.

In addition, the imaging device is incorporated in various electronic devices, and is required to be able to capture images with higher resolution. Conventionally, photoelectric conversion elements using silicon as a photoelectric conversion layer have been used for image pickup apparatuses, but image pickup apparatuses using crystalline selenium, which is a material having a higher light absorption coefficient, for photoelectric conversion elements have been proposed ( Patent Document 2).

JP 2011-119711 A JP, 2014-17440, A

CMOS image sensors are being mounted on various devices, and improvement in imaging performance is expected. The dynamic range of the current CMOS image sensor is about 3 digits to 4 digits (60 dB to 80 dB), and it is desired to improve it to 5 digits to 6 digits (100 dB to 120 dB) equivalent to a silver salt film or the naked eye. .

In order to improve the dynamic range, there have been proposed a method of imaging by switching the charge storage portion in the pixel, a method of performing analog data processing, and the like. However, the processing may be delayed due to complicated software control. In addition, image quality may deteriorate due to noise or the like accompanying an increase in the number of transistors in a pixel.

Further, in order to increase the resolution of the image sensor, it is necessary to reduce the area per pixel. Since the reduction of the pixel area is accompanied by the reduction of the light receiving area of the photoelectric conversion element, the photosensitivity is lowered. One solution is to use a photoelectric conversion element with high photosensitivity using the avalanche multiplication effect.

Therefore, an object of one embodiment of the present invention is to provide an imaging device that can widen the dynamic range with a simple structure. Another object is to provide an imaging device with low power consumption. Another object is to provide an imaging device that can capture an image with less noise. Another object is to provide an imaging device with high resolution. Another object is to provide a photoelectric conversion element with high photosensitivity. Another object is to provide a highly reliable imaging device. Another object is to provide a novel imaging device or the like. Another object is to provide a method for driving the imaging device. Another object is to provide a novel semiconductor device or the like.

Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

One embodiment of the present invention relates to an imaging device that can automatically change the sensitivity of individual pixels to perform imaging.

One embodiment of the present invention is an imaging device including a capacitor in a pixel. The capacitor has a MIS structure in which a metal layer, an insulating layer, and a semiconductor layer are stacked, and the semiconductor layer includes a metal oxide.

Another embodiment of the present invention includes a photoelectric conversion element, first to fourth transistors, and a capacitor, and one electrode of the photoelectric conversion element is a source or a drain of the first transistor. One of the source and drain of the first transistor is electrically connected to one of the source and drain of the second transistor, and the other of the source and drain of the first transistor is The other of the source and the drain of the first transistor is electrically connected to the gate of the third transistor, and the one of the source and the drain of the third transistor is electrically connected to the first electrode of the capacitor. 4 is electrically connected to one of a source and a drain of the transistor 4 and the capacitor has a MIS structure in which a metal layer, an insulating layer, and a semiconductor layer are stacked. The semiconductor layer is an image pickup apparatus having a metal oxide.

The photoelectric conversion element preferably has selenium or a compound containing selenium in the photoelectric conversion layer.

The metal layer can act as one electrode and the semiconductor layer can act as the other electrode. Further, the capacitor can have a transistor structure in which a gate electrode includes a metal layer and a semiconductor layer includes a source region and a drain region.

The semiconductor layer includes a first metal oxide layer and a second metal oxide layer, and the first metal oxide layer, the second metal oxide layer, and the insulating layer overlap with each other. The first metal oxide layer has a region in contact with the insulating layer, and the band gap of the first metal oxide layer can be larger than that of the second metal oxide layer.

There may be a plurality of capacitive elements.

The metal oxide preferably includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

By using one embodiment of the present invention, an imaging device that can widen the dynamic range with a simple structure can be provided. Alternatively, an imaging device with low power consumption can be provided. Alternatively, an imaging device that can capture an image with less noise can be provided. Alternatively, an imaging device with high resolution can be provided. Alternatively, a photoelectric conversion element with high photosensitivity can be provided. Alternatively, a highly reliable imaging device can be provided. Alternatively, a novel imaging device or the like can be provided. Alternatively, a method for driving the imaging device can be provided. Alternatively, a novel semiconductor device or the like can be provided.

FIG. 6 illustrates a pixel circuit. The figure explaining the image of a wide dynamic range. 6 is a timing chart illustrating the operation of a pixel circuit. 3A and 3B illustrate a structure of a capacitor and a graph showing a CV characteristic. 3A and 3B illustrate a structure of a capacitor and a graph showing a CV characteristic. The figure explaining the relationship between illumination intensity and the electric potential of a charge storage part. FIG. 6 illustrates a pixel circuit. FIG. 6 illustrates a pixel circuit. FIG. 6 illustrates a pixel circuit. The figure which shows the structure of the pixel of an imaging device, and the block diagram of an imaging device. Sectional drawing which shows the structure of an imaging device. Sectional drawing which shows the structure of an imaging device. A cross-sectional STEM photograph of an imaging device. Sectional drawing which shows the structure of an imaging device. The perspective view of the package which accommodated the imaging device. FIG. 9 illustrates a configuration example of an electronic device.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. Note that hatching of the same elements constituting the drawings may be appropriately omitted or changed between different drawings.

(Embodiment 1)
In this embodiment, an imaging device that is one embodiment of the present invention will be described with reference to drawings.

One embodiment of the present invention is an imaging device including a capacitor in a pixel, and the capacitor has a MIS structure in which a metal layer, an insulating layer, and a semiconductor layer including a metal oxide are stacked. In the capacitor, the capacitance value can be changed to a binary value or higher depending on the applied voltage.

Therefore, a pixel that detects light with low illuminance has high sensitivity, and a pixel that detects light with high illuminance has low sensitivity. Therefore, imaging with a wide dynamic range can be performed without special control from the outside.

An example of wide dynamic range imaging will be described with reference to FIGS. FIGS. 2A to 2C are examples of images obtained by taking images of indoor interiors and people, and outdoor scenery through windows during the day. In this example, it is assumed that the illuminance difference between the indoor and the outdoor is sufficiently large, such as the illuminance when the indoor light is turned on indoors and the illuminance under sunny weather.

FIG. 2A is an example in which imaging is performed in accordance with indoor illuminance. For example, when the exposure time is set in accordance with indoors where the illuminance is low, indoors can be imaged clearly. On the other hand, outdoors where the illuminance is high is overexposed, resulting in a white and low contrast image.

FIG. 2B is an example in which imaging is performed in accordance with outdoor illuminance. Contrary to FIG. 2A, when the exposure time is set according to the outdoors where the illuminance is high, the outdoors can be imaged clearly. On the other hand, indoors with low illuminance are underexposed, resulting in black images with low contrast.

FIG. 2C is an example of an ideal image, which is a clear image both indoors and outdoors. Obtaining information in a wide range from a dark part to a bright part as in the image corresponds to imaging in a wide dynamic range. In one embodiment of the present invention, this is realized by using a MIS capacitor in a pixel.

FIG. 1 illustrates a pixel circuit of an imaging device of one embodiment of the present invention. The pixel circuit includes a photoelectric conversion element 10, a transistor 51, a transistor 52, a transistor 53, a transistor 54, and a capacitor 57.

One electrode (anode) of the photoelectric conversion element 10 is electrically connected to one of a source and a drain of the transistor 51. One electrode of the photoelectric conversion element 10 is electrically connected to one of a source and a drain of the transistor 52. The other of the source and the drain of the transistor 51 is electrically connected to the gate of the transistor 53. The gate of the transistor 53 is electrically connected to one electrode of the capacitor 57. One of the source and the drain of the transistor 53 is electrically connected to one of the source and the drain of the transistor 54.

The other electrode (cathode) of the photoelectric conversion element 10 is electrically connected to the wiring 72. A gate of the transistor 51 is electrically connected to the wiring 75. The other of the source and the drain of the transistor 53 is electrically connected to the wiring 79. A gate of the transistor 52 is electrically connected to the wiring 76. The other of the source and the drain of the transistor 52 is electrically connected to the wiring 73. The other of the source and the drain of the transistor 54 is electrically connected to the wiring 71. A gate of the transistor 54 is electrically connected to the wiring 78.

Here, the wiring 71 can function as an output line for outputting a signal from the pixel. The wiring 73, the wiring 77, and the wiring 79 can function as power supply lines. For example, the wiring 73 and the wiring 77 can function as a low potential power supply line, and the wiring 79 can function as a high potential power supply line. The wiring 75, the wiring 76, and the wiring 78 can function as signal lines for controlling on / off of each transistor.

The photoelectric conversion element 10 is preferably a photoelectric conversion element that produces an avalanche multiplication effect in order to increase the light detection sensitivity at low illuminance. In order to produce the avalanche multiplication effect, a relatively high potential HVDD (for example, 10 V or more) is required. Therefore, the wiring 72 is preferably electrically connected to a power source that can supply the potential HVDD. Note that the photoelectric conversion element 10 can be used by applying a potential that does not cause an avalanche multiplication effect.

The transistor 51 can have a function of transferring the potential of the charge accumulation unit (NR) that changes in accordance with the output of the photoelectric conversion element 10 to the charge detection unit (ND). The transistor 52 can have a function of initializing the potentials of the charge storage portion (NR) and the charge detection portion (ND). The transistor 53 can have a function of outputting a signal corresponding to the potential of the charge detection portion (ND). The transistor 54 can have a function of selecting a pixel from which a signal is read.

When a high voltage is applied to the photoelectric conversion element 10, it is necessary to use a high breakdown voltage transistor that can withstand the high voltage as a transistor connected to the photoelectric conversion element 10. As the high breakdown voltage transistor, for example, a transistor using a metal oxide in a channel formation region (hereinafter referred to as an OS transistor) or the like can be used. Specifically, OS transistors are preferably used as the transistor 51 and the transistor 52.

The transistor 51 and the transistor 52 are desired to have excellent switching characteristics, but the transistor 53 and the transistor 54 are preferably transistors having high on-state current because it is desired to have excellent amplification characteristics. Therefore, it is preferable to apply a transistor using silicon as an active layer or an active region (hereinafter, Si transistor) as the transistor 53 and the transistor 54.

With the above-described structures of the transistors 51 to 54, an imaging device with high light detection sensitivity at low illuminance and capable of outputting a signal with little noise can be manufactured. In addition, since the light detection sensitivity is high, the light capture time can be shortened and imaging can be performed at high speed.

Note that the transistor is not limited to the above structure, and an OS transistor may be applied to the transistor 53 and the transistor 54. Alternatively, Si transistors may be applied to the transistors 51 and 52. In any case, the imaging operation of the pixel circuit is possible.

Here, the operation of the pixel will be described with reference to the timing chart of FIG. In the following description, the wiring 76 connected to the gate of the transistor 52 includes VDD as “H”, GND as “L”, wiring 75 connected to the gate of the transistor 51, and wiring connected to the gate of the transistor 54. In 78, an example in which VDD is supplied as “H”, GND as “L”, and the potential of VDD is supplied to the wiring 79 connected to the source of the transistor 53 will be described. Note that a potential other than the above may be supplied to each wiring.

At time T1, the wiring 76 is set to “H”, the wiring 75 is set to “H”, and the potentials of the charge storage portion (NR) and the charge detection portion (ND) are set to the reset potential (GND) (reset operation). Note that the potential HVDD may be supplied to the wiring 76 as “H” during the reset operation.

By setting the wiring 76 to “L” and the wiring 75 to “L” at time T2, the potential of the charge storage portion (NR) changes (accumulation operation). The potential of the charge storage portion (NR) changes from GND to VDD at the maximum according to the intensity of light incident on the photoelectric conversion element 10.

At time T3, the wiring 75 is set to “H”, and the charge in the charge storage portion (NR) is transferred to the charge detection portion (ND) (transfer operation).

At time T4, the wiring 76 is set to “L” and the wiring 75 is set to “L”, and the transfer operation is finished. At this point, the potential of the charge detection unit (ND) is determined.

In a period from time T5 to T6, the wiring 76 is set to “L”, the wiring 75 is set to “L”, and the wiring 78 is set to “H”, and a signal corresponding to the potential of the charge detection portion (ND) is output to the wiring 71. That is, an output signal corresponding to the intensity of light incident on the photoelectric conversion element 10 in the accumulation operation can be obtained.

The capacitor 57 is an element of the charge detection unit (ND) and has a function of holding the potential of the charge detection unit (ND). Here, assuming that a certain amount of positive charge is transferred to the charge detection unit (ND) initialized to a low potential, the potential of the charge detection unit (ND) is set when the capacitance value of the capacitive element 57 is small. It tends to rise, and when the capacitance value of the capacitive element 57 is large, it is difficult to rise.

That is, in one embodiment of the present invention, underexposure is compensated for by reducing the capacitance value of the capacitive element 57 in imaging at low illuminance, and overexposure is prevented by increasing the capacitance value of the capacitive element 57 in imaging at high illuminance. To do.

The capacitor 57 has a MIS structure, and can have a transistor structure as shown in FIG. 4A, for example. The capacitor 57 having a transistor structure includes an electrode 41, an electrode 42, a semiconductor layer 43, an insulating layer 44, and a conductive layer 45. The electrode 41 is electrically connected to the source region and the drain region in the semiconductor layer 43.

The electrode 41 functions as one electrode of the capacitive element 57. The electrode 42 functions as the other electrode of the capacitive element 57. The semiconductor layer 43 functions as one electrode or a dielectric of the capacitor 57. The insulating layer 44 is a gate insulating film of the transistor and functions as a dielectric of the capacitor 57. The conductive layer 45 is a back gate of the transistor, and the threshold voltage can be controlled by applying a constant potential. Note that the conductive layer 45 may not be provided.

Further, the capacitor 57 may have a stacked structure in which a semiconductor layer 43 and an insulating layer 44 are provided between the electrode 41 and the electrode 42 as illustrated in FIG. Here, one embodiment of the present invention is characterized in that a metal oxide is used for the semiconductor layer 43.

FIG. 4C is an example of a CV characteristic (low frequency) indicating a change in the capacitance value (C) when a voltage (Vg) is applied between the electrodes of the capacitor 57. A solid line indicates characteristics when a metal oxide (OS) is used for the semiconductor layer 43, and a broken line indicates characteristics when silicon (Si) is used for the semiconductor layer 43. Note that, above the threshold voltage (V _th ), the characteristics of both are shown to overlap, but they may be different.

Since the capacitor 57 using a metal oxide for the semiconductor layer 43 operates as a storage device using electrons as carriers, carriers (holes) are hardly accumulated in the semiconductor layer 43 even when a negative voltage is applied. Therefore, below the threshold voltage (V _th ), the semiconductor layer 43 acts as a dielectric, and the capacitance value maintains the minimum value (C _min ). Further, when the threshold voltage (V _th ) is exceeded, carriers (electrons) are accumulated in the semiconductor layer 43, so that the capacitance value increases to a value (C _ox ) when only the insulating layer 44 acts as a dielectric. .

Therefore, before and after the threshold voltage (V _th ), the capacitance value of the capacitive element 57 can be changed to a binary value. In addition, although a value between two values can be taken in the transient state, there is also an advantage that the output changes smoothly.

On the other hand, when silicon is used for the semiconductor layer 43, it changes to an accumulation state, a depletion state, or an inversion state depending on the applied voltage, so that a stable change in capacitance value before and after the threshold voltage (V _th ) is I can't hope.

For example, the threshold voltage (V _th ) of the capacitor 57 using a metal oxide for the semiconductor layer 43 is about 1 to 2V. Therefore, in the pixel circuit shown in FIG. 1, when the potential that the charge detection unit (ND) can take depending on the detected illuminance is in the range of about 0 to 3 V, the capacitance value of the capacitor 57 is changed by the illuminance. be able to.

FIG. 6A shows the relationship between the charge detection portion (ND) and illuminance. The solid line is an example in which the MIS type capacitive element A using a metal oxide for the semiconductor layer 43 is applied to the pixel circuit, and the two broken lines are general MIM (Metal Insulator Metal) type capacitive elements B. Or it is an example at the time of applying the capacitive element C to a pixel circuit.

When the capacitive element A is used, the capacitance value of the capacitive element A varies depending on the potential of the charge detection unit (ND). Therefore, as the illuminance increases, the gradient of the potential of the charge detection unit (ND) changes so as to decrease at a certain illuminance. Therefore, pixels that detect relatively low illuminance operate with high sensitivity, and pixels that detect relatively high illuminance operate with low sensitivity, enabling imaging in a wide dynamic range from low to high illuminance. Become.

On the other hand, when the MIM type capacitive elements B and C are used in the pixel circuit, the potential of the charge detection unit (ND) changes linearly. For example, when the capacitive element B having a relatively small capacitance value is used and priority is given to sensitivity at low illuminance, the potential of the charge detection unit (ND) becomes constant above a certain illuminance. In addition, when the capacitive element C having a relatively large capacitance value is used and priority is given to sensitivity at high illuminance, sensitivity at low illuminance is greatly reduced. Therefore, when the capacitive elements B and C are used, it is difficult to widen the dynamic range.

5A and 5B, the semiconductor layer of the capacitor 57 may be a stacked layer of a semiconductor layer 43a and a semiconductor layer 43b. At this time, the semiconductor layer 43a and the semiconductor layer 43b are preferably metal oxides, and the band gap of the semiconductor layer 43a is preferably smaller than the band gap of the semiconductor layer 43b.

In this case, as shown in FIG. 5C, when the first threshold voltage (V _th1 ) is exceeded, carriers are first accumulated in the semiconductor layer 43a, so that the capacitance values are the semiconductor layer 43a and the semiconductor layer 43b. and increasing the insulating layer 44 from the value when the dielectric _{(C S1OX)} to the semiconductor layer 43b and the value when the insulating layer 44 and a dielectric _{(C S2OX).} Subsequently, when the second threshold voltage (V _th2 ) is exceeded, carriers start to be accumulated in the semiconductor layer 43b, so that the capacitance value becomes a value (C _OX ) when only the insulating layer 44 is a dielectric. To rise.

Therefore, the capacitance value of the capacitive element 57 can be changed to three values. FIG. 6B shows the relationship between the charge detection portion (ND) and the illuminance at this time. In this case, as the illuminance increases, the gradient of the potential of the charge detection portion (ND) changes so as to decrease in two steps. Therefore, the sensitivity at a low illuminance can be further increased and the sensitivity at a high illuminance can be lowered as compared with the case where the capacitance value changes to a binary value, so that imaging with a wider dynamic range is possible. In addition, the sensitivity does not change abruptly at the illuminance near the middle between the low illuminance and the high illuminance, and imaging with appropriate sensitivity is possible in a wide illuminance range.

However, since it is necessary to apply a high voltage to the capacitor 57, it is preferable to use a combination with a photoelectric conversion element using an avalanche multiplication effect.

The pixel circuit is not limited to the configuration shown in FIG. For example, as illustrated in FIG. 7A, one of the source and the train of the transistor 52 may be electrically connected to the other of the source and the drain of the transistor 51.

Alternatively, as illustrated in FIG. 7B, one electrode of the capacitor 57 may be electrically connected to one of a source and a drain of the transistor 51.

Alternatively, as illustrated in FIG. 7C, a transistor 58 having a function of resetting the node ND may be provided. One of a source and a drain of the transistor 58 is electrically connected to the wiring 73, the other of the source and the drain is electrically connected to the other of the source and the drain of the transistor 51, and a gate has a function of supplying a signal line 74 is electrically connected.

Alternatively, as illustrated in FIG. 8A, the other of the source and the drain of the transistor 54 may be electrically connected to the other of the source and the drain of the transistor 53.

Alternatively, as illustrated in FIG. 8B, the other electrode (cathode) of the photoelectric conversion element 10 and one of the source and the drain of the transistor 51 are electrically connected, and the other of the source and the drain of the transistor 51 and the capacitor The other electrode of 57 may be configured to be electrically connected.

In a configuration in which one electrode (anode) of the photoelectric conversion element 10 and one of the source or drain of the transistor 51 are electrically connected, the charge storage unit (NR) and the charge detection unit (ND) are reset to a low potential. However, the structure shown in FIG. 8B is reset to a high potential. Therefore, a wiring 73 that supplies a low potential is electrically connected to one electrode (anode) of the photoelectric conversion element 10, and a wiring 72 that supplies a high potential is electrically connected to the other of the source and the drain of the transistor 52. A wiring 84 for supplying a high potential is electrically connected to one electrode of the capacitor 57.

Alternatively, as illustrated in FIG. 8C, a back gate may be provided for each transistor (including the capacitor 57). By applying a constant voltage to the back gate, the threshold voltage of each transistor can be controlled. Note that FIG. 8C illustrates a structure in which all transistors have a back gate; however, a structure having a transistor without a back gate may be used.

Alternatively, as illustrated in FIG. 9A, a structure in which a plurality of capacitor elements each provided with a back gate are provided may be employed. Although FIG. 9A shows a structure in which the capacitive elements 57 and 59 are provided, the number may be larger. As described above, the threshold voltage can be controlled by applying a constant voltage to the back gate. Therefore, by applying different constant voltages to the back gates of the capacitive elements 57 and 59, characteristics similar to the CV characteristics shown in FIG. 5C can be obtained. That is, the capacitance value can be changed to ternary values, and imaging with a wide dynamic range can be performed.

One embodiment of the present invention may be used for a mode in which some transistors are shared by a plurality of pixels. FIG. 9B illustrates an example in which the transistors 53, 54, and 56 are shared by a plurality of pixels. The transistor 56 has a function of resetting the charge detection portion (ND2) to the potential of the wiring 82 (for example, GND) by a signal supplied from the wiring 81. Note that the configuration and operation will be briefly described below, but description of portions common to the pixel circuit shown in FIG. 1 is omitted.

The pixel 85a and the pixel 85b each have a charge accumulation portion (NR1) and a charge accumulation portion (NR2). The capacitive element 57 functions as an element of the charge storage unit (NR2).

The pixel 85a and the pixel 85b are simultaneously exposed to each other, and the signal potential of the charge storage portion (NR1) is determined. Then, the transistor 51 is turned on by a signal supplied from the wiring 75 (GTX), and each signal potential is transferred to the charge accumulation portion (NR2).

Next, in the pixel 85a, the transistor 55 is turned on by a signal supplied from the wiring 80 (TX1), the signal potential of the charge accumulation unit (NR2) is transferred to the charge detection unit (ND2), and is read as image data. .

Next, in the pixel 85b, the transistor 55 is turned on by a signal supplied from the wiring 80 (TX2), the signal potential of the charge accumulation unit (NR2) is transferred to the charge detection unit (ND2), and is read as image data. . Further, when there are pixels sharing the transistors 53, 54, and 56, the image data may be read out by the same operation as described above.

As described above, an OS transistor is preferably used as a transistor provided in the pixel circuit. The OS transistor exhibits extremely low off-state current characteristics, and the leakage current of the OS transistor normalized by the channel width is 10 × 10 ⁻²¹ A / μm (10 × 10 V) at a source-drain voltage of 10 V and room temperature (about 25 ° C.). Zept A / μm) or less.

Therefore, when an OS transistor is used for the transistor 51 and the transistor 52, a period during which charge can be held in the charge detection portion (ND) and the charge accumulation portion (NR) can be extremely long due to the low off-state current characteristics. Therefore, it is possible to apply a global shutter system in which charge accumulation operation is simultaneously performed in all pixels without complicating a circuit configuration and an operation method.

As a semiconductor material used for the OS transistor (including the capacitor elements 57 and 59), a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. A typical example is an oxide semiconductor containing indium. For example, a CAC-OS described later can be used.

The semiconductor layer is represented by an In-M-Zn-based oxide containing indium, zinc, and M (metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). It can be a membrane.

In the case where the oxide semiconductor included in the semiconductor layer is an In-M-Zn-based oxide, the atomic ratio of the metal elements of the sputtering target used for forming the In-M-Zn oxide is In ≧ M, Zn It is preferable to satisfy ≧ M. As the atomic ratio of the metal elements of such a sputtering target, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 3, In: M: Zn = 4: 2: 4.1, In: M: Zn = 5: 1: 6, In: M: Zn = 5: 1: 7, In: M: Zn = 5: 1: 8 etc. are preferable. Note that the atomic ratio of the semiconductor layer to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target.

As the semiconductor layer, an oxide semiconductor with low carrier density is used. For example, the semiconductor layer has a carrier density of 1 × 10 ¹⁷ / cm ³ or less, preferably 1 × 10 ¹⁵ / cm ³ or less, more preferably 1 × 10 ¹³ / cm ³ or less, more preferably 1 × 10 ¹¹ / cm 3. ³ or less, more preferably less than 1 × 10 ¹⁰ / cm ³ , and an oxide semiconductor having a carrier density of 1 × 10 ⁻⁹ / cm ³ or more can be used. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Accordingly, it can be said that the oxide semiconductor has stable characteristics because the impurity concentration is low and the defect state density is low.

Note that the composition is not limited thereto, and a transistor having an appropriate composition may be used depending on required semiconductor characteristics and electrical characteristics (such as field-effect mobility and threshold voltage) of the transistor. In addition, in order to obtain the required semiconductor characteristics of the transistor, it is preferable that the semiconductor layer have appropriate carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like. .

In the oxide semiconductor constituting the semiconductor layer, when silicon or carbon, which is one of Group 14 elements, is included, oxygen deficiency increases and the n-type semiconductor is formed. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

Further, when alkali metal and alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, which may increase off-state current of the transistor. For this reason, the concentration of alkali metal or alkaline earth metal (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less. To.

In addition, when nitrogen is contained in the oxide semiconductor included in the semiconductor layer, electrons as carriers are generated, the carrier density is increased, and the oxide semiconductor is easily n-type. As a result, a transistor including an oxide semiconductor containing nitrogen is likely to be normally on. Therefore, the nitrogen concentration (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is preferably 5 × 10 ¹⁸ atoms / cm ³ or less.

The semiconductor layer may have a non-single crystal structure, for example. The non-single crystal structure includes, for example, a CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor, or C-Axis Aligned and A-B-plane Annealed Crystalline Structure, a C-axis aligned crystal, and a C-axis aligned crystal structure. Includes a microcrystalline structure or an amorphous structure. In the non-single-crystal structure, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

An oxide semiconductor film having an amorphous structure has, for example, disordered atomic arrangement and no crystal component. Alternatively, an oxide semiconductor film with an amorphous structure has, for example, a completely amorphous structure and has no crystal part.

Note that the semiconductor layer may be a mixed film including two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. Good. For example, the mixed film may have a single-layer structure or a stacked structure including any two or more of the above-described regions.

Hereinafter, a structure of a CAC (Cloud-Aligned Composite) -OS which is one embodiment of a non-single-crystal semiconductor layer is described.

The CAC-OS is one structure of a material in which an element included in an oxide semiconductor is unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. Note that in the following, in an oxide semiconductor, one or more metal elements are unevenly distributed, and a region including the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. The state mixed with is also referred to as a mosaic or patch.

Note that the oxide semiconductor preferably contains at least indium. In particular, it is preferable to contain indium and zinc. In addition, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. One kind selected from the above or a plurality of kinds may be included.

For example, a CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OSs may be referred to as CAC-IGZO in particular) is an indium oxide (hereinafter referred to as InO). _X1 (X1 is greater real than 0) and.), or indium zinc oxide _{(hereinafter, in X2 Zn Y2 O Z2 (} X2, Y2, and Z2 is larger real than 0) and a.), gallium An oxide (hereinafter referred to as GaO _X3 (X3 is a real number greater than 0)) or a gallium zinc oxide (hereinafter referred to as Ga _X4 Zn _Y4 O _Z4 (where X4, Y4, and Z4 are greater than 0)) to.) and the like, the material becomes mosaic by separate into, mosaic _{InO X1} or _in X2 _Zn Y2 _{O Z2,} is a configuration in which uniformly distributed in the film (hereinafter Also referred to as a cloud-like.) A.

That, CAC-OS includes a region _{GaO X3} is the main _component, and In _{X2 Zn} Y2 _{O Z3,} or _{InO X1} is the main component region is a composite oxide semiconductor having a structure that is mixed. Note that in this specification, for example, the first region indicates that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the second region.

Note that IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. As a typical example, InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _{(1 + x0)} Ga _(1-x0) O ₃ (ZnO) _m0 (−1 ≦ x0 ≦ 1, m0 is an arbitrary number) A crystalline compound may be mentioned.

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.

On the other hand, CAC-OS relates to a material structure of an oxide semiconductor. CAC-OS refers to a region observed in the form of nanoparticles mainly composed of Ga in a material structure including In, Ga, Zn and O, and nanoparticles mainly composed of In. The region observed in a shape is a configuration in which the regions are randomly dispersed in a mosaic shape. Therefore, in the CAC-OS, the crystal structure is a secondary element.

Note that the CAC-OS does not include a stacked structure of two or more kinds of films having different compositions. For example, a structure composed of two layers of a film mainly containing In and a film mainly containing Ga is not included.

Incidentally, a region _{GaO X3} is the main _component, and In _{X2 Zn} Y2 _{O Z2} or _{InO X1} is the main component region, in some cases clear boundary can not be observed.

Instead of gallium, selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. In the case where one or a plurality of types are included, the CAC-OS includes a region that is observed in a part of a nanoparticle mainly including the metal element and a nanoparticle mainly including In. The region observed in the form of particles refers to a configuration in which each region is randomly dispersed in a mosaic shape.

The CAC-OS can be formed by a sputtering method under a condition where the substrate is not intentionally heated, for example. In the case where a CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. Good. Further, the flow rate ratio of the oxygen gas to the total flow rate of the deposition gas during film formation is preferably as low as possible. .

The CAC-OS has a feature that a clear peak is not observed when measurement is performed using a θ / 2θ scan by an out-of-plane method, which is one of X-ray diffraction (XRD) measurement methods. Have. That is, it can be seen from X-ray diffraction that no orientation in the ab plane direction and c-axis direction of the measurement region is observed.

In addition, in the CAC-OS, in an electron beam diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam), a ring-shaped high luminance region and a plurality of regions in the ring region are provided. A saddle point is observed. Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.

In addition, for example, in a CAC-OS in an In—Ga—Zn oxide, GaO _X3 is a main component by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX). It can be confirmed that the region and the region mainly composed of In _X2 Zn _Y2 O _Z2 or InO _X1 are unevenly distributed and mixed.

The CAC-OS has a structure different from that of the IGZO compound in which the metal element is uniformly distributed, and has a property different from that of the IGZO compound. That is, in the CAC-OS, a region in which GaO _X3 or the like is a main component and a region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component are phase-separated from each other, and a region in which each element is a main component. Has a mosaic structure.

Here, the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component is a region having higher conductivity than a region containing GaO _X3 or the like as a main component. _That, In _{X2 Zn} Y2 _{O Z2} or _{InO X1,} is an area which is the main component, by carriers flow, expressed the conductivity of the oxide semiconductor. Therefore, a region where In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component is distributed in a cloud shape in the oxide semiconductor, whereby high field-effect mobility (μ) can be realized.

On the other hand, areas such as _{GaO X3} is the main _component, as compared to the In _{X2 Zn} Y2 _{O Z2} or _{InO X1} is the main component area, it is highly regions insulating. That is, a region containing GaO _X3 or the like as a main component is distributed in the oxide semiconductor, whereby leakage current can be suppressed and good switching operation can be realized.

Therefore, when CAC-OS is used for a semiconductor element, the insulating property caused by GaO _{X3 and the} like and the conductivity caused by In _X2 Zn _Y2 O _Z2 or InO _X1 act complementarily, thereby increasing the An on-current (I _on ) and high field effect mobility (μ) can be realized.

In addition, a semiconductor element using a CAC-OS has high reliability. Therefore, the CAC-OS is suitable as a constituent material for various semiconductor devices.

As described above, by providing the pixel circuit with the MIS capacitor using a metal oxide in the semiconductor layer, an imaging device capable of imaging with a wide dynamic range can be formed.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 2)
In this embodiment, an example of an imaging device to which one embodiment of the present invention can be applied is described with reference to drawings.

FIG. 10A illustrates an example of a pixel structure of the imaging device including the pixel circuit described in Embodiment 1. The imaging device can include a layer 61, a layer 62, and a layer 63, each having a region that overlaps with each other.

The layer 61 has the configuration of the photoelectric conversion element 10. The photoelectric conversion element 10 includes an electrode 65 corresponding to a pixel electrode, a photoelectric conversion unit 66, and an electrode 67 corresponding to a common electrode.

The electrode 65 is preferably a low-resistance metal layer. For example, aluminum, titanium, tungsten, tantalum, silver, or a stacked layer thereof can be used.

For the electrode 67, a conductive layer having a high light-transmitting property with respect to visible light is preferably used. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene, or the like can be used. Note that the electrode 67 may be omitted.

For the photoelectric conversion unit 66, for example, a pn junction photodiode using a selenium-based material as a photoelectric conversion layer can be used. It is preferable to use a selenium-based material that is a p-type semiconductor for the layer 66a and a gallium oxide that is an n-type semiconductor for the layer 66b.

A photoelectric conversion element using a selenium-based material has a high external quantum efficiency with respect to visible light. In the photoelectric conversion element, by using the avalanche multiplication effect, a highly sensitive sensor with a large amplification of electrons with respect to the amount of incident light can be obtained. In addition, since the selenium-based material has a high light absorption coefficient, it has production advantages such that the photoelectric conversion layer can be formed as a thin film. A thin film of a selenium-based material can be formed using a vacuum evaporation method, a sputtering method, or the like.

Examples of the selenium-based material include crystalline selenium such as single crystal selenium and polycrystalline selenium, amorphous selenium, copper, indium, selenium compound (CIS), or copper, indium, gallium, selenium compound (CIGS), etc. Can be used.

The n-type semiconductor is preferably formed using a material having a wide band gap and a light-transmitting property with respect to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or an oxide in which they are mixed can be used. These materials also have a function as a hole injection blocking layer, and can reduce the dark current.

Note that the layer 61 is not limited to the above structure, and a pn junction photodiode using one of a p-type silicon semiconductor and an n-type silicon semiconductor as the layer 66a and the other of the p-type silicon semiconductor and the n-type silicon semiconductor as the layer 66b. It may be. Alternatively, a pin junction photodiode in which an i-type silicon semiconductor layer is provided between the layer 66a and the layer 66b may be used.

The pn junction photodiode or the pin junction photodiode can be formed using single crystal silicon. At this time, it is preferable that the layer 61 and the layer 62 are electrically joined using a bonding process. In addition, the pin junction photodiode can be formed using a thin film such as amorphous silicon, microcrystalline silicon, or polycrystalline silicon.

The layer 62 can be, for example, a layer including an OS transistor (the transistor 51 and the transistor 52). In the pixel circuit illustrated in FIG. 1, the potential of the charge detection unit (ND) decreases when the intensity of light incident on the photoelectric conversion element 10 is small. Since the OS transistor has an extremely low off-state current, a current corresponding to the gate potential can be accurately output even when the gate potential is extremely small. Therefore, the range of illuminance that can be detected, that is, the dynamic range can be expanded.

Further, due to the low off-state current characteristics of the transistor 51 and the transistor 52, the period in which charges can be held in the charge detection portion (ND) and the charge accumulation portion (NR) can be extremely long. Therefore, it is possible to apply a global shutter system in which charge accumulation operation is simultaneously performed in all pixels without complicating a circuit configuration and an operation method.

The layer 63 can be a supporting substrate or a layer having a Si transistor (transistor 53, transistor 54). The Si transistor can have a structure having an active region on a single crystal silicon substrate and a crystalline silicon active layer on an insulating surface. Note that in the case where a single crystal silicon substrate is used for the layer 63, a pn junction photodiode or a pin junction photodiode may be formed over the single crystal silicon substrate. In this case, the layer 61 can be omitted.

FIG. 10B is a block diagram illustrating a circuit configuration of the imaging device of one embodiment of the present invention. The imaging apparatus includes a pixel array 21 having pixels 20 arranged in a matrix, a circuit 22 (row driver) having a function of selecting a row of the pixel array 21, and a correlation double with respect to an output signal of the pixel 20. A circuit 23 (CDS circuit) for performing sampling processing, a circuit 24 (A / D conversion circuit or the like) having a function of converting analog data output from the circuit 23 into digital data, and data converted by the circuit 24 And a circuit 25 (column driver) having a function of selecting and reading out. Note that the circuit 23 may be omitted.

For example, the elements of the pixel array 21 excluding the photoelectric conversion element can be provided in the layer 62 illustrated in FIG. Elements of the circuits 22 to 25 can be provided in the layer 63. These circuits can be composed of CMOS circuits using Si transistors.

With such a structure, a transistor suitable for each circuit can be used, and the area of the imaging device can be reduced.

11A, 11 </ b> B, and 11 </ b> C are diagrams illustrating a specific configuration of the imaging device illustrated in FIG. FIG. 11A is a cross-sectional view illustrating the channel length direction of the transistors 51, 52, 53, and 54. FIG. 11B is a cross-sectional view taken along dashed-dotted line A1-A2 and illustrates a cross section of the transistor 52 in the channel width direction. FIG. 11C is a cross-sectional view taken along dashed-dotted line B1-B2, and shows a cross section of the transistor 53 in the channel width direction.

The imaging device can be a stack of layers 61 to 63. The layer 61 can include a partition 92 in addition to the photoelectric conversion element 10 having a selenium layer. The partition wall 92 is provided so as to cover the step of the electrode 65. The selenium layer used for the photoelectric conversion element 10 has a high resistance and can be configured not to be separated between pixels.

The layer 62 is provided with transistors 51 and 52 which are OS transistors and a capacitor 57. Although each of the transistors 51 and 52 and the capacitor 57 has a structure including the back gate 91, any of them may have a back gate. As shown in FIG. 11B, the back gate 91 may be electrically connected to a front gate of a transistor provided to face the back gate 91. Alternatively, the back gate 91 may be configured to be able to supply a fixed potential different from that of the front gate.

FIG. 11A illustrates a self-aligned top gate transistor as the OS transistor. However, as illustrated in FIG. 12A, a non-self-aligned top gate transistor may be used. Good. FIG. 13 is a cross-sectional STEM photograph of a part of a pixel using a non-self-aligned top gate transistor. 13 is a cross section at an arbitrary position and does not correspond to FIGS. 11A and 12A. In addition, FIG. 13 also shows wiring, contact portions, and the like not shown in FIGS. 11A and 12A.

In the layer 63, a transistor 53 and a transistor 54 which are Si transistors are provided. 11A illustrates a structure in which the Si transistor includes a fin-type semiconductor layer provided on the silicon substrate 200. However, as illustrated in FIG. 12B, the silicon substrate 201 includes an active region. It may be a planar type. Alternatively, as illustrated in FIG. 12C, a transistor including a silicon thin film semiconductor layer 210 may be used. The semiconductor layer 210 can be, for example, single crystal silicon (SOI (Silicon on Insulator)) formed on the insulating layer 220 on the silicon substrate 202. Alternatively, it may be polycrystalline silicon formed on an insulating surface such as a glass substrate. In addition, the layer 63 can be provided with a circuit for driving the pixel.

An insulating layer 93 having a function of preventing hydrogen diffusion is provided between the region where the OS transistor is formed and the region where the Si transistor is formed. Hydrogen in the insulating layer provided in the vicinity of the active regions of the transistors 53 and 54 terminates dangling bonds of silicon. On the other hand, hydrogen in the insulating layer provided in the vicinity of the oxide semiconductor layer which is an active layer of the transistors 51 and 52 is one of the factors that generate carriers in the oxide semiconductor layer.

The reliability of the transistors 53 and 54 can be improved by confining hydrogen in one layer by the insulating layer 93. In addition, since the diffusion of hydrogen from one layer to the other layer is suppressed, the reliability of the transistors 51 and 52 can be improved.

As the insulating layer 93, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used.

FIG. 14A is a cross-sectional view illustrating an example in which a color filter or the like is added to the imaging device of one embodiment of the present invention. In the cross-sectional view, a part of a region having a pixel circuit for three pixels is shown. An insulating layer 300 is formed on the layer 61 where the photoelectric conversion element 10 is formed. The insulating layer 300 can be formed using a silicon oxide film having high light-transmitting property with respect to visible light. A silicon nitride film may be stacked as a passivation film. Further, a dielectric film such as hafnium oxide may be laminated as the antireflection film.

A light shielding layer 310 may be formed on the insulating layer 300. The light shielding layer 310 has a function of preventing color mixing of light passing through the upper color filter. For the light-blocking layer 310, a metal layer such as aluminum or tungsten can be used. Further, the metal layer and a dielectric film having a function as an antireflection film may be stacked.

An organic resin layer 320 can be provided as a planarization film over the insulating layer 300 and the light shielding layer 310. A color filter 330 (color filter 330a, color filter 330b, color filter 330c) is formed for each pixel. For example, colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) are assigned to the color filters 330a, 330b, and 330c. Thus, a color image can be obtained.

An insulating layer 360 having a light-transmitting property with respect to visible light or the like can be provided over the color filter 330.

In addition, as illustrated in FIG. 14B, an optical conversion layer 350 may be used instead of the color filter 330. With such a configuration, an imaging device capable of obtaining images in various wavelength regions can be obtained.

For example, if a filter that blocks light having a wavelength shorter than or equal to that of visible light is used for the optical conversion layer 350, an infrared imaging device can be obtained. If a filter that blocks light having a wavelength of near infrared or shorter is used for the optical conversion layer 350, a far infrared imaging device can be obtained. If a filter that blocks light having a wavelength longer than or equal to that of visible light is used for the optical conversion layer 350, an ultraviolet imaging device can be obtained.

In addition, when a scintillator is used for the optical conversion layer 350, an imaging device that can be used for an X-ray imaging device or the like and obtain an image that visualizes the intensity of radiation can be obtained. When radiation such as X-rays transmitted through the subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by a photoluminescence phenomenon. Then, the photoelectric conversion element 10 detects the light to acquire image data. Further, the imaging device having the configuration may be used for a radiation detector or the like.

A scintillator contains a substance that emits visible light or ultraviolet light by absorbing energy when irradiated with radiation such as X-rays or gamma rays. For example, Gd ₂ O ₂ S: Tb, Gd ₂ O ₂ S: Pr, Gd ₂ O ₂ S: Eu, BaFCl: Eu, NaI, CsI, CaF ₂ , BaF ₂ , CeF ₃ , LiF, LiI, ZnO, etc. What was disperse | distributed to resin or ceramics can be used.

Note that the photoelectric conversion element 10 using a selenium-based material can directly convert radiation such as X-rays into electric charges, and thus can be configured to eliminate a scintillator.

As shown in FIG. 14C, a microlens array 340 may be provided over the color filter 330a, the color filter 330b, and the color filter 330c. Light passing through the individual lenses of the microlens array 340 passes through the color filter directly below and is irradiated onto the photoelectric conversion element 10. Alternatively, the microlens array 340 may be provided over the optical conversion layer 350 illustrated in FIG.

Hereinafter, an example of a package and a camera module containing an image sensor chip will be described. The configuration of the imaging device can be used for the image sensor chip.

FIG. 15A1 is an external perspective view of the upper surface side of the package containing the image sensor chip. The package includes a package substrate 410 for fixing the image sensor chip 450, a cover glass 420, and an adhesive 430 for bonding the two.

FIG. 15A2 is an external perspective view of the lower surface side of the package. The bottom surface of the package has a BGA (Ball grid array) configuration with solder balls as bumps 440. In addition, not only BGA but LGA (Land grid array), PGA (Pin grid array), etc. may be sufficient.

FIG. 15A3 is a perspective view of the package shown with the cover glass 420 and part of the adhesive 430 omitted. An electrode pad 460 is formed on the package substrate 410, and the electrode pad 460 and the bump 440 are electrically connected through a through hole. The electrode pad 460 is electrically connected to the image sensor chip 450 by a wire 470.

FIG. 15B1 is an external perspective view of the upper surface side of the camera module in which the image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 411 that fixes the image sensor chip 451, a lens cover 421, a lens 435, and the like. In addition, an IC chip 490 having functions such as a drive circuit and a signal conversion circuit of the imaging device is also provided between the package substrate 411 and the image sensor chip 451, and has a configuration as a SiP (System in package). Yes.

FIG. 15B2 is an external perspective view of the lower surface side of the camera module. The package substrate 411 has a QFN (Quad Flat No-Lead Package) configuration in which mounting lands 441 are provided on a lower surface and side surfaces. The configuration is an example, and may be a QFP (Quad Flat Package), the BGA described above, or the like.

FIG. 15B3 is a perspective view of the module shown with a part of the lens cover 421 and the lens 435 omitted. The land 441 is electrically connected to the electrode pad 461, and the electrode pad 461 is electrically connected to the image sensor chip 451 or the IC chip 490 by wires 471.

By mounting the image sensor chip in a package having the above-described form, mounting on a printed board or the like is facilitated, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

(Embodiment 3)
Electronic devices that can use the imaging device according to one embodiment of the present invention include a display device, a personal computer, an image storage device or an image playback device including a recording medium, a mobile phone, a portable game machine, and a portable data terminal , Digital book terminals, video cameras, digital still cameras and other cameras, goggles-type displays (head-mounted displays), navigation systems, sound playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction devices Automatic teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIGS.

FIG. 16A illustrates a monitoring camera, which includes a housing 951, a lens 952, a support portion 953, and the like. The imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the monitoring camera. The surveillance camera is an idiomatic name and does not limit the application. For example, a device having a function as a surveillance camera is also called a camera or a video camera.

FIG. 16B illustrates a video camera, which includes a first housing 971, a second housing 972, a display portion 973, operation keys 974, a lens 975, a connection portion 976, and the like. The operation key 974 and the lens 975 are provided in the first housing 971, and the display portion 973 is provided in the second housing 972. The imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the video camera.

FIG. 16C illustrates a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light-emitting portion 967, a lens 965, and the like. The imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the digital camera.

FIG. 16D illustrates a wristwatch-type information terminal including a housing 931, a display portion 932, a wristband 933, operation buttons 935, a crown 936, a camera 939, and the like. The display unit 932 may be a touch panel. The imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the information terminal.

FIG. 16E illustrates an example of a mobile phone, which includes a housing 981, a display portion 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like. The mobile phone includes a touch sensor in the display portion 982. All operations such as making a call or inputting characters can be performed by touching the display portion 982 with a finger, a stylus, or the like. The imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the mobile phone.

FIG. 16F illustrates a portable data terminal, which includes a housing 911, a display portion 912, a camera 919, and the like. Information can be input and output by a touch panel function of the display portion 912. The imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the portable data terminal.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

DESCRIPTION OF SYMBOLS 10 Photoelectric conversion element 20 Pixel 21 Pixel array 22 Circuit 23 Circuit 24 Circuit 25 Circuit 41 Electrode 42 Electrode 43 Semiconductor layer 43a Semiconductor layer 43b Semiconductor layer 44 Insulating layer 45 Conductive layer 51 Transistor 52 Transistor 53 Transistor 54 Transistor 55 Transistor 56 Transistor 57 Capacitor Element 58 Transistor 59 Capacitor 61 Layer 62 Layer 63 Layer 65 Electrode 66 Photoelectric conversion portion 66a Layer 66b Layer 67 Electrode 71 Wiring 72 Wiring 73 Wiring 74 Wiring 75 Wiring 76 Wiring 77 Wiring 78 Wiring 79 Wiring 81 Wiring 81 Wiring 82 Wiring 84 Wiring 85a pixel 85b pixel 91 back gate 92 partition wall 93 insulating layer 200 silicon substrate 201 silicon substrate 202 silicon substrate 210 semiconductor layer 220 insulating layer 300 Layer 310 Light shielding layer 320 Organic resin layer 330 Color filter 330a Color filter 330b Color filter 330c Color filter 340 Micro lens array 350 Optical conversion layer 360 Insulating layer 410 Package substrate 411 Package substrate 420 Cover glass 421 Lens cover 430 Adhesive 435 Lens 440 Bump 441 Land 450 Image sensor chip 451 Image sensor chip 460 Electrode pad 461 Electrode pad 470 Wire 471 Wire 490 IC chip 911 Housing 912 Display unit 919 Camera 931 Housing 932 Display unit 933 Wristband 935 Button 936 Crown 939 Camera 951 Housing 952 Lens 953 Supporting part 961 Case 962 Shutter button 963 Microphone 965 'S 967 emitting portion 971 housing 972 housing 973 display unit 974 operation keys 975 lens 976 connection portion 981 housing 982 display unit 983 operation button 984 an external connection port 985 speaker 986 microphone 987 camera

Claims (9)

A pixel has a capacitive element and a photoelectric conversion element,
The capacitive element has a MIS structure in which a metal layer, an insulating layer, and a semiconductor layer are stacked,
The imaging device in which the semiconductor layer includes a metal oxide. A photoelectric conversion element, first to fourth transistors, and a capacitor;
One electrode of the photoelectric conversion element is electrically connected to one of a source or a drain of the first transistor,
One of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor;
The other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor;
The other of the source and the drain of the first transistor is electrically connected to the gate of the third transistor;
One of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;
The capacitive element has a MIS structure in which a metal layer, an insulating layer, and a semiconductor layer are stacked,
The imaging device in which the semiconductor layer includes a metal oxide. In claim 2,
The photoelectric conversion element is an imaging device having selenium or a compound containing selenium in a photoelectric conversion layer. In any one of Claims 1 thru | or 3,
The imaging device in which the metal layer acts as one electrode and the semiconductor layer acts as the other electrode. 5. The imaging device according to claim 4, wherein the capacitor element has a transistor structure including the metal layer on a gate electrode and a source region and a drain region on the semiconductor layer. In any one of Claims 1 thru | or 3,
The semiconductor layer has a first metal oxide layer and a second metal oxide layer,
The first metal oxide layer, the second metal oxide layer, and the insulating layer have overlapping regions;
The first metal oxide layer has a region in contact with the insulating layer;
An imaging device in which a band gap of the first metal oxide layer is larger than that of the second metal oxide layer. In any one of Claims 1 thru | or 3,
An imaging apparatus having a plurality of capacitive elements. In any one of Claims 1 thru | or 3,
The metal oxide includes an imaging device including In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf). An electronic apparatus comprising the imaging device according to any one of claims 1 to 3 and a display device.

Images