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WO2018182705A1 - Éléments fusibles à semi-conducteur et leurs procédés de production - Google Patents

Éléments fusibles à semi-conducteur et leurs procédés de production Download PDF

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Publication number
WO2018182705A1
WO2018182705A1 PCT/US2017/025458 US2017025458W WO2018182705A1 WO 2018182705 A1 WO2018182705 A1 WO 2018182705A1 US 2017025458 W US2017025458 W US 2017025458W WO 2018182705 A1 WO2018182705 A1 WO 2018182705A1
Authority
WO
WIPO (PCT)
Prior art keywords
multilayered
metal layer
drain
fuse
die
Prior art date
Application number
PCT/US2017/025458
Other languages
English (en)
Inventor
Han Wui Then
Ravi Pillarisetty
Sansaptak DASGUPTA
Marko Radosavljevic
Paul B. Fischer
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2017/025458 priority Critical patent/WO2018182705A1/fr
Publication of WO2018182705A1 publication Critical patent/WO2018182705A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Definitions

  • fuse elements and methods of producing the same are disclosed.
  • Known fuse elements integrated onto semiconductor devices and/or semiconductor dies usually require metal layers and/or structures having dissimilar materials.
  • current passing through a contact disposed between two metal layers that are composed of different metals accelerates electron migration, thereby effectively rendering a respective fuse element inoperable for later operation.
  • numerous predetermined and/or selected fuse elements e.g., a portion of the fuse elements defined
  • a relatively high current e.g., a current greater than a threshold
  • these known programmable fuse elements are often implemented in read-only memory (ROM) of fabricated semiconductor devices. Because of additional processing steps, material and/or space requirements beyond normal fabrication,
  • the known fuse element 100 includes a multilayered structure 101 , which includes a first metal layer 102, an interlayer dielectric 104, a second metal layer 106 that is composed of a different material from the first metal layer 102, and a interlayer dielectric 108, which may be etched off to expose the second metal layer 106 (e.g., for programming, etc.).
  • a metal contact 110 disposed in the interlayer dielectric 104 extends between the first metal layer 102 and the second metal layer 106.
  • the first and second metal layers 102, 106 are different metals from those used in fabrication of semiconductor structures such as transistors and/or metal interconnects. Therefore, defining and/or fabricating the fuse element 100 may require additional processing time and/or costs.
  • FIG. 2 A illustrates an example wafer 200 in which the examples disclosed herein may be implemented.
  • the wafer 200 of the illustrated example consists of multiple semiconductor dies (e.g., system on a chip dies). These dies may be incorporated with semiconductor fuse elements disclosed herein during fabrication processes/steps.
  • the individual semiconductor dies are functionally tested prior to being separated (e.g., cut) from the wafer 200.
  • test patterns are provided to each individual die and each individual die is monitored to have a designated response. In some examples, faulty dies discovered during this testing are discarded.
  • an interlay er dielectric is etched (e.g., selectively etched, etched using a mask layer, etc.) to expose a drain of a transistor disposed on a die (e.g., a substrate of a die) (block 302).
  • the transistor is a gallium nitride n-type transistor.
  • multiple etching processes are used to expose the drain.
  • a dielectric layer is provided on or coupled to the exposed drain on the die (block 304).
  • the dielectric layer is deposited and/or layered onto the exposed drain of the transistor.
  • a metal interconnect is coupled to the drain via the dielectric layer (block 306).
  • the metal interconnect may be applied using a deposition and/or metallization process.
  • the dielectric layer is coupled to the drain along with metal interconnect (e.g., the both the metal interconnect and the dielectric layer are applied/provided simultaneously and/or during a same process, etc.).
  • the multilayered die structure 400 includes a gate (e.g., a gate structure, a gate precursor, etc.) 402 that includes a gate dielectric 403 and a gate spacer 405, a source (e.g., an indium gallium nitride source) 404, a drain (e.g., an indium gallium nitride drain) 406, a substrate or body (e.g., a semiconductor substrate) 410 that is composed of gallium nitride in this example, and a silicon layer 412 disposed below the body 410.
  • the example multilayered die structure 400 also includes a first interlayer dielectric 414 and a second interlayer dielectric 416 that is disposed above the first interlayer dielectric 414.
  • the example second interlayer dielectric 416 includes contact precursors or structures 418.
  • gate stand-in material e.g., a dummy material, a holder material, etc.
  • gate stand-in material 420 is disposed in the second interlayer dielectric 416 proximate and/or above the source 404.
  • another stand-in material 424 is also disposed in the second interlayer dielectric proximate the gate 402.
  • stand-in material 426 is disposed in and/or above the second interlayer dielectric 416 proximate the drain 406.
  • FIG. 4B a mask 430 has been provided above the second interlayer dielectric 416.
  • the stand-in materials 424, 426 are etched away (e.g., a chemical etch process, a wet-etch process, a mechanical etching process, etc.) based on the aforementioned pattern of the masking 430.
  • openings 434, 436 are defined at the respective contact structures 418.
  • the first interlayer dielectric 414 is not yet etched.
  • both of the stand-in materials 424, 426 are etched during the same etching process.
  • FIG. 4C depicts an additional etching process that has been used to define an opening 437 corresponding to the drain 406 and an opening 438 corresponding to the gate 402.
  • a wet chemistry etch and/or a selective etch has been performed to increase respective depths of the openings 437, 438.
  • the common materials may be applied during the same process, thereby increasing manufacturing/fabrication efficiency.
  • the metal contact 442 may have a different composition and/or processing from the metal contact 446.
  • the dielectric layer 444 and the dielectric layer 448 may differ from one another in thickness and/or composition.
  • the dielectric layers 448, 444 are composed of silicon dioxide (Si02), which may range in thickness from approximately 2 to 10 nanometers (nm), for example.
  • Si02 silicon dioxide
  • any appropriate material and/or dielectric layer stack may be used including materials with relative high dielectric constants (e.g., high kappa or K-values at a thickness of
  • a top surface 450 of the second interlayer dielectric 416 has been polished and/or etched to remove any appropriate masking or layers, thereby exposing the stand-in material 420.
  • an additional etching process may be used to etch the stand-in material 420 so that a metal connect may be coupled (e.g., electrically and/or mechanically coupled) to the source 404.
  • a voltage above a threshold is applied to the metal contact 442, thereby causing breakdown of the dielectric layer 444 and, in turn, causing an electrical short between the metal contact 442 and the drain 406.
  • the metal contact 442 is shorted to the drain 406, thereby causing an electrical coupling to be formed between the metal contact 442 and the drain 406.
  • the applied current renders an associated transistor of the fuse structure 440 to be enabled instead of disabling the transistor, as described above in connection with the known fuse element 100 of FIG. 1.
  • an interlayer dielectric is etched to expose a drain of a transistor (block 502).
  • the interlayer dielectric may be chemical etched, mechanically etched, and/or selectively etched.
  • at least portion of the drain is also etched.
  • a metal interconnect/contact is provided to the drain (block 504).
  • the metal interconnect of the illustrated example is both electrically and mechanically coupled to the gate of the transistor.
  • FIGS. 6A and 6B are detailed cross-sectional views of an example multilayered fuse device 600 produced using the example method 500 of FIG. 5.
  • the example fuse device 600 includes a fuse structure (e.g., a multilayer fuse, a layered fuse stack-up, layering leading up to and including the drain 406) 602, which is described below in detail in connection with FIG. 6B, an interlayer dielectric 604, a layered portion (e.g., a portion that is added to define fuse functionality) 608, and a metal contact (e.g., a trench contact metal) 610.
  • a fuse structure e.g., a multilayer fuse, a layered fuse stack-up, layering leading up to and including the drain 406
  • an interlayer dielectric 604 e.g., a layered portion that is added to define fuse functionality
  • a metal contact e.g., a trench contact metal
  • the fuse structure 602 is shown in detail.
  • the layered portion 608 includes an upper metal layer 620, a reactive metal layer 622 that is below the upper metal layer 620, and an oxygen-rich layer 624 that is below the reactive metal layer 622.
  • the metal contact 610 and the drain 406 are shown below the oxygen-rich layer 624 of the layered portion 608.
  • the reactive metal layer 622 which is implemented as hafnium in this example, is approximately 2-8 nm (e.g., 7 nm) thick.
  • tantalum or zirconium may be used instead at a similar thickness, for example.
  • the oxygen-rich layer 624 which is implemented as hafnium di-oxide in this example, is approximately 2-8 nm thick (e.g., 3 nm thick).
  • the example materials and thicknesses used are only examples, and appropriate thickness and/or material composition(s) may be used, as appropriate, for the application. Further, the layer composition and/or stacking may be varied.
  • Example 2 includes the subject matter of Example 1, and further includes a semiconductor substrate below the source and the drain.
  • Example 8 includes the subj ect matter of any one of Examples 1 to 7, where the dielectric layer includes silicon dioxide.
  • Example 15 includes a multilayered die comprising a transistor including a source, a drain, and a gate, and a multilayered fuse electrically coupled to the drain, where the multilayered fuse defines a programmable fuse element.
  • the multilayered fuse includes a first metal layer, a second metal layer including a different material from the first metal layer, a reactive metal layer disposed between the first and second metal layers, and an oxygen-rich layer proximate the reactive metal layer.
  • Example 16 includes the subject matter of Example 15, where the reactive metal layer includes hafnium.
  • Example 21 includes the subject matter of Example 20, where the oxygen-rich layer includes tantalum pentoxide.
  • Example 25 includes a method comprising etching a first interlayer dielectric to expose a drain of a transistor on a die, and coupling a multilayered fuse to the drain.
  • the multilayered fuse includes a first metal layer, a second metal layer including a different material from the first metal layer, a reactive metal layer disposed between the first and second metal layers, and an oxygen-rich layer proximate the reactive metal layer.
  • Example 26 includes the subject matter of Example 25, where coupling the multilayered fuse to the drain includes assembling the multilayered fuse to a metal interconnect that is coupled to the drain.
  • Example 34 includes the subject matter of any one of Examples 25-33, where the first metal layer includes titanium nitride.
  • Example 35 includes the subject matter of any one of Examples 25-34, where the second metal layer includes tungsten.
  • Example 35 includes the subject matter of any one of Examples 25-34, where the second metal layer includes tungsten.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

L'invention concerne des éléments fusibles à semi-conducteur et leur procédé de production. Une puce multicouche divulguée à titre d'exemple comprend un transistor comportant une source, un drain et une grille, une interconnexion métallique s'étendant à travers un diélectrique intercouche, et une couche diélectrique disposée entre l'interconnexion métallique et le drain pour définir un élément fusible programmable.
PCT/US2017/025458 2017-03-31 2017-03-31 Éléments fusibles à semi-conducteur et leurs procédés de production WO2018182705A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2017/025458 WO2018182705A1 (fr) 2017-03-31 2017-03-31 Éléments fusibles à semi-conducteur et leurs procédés de production

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2017/025458 WO2018182705A1 (fr) 2017-03-31 2017-03-31 Éléments fusibles à semi-conducteur et leurs procédés de production

Publications (1)

Publication Number Publication Date
WO2018182705A1 true WO2018182705A1 (fr) 2018-10-04

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6372652B1 (en) * 2000-01-31 2002-04-16 Chartered Semiconductor Manufacturing Ltd. Method for forming a thin-film, electrically blowable fuse with a reproducible blowing wattage
US20120273798A1 (en) * 2011-04-29 2012-11-01 International Business Machines Corporation Method of forming silicide contacts of different shapes selectively on regions of a semiconductor device
US20130126979A1 (en) * 2011-11-22 2013-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits with electrical fuses and methods of forming the same
US8450163B2 (en) * 2010-04-30 2013-05-28 Globalfoundries Inc. Semiconductor device comprising metal gates and semiconductor resistors formed on the basis of a replacement gate approach
US20150001638A1 (en) * 2009-02-03 2015-01-01 Infineon Technologies Ag Silicided Semiconductor Structure and Method of Forming the Same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6372652B1 (en) * 2000-01-31 2002-04-16 Chartered Semiconductor Manufacturing Ltd. Method for forming a thin-film, electrically blowable fuse with a reproducible blowing wattage
US20150001638A1 (en) * 2009-02-03 2015-01-01 Infineon Technologies Ag Silicided Semiconductor Structure and Method of Forming the Same
US8450163B2 (en) * 2010-04-30 2013-05-28 Globalfoundries Inc. Semiconductor device comprising metal gates and semiconductor resistors formed on the basis of a replacement gate approach
US20120273798A1 (en) * 2011-04-29 2012-11-01 International Business Machines Corporation Method of forming silicide contacts of different shapes selectively on regions of a semiconductor device
US20130126979A1 (en) * 2011-11-22 2013-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits with electrical fuses and methods of forming the same

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