WO2018182664A1

WO2018182664A1 - Gate for a transistor

Info

Publication number: WO2018182664A1
Application number: PCT/US2017/025248
Authority: WO
Inventors: Van H. Le; Abhishek A. Sharma; Gilbert W. DEWEY; Ravi Pillarisetty; Shriram SHIVARAMAN; Tahir Ghani
Original assignee: Intel Corporation
Priority date: 2017-03-31
Filing date: 2017-03-31
Publication date: 2018-10-04

Abstract

Substrates, assemblies, and techniques for a transistor, where the transistor includes a gate, where the gate includes an inside portion and an outside portion, a dielectric, where the dielectric abuts the inside portion of the gate, a channel on the dielectric, and a nitride, where the nitride abuts a portion of the outside portion of the gate. In an example, a portion of the dielectric is between the channel and the nitride.

Description

GATE FOR A TRANSISTOR

Technical Field

[0001] The present disclosure relates generally to the field of transistors, and more particularly, to a gate for a transistor.

Background

[0002] Most, if not all, logic devices require some type of memory cell such as random access memory (RAM). Dynamic random-access memory (DRAM) is a type of random-access memory that stores each bit of data in a separate capacitor. The capacitor can be charged or discharged and these two states are taken to represent the two values of a bit, (i.e., 1 and 0). DRAM is widely used in digital electronics where low-cost and high-capacity memory is required. One of the largest applications for DRAM is the main memory, or RAM, in modern computers and electronics. The DRAM is typically coupled to a transistor. However, transistors leak a small amount current and can cause the capacitor of the DRAM to discharge and fade.

Brief Description of the Drawings

[0003] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0004] FIGURE 1 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0005] FIGURE 2A is a simplified top view block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0006] FIGURE 2B is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0007] FIGURE 2C is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0008] FIGURE 2D is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0009] FIGURE 2E is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure; [0010] FIGURE 3 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0011] FIGURE 4 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0012] FIGURE 5 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0013] FIGURE 6A is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0014] FIGURE 6B is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0015] FIGURE 6C is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0016] FIGURE 6D is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0017] FIGURE 6E is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0018] FIGURE 6F is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0019] FIGURE 6G is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0020] FIGURE 6H is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0021] FIGURE 61 is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0022] FIGURE 6J is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0023] FIGURE 6K is a simplified block diagram illustrating an embodiment of a portion of an electronic device, in accordance with one embodiment of the present disclosure;

[0024] FIGURE 7 is an interposer implementing one or more of the embodiments disclosed herein; and

[0025] FIGURE 8 is a computing device built in accordance with an embodiment disclosed herein. [0026] The figures of the drawings are not necessarily drawn to scale, as their dimensions can be varied considerably without departing from the scope of the present disclosure.

Detailed Description

[0027] The following detailed description sets forth example embodiments of apparatuses, methods, and systems relating to an access transmission gate. Features such as structure(s), function(s), and/or characteristic(s), for example, are described with reference to one embodiment as a matter of convenience; various embodiments may be implemented with any suitable one or more of the described features.

[0028] In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the embodiments disclosed herein may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the embodiments disclosed herein may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

[0029] Disclosed herein are substrates, assemblies, and techniques for enabling a device that includes one or more transistors. The transistors can include a gate and the gate can include a non-planar, U-shaped profile or geometry to create a fin-like gate and channel to promote electrostatic control. The U-shaped profile can allow the source, drain, and gate lines to be decoupled into orthogonal layers and allow for efficient routing of the current. This can allow for a higher current per unit area, for electrostatic control at scaled dimensions, and a longer gate length (Lg). In a specific example, a transistor includes a gate with a U-shaped profile. A dielectric can be on or above and inside the gate where the dielectric surrounds an inside portion of the gate (the inside portion of the "U"). The dielectric can also surround a portion of a channel on or above the dielectric and gate. A nitride can partially surround an outside portion of the gate and the dielectric can be between the channel and the nitride. A source and a drain can be on or above or over the channel and the nitride.

[0030] The terms "over," "above," "under," "below," "between," and "on" as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over, above, or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

[0031] Implementations of the embodiments disclosed herein may be formed or carried out on a substrate, such as a non-semiconductor substrate or a semiconductor substrate. In one implementation, the non-semiconductor substrate may be silicon dioxide, inter-layer dielectric composed of silicon dioxide, silicon nitride, titanium oxide and other transition metal oxides. Although a few examples of materials from which the non- semiconducting substrate may be formed are described here, any material that may serve as a foundation upon which a non-semiconductor device may be built falls within the spirit and scope of the embodiments disclosed herein.

[0032] In another implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V or group IV materials. In other examples, the substrate may be a flexible substrate including 2D materials such as graphene and molybdenum disulphide, organic materials such as pentacene, transparent oxides such as indium gallium zinc oxide poly/amorphous (low temperature of dep) lll-V semiconductors and germanium/silicon, and other non-silicon flexible substrates. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the embodiments disclosed herein.

[0033] In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0034] Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments. For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0035] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. As used herein, a "package" and an "IC package" are synonymous. As used herein, the terms "chip" and "die" may be used interchangeably.

[0036] FIGURE 1 is a simplified block diagram of an electronic device 100 that includes one or more transistors and arrays in accordance with an embodiment of the present disclosure. Electronic device 100 can be any electronic device that includes memory (e.g., computer, smartphone, laptop, desktop, Internet-of-Things (loT) device, vehicle electronics, handheld electronic device, personal digital assistant, wearable, household electronics, etc.). Electronic device 100 can include one or more electronic elements 102a-102d. Each electronic element 102a-102d can include one or more transistors 104 and/or one or more transistor arrays 106. Each transistor array 106 can be a systematic arrangement of a plurality of transistors 104, (e.g., in rows and columns).

[0037] Transistor 104 can be configured to include a gate that has a U-shaped profile with a dielectric and a channel in the middle and can be configured to reduce leakage as compared to traditional transistors. The U-shaped profile can create a fin-like gate and channel to promote electrostatic control and allow the source, drain, and gate lines of the transistor to be decoupled into orthogonal layers for efficient routing of current. In an example, a dielectric can be inside the gate or inside the "U" of the U-shaped gate as well as on or above the gate. A channel can be on or above the dielectric and the gate. The dielectric can surround a portion of the channel that is not in contact with a gate or drain. A nitride can surround the outside portion of the gate that is not in contact with the oxide. The source and the drain can be over the channel and the nitride.

[0038] Transistor 104 can be a transistor or an electronic switch that can be either in an "on" or "off" state and the term "transistor" includes a metal-oxide-semiconductor (MOS), complementary MOS (CMOS), n-channel MOS (NMOS) p-channel MOS (PMOS), MOS field- effect transistors (MOSFET), bipolar junction transistor (BJT), filed effect transistor (FET), finFET, junction gate FET (JFET), insulated gate FET (IGFET), n-channel field effect transistor (NFET) insulated-gate bipolar transistor, or other similar transistor that can be configured to perform the functions, features, and operations disclosed herein. In an example, transistor 104 can be a backend transistor. A backend transistor is a thin filmed transistor above a metal one layer. Backend transistors can allow device functionally to be scaled by stacking memory and logic in the backend. However, some backend transistors suffer from high contact resistance and a relatively large amount of leakage. This may render some backend transistors useless due to low drive current and thus degrade the performance of the memory or logic system.

[0039] Transistor 104 can be coupled to a capacitive element. The capacitive element may be a memory element such as embedded dynamic random access memory (eDRAM). in another example, transistor 104 can be coupled to a resistive element such as resistive random-access memory (RRAM). In yet another example, transistor 104 can be coupled to some other type of memory or element. eDRAM can be integrated on the same die or multi- chip module (MCM) of an application-specific integrated circuit (ASIC) or microprocessor. Embedding memory on the ASIC or microprocessor allows for relatively wide buses and high operation speeds. Also, due to the much higher density of DRAM in comparison to SRAM, larger amounts of memory can be installed on smaller chips.

[0040] One issue with traditional transistors is that they leak a relatively large amount of current. The term "leak" or "leakage" refers to the small amount of current all transistors conduct, even when they are turned off. If the transistors is coupled to a capacitive element, the leakage causes a gradual loss of energy from a capacitive element as the current slowly discharges from the capacitive element. Leakage is currently one of the main factors limiting increased computer processor performance. Transistor 104 can be configured to resolve these issues (and others). For example, transistor 104 can be configured to reduce the amount of leakage from capacitive element as compared to traditional transistors.

[0041] Turning to FIGURES 2A-2C, FIGURES 2A-2C illustrate one embodiment of transistor 104. Transistor 104 can include an oxide 108, a source 110, a drain 112, a gate 114, a dielectric 116, a channel 118, and a nitride 120. Source 110 and drain 112 can be coupled to each other using channel 118. Nitride 120 can help insulate gate 114, dielectric 116 and channel 118 and can help ensure there is relatively low leakage in transistor 104. Gate 114 can be configured as a gate or word line. Source 110 can be configured as a source. Drain 112 can be configured as a drain or bit line.

[0042] In the case of an NMOS transistor, when a positive voltage that is greater than the threshold voltage of the NMOS transistor is applied, channel 118 will allow current to flow from source 110 to drain 112. In the case of a PMOS transistor, when a negative voltage that is greater than the threshold voltage of the PMOS transistor is applied, then channel 118 will allow the current to flow. In both the NMOS transistor and the PMOS transistor, when the voltage is below the threshold voltage, the transistor will shut off and the current does not flow. Dielectric 116 and nitride 120 can act as an insulator and help ensure there is relatively low leakage in transistor 104.

[0043] Oxide 108 can be a non-semiconducting substrate and may be composed of silicon dioxide, inter-layer dielectric composed of silicon dioxide, silicon nitride, titanium oxide, other transition metal oxides, aluminum oxide, sapphire substrates, silicon carbide, or other material that may server as a non-conductive layer. Source 110 can be composed of different metals with various work functions from ranges of about 5.6 eV to about 3.8 eV. More specifically, source 110 can be composed of layers or bi-layers of tungsten, cobalt, titanium nitride, tantalum nitride, titanium, aluminum, indium tin oxide, tantalum, ruthenium, hafnium, and other similar materials. Drain 112 can be composed of different metals with various work functions from ranges of about 5.6 eV to about 3.8 eV. More specifically, drain 112 can be composed of layers or bi-layers of tungsten, cobalt, titanium nitride, tantalum nitride, titanium, aluminum, indium tin oxide, tantalum, ruthenium, hafnium, and other similar materials. Gate 114 can be comprised of different metals with various work functions from ranges of about 5.6 eV to about 3.8 eV. More specifically, drain 112 can be composed of layers or bi-layers of tungsten, cobalt, titanium nitride, tantalum nitride, titanium, aluminum, indium tin oxide, tantalum, ruthenium, hafnium, and other similar materials. The metals with various work functions for source 110, drain 112 and gate 114 can be selected to help tune the threshold voltage of transistor 104. Dielectric 116 can be a dielectric and may be comprised of one or more layers of silicon oxide, silicon dioxide, ternary metal oxides and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. More specifically, the high-k dielectric materials can include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

[0044] Channel 118 can be composed of indium gallium zinc oxide, zinc oxide, zinc oxynitrides, gallium oxide, tin oxide, copper oxide, indium zinc oxide, indium oxide some other semiconducting metal oxide, or other semiconducting material. Nitride 120 may be an insulator to help reduce leakage in transistor 104 and may be composed of trinitride or silicon oxynitride. In some examples, nitride 120 may be composed of carbon doped silicon oxides or some other material that can insulate gate 114, dielectric 116, and channel 118 from oxide 108 and help reduce leakage in transistor 104.

[0045] Turning to FIGURES 2D and 2E, FIGURES 2D and 2E illustrates different embodiments of gate 114. As illustrated in FIGURES 2D and 2E, gates 114a and 114b can include an inside portion 156, a side outside portion 158, a bottom portion 160, and a top outside portion 162. FIGURE 2D illustrates gate 114a with an imperfect U-shaped profile. FIGURE 2E illustrates gate 114b with a profile that resembles a V-shaped profile. The profiles for gates 114, 114a, and 114b not intended to be exhaustive or to limit the scope of the disclosure to the precise profiles disclosed. Various equivalent profiles of gates 114, 114a, and 114b are possible within the scope of the disclosure, as those skilled in the relevant art will recognize and the illustrated profiles are not intended to be limiting but only to provide illustrated examples.

[0046] Turning to FIGURE 3, FIGURE 3 illustrates one embodiment of transistor 104. In a specific implementation, transistor 104 can be coupled to a capacitive element 122 using connector 124. Capacitive element 122 may be a memory element such as RAM or eDRAM. In other examples, capacitive element 122 may not be a capacitive element but a phase change material or resistive element such as a resistive memory element (e.g., RRAM). In yet another example, capacitive element 112 may be magnetoresistive RAM (MRAM), phase change memory, or some other type of memory element. Connector 124 can be configured as metal connections for transistor 104 and may be a metal connection from capacitive element 122 to drain 112. Connector 124 can be part of a metal-2 or metal-3 extended connection, part of a metal-4 or metal-5 extended connection (as illustrated in FIGURE 5) or part of some other metal layer or extended connection.

[0047] Transistor 104 can be configured to allow access to capacitive element 122 and charge or change the resistance of capacitive element 122. For example, transistor 104 can be configured to program capacitive element 122, charge or discharge capacitive element 122, deselect or not disturb capacitive element 122, read capacitive element 122, etc. In one implementation, capacitive element 122 can acquire a charge by applying a gate bias to the transistor such that current flows through the transistor 104 from source 110 to drain 112 and charges a metal terminal of capacitive element 122. When transistor 104 is turned off, the channel resistance is increased significantly and leakage from capacitive element 122 may be reduced as compared to traditional transistors due to the inherent material properties of transistor 104.

[0048] In a specific example, transistor 104 may be a low off-state leakage write transistor, such as amorphous oxide semiconductors. Capacitive element 122 may be a smaller charge storage metal-insulator-metal (MIM) capacitor. The ability to use the smaller MIM cap is due to the lower leakage offered by transistor 104. As a result, different integration schemes that create metal oxide thin film transistors with scaled dimensions can be used in realizing a monolithic, back end of line (BEOL), embedded 1T-1C DRAM that allows for density improvements over current transistors.

[0049] Turning to FIGURE 4, FIGURE 4 illustrate one embodiment of transistor 104. Transistor 104 can be over a silicon based element such as logic circuitry. For example, transistor 104 can be over logic element 126. Logic element 126 can be on or over a base substrate 128. Base substrate 128 may be a silicon based substrate. Logic element 126 can include transistors, logic (e.g., adders, registers, etc.), micro-processor circuits for processing data and other circuitry. In an example, logic element 126 can communicate with capacitive element 122 through transistor 104 and cause data (or a charge) to be stored in one or more capacitive elements 122.

[0050] Scaling of logic devices is typically accomplished by reducing the size of the logic device. One approach is based on increasing the number of logic elements per unit area. To increase the number of logic elements per unit area, the density of dies needs to be increased and additional logic devices need to be fabricated above the silicon. To increase the density of dies in an integrated circuit (IC) package of a particular footprint, one or more transistors 104 may be stacked on top of each other such that instead of fabricating transistor 104 on base substrate 128, transistor 104 can be fabricated above base substrate 128.

[0051] Turning to FIGURE 5, FIGURE 5 illustrates an example of an IC package that includes one embodiment of transistor 104. The IC package can be on base substrate 128 and can include one or more logic elements 126, a first metal layer 132, a second metal layer 134, a third metal layer 136, a fourth metal layer 138, a fifth metal layer 140, a sixth metal layer 142, a seventh metal layer 144, and an eight metal layer 146. As illustrated in FIGURE 5, transistor 104 can be in or on fifth metal layer 140 and capacitive element 122 can be in or on sixth metal layer 142. It should be noted that more or less metal layers than illustrated in FIGURE 5 may be present. Also, one or more transistors 104 may be in or on one or more different metal layers than the illustrated fifth metal layer 140 and one or more capacitive elements 122 may be in or on one or more different metal layers than the illustrated sixth metal layer 142.

[0052] If base substrate 128 is a semiconductor substrate, the semiconductor substrate (and any additional silicon based layers) may be formed using alternate materials, which may or may not be combined with silicon. This includes, but is not limited to, silicon, silicon germanium, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V or group IV materials. In other examples, the substrate of any layer may be a flexible substrate including 2D materials such as graphene and molybdenum disulfide, organic materials such as pentacene, transparent oxides such as indium gallium zinc oxide poly/amorphous (low temperature of dep) lll-V semiconductors and germanium/silicon, and other non-silicon flexible substrates.

[0053] In an example, a plurality of electrical components can include one or more transistors 104 and/or one or more arrays 106 of transistors 104. In addition, a plurality of transistors, such as MOSFET or simply MOS transistors, can include one or more transistors 104 and may be fabricated on base substrate 128. In various embodiments, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that various embodiments may also be carried out using nonplanar transistors.

[0054] Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide and/or a high- k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

[0055] The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type work function metal or N-type work function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

[0056] For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a work function that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a work function that is between about 3.9 eV and about 4.2 eV.

[0057] In some implementations, when viewed as a cross-section of the transistor along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[0058] In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0059] Source and drain regions can be formed within base substrate 128 adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion- implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

[0060] One or more interlayer dielectrics (ILD) may be deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide, carbon doped oxide, silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass, and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

[0061] Turning to FIGURE 6A, FIGURE 6A illustrates a simplified block diagram of an early stage in the formation of transistor 104 in accordance with an embodiment of the present disclosure. As illustrated in FIGURE 6A, gate 114 can be deposited on oxide 108. Gate 114 may be deposited using a spin-on deposition from slurry, sputtering, chemical vapor deposition (CVD), thermal vacuum deposition (TVD), atomic layer deposition (ALD), or any combination, or some other form of deposition that can deposit gate 114 on oxide 108. Oxide 108 may be about one (1) nanometers to about forty (40) nanometers in thickness. Gate 114 may also be about 1 nanometers to about 40 nanometers in thickness. Gate 114 can be can be etched, polished, planarized, and/or patterned.

[0062] Turning to FIGURE 6B, FIGURE 6B illustrates a simplified block diagram of an early stage in the formation of transistor 104 in accordance with an embodiment of the present disclosure. In an example, nitride 120 can be deposited on gate 114. Nitride 120 may be deposited using a spin-on deposition from slurry, sputtering, CVD, TVD, ALD, or any combination, or some other form of deposition that can deposit nitride 120 on gate 114. Nitride 120 may be about 1 nanometer to about twenty (20) nanometers in thickness. Nitride 120 can be can be etched, polished, planarized, and/or patterned.

[0063] Turning to FIGURE 6C, FIGURE 6C illustrates a simplified block diagram of an early stage in the formation of transistor 104 in accordance with an embodiment of the present disclosure. In an example, oxide 108 can be deposited on nitride 120. Oxide 108 may be deposited using a spin-on deposition from slurry, sputtering, CVD, TVD, ALD, or any combination, or some other form of deposition that can deposit oxide 108 on nitride 120. Oxide 108 may be about three (3) nanometers to about 40 nanometers in thickness. Oxide 108 can be etched, polished, planarized, and/or patterned

[0064] Turning to FIGURE 6D, FIGURE 6D illustrates a simplified block diagram of an early stage in the formation of transistor 104 in accordance with an embodiment of the present disclosure. In an example, etch stop 148 can be deposited on oxide 108. Etch stop 148 may be composed of titanium nitride, titanium oxide, TiONx, aluminum nitride, aluminum oxide, or some other metal oxideor material that can act as an etch stop (e.g., can be polished and has etch selectivity against silicon dioxide and silicon nitride) and is a different material than oxide 108 and nitride 120. Etch stop 148 may be deposited using a spin-on deposition from slurry, sputtering, CVD, TVD, ALD, or any combination, or some other form of deposition that can deposit etch stop 148 on nitride 120. Etch stop 148 may be about 1 nanometer to about 40 nanometers in thickness. Etch stop 148 can be can be can be etched, polished, planarized, and/or patterned.

[0065] Turning to FIGURE 6E, FIGURE 6E illustrates a simplified block diagram of a stage in the formation of transistor 104 in accordance with an embodiment of the present disclosure. As illustrated in FIGURE 6C, oxide 108, nitride 120, and gate 114 that are not under etch stop 148 can be etched to create a channel cavity 150. Channel cavity 150 can extend down to gate 114.

[0066] Turning to FIGURE 6F, FIGURE 6F illustrates a simplified block diagram of a stage in the formation of transistor 104 in accordance with an embodiment of the present disclosure. As illustrated in FIGURE 6E, dielectric 116 can be deposited on etch stop 148 and in channel cavity 150. Dielectric 116 may be deposited using a spin-on deposition from slurry, sputtering, CVD, TVD, ALD, or any combination, or some other form of deposition that can deposit dielectric 116 on etch stop 148 and in channel cavity 150. Dielectric 116 may be about 1 nanometer to about 40 nanometers in thickness. Dielectric 116 can be can be can be etched, polished, planarized, and/or patterned.

[0067] Turning to FIGURE 6G, FIGURE 6G illustrates a simplified block diagram of a stage in the formation of transistor 104 in accordance with an embodiment of the present disclosure. As illustrated in FIGURE 6G, channel 118 can be deposited in channel cavity 150 over dielectric 116. Channel 118 may be deposited using a spin-on deposition from slurry, sputtering, CVD, TVD, ALD, or any combination, or some other form of deposition that can deposit channel 118 in channel cavity 150 and on dielectric 116. Channel 118 may be about 1 nanometer to about 40 nanometers in thickness. Channel 118 can be can be can be etched, polished, planarized, and/or patterned.

[0068] Turning to FIGURE 6H, FIGURE 6H illustrates a simplified block diagram of a stage in the formation of transistor 104 in accordance with an embodiment of the present disclosure. As illustrated in FIGURE 6H, etch stop 148, dielectric 116, and channel 118 above etch stop 148 can be etched down to oxide 108 and the top of nitride 120. The now exposed top of oxide 108, nitride 120, dielectric 116, and channel 118 can be etched, polished, planarized, and/or patterned.

[0069] Turning to FIGURE 61, FIGURE 61 illustrates a simplified block diagram of a stage in the formation of transistor 104 in accordance with an embodiment of the present disclosure. As illustrated in FIGURE 61, oxide 108 can be deposited on the existing oxide 108, nitride 120, dielectric 116, and channel 118. Oxide 108 may be deposited using a spin-on deposition from slurry, sputtering, CVD, TVD, ALD, or any combination, or some other form of deposition that can deposit oxide 108 on the existing oxide 108, nitride 120, dielectric 116, and channel 118. Oxide 108 may be about 3 nanometers to about 40 nanometers in thickness.

[0070] Turning to FIGURE 6J, FIGURE 6J illustrates a simplified block diagram of a stage in the formation of transistor 104 in accordance with an embodiment of the present disclosure. As illustrated in FIGURE 6J, oxide 108 can be etched to create a source or drain cavity 152. Source or drain cavity 152 can extend into oxide 108 and down to the top of nitride 120, dielectric 116, and channel 118.

[0071] Turning to FIGURE 6K, FIGURE 6K illustrates a simplified block diagram of a stage in the formation of transistor 104 in accordance with an embodiment of the present disclosure. As illustrated in FIGURE 6K, channel 118 can be etched to extend source or drain cavity 152 into channel 118. Source 110 or drain 112 can be deposited in source or drain cavity 152. For example, source 110 can be deposited in source or drain cavity 152 to create transistor 104 illustrated in FIGURE 2B. Source or drain cavity 152 extends into channel 118 to help provide good contact between source 110 and drain 112 along channel 118. Source 110 and drain 112 may be deposited using a spin-on deposition from slurry, sputtering, CVD, TVD, ALD, or any combination, or some other form of deposition that can deposit source 110 or drain 112 in source or drain cavity 152. Source 110 and drain 112 may each be about 1 nanometer to about 40 nanometers in thickness. [0072] Turning to FIGURE 7, FIGURE 7 illustrates an interposer 700 that can include or interact with one or more embodiments disclosed herein. The interposer 700 is an intervening substrate used to bridge a first substrate 702 to a second substrate 704. The first substrate 702 may be, for instance, an integrated circuit die. The second substrate 704 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 700 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 700 may couple an integrated circuit die to a ball grid array (BGA) 706 that can subsequently be coupled to the second substrate 704. In some embodiments, the first and second substrates 702/704 are attached to opposing sides of the interposer 700. In other embodiments, the first and second substrates 702/704 are attached to the same side of the interposer 700. And in further embodiments, three or more substrates are interconnected by way of the interposer 700.

[0073] The interposer 700 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.

[0074] The interposer may include metal interconnects 708 and vias 710, including but not limited to through-silicon vias (TSVs) 712. The interposer 700 may further include embedded devices 714, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 700. In accordance with various embodiments, apparatuses or processes disclosed herein may be used in the fabrication of interposer 700.

[0075] Turning to FIGURE 8, FIGURE 8 illustrates a computing device 800 in accordance with various embodiments. The computing device 800 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system- on-a-chip (SoC) die. The components in the computing device 800 include, but are not limited to, an integrated circuit die 802 and at least one communications logic unit 808. In some implementations the communications logic unit 808 is fabricated within the integrated circuit die 802 while in other implementations the communications logic unit 808 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 802. The integrated circuit die 802 may include a CPU 804 as well as on-die memory 806, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STT-MRAM).

[0076] Computing device 800 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 810 (e.g., DRAM), nonvolatile memory 812 (e.g., ROM or flash memory), a graphics processing unit 814 (GPU), a digital signal processor 816, a crypto processor 842 (a specialized processor that executes cryptographic algorithms within hardware), a chipset 820, an antenna 822, a display or a touchscreen display 824, a touchscreen controller 826, a battery 828 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 828, a compass 830, a motion coprocessor or sensors 832 (that may include an accelerometer, a gyroscope, and a compass), a speaker 834, a camera 836, user input devices 838 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 840 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

[0077] The communications logic unit 808 enables wireless communications for the transfer of data to and from the computing device 800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communications logic unit 808 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 800 may include a plurality of communications logic units 808. For instance, a first communications logic unit 808 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communications logic unit 808 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0078] The processor 804 of the computing device 800 can communicate with one or more devices that are formed in accordance with various embodiments. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[0079] The communications logic unit 808 may also include one or more devices, such as transistors or metal interconnects, that are in communication with various ones of the embodiments disclosed herein. In further embodiments, another component housed within the computing device 800 may contain one or more devices, such as transistors or metal interconnects, that are formed in accordance with implementations of the embodiments disclosed herein.

[0080] In various embodiments, the computing device 800 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 800 may be any other electronic device that processes data.

[0081] The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the scope of the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the embodiments disclosed herein are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

OTHER NOTES AND EXAMPLES.

[0082] Example 1 is an apparatus including a backend transistor, where the backend transistor includes a gate, where the gate includes an inside portion and an outside portion.

The backend transistor also can include a dielectric, where the dielectric at least partially abuts the inside portion of the gate, a channel on the dielectric, and a nitride, where the nitride abuts a portion of the outside portion of the gate. [0083] In Example 2, the subject matter of Example 1 can optionally include where a portion of the dielectric is between the channel and the nitride.

[0084] In Example 3, the subject matter of any one of Examples 1 and 2 can optionally include where a source and a drain, where the channel couples the source to the drain.

[0085] In Example 4, the subject matter of any one of Examples 1-3 can optionally include where the source and the drain are on the channel and the nitride.

[0086] In Example 5, the subject matter of any one of Examples 1-4 can optionally include where the gate is on an oxide.

[0087] In Example 6, the subject matter of any one of Examples 1-5 can optionally include where the backend transistor is above a logic element.

[0088] In Example 7, the subject matter of any one of Examples 1-6 can optionally include where the backend transistor is coupled to a capacitive element.

[0089] In Example 8, the subject matter of any one of Examples 1-7 can optionally include where the capacitive element is embedded dynamic random access memory.

[0090] In Example 9, a method for creating a gate for a backend transistor can include depositing a gate on a layer of oxide, depositing a nitride on the gate, etching the gate and the nitride to create a channel cavity, depositing a dielectric in the channel cavity, depositing a channel on the dielectric in the channel cavity, and etching the channel.

[0091] In Example 10, the subject matter of Example 9 can optionally include depositing a second layer of oxide on the nitride after the nitride has been deposited on the gate, and depositing an etch stop on the second layer of oxide, where the etch stop is not over at least a portion of the gate.

[0092] In Example 11, the subject matter of any one of Examples 9 and 10 can optionally include where a portion of the dielectric is between the channel and the nitride.

[0093] In Example 12, the subject matter of any one of Examples 9-11 can optionally include where the backend transistor is on an oxide.

[0094] In Example 13, the subject matter of any one of Examples 9-12 can optionally include where the backend transistor is above a logic element.

[0095] In Example 14, the subject matter of any one of Examples 9-13 can optionally include where the backend transistor is coupled to a capacitive element.

[0096] In Example 15, the subject matter of any one of Examples 9-14 can optionally include where the capacitive element is embedded dynamic random access memory. [0097] Example 16 is a computing device including a processor mounted on a substrate, a communications logic unit within the processor, a memory within the processor, a graphics processing unit within the computing device, an antenna within the computing device, a display on the computing device, a battery within the computing device, a power amplifier within the processor, and a voltage regulator within the processor. The memory can be coupled to a backend transistor and the backend transistor can include a gate, where the gate includes an inside portion and an outside portion, a dielectric, where the dielectric abuts the inside portion of the gate, a channel on the dielectric, and a nitride, where the nitride abuts a portion of the outside portion of the gate.

[0098] In Example 17 the subject matter of Example 16 can optionally include where a portion of the dielectric is between the channel and the nitride.

[0099] In Example 18 the subject matter of any one of Examples 16 and 17 can optionally include where the backend transistor further includes a source and a drain, where the channel couples the source to the drain.

[00100] In Example 19, the subject matter of any one of the Examples 16-18 can optionally include where the source and the drain are on the channel and the nitride.

[00101] In Example 20, the subject matter of any one of the Examples 15-19 can optionally include where the gate is on an oxide.

[00102] Example 21 is an integrated circuit (IC) assembly including a non-silicon substrate and a backend transistor on top of the non-silicon substrate, where the backend transistor includes a gate, where the gate includes an inside portion and an outside portion, a dielectric, where the dielectric abuts the inside portion of the gate, a channel on the dielectric, and a nitride, where the nitride abuts a portion of the outside portion of the gate.

[00103] In Example 22, the subject matter of Example 21 can optionally include where a portion of the dielectric is between the channel and the nitride.

[00104] In Example 23, the subject matter of any one of the Examples 21 and 22-23 can optionally include where a source and a drain, where the channel couples the source to the drain and the source and the drain are on the channel and the nitride.

[00105] In Example 24, the subject matter of any one of the Examples 21-23 can optionally include where the backend transistor is over a logic element.

[00106] In Example 25, the subject matter of any one of the Examples 22-24 can optionally include where the backend transistor is coupled to a capacitive element.

Claims

1. An apparatus comprising:

a backend transistor, wherein the backend transistor includes:

a gate, wherein the gate includes an inside portion and an outside portion; a dielectric, wherein the dielectric abuts the inside portion of the gate;

a channel on the dielectric; and

a nitride, wherein the nitride abuts a portion of the outside portion of the gate.

2. The apparatus of Claim 1, wherein a portion of the dielectric is between the channel and the nitride.

3. The apparatus of Claim 2, wherein the backend transistor further includes: a source; and

a drain, wherein the channel couples the source to the drain.

4. The apparatus of Claim 3, wherein the source and the drain are on the channel and the nitride.

5. The apparatus of Claim 1, wherein the gate is on an oxide.

6. The apparatus of any one of Claims 1-5, wherein the backend transistor is above a logic element.

7. The apparatus of any one of Claims 1-5, wherein the backend transistor is coupled to a capacitive element.

8. The apparatus of Claim 7, wherein the capacitive element is embedded dynamic random access memory.

9. A method for creating a gate for backend transistor, the method comprising: depositing a gate on a layer oxide;

depositing a nitride on the gate; etching the gate and the nitride to create a channel cavity;

depositing a dielectric in the source or drain cavity;

depositing a channel on the dielectric in the source or drain cavity; and

etching the channel.

10. The method of Claim 9, further comprising:

depositing a second layer of oxide on the nitride after the nitride has been deposited on the gate; and

depositing an etch stop on the second layer of oxide, wherein the etch stop is not above at least a portion of the gate.

11. The method of Claim 9, wherein a portion of the dielectric is between the channel and the nitride.

12. The method of Claim 9, wherein the backend transistor is on an oxide.

13. The method of any one of Claims 9-12, wherein the backend transistor is above a logic element.

14. The method of any one of Claims 9-12, wherein the backend transistor is coupled to a capacitive element.

15. The method of Claim 14, wherein the capacitive element is embedded dynamic random access memory.

16. A computing device comprising:

a processor mounted on a substrate;

a communications logic unit within the processor;

a memory within the processor;

a graphics processing unit within the computing device;

an antenna within the computing device;

a display on the computing device; a battery within the computing device;

a power amplifier within the processor; and

a voltage regulator within the processor;

wherein the memory is coupled to a backend transistor and the backend transistor includes:

a channel on the dielectric; and

17. The computing device of Claim 16, wherein a portion of the dielectric is between the channel and the nitride.

18. The computing device of Claim 16, wherein the backend transistor further includes:

a source; and

a drain, wherein the channel couples the source to the drain.

19. The computing device of any one of Claims 16-18, wherein the source and the drain are on the channel and the nitride.

20. The computing device of any one of Claims 16-18, wherein the gate is on an oxide.

21. An integrated circuit (IC) assembly, comprising:

a non-silicon substrate; and

a backend transistor on top of the non-silicon substrate, wherein the backend transistor includes:

a channel on the dielectric; and

22. The IC assembly of Claim 21, wherein a portion of the dielectric is between the channel and the nitride.

23. The IC assembly of Claim 21, wherein the backend transistor further includes: a source; and

a drain, wherein the channel couples the source to the drain and the source and the drain are on the channel and the nitride.

24. The IC assembly of any one of Claims 22-23, wherein the backend transistor is above a logic element.

25. The IC assembly of any one of Claims 22-23, wherein the backend transistor is coupled to a capacitive element.