WO2018182667A1

WO2018182667A1 - Spintronic memory with enhanced crystallized layer

Info

Publication number: WO2018182667A1
Application number: PCT/US2017/025256
Authority: WO
Inventors: Kaan OGUZ; Christopher J. WIEGAND; Kevin P. O'brien; Brian S. Doyle; Mark L. Doczy; Md Tofizur Rahman; Daniel G. OUELLETTE; Tahir Ghani; Oleg Golonzka
Original assignee: Intel Corporation
Priority date: 2017-03-31
Filing date: 2017-03-31
Publication date: 2018-10-04

Abstract

An embodiment includes an apparatus comprising: a magnetic tunnel junction (MTJ) including a fixed magnetic layer and a tunnel barrier layer; a first layer on the tunnel barrier layer; a second layer on the first layer; and an oxide layer on the second layer; wherein: (a)(i) the first layer includes a plurality of metals and directly contacts the tunnel barrier layer, and (a)(ii) the second layer includes the plurality of metals and an element selected from the group consisting of carbon, silicon, germanium, tin, phosphorous, or combinations thereof. Other embodiments are described herein.

Description

Spintronic Memory with Enhanced Crystallized Layer

Technical Field

[0001] Embodiments of the invention are in the field of semiconductor devices and, in particular, memory.

Background

[0002] Some magnetic memories, such as a spin transfer torque memory (STTM), utilize a magnetic tunnel junction (MTJ) for switching and detection of the memory's magnetic state. Figure 1 includes spin transfer torque random access memory (STTRAM), a form of STTM. Figure 1 includes a MTJ consisting of ferromagnetic (FM) layers 125, 127 and tunneling barrier 126 (e.g., magnesium oxide (MgO)). The MTJ couples bit line (BL) 105 to selection switch 120 (e.g., transistor), word line (WL) 110, and sense line (SL) 115. Memory 100 is "read" by assessing the change of resistance (e.g., tunneling magnetoresi stance (TMR)) for different relative magnetizations of FM layers 125, 127.

[0003] More specifically, MTJ resistance is determined by the relative magnetization directions of layers 125, 127. When the magnetization directions between the two layers are anti-parallel, the MTJ is in a high resistance state. When the magnetization directions between the two layers are parallel, the MTJ is in a low resistance state. Layer 127 is the "reference layer" or "fixed layer" because its magnetization direction is fixed. Layer 125 is the "free layer" because its magnetization direction is changed by passing a driving current polarized by the reference layer (e.g., positive voltage applied to layer 127 rotates the magnetization direction of layer 125 opposite to that of layer 127 and negative voltage applied to layer 127 rotates the magnetization direction of layer 125 to the same direction of layer 127).

Brief Description of the Drawings

[0004] Features and advantages of embodiments of the present invention will become apparent from the appended claims, the following detailed description of one or more example embodiments, and the corresponding figures, in which:

[0005] Figure 1 depicts a conventional magnetic memory cell.

[0006] Figures 2-3 depict conventional MTJs.

[0007] Figure 4 includes a memory stack in an embodiment. [0008] Figures 5A, 5B, 5C, 5D, 5E include embodiments of free layers.

[0009] Figure 6 includes a memory cell in an embodiment.

[0010] Figure 7 depicts a method of forming a memory in an embodiment.

[0011] Figures 8, 9, 10 depict systems for use with embodiments.

Detailed Description

[0012] Reference will now be made to the drawings wherein like structures may be provided with like suffix reference designations. In order to show the structures of various embodiments more clearly, the drawings included herein are diagrammatic representations of integrated circuit structures. Thus, the actual appearance of the fabricated integrated circuit structures, for example in a photomicrograph or atom probe image, may appear different while still incorporating the claimed structures of the illustrated embodiments. Moreover, the drawings may only show the structures useful to understand the illustrated embodiments. Additional structures known in the art may not have been included to maintain the clarity of the drawings. "An embodiment", "various embodiments" and the like indicate embodiment s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Some embodiments may have some, all, or none of the features described for other embodiments. "First", "second", "third" and the like describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. "Connected" may indicate elements are in direct physical or electrical contact with each other and "coupled" may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact. Also, while similar or same numbers may be used to designate same or similar parts in different figures, doing so does not mean all figures including similar or same numbers constitute a single or same embodiment.

[0013] STTRAM, described above, is just one example of "beyond CMOS" technology (or "non-CMOS based" technology), which relates to devices and processes not entirely implemented with complementary metal-oxide-semiconductor (CMOS) techniques. Beyond CMOS technology may rely on spin polarization (which concerns the degree to which the spin or intrinsic angular momentum of elementary particles is aligned with a given direction) and, more generally, spintronics (a branch of electronics concerning the intrinsic spin of an electron, its associated magnetic moment, and the electron's fundamental electronic charge). Spintronics devices may concern TMR, which uses quantum-mechanical tunneling of electrons through a thin insulator to separate ferromagnetic layers, and STT, where a current of spin polarized electrons may be used to control the magnetization direction of ferromagnetic electrodes.

[0014] Beyond CMOS devices include, for example, spintronics devices implemented in memory (e.g., 3 terminal STTRAM), spin logic devices (e.g., logic gates), tunnel field-effect transistors (TFETs), impact ionization MOS (JJVIOS) devices, nano-electro-mechanical switches (NEMS), negative common gate FETs, resonant tunneling diodes (RTD), single electron transistors (SET), spin FETs, nanomagnet logic (NML), domain wall logic, domain wall memory, magnetic sensors, and the like.

[0015] Regarding STTM specifically, one form of STTM includes perpendicular STTM (pSTTM). Where a traditional MTJ or non-perpendicular MTJ generates a magnetization "in plane" (with which "high" and "low" memory states are set), a perpendicular MTJ (pMTJ) generates magnetization "out of plane". This reduces the switching current needed to switch between high and low memory states. This also allows for better scaling (e.g., smaller size memory cells). Traditional MTJs are converted to pMTJs by, for example, thinning the free layer, thereby making the tunnel barrier/free layer interface more dominant in magnetic field influence (and the interface promotes anisotropic out of plane magnetization). The interface is highlighted with bold dashed lines and ¾ in Figure 2 (and other figures included herein) which addresses the anisotropic energy at the interface. Figure 2 includes such a system 200 with cobalt, iron, boron (CoFeB) free layer 225 interfacing magnesium oxide (MgO) tunnel barrier 226, which further couples to CoFeB fixed layer 227 and Tantalum (Ta) contacts 214 (which may couple to a selection switch such as transistor 120 of Figure 1), 216 (which may couple, by way of one or more vias, to a bit line such as bit line 105 of Figure 1).

[0016] Figure 3 depicts a system 300 with a MTJ, where a second oxidized MgO interface 320 (sometimes referred to as a "cap layer") contacts CoFeB free layer 325 (which further couples to a tunnel barrier MgO 326, which is formed on CoFeB fixed layer 327). Adding cap layer 320 may increase stability for the memory, which is a problem for devices such as the device of Figure 2. Thus, Figure 3 includes MgO at both free layer interfaces (i.e., layers 320, 326). However, introducing MgO layer 320 on top of CoFeB free layer 325 increases the memory's total resistance significantly (as compared to having just one oxide layer interface the free layer as in Figure 2), which makes the design impractical for scaled devices (e.g., 22 nm) because of degradation in resistance-area (RA) product and TMR. In other words, if MgO layer 326 is predominately responsible for resistance and voltage drop in conventional MTJs, adding yet another layer of MgO in series with layer 326 increases RA product, thereby driving up write voltage, decreasing battery life, decreasing TMR, and the like.

[0017] RA product refers to a measurement unequal to resistivity. Resistivity has units in ohm-cm, whereas RA product has units in ohm-um² (and is based on material resistivity (p), dot area (A), and MgO thickness (T_Mgo) such that increasing MgO thickness exponentially increases the RA of the device). While resistivity represents an "inherent resistance" and is independent of the thickness of a material layer, RA product is exponentially proportional to the thickness of the material (e.g., MgO thickness). (Regarding "thickness", layer 320 is disposed "horizontally" for purposes of discussion herein and has a "thickness" in the vertical orientation. The length and width for layer 320 are "in plane" and the height or thickness is "out of plane".)

[0018] Returning to Figure 3, a higher RA product increases STTM resistance. While this does not necessarily increase write current, a higher RA product does increase write voltage (write voltage = Jc * RA product)(Jc refers to a critical switching current density to write a bit), which may be problematic for switching devices (e.g., transistor 120 of Figure 1) which have voltage restrictions. Also, a larger STTM resistance degrades current provided by a select transistor (e.g., MOS transistor 120 of Figure 1) since the Gate-to- Source voltage is smaller due to the larger IR drop across the STTM resistance. Further, there is RA contribution from layers 320 and 326. While increasing the RA from layer 326 will not lower TMR, increasing the RA from layer 320 will lower TMR (and decreasing the RA from layer 320 will increase TMR).

[0019] Applicant determined that forming cap layer 320 in a damaged/non-crystalline form can help decrease the resistance of layer 320. For example, forming cap layer 320 at a very thin level (e.g., 6 angstroms or less) forms a layer of somewhat varying consistency and which may not properly crystallize. As a result, the resistance (e.g., RA product) for the cap layer 320 decreases as current may more easily pass along fractures and faults in the cap layer. However, Applicant determined that while the poorly crystallized cap layer 320 had positive effects on resistance, the cap layer also has adverse effects on free layer 325. Specifically, the free layer 320 may crystallize from damaged and improperly crystallized cap layer 320 (during a subsequent annealing step) in addition to or instead of the thicker and more properly crystallized tunnel barrier layer 326. While a non-amorphous and highly crystalized free layer ("heavily textured") may be more likely if the free layer 325 is crystallized from crystallized layer 326, a non-amorphous and consistently crystalized free layer is less likely if the free layer's crystal structure is influenced by a poor crystal structure present in damaged layer 320. Applicant determined this presents a problem because the TMR of the pSTTM stack 300 depends on the free layer 325 properly crystallizing.

[0020] However, Applicant addressed the identified problem and determined the embodiment of Figure 4 helps prevent crystallization from the cap MgO layer, which increases TMR for the stack. Free layer 405 includes a lower layer 415 that forms a BCC (001) crystal structure after annealing at temperatures above 350C. Specifically, free layer 405 includes both: (a) a thin layer of CoFeB 415 (where some or all of the boron eventually leaves the layer) at the top interface to the tunnel barrier 404, and (b) a thin layer 425 of (CoFeB)ioo-xC_x alloy at the bottom interface to cap layer 406. This arrangement is important at least because the crystallization temperature of the (CoFeB)ioo-_xC_x alloy layer 425 is higher than a crystallization temperature for CoFeB layer 415 (also included in free layer 405). Thus, layer 415 crystallizes at a lower temperature than layer 425. In an embodiment at least a majority of layer 415 includes a BCC (001) crystal structure based on the crystal structure of tunnel barrier/spin filter 404. Free layer 425 may crystallize if the anneal temperature rises to a high enough level, but even at that point layer 415 will have already crystallized while layer 425 (still amorphous at that time) protects layer 415 crystal growth from adverse effects due to damaged/non-crystalline cap layer 406. In some embodiments layer 425 does not crystallize (e.g., because the anneal temperature never rises high enough and/or is not applied long enough) or crystallizes such that a majority of layer 425 is not the desired BCC (001) structure present in layer 415. In such a case where layer 425 is less crystallized than layer 415, layer 425 may have retained much or all of its deposited amorphous state such that layer 425 is more amorphous than layer 415. [0021] Accordingly, stack 400 exhibits high TMR because TMR is primarily driven by the interface between layers 404/415 and not layers 425/406. Because layer 415 is now more likely to include a quality BCC (001) structure due to the influence from layer 404 (and the shielding of influence from layer 406), stack 400 will exhibit high TMR.

[0022] In an embodiment, plotting TMR vs. annealing temperature shows the onset of crystallization (which corresponds to an elevated TMR greater than 50, 80, or 100%) for a CoFeB-C alloy layer (e.g., layer 425) is at least 50 C higher than the crystallization temperature for a CoFeB layer alone (e.g., layer 415), which reduces or eliminates adverse crystallization of layer 415 due to influences from cap layer 406.

[0023] Thus, memory 400 provides an embodiment with the following sequence of layers: electrode 401, pinning layer 402, fixed layer 403 (of MTJ 411), tunnel barrier 404, first free layer 415, second free layer 425 (where layers 415, 425 collectively form free layer 405), cap layer 406, magnetic layer 407 (which may be, for example, (a) one or more layers of CoFeB or (b) alternating layers of cobalt and (b)(1) palladium layers and/or (b)(2) platinum layers), cladding layer 408, and electrode layer 410. Layer 407 may be a "stability boost magnet" that helps stabilize the memory state of memory 400. In an embodiment contact layers 401, 410 each include a metal such as tantalum and/or ruthenium. Pinning layer 402 may be otherwise known as a Synthetic Antiferromagnetic layer (SAF).

[0024] In an embodiment cladding layer 408 may be between contact layers 401, 410. The cladding layer may include, for example, tantalum. A cladding layer, as used herein, is a layer that substantially covers a portion of a structure, such as memory 400. For example, layer 408 is shown primarily covering an upper surface of layer 407. Layer 408 is not included in all embodiments. In some embodiments layer 408 serves as a contact layer (so that layer 410 may be unnecessary). Layer 408 may serve as an adhesion layer for the top contact 410 and may include, for example, tantalum.

[0025] Cap layer 406 and/or tunnel barrier 404 may include MgO. First layer 415 may include a plurality of metals (e.g., cobalt and iron) and may directly contact the tunnel barrier layer 404. Second layer 425 may include the same plurality of metals (e.g., cobalt and iron) as layer 415 but may also include an element selected from the group consisting of carbon, silicon, germanium, tin, or phosphorous. The second layer 425 may directly contact the oxide cap layer 406.

[0026] As mentioned above, in an embodiment layers 415, 425 each include cobalt and iron. In addition, both of layers 415, 425 may include boron. However, the amount of boron present in either of the layers may be a function of anneal temperature and the duration (time) of the anneal process. Thus, in an embodiment where the anneal is performed at a temperature above the crystallization temperature of layer 415 but below the crystallization temperature of layer 425 (e.g., at or below 400 degrees C for about 30 minutes) boron may migrate out of layer 415 more than with layer 425, thereby leaving in the final post-anneal product far more boron in layer 425 than layer 415. For example, in such an instance the second CoFeB layer 425 has more boron atomic mass than the first CoFeB layer 415. In some embodiments layer 415 may include little to no boron due to the annealing while layer 425 still includes boron after annealing.

[0027] Along these same lines the first layer 415 may include a first material composition. That composition may be primarily CoFe and any originally deposited boron may have migrated out of layer 415 during annealing. As mentioned above, boron may still be present in layer 425. In such a case layer 425 includes a second material composition, which may be (CoFeB)ioo-xC_x. Due to the presence of carbon and boron in layer 425, the cobalt and the iron collectively comprise a higher percentage of the first material composition than the second material composition.

[0028] As mentioned above, layer 425 may include an element such as carbon, silicon, germanium, tin, phosphorous, and combinations thereof. In some embodiments the first layer 415 generally does not include the element (e.g., has less than 1% atomic mass of the element). Such an arrangement helps keep a differential in crystallization temperatures between layers 415, 425.

[0029] In an embodiment the first layer has a first thickness 415' and the second layer 425 has a second thickness 425' that is thinner than the first thickness. Further, in an embodiment the oxide layer 406 has a thickness 406' that is thinner than thickness 404' for the tunnel barrier layer 404. In an embodiment thickness 415' is around 1.5 nm but in other embodiments is generally between .5 and 2.0 nm. In the same embodiment thickness 425' is around .5 nm but in other embodiments is generally between .1 and .7 nm. These thicknesses are critical values in some embodiments in order to arrive at proper RA product and TMR levels for memory stacks.

[0030] As mentioned above cap layer 406 may be damaged/non-crystalline to lower its resistance level while maintaining its perpendicular anisotropy contributions. In such a case the cap oxide layer 406 has a RA product that is less than an RA product of the tunnel barrier layer 404.

[0031] Various embodiments may be used with various forms of composite free layers. For example, in Figure 5 A the free layer includes first and second layers 515, 525. The first layer 515 is approximately 1.0 nm thick and includes CoFeB. The second layer 525 is approximately .5 nm thick and includes (CoFeB)ioo-_xC_x. The amount of boron in layer 515 may change after annealing.

[0032] In Figure 5B the free layer includes first and second layers 515, 525. The first layer 515 is approximately 1.0 nm thick and includes CoFeB₃₀. The second layer 525 is approximately .5 nm thick and includes (Co₂oFe6oB₂o)ioo-_xC_x. The first and second layers each include boron; however the second layer has a chemical composition with a lower percentage of boron (e.g., 20%) than a chemical composition of the first layer (e.g., 30%).

[0033] In Figure 5C the free layer includes first and second layers 515, 525 as well as third layer 526. The first layer 515 is approximately .5 nm thick and includes CoFeB₃₀. The second layer 525 is approximately .6 nm thick and includes (CoFeB)ioo-_xC_x. The third layer 526 is approximately .4 nm thick and includes Co₂oFe₆oB₂o. The first and third layers each include boron; however the third layer has a chemical composition with a lower percentage of boron (e.g., 20%) than a chemical composition of the first layer (e.g., 30%).

[0034] In Figure 5D the free layer includes first and second layers 515, 525 as well as third layer 526. The first layer 515 is approximately 1.55 nm thick and includes CoFeB. The second layer 525 is approximately .6 nm thick and includes (CoFeB)i₀o-_xC_x. The third layer 526 is approximately .3 nm thick and includes tungsten.

[0035] In Figure 5E the free layer includes first and second layers 515, 525 as well as third and fourth layers 526, 527. The first layer 515 is approximately 1.55 nm thick and includes CoFeB. The second layer 525 is approximately .3 nm thick and includes (CoFeB)i₀o-_xC_x. The third layer 526 is approximately .3 nm thick and includes tungsten. The fourth layer 527 is approximately .3 nm thick and includes CoFeB.

[0036] Figure 6 depicts an embodiment wherein memory 600 comprises a perpendicular STTM that includes MTJ 611. The MTJ has perpendicular anisotropy. The memory cell includes a 1T-1X (T = transistor, X = capacitor or resistor) at a small cell size. The MTJ comprises contacts 601, 610, pinning layer 602, fixed layer 603, tunnel barrier layer 604, free layer 605, cap layer 606, composite stability boost magnet layer 607 (e.g., including (a) CoFeB or (b) alternating cobalt and (b)(1) palladium layers and/or (b)((2) platinum layers), and cladding layer 608. The MTJ couples bit line 625 to selection switch 621 (e.g., transistor), word line 620, and sense line 615. Free layer 605 may include first, second, and third layers 615, 625, 626. First layer 615 may include crystallized CoFe with a BCC (001) structure. Second layer 625 may include amorphous or poorly crystallized CoFeB alloyed with carbon. Third layer 626 may include tungsten.

[0037] The MTJ of Figure 6 may be located on a substrate. In an embodiment, the substrate is a bulk semi conductive material as part of a wafer. In an embodiment, the semi conductive substrate is a bulk semi conductive material as part of a chip that has been singulated from a wafer. In an embodiment, the semi conductive substrate is a semiconductive material that is formed above an insulator such as a semiconductor on insulator (SOI) substrate. There may be one or more layers between the MTJ and the substrate. There may be one or more layers above the MTJ.

[0038] Figure 7 includes a method 700 in an embodiment. Block 701 includes forming a MTJ including a fixed magnetic layer and a tunnel barrier layer. Block 702 includes forming a first layer, which includes a plurality of metals (e.g., CoFeB), in direct contact with the tunnel barrier layer. Block 703 includes forming a second layer on the first layer, wherein the second layer includes the plurality of metals (e.g., CoFeB) and an element selected from the group consisting of carbon, silicon, germanium, tin, phosphorous, and combinations thereof. Block 704 includes forming an oxide layer (e.g., MgO) in direct contact with the second layer. Block 705 includes annealing the first layer at a temperature (e.g., 395 degrees C), which is above a crystallization temperature of the first layer (e.g., 390-400 degrees C) but below a crystallization temperature of the second layer (e.g., > 400 degrees C), to crystallize a majority of the first layer with a BCC (001) crystal structure. Block 705 actually entails subjecting the entire memory stack to elevated temperatures which may be high enough to anneal a layer, such as the first layer (but possibly not high enough to anneal another layer, such as the second layer). In an embodiment block 705 further includes migrating boron out of the first layer in response to annealing the first layer at the temperature which is above a crystallization temperature of the first layer but below a crystallization temperature of the second layer.

[0039] Returning to Figure 4 and as mentioned above, in an embodiment the tunnel barrier layer 404 and the oxide layer 406 both include magnesium oxide. However, in other embodiments layer 404 and/or layer 406 may include any one or more of the following: tungsten oxide (W0₂), vanadium oxide (VO and/or V₂0₂), indium oxide (InOx), aluminum oxide (AI₂O₃), ruthenium oxide (RuOx), MgAlOx, HfOx, and/or TaO. For example, in an embodiment layer 404 includes MgO and layer 406 includes any one or more of the following: W0₂, VO, V₂0₂, InOx, A1₂0₃, RuOx, MgAlOx, HfOx, and/or TaO.

[0040] Figure 4 is an example of an embodiment whereby a combination of layers induces increased stability (due to layers 406, 407) and TMR (due to properly crystallized layer 415) without unnecessarily increasing RA product (as is the case with the dual MgO layers found in Figure 3). In other words, this arrangement of layers (a free layer portion that is allowed to crystallize in response to the tunnel barrier and which is blocked from crystallizing based on the cap oxide layer by an additional free layer) induces greater stability without overly increasing RA product (which may adversely affect write/read voltages) or diminishing TMR (which may complicate accurate reads of memory states).

[0041] Referring now to Figure 8, shown is a block diagram of an example system with which embodiments can be used. As seen, system 900 may be a smartphone or other wireless communicator or any Internet of Things (IoT) device. A baseband processor 905 is configured to perform various signal processing with regard to communication signals to be transmitted from or received by the system. In turn, baseband processor 905 is coupled to an application processor 910, which may be a main CPU of the system to execute an OS and other system software, in addition to user applications such as many well-known social media and multimedia apps. Application processor 910 may further be configured to perform a variety of other computing operations for the device. [0042] In turn, application processor 910 can couple to a user interface/display 920 (e.g., touch screen display). In addition, application processor 910 may couple to a memory system including a non-volatile memory, namely a flash memory 930 (which may include memory cells such as those described in Figures 4, 5, and/or 6) and a system memory, namely a DRAM 935 (which may include memory cells such as those described in Figures 4, 5, and/or 6). In some embodiments, flash memory 930 may include a secure portion 932 (which may include memory cells such as those described in Figures 4, 5 and/or 6) in which secrets and other sensitive information may be stored. As further seen, application processor 910 also couples to a capture device 945 such as one or more image capture devices that can record video and/or still images.

[0043] A universal integrated circuit card (UICC) 940 comprises a subscriber identity module, which in some embodiments includes a secure storage 942 (which may include memory cells such as those described in Figures 4, 5, and/or 6) to store secure user information. System 900 may further include a security processor 950 (e.g., Trusted Platform Module (TPM)) that may couple to application processor 910. A plurality of sensors 925, including one or more multi-axis accelerometers may couple to application processor 910 to enable input of a variety of sensed information such as motion and other environmental information. In addition, one or more authentication devices 995 may be used to receive, for example, user biometric input for use in authentication operations.

[0044] As further illustrated, a near field communication (NFC) contactless interface 960 is provided that communicates in a NFC near field via an NFC antenna 965. While separate antennae are shown, understand that in some implementations one antenna or a different set of antennae may be provided to enable various wireless functionalities.

[0045] A power management integrated circuit (PMIC) 915 couples to application processor 910 to perform platform level power management. To this end, PMIC 915 may issue power management requests to application processor 910 to enter certain low power states as desired. Furthermore, based on platform constraints, PMIC 915 may also control the power level of other components of system 900.

[0046] To enable communications to be transmitted and received such as in one or more IoT networks, various circuitries may be coupled between baseband processor 905 and an antenna 990. Specifically, a radio frequency (RF) transceiver 970 and a wireless local area network (WLAN) transceiver 975 may be present. In general, RF transceiver 970 may be used to receive and transmit wireless data and calls according to a given wireless communication protocol such as 3G or 4G wireless communication protocol such as in accordance with a code division multiple access (CDMA), global system for mobile communication (GSM), long term evolution (LTE) or other protocol. In addition a GPS sensor 980 may be present, with location information being provided to security processor 950 for use as described herein when context information is to be used in a pairing process. Other wireless communications such as receipt or transmission of radio signals (e.g., AM/FM) and other signals may also be provided. In addition, via WLAN transceiver 975, local wireless communications, such as according to a Bluetooth™ or IEEE 802.11 standard can also be realized.

[0047] Referring now to Figure 9, shown is a block diagram of a system in accordance with another embodiment of the present invention. Multiprocessor system 1000 is a point-to-point interconnect system such as a server system, and includes a first processor 1070 and a second processor 1080 coupled via a point-to-point interconnect 1050. Each of processors 1070 and 1080 may be multicore processors such as SoCs, including first and second processor cores (i.e., processor cores 1074a and 1074b and processor cores 1084a and 1084b), although potentially many more cores may be present in the processors. In addition, processors 1070 and 1080 each may include a secure engine 1075 and 1085 to perform security operations such as attestations, IoT network onboarding or so forth.

[0048] First processor 1070 further includes a memory controller hub (MCH) 1072 and point-to-point (P-P) interfaces 1076 and 1078. Similarly, second processor 1080 includes a MCH 1082 and P-P interfaces 1086 and 1088. MCH's 1072 and 1082 couple the processors to respective memories, namely a memory 1032 and a memory 1034, which may be portions of main memory (e.g., a DRAM) locally attached to the respective processors. These memories may include memory cells such as those described in Figures 4, 5, and/or 6. First processor 1070 and second processor 1080 may be coupled to a chipset 1090 via P-P interconnects 1052 and 1054, respectively. Chipset 1090 includes P-P interfaces 1094 and 1098. [0049] Furthermore, chipset 1090 includes an interface 1092 to couple chipset 1090 with a high performance graphics engine 1038, by a P-P interconnect 1039. In turn, chipset 1090 may be coupled to a first bus 1016 via an interface 1096. Various input/output (I/O) devices 1014 may be coupled to first bus 1016, along with a bus bridge 1018 which couples first bus 1016 to a second bus 1020. Various devices may be coupled to second bus 1020 including, for example, a keyboard/mouse 1022, communication devices 1026 and a data storage unit 1028 such as a non-volatile storage or other mass storage device (which may include memory cells such as those described in Figures 4, 5, and/or 6). As seen, data storage unit 1028 may include code 1030, in one embodiment. As further seen, data storage unit 1028 also includes a trusted storage 1029 (which may include memory cells such as those described in Figures 4, 5, and/or 6) to store sensitive information to be protected. Further, an audio I/O 1024 may be coupled to second bus 1020.

[0050] Embodiments may be used in environments where IoT devices may include wearable devices or other small form factor IoT devices. Referring now to Figure 10, shown is a block diagram of a wearable module 1300 in accordance with another embodiment. In one particular implementation, module 1300 may be an Intel® Curie™ module that includes multiple components adapted within a single small module that can be implemented as all or part of a wearable device. As seen, module 1300 includes a core 1310 (of course in other embodiments more than one core may be present). Such core may be a relatively low complexity in-order core, such as based on an Intel Architecture® Quark™ design. In some embodiments, core 1310 may implement a TEE as described herein. Core 1310 couples to various components including a sensor hub 1320, which may be configured to interact with a plurality of sensors 1380, such as one or more biometric, motion environmental or other sensors. A power delivery circuit 1330 is present, along with a non-volatile storage 1340 (which may include memory cells such as those described in Figures 4, 5, and/or 6). In an embodiment, this circuit may include a rechargeable battery and a recharging circuit, which may in one embodiment receive charging power wirelessly. One or more input/output (IO) interfaces 1350, such as one or more interfaces compatible with one or more of USB/SPI/I2C/GPIO protocols, may be present. In addition, a wireless transceiver 1390, which may be a Bluetooth™ low energy or other short-range wireless transceiver is present to enable wireless communications as described herein. Understand that in different implementations a wearable module can take many other forms. Wearable and/or IoT devices have, in comparison with a typical general purpose CPU or a GPU, a small form factor, low power requirements, limited instruction sets, relatively slow computation throughput, or any of the above.

[0051] While several embodiments herein describe perpendicular STTM, other embodiments are not so limited and may concern in plane (non-perpendicular) STTM, as well as embodiments that are neither fully in plane (non-perpendicular) nor fully out of plane (perpendicular) but are instead something in between in plane and out of plane.

[0052] At times herein a layer "A" is said to "directly contact" a layer "B". This includes situations where one considers, for example, the layer A to be a sublayer of another layer. Further, for instance, the layer B may include oxidation at its surface/interface to layer "C". Such a situation would still comprise layer B directly contacting layer C despite the layer B including surface oxidation.

[0053] While several embodiments include layers comprising CoFeB (e.g., layer 407), other embodiments may include fixed, free, and/or boost magnet layers that are composite layers. Any such composite layer could itself include a combination of layers such as CoFe/CoFeB; CoFeB/Ta/CoFeB; or CoFe/CoFeB/Ta/CoFeB/CoFe. Further, other embodiments may include tunnel barriers having something other than MgO, such as other oxides (e.g., aluminum oxide).

[0054] The following examples pertain to further embodiments.

[0055] Example 1 includes an apparatus comprising: a magnetic tunnel junction (MTJ) including a fixed magnetic layer and a tunnel barrier layer; an oxide layer; a first layer between the oxide layer and the tunnel barrier layer; a second layer between the first layer and the oxide layer; wherein: (a)(i) the first layer includes a plurality of metals and directly contacts the tunnel barrier layer, and (a)(ii) the second layer includes the plurality of metals and an element selected from the group consisting of carbon, silicon, germanium, tin, phosphorous, or combinations thereof.

[0056] Another version of Example 1 includes an apparatus comprising: a magnetic tunnel junction (MTJ) including a fixed magnetic layer and a tunnel barrier layer; a first layer on the tunnel barrier layer; a second layer on the first layer; and an oxide layer on the second layer; wherein: (a)(i) the first layer includes a plurality of metals and directly contacts the tunnel barrier layer, and (a)(ii) the second layer includes the plurality of metals and an element selected from the group consisting of carbon, silicon, germanium, tin, phosphorous, or combinations thereof.

[0057] Example 2 includes the apparatus of example 1 wherein the second layer directly contacts the oxide layer.

[0058] Example 3 includes the apparatus of example 2 wherein the oxide layer and the tunnel barrier layer each include magnesium oxide.

[0059] Example 4 includes the apparatus of example 3 wherein the plurality of metals includes cobalt and iron.

[0060] Example 5 includes the apparatus of example 4 wherein the first layer does not include the element.

[0061] Another version of Example 5 includes the apparatus of example 4 wherein the first layer includes less than 1% atomic mass of the element.

[0062] Example 6 includes the apparatus of example 4 wherein the element includes carbon.

[0063] Example 7 includes the apparatus of example 4 wherein the first layer generally includes a BCC (001) crystal structure.

[0064] For instance, a majority (>50%) includes the structure.

[0065] Example 8 includes the apparatus of example 7 wherein the second layer generally does not include a BCC (001) crystal structure.

[0066] For instance, a majority (>50%) does not include the structure.

[0067] Example 9 includes the apparatus of example 2 wherein the second layer is more amorphous than the first layer.

[0068] Another version example 9 includes the apparatus of example 2 wherein the second layer is less crystallized than the first layer. [0069] Example 10 includes the apparatus of example 2 wherein the first layer has a first crystallization temperature and the second layer has a second crystallization temperature that is higher than the first crystallization temperature.

[0070] Example 11 includes the apparatus of example 4 wherein: the first layer is primarily located in a plane; the first layer has a first thickness orthogonal to the plane; and the second layer has a second thickness that is thinner than the first thickness.

[0071] Example 12 includes the apparatus of example 11 wherein the oxide layer is thinner than the tunnel barrier layer.

[0072] Example 13 includes the apparatus of example 12 wherein the oxide layer has a resistance area (RA) product that is less than an RA product of the tunnel barrier layer.

[0073] Example 14 includes the apparatus of example 4 wherein: the first layer includes a first material composition and the second layer includes a second material composition; the cobalt and the iron collectively comprise a first percentage of the first material composition and the cobalt and the iron collectively comprise a second percentage of the second material composition; the first percentage is greater than the second percentage.

[0074] For instance, the first percentage may be >95% CoFe and the second percentage may be <95% CoFe.

[0075] Example 15 includes the apparatus of example 4 comprising a third layer between the first and second layers, wherein the third layer comprises a member selected from the group consisting of tungsten, molybdenum, tantalum, hafnium, or combinations thereof.

[0076] Example 16 includes the apparatus of example 4 comprising a third layer between the first and second layers, wherein: the first and third layers each include boron; the third layer has a chemical composition with a lower percentage of boron than a chemical composition of the first layer.

[0077] Another version of example 16 includes the apparatus of example 4 comprising a third layer between the first and second layers, wherein: the first and third layers each include boron; the third layer has a chemical composition with a percentage of boron; the first layer has a chemical composition with a percentage of boron that is more than the third layer's percentage of boron. [0078] Example 17 includes the apparatus of example 4 comprising a third layer between the first and second layers, wherein: the first layer is primarily located in a plane and has a first thickness orthogonal to the plane; the third layer is thinner than the first layer; the first and third layers include material compositions that are generally the same as one another.

[0079] Example 18 includes the apparatus of example 4 wherein the MTJ includes a free layer and the free layer includes the first and second layers.

[0080] Example 19 includes the apparatus of example 2 comprising first and second contact layers and an additional magnetic layer between the oxide layer and the second contact layer.

[0081] Example 20 includes the apparatus of example 1 comprising a perpendicular spin torque transfer memory (STTM) that includes the MTJ.

[0082] Example 21 includes the apparatus of example 1, wherein the MTJ has perpendicular anisotropy.

[0083] Example 22 includes a method comprising: forming a magnetic tunnel junction (MTJ) including a fixed magnetic layer and a tunnel barrier layer; forming a first layer, which includes a plurality of metals, in direct contact with the tunnel barrier layer; forming a second layer on the first layer, wherein the second layer includes the plurality of metals and an element selected from the group consisting of carbon, silicon, germanium, tin, phosphorous, and combinations thereof; forming an oxide layer in direct contact with the second layer; and annealing the first layer at a temperature, which is above a crystallization temperature of the first layer but below a crystallization temperature of the second layer, to crystallize a majority of the first layer with a BCC (001) crystal structure.

[0084] Again, "annealing the first layer" may relate to the subjecting the entire memory stack to an elevated temperature and that elevated temperature may be high enough to anneal the first layer but may or may not be high enough to anneal the second layer.

[0085] Another version of example 22 includes a method comprising: forming a magnetic tunnel junction (MTJ) including a fixed magnetic layer and a tunnel barrier layer; forming a first layer, which includes a plurality of metals, in direct contact with the tunnel barrier layer; forming a second layer on the first layer, wherein the second layer includes the plurality of metals and an element selected from the group consisting of carbon, silicon, germanium, tin, phosphorous, and combinations thereof; forming an oxide layer in direct contact with the second layer; and annealing the first layer at a temperature, which is above a crystallization temperature of the first layer but below a crystallization temperature of the second layer, to crystallize the first layer with a BCC (001) crystal structure.

[0086] Example 23 includes the method of example 22 wherein: the oxide layer and the tunnel barrier layer each include magnesium oxide; the plurality of metals includes cobalt and iron; and the element includes carbon.

[0087] Example 24 includes an apparatus comprising: a magnetic tunnel junction (MTJ) including fixed and tunnel barrier layers; a magnesium oxide (MgO) layer on the MTJ; a first cobalt, iron, and boron (CoFeB) layer directly contacting the tunnel barrier layer; and a second CoFeB layer, between the first and MgO layers, including carbon and directly contacting the MgO layer; wherein the second CoFeB layer has more boron atomic mass than the first CoFeB layer.

[0088] Another version of Example 24 includes an apparatus comprising: a magnetic tunnel junction (MTJ) including fixed and tunnel barrier layers; a magnesium oxide (MgO) layer on the MTJ; a first layer, directly contacting the tunnel barrier layer, which includes cobalt and iron; a second layer, between the first and MgO layers and directly contacting the MgO layer, which includes cobalt, iron, boron, and carbon; wherein the second CoFeB layer has more boron atomic mass than the first CoFeB layer.

[0089] Another version of example 24 includes an apparatus comprising: a magnetic tunnel junction (MTJ) including fixed and tunnel barrier layers; a magnesium oxide (MgO) layer on the MTJ; a first layer: (a)(i) directly contacting the tunnel barrier layer, and (a)(ii) including cobalt and iron; a second layer: (b)(i) directly contacting the MgO layer, and (b)(ii) including cobalt, iron, boron, and carbon; wherein the second layer has more boron atomic mass than the first layer.

[0090] For instance, the first layer may include no boron or simply contain less boron (as judged by atomic mass) than the second layer. [0091] Example 25 includes the apparatus of example 24 wherein a majority of the first CoFeB layer includes a BCC (001) crystal structure and a majority of the second CoFeB layer does not include a BCC (001) crystal structure.

[0092] Example 26 includes a system comprising: a processor; and a memory, coupled to the processor, according to example 1.

[0093] Example 27 includes the apparatus according to any of examples 8 to 20 wherein the second layer directly contacts the oxide layer.

[0094] Example 28 includes the apparatus according to any of examples 8 to 20 wherein the oxide layer and the tunnel barrier layer each include magnesium oxide.

[0095] Example 29 includes the apparatus according to any of examples 8 to 20 wherein the plurality of metals includes cobalt and iron.

[0096] Example 30 includes the apparatus according to any of examples 6 to 20 wherein the first layer includes less than 1% atomic mass of the element.

[0097] Example 31 includes the apparatus according to any of examples 5 and 7 to 20 wherein the element includes carbon.

[0098] Example 32 includes the apparatus according to any of examples 5 to 6 and 9 to 20 wherein the first layer generally includes a BCC (001) crystal structure.

[0099] Example 33 includes the apparatus according to any of examples 5 to 6 and 9 to 20 wherein the second layer generally does not include a BCC (001) crystal structure.

[00100] Example 34 includes the apparatus according to any of examples 3 to 8 and 10 to 20 wherein the second layer is more amorphous than the first layer.

[00101] Example 35 includes the apparatus according to any of examples 3 to 9 and 11 to 20 wherein the first layer has a first crystallization temperature and the second layer has a second crystallization temperature that is higher than the first crystallization temperature.

[00102] Example 36 includes the apparatus according to any of examples 5 to 10 and 14 to 20 wherein: the first layer is primarily located in a plane; the first layer has a first thickness orthogonal to the plane; and the second layer has a second thickness that is thinner than the first thickness.

[00103] Example 37 includes the apparatus according to any of examples 2 to 10 and 13 to 20 wherein the oxide layer is thinner than the tunnel barrier layer.

[00104] Example 38 includes the apparatus according to any of examples 2 to 11 and 14 to 20 wherein the oxide layer has a resistance area (RA) product that is less than an RA product of the tunnel barrier layer.

[00105] Example 39 includes the apparatus according to any of examples 2 to 3, 5 to 13, and 15 to 20 wherein: the first layer includes a first material composition and the second layer includes a second material composition; the cobalt and the iron collectively comprise a first percentage of the first material composition and the cobalt and the iron collectively comprise a second percentage of the second material composition; the first percentage is greater than the second percentage.

[00106] Example 40 includes the apparatus according to any of examples 2 to 3, 5 to 14, and 18 to 20 comprising a third layer between the first and second layers, wherein the third layer comprises a member selected from the group consisting of tungsten, molybdenum, tantalum, hafnium, or combinations thereof.

[00107] Example 41 includes the apparatus according to any of examples 2 to 3, 5 to 14, and 18 to 20 comprising a third layer between the first and second layers, wherein: the first and third layers each include boron; the third layer has a chemical composition with a percentage of boron; the first layer has a chemical composition with a percentage of boron that is more than the third layer's percentage of boron.

[00108] Example 42 includes the apparatus according to any of examples 2 to 3, 5 to 14, and 18 to 20 comprising a third layer between the first and second layers, wherein: the first layer is primarily located in a plane and has a first thickness orthogonal to the plane; the third layer is thinner than the first layer; and the first and third layers include material compositions that are generally the same as one another. [00109] Example 43 includes the apparatus according to any of examples 2 to 3, 5 to 17, and 19 to 20 wherein the MTJ includes a free layer and the free layer includes the first and second layers.

[00110] Example 44 includes the apparatus according to any of examples 3 to 18 comprising first and second contact layers and an additional magnetic layer between the oxide layer and the second contact layer.

[00111] Example 45 includes the apparatus according to any of examples 2 to 19 comprising a perpendicular spin torque transfer memory (STTM) that includes the MTJ.

[00112] The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the "top" surface of that substrate; the substrate may actually be in any orientation so that a "top" side of a substrate may be lower than the "bottom" side in a standard terrestrial frame of reference and still fall within the meaning of the term "top." The term "on" as used herein (including in the claims) does not indicate that a first layer "on" a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

What is claimed is: 1. An apparatus comprising:

a magnetic tunnel junction (MTJ) including a fixed magnetic layer and a tunnel barrier layer;

a first layer on the tunnel barrier layer;

a second layer on the first layer; and

an oxide layer on the second layer;

wherein: (a)(i) the first layer includes a plurality of metals and directly contacts the tunnel barrier layer, and (a)(ii) the second layer includes the plurality of metals and an element selected from the group consisting of carbon, silicon, germanium, tin, phosphorous, or combinations thereof.

2. The apparatus of claim 1 wherein the second layer directly contacts the oxide layer.

3. The apparatus of claim 2 wherein the oxide layer and the tunnel barrier layer each include magnesium oxide.

4. The apparatus of claim 3 wherein the plurality of metals includes cobalt and iron.

5. The apparatus of claim 4 wherein the first layer includes less than 1% atomic mass of the element.

6. The apparatus of claim 4 wherein the element includes carbon.

7. The apparatus of claim 4 wherein the first layer generally includes a BCC (001) crystal structure.

8. The apparatus of claim 7 wherein the second layer generally does not include a BCC (001) crystal structure.

9. The apparatus of claim 2 wherein the second layer is more amorphous than the first layer.

10. The apparatus of claim 2 wherein the first layer has a first crystallization temperature and the second layer has a second crystallization temperature that is higher than the first crystallization temperature.

11. The apparatus of claim 4 wherein:

the first layer is primarily located in a plane;

the first layer has a first thickness orthogonal to the plane; and

the second layer has a second thickness that is thinner than the first thickness.

12. The apparatus of claim 11 wherein the oxide layer is thinner than the tunnel barrier layer.

13. The apparatus of claim 12 wherein the oxide layer has a resistance area (RA) product that is less than an RA product of the tunnel barrier layer.

14. The apparatus of claim 4 wherein:

the first layer includes a first material composition and the second layer includes a second material composition;

the cobalt and the iron collectively comprise a first percentage of the first material composition and the cobalt and the iron collectively comprise a second percentage of the second material composition;

the first percentage is greater than the second percentage.

15. The apparatus of claim 4 comprising a third layer between the first and second layers, wherein the third layer comprises a member selected from the group consisting of tungsten, molybdenum, tantalum, hafnium, or combinations thereof.

16. The apparatus of claim 4 comprising a third layer between the first and second layers, wherein: the first and third layers each include boron;

the third layer has a chemical composition with a percentage of boron;

the first layer has a chemical composition with a percentage of boron that is more than the third layer's percentage of boron.

17. The apparatus of claim 4 comprising a third layer between the first and second layers, wherein:

the first layer is primarily located in a plane and has a first thickness orthogonal to the plane;

the third layer is thinner than the first layer; and

the first and third layers include material compositions that are generally the same as one another.

18. The apparatus of claim 4 wherein the MTJ includes a free layer and the free layer includes the first and second layers.

19. The apparatus of claim 2 comprising first and second contact layers and an additional magnetic layer between the oxide layer and the second contact layer.

20. The apparatus of claim 1 comprising a perpendicular spin torque transfer memory (STTM) that includes the MTJ.

21. A system comprising:

a processor; and

a memory, coupled to the processor, according to any one of claims 1 to 20.

22. A method comprising:

forming a magnetic tunnel junction (MTJ) including a fixed magnetic layer and a tunnel barrier layer;

forming a first layer, which includes a plurality of metals, in direct contact with the tunnel barrier layer; forming a second layer on the first layer, wherein the second layer includes the plurality of metals and an element selected from the group consisting of carbon, silicon, germanium, tin, phosphorous, or combinations thereof;

forming an oxide layer in direct contact with the second layer; and

annealing the first layer at a temperature, which is above a crystallization temperature of the first layer but below a crystallization temperature of the second layer, to crystallize the first layer with a BCC (001) crystal structure.

23. The method of claim 22 wherein:

the oxide layer and the tunnel barrier layer each include magnesium oxide;

the plurality of metals includes cobalt and iron; and

the element includes carbon.

24. An apparatus comprising:

a magnetic tunnel junction (MTJ) including fixed and tunnel barrier layers;

a magnesium oxide (MgO) layer on the MTJ;

a first layer: (a)(i) directly contacting the tunnel barrier layer, and (a)(ii) including cobalt and iron;

a second layer: (b)(i) directly contacting the MgO layer, and (b)(ii) including cobalt, iron, boron, and carbon;

wherein the second layer has more boron atomic mass than the first layer.

25. The apparatus of claim 24 wherein a majority of the first CoFeB layer includes a BCC (001) crystal structure and a majority of the second CoFeB layer does not include a BCC (001) crystal structure.