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WO2018182571A1 - Lignes de polarisation de flux de courant commandé dans des dispositifs à bits quantiques - Google Patents

Lignes de polarisation de flux de courant commandé dans des dispositifs à bits quantiques Download PDF

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Publication number
WO2018182571A1
WO2018182571A1 PCT/US2017/024396 US2017024396W WO2018182571A1 WO 2018182571 A1 WO2018182571 A1 WO 2018182571A1 US 2017024396 W US2017024396 W US 2017024396W WO 2018182571 A1 WO2018182571 A1 WO 2018182571A1
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Prior art keywords
center conductor
quantum
squid
flux bias
quantum circuit
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Application number
PCT/US2017/024396
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English (en)
Inventor
Jeanette M. Roberts
Stefano Pellerano
Roman CAUDILLO
Zachary R. YOSCOVITS
James S. Clarke
Adel A. ELSHERBINI
David J. Michalak
Ravi Pillarisetty
Hubert C. GEORGE
Nicole K. THOMAS
Kanwaljit SINGH
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Intel Corporation
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Priority to PCT/US2017/024396 priority Critical patent/WO2018182571A1/fr
Publication of WO2018182571A1 publication Critical patent/WO2018182571A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F7/00—Magnets
    • H01F7/06—Electromagnets; Actuators including electromagnets
    • H01F7/064—Circuit arrangements for actuating electromagnets
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/02—Measuring direction or magnitude of magnetic fields or magnetic flux
    • G01R33/035—Measuring direction or magnitude of magnetic fields or magnetic flux using superconductive devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/383—Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects
    • H10D48/3835—Semiconductor qubit devices comprising a plurality of quantum mechanically interacting semiconductor quantum dots, e.g. Loss-DiVincenzo spin qubits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00

Definitions

  • This disclosure relates generally to the field of quantum computing, and more specifically, to flux bias lines for use in quantum circuit/qubit devices.
  • Quantum computing refers to the field of research related to computation systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.
  • FIG. 1A provides a schematic illustration of a superconducting quantum circuit, according to some embodiments of the present disclosure.
  • FIG. IB provides a schematic illustration of an exemplary physical layout of a
  • FIG. 1C provides a schematic illustration of an exemplary transmon according to some embodiments of the present disclosure.
  • FIG. 2 provides a schematic illustration of an exemplary physical layout of a SQUID portion of a quantum circuit and a conventional flux bias line structure.
  • FIGS. 3A-3B provide schematic illustrations of alternative exemplary physical layouts of a SQUID portion of a quantum circuit and a flux bias line structure with a single center conductor line forming two partial loops and terminating with a ground connection, according to some embodiments of the present disclosure.
  • FIGS. 4A-4B provide schematic illustrations of alternative exemplary physical layouts of a SQUID portion of a quantum circuit and a flux bias line structure with a single center conductor line forming two partial loops and terminating with a signal connection, according to some embodiments of the present disclosure.
  • FIGS. 5A-5B provide schematic illustrations of alternative exemplary physical layouts of a SQUID portion of a quantum circuit and a flux bias line structure with a single center conductor line split into two center conductor lines each forming a partial loop and including an inductor, according to some embodiments of the present disclosure.
  • FIGS. 6A-6B provide schematic illustrations of alternative exemplary physical layouts of a SQUID portion of a quantum circuit and a flux bias line structure with two separately driven center conductor lines each forming a partial loop, according to some embodiments of the present disclosure.
  • FIGS. 7A-7B provide schematic illustrations of alternative exemplary physical layouts of a SQUID portion of a quantum circuit and a flux bias line structure with a single center conductor line forming a single partial loop, according to some embodiments of the present disclosure.
  • FIG. 8 provides a flow chart of an exemplary method for fabricating a quantum circuit assembly with any of the flux bias line structures disclosed herein, according to some embodiments of the present disclosure.
  • FIGS. 9A and 9B are top views of a wafer and dies that may include one or more qubit devices with flux bias line structures disclosed herein.
  • FIG. 10 is a cross-sectional side view of a device assembly that may include one or more of qubit devices with flux bias line structures disclosed herein.
  • FIG. 11 is a block diagram of an example quantum computing device that may include one or more of qubit devices with flux bias line structures disclosed herein, in accordance with various embodiments.
  • quantum computing or quantum information processing, refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data.
  • quantum-mechanical phenomena is the principle of quantum superposition, which asserts that any two or more quantum states can be added together, i.e. superposed, to produce another valid quantum state, and that any quantum state can be represented as a sum of two or more other distinct states.
  • Quantum entanglement is another example of quantum-mechanical phenomena. Entanglement refers to groups of particles being generated or interacting in such a way that the state of one particle becomes intertwined with that of the others. Furthermore, the quantum state of each particle cannot be described independently. Instead, the quantum state is given for the group of entangled particles as a whole.
  • quantum-mechanical phenomena is sometimes described as a "collapse" because it asserts that when we observe (measure) particles, we unavoidably change their properties in that. once observed, the particles cease to be in a state of superposition or entanglement (i.e. by trying to ascertain anything about the particles, we collapse their state).
  • Quantum computers use so-called quantum bits, referred to as qubits (both terms “bits” and “qubits” often interchangeably refer to the values that they hold as well as to the actual devices that store the values). Similar to a bit of a classical computer, at any given time, a qubit can be either 0 or 1. However, in contrast to a bit of a classical computer, a qubit can also be 0 and 1 at the same time, which is a result of superposition of quantum states.
  • Entanglement also contributes to the unique nature of qubits in that input data to a quantum processor can be spread out among entangled qubits, allowing manipulation of that data to be spread out as well: providing input data to one qubit results in that data being shared to other qubits with which the first qubit is entangled.
  • Another challenge that is unique to quantum computing is the ability to provide substantially lossless connectivity between qubits at very low powers, e.g. as low as a power of a single photon that may be present in a particular resonator interconnecting two qubits.
  • superconducting qubits are promising candidates for building a quantum computer.
  • Superconducting qubits operate based on the Josephson effect, which refers to a macroscopic quantum phenomenon of supercurrent, i.e. a current that, due to zero electrical resistance, flows indefinitely long without any voltage applied, across a device known as a Josephson Junction.
  • Josephson Junctions are integral building blocks in quantum circuits employing
  • superconducting qubit devices forming the basis of quantum circuit elements that can approximate functionality of theoretically designed qubits.
  • a pair of Josephson Junctions and a loop of a superconducting material (i.e. a superconducting loop) connecting them form a so-called superconducting quantum interference device (SQUID).
  • SQUID superconducting quantum interference device
  • Applying magnetic field to the SQUID region of a superconducting qubit is generally referred to as a "flux control" of a qubit, and the magnetic field is generated by providing direct current (DC) or a pulse of current through an electrically conductive line generally referred to as a "flux bias line” (also known as a “flux line” or a “flux coil line”).
  • DC direct current
  • a flux bias line also known as a "flux line” or a "flux coil line”
  • Embodiments of the present disclosure propose new flux bias line configurations for controlling frequencies of superconducting qubits.
  • One exemplary proposed flux bias line structure includes a single center conductor line forming two partial loops.
  • Another exemplary structure includes two separately driven center conductor lines, each of the two center conductor lines forming a respective partial loop.
  • Yet another exemplary flux bias line structure includes a single center conductor line split into two center conductor lines, each of the two center conductor lines forming a respective partial loop and comprising a respective inductor loop.
  • Such structures provide improvements over conventional flux bias lines in generating a magnetic field that can tune the frequency of a qubit with sufficient degree of control while ensuring that the magnetic field does not substantially affect other components of a quantum circuit placed at farther distance.
  • the term line" in context of e.g. flux bias lines does not necessarily imply a straight line.
  • portions of any of the flux bias lines proposed herein may be formed with any suitable geometry according to various embodiments of the present disclosure, such as e.g. a straight line, a curved line, a loop, etc
  • the flux bias lines proposed herein include one or more center conductor lines forming one or more partial loops, where the term " partial loop" refers to a shape of a line that is at least partially circular or/and curved over on itself.
  • a partial loop formed by a portion of a center conductor line of a flux bias line structure may trace out an area on a plane of the line that is nearly but not completely enclosed - e.g., a portion of a center conductor line may trace out at least 70% of the perimeter of any enclosed two- dimensional shape such as a square, triangle, circle, or any arbitrary closed shape.
  • loop may be used, with an understanding that the loop may be a partial loop as described above.
  • the terms such as e.g. "flux bias line structure,” “transmission line structure,” “center conductor line structure,” and “ground plane structure” may be referred to without using the word “structure.”
  • the term “center conductor line” may be used interchangeably with the terms such as “conductor strip,” “signal path,” or “signal line” as known in microwave engineering.
  • the phrase “A and/or B” means (A), (B), or (A and B).
  • the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
  • the term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.
  • the notation "A/B/C” means (A), (B), and/or (C).
  • materials described herein as "superconducting materials” may refer to materials which exhibit superconducting behavior at typical qubit operating conditions (e.g. materials which exhibit superconducting behavior at very low temperatures at which qubits typically operate, and which may or may not exhibit such behavior at e.g. room temperatures).
  • the present disclosure may include references to microwave signals, this is done only because current qubits are designed to work with such signals because the energy in the microwave range is higher than thermal excitations at the temperature that qubits are operated at.
  • techniques for the control and measurement of microwaves are well known. For these reasons, typical frequencies of qubits are in 1-10 GHz, e.g. in 5-10 GHz, range, in order to be higher than thermal excitations, but low enough for ease of microwave engineering.
  • qubits can be designed to have any frequency. Therefore, in general, qubits could be designed to operate with signals in other ranges of electromagnetic spectrum and embodiments of the present disclosure could be modified accordingly. All of these alternative implementations are within the scope of the present disclosure.
  • quantum computing refers to the use of quantum mechanical properties to perform calculations. Some of these properties include superposition and entanglement.
  • classical computers are composed of bits that can either be in a 1 or a 0 state
  • a quantum computer is composed of quantum bits (i.e., qubits) which have states of
  • Quantum mechanics allows for superpositions of the
  • a qubit state When a qubit state is measured, it collapses to either state
  • Entanglement occurs when the interaction between two particles (e.g. two qubits) is such that the states of the two cannot be specified independently, but rather can only be specified for the whole system. This causes the states of the two qubits to be linked together such that measurement of one of the qubits, causes the state of the other qubit to collapse.
  • two particles e.g. two qubits
  • a physical system that can act as a qubit is needed. Such a system needs to have at least two states to act as 0 and 1 states. Note that it is not necessary to have a system with exactly only two states if the spacing between each energy level is different, such that each level can be addressed individually.
  • one type of physical system that could be used to implement qubits is based on use of superconducting materials and, therefore, such qubits are typically referred to as superconducting/superconductive qubits.
  • transmon qubits also simply referred to as "transmons”
  • two basic elements of superconducting quantum circuits are inductors and capacitors.
  • circuits made using only these two elements cannot make a system with two energy levels because, due to the even spacing between the system's energy levels, such circuits will produce harmonic oscillators with a ladder of equivalent states.
  • a nonlinear element is needed to have an effective two-level quantum state system, or qubit.
  • Josephson Junction is an example of such non-linear, non-dissipative circuit element.
  • Josephson Junctions may form the central circuit elements of a superconducting quantum computer.
  • a Josephson Junction acts as a superconducting tunnel junction. Cooper pairs tunnel across the barrier from one superconducting layer to the other. The electrical characteristics of this tunneling are governed by so-called Josephson relations which provide the basic equations governing the dynamics of the Josephson effect:
  • Equation (3) ⁇ is the phase difference in the superconducting wave function across the junction
  • l c the critical current
  • V is the voltage across the Josephson Junction
  • I is the current flowing through the Josephson Junction
  • h is the reduced Planck's constant
  • e electron's charge
  • Equation (3) looks like the equation for an inductor with inductance L [0042] Since inductance is a function of ⁇ , which itself is a function of I, the inductance of a Josephson Junction is non-linear, which makes an LC circuit formed using a Josephson Junction as the inductor have uneven spacing between its energy states.
  • Josephson Junctions in a transmon, which is one ensemble of superconducting qubit.
  • superconducting qubits such as e.g. charge qubits or flux qubits
  • Josephson Junctions combined with other circuit elements have similar functionality of providing the non-linearity necessary for forming an effective two-level quantum state, or qubit.
  • one or more Josephson Junctions allow realizing a quantum circuit element which has uneven spacing between its energy levels resulting in a unique ground and excited state system for the qubit. This is illustrated in FIG.
  • an exemplary superconducting quantum circuit 100 includes two or more qubits 102 (reference numerals following after a dash, such as e.g. qubit 102-1 and 102-2 indicate different instances of the same or analogous element).
  • Each of the superconducting qubits 102 may include one or more Josephson Junctions 104 connected to one or more other circuit elements 106, which, in combination with the Josephson Junction(s) 104, form a non-linear circuit providing a unique two-level quantum state for the qubit.
  • the drcuit elements 106 could be e.g. capacitors in transmons or superconducting loops in flux qubits.
  • an exemplary superconducting quantum circuit 100 typically includes means 108 for providing external control of qubits 102 and means 110 for providing internal control of qubits 102.
  • external control refers to controlling the qubits 102 from outside of, e.g., an integrated drcuit (IC) chip comprising the qubits, including control by a user of a quantum computer, while “internal control” refers to controlling the qubits 102 within the IC chip.
  • qubits 102 are transmon qubits
  • external control may be implemented by means of flux bias lines and by means of readout and drive lines (also known as "microwave lines” since qubits are typically designed to operate with microwave signals), described in greater detail below.
  • readout and drive lines also known as "microwave lines” since qubits are typically designed to operate with microwave signals
  • internal control lines for such qubits may be implemented by means of resonators, e.g., coupling and readout resonators, also described in greater detail below.
  • any one of the qubits 102, the external control means 108, and the external control means 110 of the quantum drcuit 100 may be provided on, over, or at least partially embedded in a substrate (not shown in FIG. 1A).
  • three classes may be distinguished: charge qubits, flux qubits, and phase qubits.
  • Transmons a type of charge qubits with the name being an abbreviation of "transmission line shunted plasma oscillation qubits" are particularly encouraging because they exhibit reduced sensitivity to charge noise.
  • FIG. IB provides a schematic illustration of an exemplary physical layout of a superconducting quantum circuit 100B where qubits are implemented as transmons, according to some embodiments of the present disclosure.
  • FIG. IB illustrates two qubits 102.
  • FIG. IB illustrates flux bias lines 112, microwave lines 114, a coupling resonator 116, a readout resonator 118, and external contacts, e.g. wirebonding pads, 120 and 122.
  • the flux bias lines 112 and the microwave lines may be viewed as examples of the external control means 108 shown in FIG. 1A.
  • the coupling resonator 116 and the readout resonator 118 may be viewed as examples of the internal control means 110 shown in FIG. 1A.
  • each qubit 102 may be read by way of its corresponding readout resonator 118. As explained below, the qubit 102 induces a resonant frequency in the readout resonator 118. This resonant frequency is then passed to the microwave lines 114 and communicated to the pads 122.
  • a readout resonator 118 may be provided for each qubit.
  • the readout resonator 118 may be a transmission line that includes a capacitive connection to ground on one side and is either shorted to the ground on the other side (for a quarter wavelength resonator) or has a capacitive connection to ground (for a half wavelength resonator), which results in oscillations within the transmission line (resonance), with the resonant frequency of the oscillations being close to the frequency of the qubit
  • the readout resonator 118 is coupled to the qubit by being in sufficient proximity to the qubit 102, more specifically in sufficient proximity to the capacitor of the qubit 102, when the qubit is implemented as a transmon, either through capacitive or inductive coupling.
  • the coupling resonator 116 allows coupling different qubits together in order to realize quantum logic gates.
  • the coupling resonator 116 is similar to the readout resonator 118 in that it is a transmission line that includes capacitive connections to ground on both sides (i.e. a half wavelength resonator), which also results in oscillations within the coupling resonator 116.
  • Each side of the coupling resonator 116 is coupled (again, either capacitively or inductively) to a respective qubit by being in sufficient proximity to the qubit, namely in sufficient proximity to the capacitor of the qubit, when the qubit is implemented as a transmon.
  • each side of the coupling resonator 116 has coupling with a respective different qubit, the two qubits are coupled together through the coupling resonator 116.
  • state of one qubit depends on the state of the other qubit, and the other way around.
  • coupling resonators may be employed in order to use a state of one qubit to control a state of another qubit.
  • the microwave line 114 may be used to not only readout the state of the qubits as described above, but also to control the state of the qubits.
  • the line operates in a half -duplex mode where, at some times, it is configured to readout the state of the qubits, and, at other times, it is configured to control the state of the qubits.
  • microwave lines such as the line 114 shown in FIG. IB may be used to only readout the state of the qubits as described above, while separate drive lines such as e.g. drive lines 124 shown in FIG. IB, may be used to control the state of the qubits.
  • the microwave lines used for readout may be referred to as readout lines (e.g. readout line 114), while microwave lines used for controlling the state of the qubits may be referred to as drive lines (e.g. drive lines 124).
  • the drive lines 124 may control the state of their respective qubits 102 by providing, using e.g. wirebonding pads 126 as shown in FIG. IB, a microwave pulse at the qubit frequency, which in turn stimulates (i.e. triggers) a transition between the 0 and 1 state of the qubit By varying the length of this pulse, a partial transition can be stimulated, giving a superposition of the 0 and 1 states of the qubit.
  • Flux bias lines, microwave lines, coupling resonators, drive lines, and readout resonators such as e.g. those described above, together form interconnects for supporting propagation of microwave signals.
  • any other connections for providing direct electrical interconnection between different quantum circuit elements and components such as e.g. connections from electrodes of Josephson Junctions to plates of the capacitors or to superconducting loops of SQUIDS or connections between two ground lines of a particular transmission line for equalizing electrostatic potential on the two ground lines, are also referred to herein as interconnects.
  • interconnect may also be used to refer to elements providing electrical interconnections between quantum circuit elements and components and non-quantum drcuit elements, which may also be provided in a quantum circuit, as well as to electrical interconnections between various non- quantum circuit elements provided in a quantum circuit.
  • non-quantum circuit elements which may be provided in a quantum circuit may include various analog and/or digital systems, e.g. analog to digital converters, mixers, multiplexers, amplifiers, etc.
  • the interconnects as shown in FIG. IB could have different shapes and layouts.
  • the term "line" as used herein in context of e.g. flux bias lines, microwave lines, etc. does not imply straight lines, unless specifically stated so.
  • some flux bias lines or parts thereof e.g. signal lines of various microwave transmission lines
  • other interconnect lines or parts thereof may comprise less curves, wiggles, and turns
  • some interconnect lines or parts thereof may comprise substantially straight lines.
  • various interconnects may intersect one another, in such a manner that they don't make an electrical connection, which can be done by using e.g.
  • Coupling resonators and readout resonators may be configured for capacitive coupling to other circuit elements at one or both ends in order to have resonant oscillations, whereas flux bias lines and microwave lines may be similar to conventional microwave transmission lines because there is no resonance in these lines.
  • Each one of these interconnects may be implemented as any suitable architecture of a microwave transmission line, such as e.g. a coplanar waveguide, a stripline, a microstrip line, or an inverted microstrip line. Typical materials to make the electrically conductive portions of these interconnects (e.g.
  • any ground plane structures which may be present in a microwave transmission line used to implement a flux bias line structure
  • aluminum Al
  • niobium Nb
  • niobium nitride NbN
  • titanium nitride TiN
  • niobium titanium NbTi
  • niobium titanium nitride NbTiN
  • suitable superconductors and alloys of superconductors, as well as non-superconducting conductors and their alloys may be used as well.
  • references to an electrically conductive material implies that a superconducting material can be used and vice versa, where the superconducting material could be any material(s) or any alloy of materials exhibiting superconductivity at qubits' operating conditions.
  • FIG. 1C illustrates an exemplary transmon device 128 which could be used as any one of the qubits 102, according to some embodiments of the present disclosure. Presence of a capacitor 130 of such a size that capacitive energy is significantly larger than the Josephson energy in a qubit of FIG. 1C indicates that the qubit is a transmon.
  • the capacitor 130 is configured to store energy in an electrical field as charges between the plates of the capacitor.
  • the capacitor 130 is depicted as an interdigitated capacitor, a particular shape of capacitor that provides a large capacitance with a small area, however, in various embodiments, other shapes and types of capacitors may be used as well. For example, such a capacitor could be implemented simply as two parallel plates with vacuum in between. Furthermore, in various embodiments, the capacitor 130 may be arranged in any direction with respect to the SQUID or a single Josephson Junction, not necessarily as shown in FIG. 1C.
  • the transmon illustrated in FIG. 1C includes two Josephson Junctions 132 incorporated into a superconducting loop 134.
  • the two Josephson Junctions 132 and the superconducting loop 134 together form a SQUID.
  • Magnetic fields generated by the flux bias line 112 extend to the SQUID (i.e. current in the flux bias line 112 create magnetic fields around the SQUID), which, in turn, tunes the frequency of the qubit
  • FIGs. 1A and IB illustrate examples of quantum circuits comprising only two qubits 102, embodiments with any larger number of qubits are possible and are within the scope of the present disclosure.
  • At least some of the flux bias lines 112 may be flux bias lines in the form of any of the arrangements described herein.
  • FIGs. IB and 1C illustrate embodiments specific to transitions
  • subject matter disclosed herein is not limited in this regard and may include other embodiments of quantum circuits implementing other types of superconducting qubits or qubits other than superconducting qubits that would also utilize flux bias lines as described herein, all of which are within the scope of the present disclosure.
  • superconducting qubit devices/circuits employing flux bias lines as described herein may be used to implement components associated with an integrated circuit (IC).
  • IC integrated circuit
  • Such components may include those that are mounted on or embedded in an IC, or those connected to an IC.
  • the IC may be either analog or digital and may be used in a number of applications within or associated with quantum systems, such as e.g. quantum processors, quantum amplifiers, quantum sensors, etc., as well as in a number of applications within or associated with non-quantum systems, depending on the components associated with the integrated circuit.
  • the integrated circuit may be employed as part of a chipset for executing one or more related functions in a system.
  • a flux bias line is placed sufficiently close to a SQUID loop of a superconducting qubit, so that the magnetic field generated by the electric current in the line can extend to the SQUID loop and tune the frequency of the qubit.
  • flux bias lines have been implemented as having a single center conductor line which splits into two lines as shown in FIG. 2 providing a schematic illustration of an exemplary physical layout 200 (a top view) of a SQUID portion 202 of a quantum circuit and a conventional flux bias line.
  • the SQUID portion 202 shown in FIG. 2 could e.g. be a portion of the transmon 128 shown in FIG. IC, or other type of superconducting qubit
  • the SQUID portion 202 includes a SQUID 204 comprising two Josephson Junctions 206 (the Josephson Junctions shown as black squares, only one of which being labeled with a reference numeral in FIG. 2 in order to not clutter the drawing), connected by a superconducting loop 208, the SQUID 204 being electrically connected to the capacitor 210 (only a portion of which is shown in FIG. 2; the electrical connection to the capacitor 210 is shown in FIG. 2 by the material with the pattern of the superconducting loop 208 extending to the capacitor 210).
  • FIG. 2 further illustrates a flux bias line 212 starting as a single center conductor line originating from an external source, e.g. from a wirebonding pad or any other electrical connection to the die that houses the quantum circuit.
  • the line 212 splits into two branches, labeled in FIG. 2 as branches 212a and 212b, forming a T-shaped object.
  • FIG. 2 and subsequent FIGS directions of the currents which may flow in flux bias lines is shown as arrows with labels that include " ⁇ for current; black triangles indicate ground termination of a line, while directions of the magnetic field generated by the currents in various portions of flux bias lines are shown either with a dot or with a cross, following the conventional notation used for magnetic fields going, respectively, in the direction "out of the page” or "into the page,” as used to show magnetic field directions according to the right-hand rule.
  • An inset 201 in FIG. 2 illustrates the right-hand rule.
  • FIG. 2 illustrates the right-hand rule.
  • a flux bias line may be implemented as coplanar waveguide transmission line structure that includes a center conductor line sandwiched, in a single plane, between two ground planes.
  • FIG. 2 and subsequent FIGS do not specifically illustrate ground planes in order to not clutter the drawings, but it is understood that such ground planes may be present in a given flux bias line structure discussed.
  • various types of microwave transmission line architectures may be employed, such as e.g.
  • a coplanar waveguide a stripline, a microstrip line, or an inverted microstrip line, each of which would include a center conductor line and one or more ground planes, where the center conductor lines of various flux bias line structures proposed herein can be used as the signal lines in any of these microwave transmission line architectures.
  • conventional flux bias line 212 is provided so that the current / provided in the line 212 is supposed to split into two halves in the branches 212a and 212b (shown as current 1 ⁇ 4 I in the branch 212a and current 1 ⁇ 2 I in the branch 212b), each of which branches forms a partial loop.
  • the current in the loop formed by the branch 212a results in generation of a magnetic field Ba in the direction that is perpendicular to and points out of the page of the drawing, the magnetic field Ba shown in FIG. 2 with a dot inside the branch 212a.
  • the current in the loop formed by the branch 212b results in generation of a magnetic field Bb in the direction that is perpendicular to and points into the page of the drawing, the magnetic field Bb shown in FIG. 2 with a cross inside the branch 212a.
  • the magnetic field Bb extends to the SQUID 204 causing the current in the SQUID loop and generation of the magnetic field Bi (where "i" of the notation "Bi” indicates "induced” magnetic field) inside the loop in the direction that is perpendicular to and points out of the page of the drawing, the magnetic field Bi shown in FIG. 2 with a dot inside the SQUID 204).
  • magnetic field Bb still serves its' purpose in tuning the frequency of the qubit by virtue of being provided in the vicinity of the SQUID 204 and by having the symmetry plane for field Ba and Bb offset with respect of the SQUID 204 to induce magnetic field Bi within the SQUID.
  • the current will split with 0.71 and 0.31 in the two branches, instead of the desired 0.51 and 0.51 split.
  • the ideal scenario described above may be significantly compromised - not only such an uneven distribution of currents impacts the ability to reduce or eliminate cross-talk at a distance (such the magnetic fields Ba and Bb will no longer be able to cancel each other) but it also affects the magnetic fields generated by each of the branches, in particular the magnetic field Bb, which affects the nearby field Bi in the SQUID 204, so that accurately tuning the frequency of the qubit becomes challenging, if not impossible.
  • such conventional flux bias lines often need to be calibrated to determine the actual amounts of current to be provided in the lines in order to achieve desired frequency tuning, a process that is both time-consuming and error-prone.
  • FIGS. 3A-3B provide schematic illustrations of alternative exemplary physical layouts 300A and 300B (top views) of a SQUID portion 302 of a quantum circuit and a flux bias line structure with a single center conductor line forming two partial loops and terminating with a ground connection, according to some embodiments of the present disclosure.
  • the physical layouts 300A and 300B as shown in FIGS. 3A and 3B, respectively, could be used in any of the quantum circuits employing flux bias lines, e.g. in any of the quantum circuits as described above with reference to FIGS. 1A-1C.
  • the SQUID portion 302 shown in FIG. 3A could e.g. be a portion of the transmon 128 shown in FIG.
  • the SQUID portion 302 may include a SQUID 304 comprising two Josephson Junctions 306 (similar to FIG. 2, the Josephson Junctions 306 are shown as black squares, only one of which being labeled with a reference numeral in FIG. 3A in order to not dutter the drawing), connected by a superconducting loop 308.
  • the SQUID 304 may be electrically connected to a capacitor 310, only a portion of which is shown in FIG. 3A (the electrical connection to the capacitor 310 is shown in FIG. 3A by the material with the pattern of the superconducting loop 308 extending to the capacitor 310).
  • FIG. 3A illustrates a flux bias line structure that includes a single center conductor line 312 originating from an external source, e.g. from a wirebonding pad or any other electrical connection to the die that houses the quantum circuit.
  • the center conductor line 312 is a continuous line that curves to form two partial loops - one partial loop is labeled in FIG. 3A as a loop 314a (the loop with a cross symbol inside) and the other partial loop is labeled in FIG. 3B as a loop 314b (the loop with a dot symbol inside) - and terminating with a ground connection 316.
  • the ground connection 316 may be any type of conductive contact connecting the center conductor line 312 to a ground potential.
  • the ground connection 316 may be implemented as a connection to the ground in a package housing the quantum circuit 300A, e.g. via a solder bump or ball, or any other type of suitable electrical connection.
  • the ground connection 316 may be implemented by providing an air bridge over e.g. a portion 318 of the center conductor line 312, to make an electrical connection to a ground plane for the center conductor line 312 (the ground plane not specifically shown in FIG. 3A).
  • ground planes are typically used when a die supports propagation of microwave signals in order to e.g. suppress microwave parallel plate modes, cross-coupling between circuital blocks, and substrate resonant modes. In general, providing ground pathways may improve signal quality, enable fast pulse excitation and improve the isolation between the different lines.
  • the SQUID 304 is provided near the loop 314a so that the magnetic field Ba extends to the SQUID 304 causing the current in the SQUID loop and generation of the magnetic field Bi inside the SQUID 304 in the direction that is perpendicular to and points out of the page of the drawing, as shown a dot inside the SQUID 304 in FIG. 3A.
  • the SQUID 304 may be provided at a distance d from the loop 314a, the distance d indicated in FIG. 3A, that may be between about 100 nanometers (nm) and 15 micrometers (micron), including all values and ranges therein, e.g.
  • the distance d would depend on the details of a particular implementation, such as e.g. materials used for the SQUID loop, substrate, flux bias line, current that would be provided in the flux bias line, etc.
  • the two partial loops shown in FIG. 3A may be of comparable sizes, e.g. they may enclose areas which are substantially equal, so that the fields generated in these loops can adequately cancel out in the distance.
  • an area enclosed by each of the loops may be between about 10,000 nm 2 and 2500 micron 2 , including all values and ranges therein, e.g. between 100 micron 2 and 1500 micron 2 or between 100 micron 2 and 900 micron 2 .
  • a perimeter of each of the two partial loops 314a and 314b may be between about 600 nm and 250 micron, induding all values and ranges therein, e.g.
  • loops 314a and 314b are shown in FIG. 3A to enclose substantially square/rectangular areas, various embodiments these loops can take on any other suitable shapes, such as e.g. substantially circular, wavy, oval, or any free form loop shapes, as long as running currents through those loops would generate magnetic fields Ba and Bb as described herein.
  • FIG. 3B provides an illustration of the SQUID portion 302 and the flux bias line 312 as shown in FIG. 3A, except that now the SQUID loop 304 is provided near the loop 314b. As can be seen by comparison of FIGS. 3A and 3B, this would result in generation of the of magnetic field Bi inside the SQUID 304 in the direction that is perpendicular to and points into the page of the drawing, as shown a cross inside the SQUID 304 in FIG. 3B. Other discussions provided for FIG. 3A are applicable to FIG. 3B and, therefore, in the interests of brevity, are not repeated.
  • FIGS. 4A-4B provide schematic illustrations of alternative exemplary physical layouts 400A and 400B (top views) of a SQUID portion 302 of a quantum circuit and a flux bias line structure with a single center conductor line forming two partial loops and terminating with a signal connection (i.e. having both one input and one output for the signal current flowing along the loops), according to some embodiments of the present disclosure.
  • the SQUID portion 302 of FIGS. 4A-4B is substantially the same as that shown in FIGS. 3A-3B and described above, which descriptions are not repeated here.
  • the physical layouts 40 ⁇ and 400B as shown in FIGS. 4A-4B, respectively could be used in any of the quantum circuits employing flux bias lines, e.g. in any of the quantum circuits as described above with reference to FIGS. 1A-1C.
  • FIG. 4A illustrates a flux bias line structure that includes a single center conductor line 412 originating from an external source, e.g. from a wirebonding pad or any other electrical connection to the die that houses the quantum circuit.
  • the center conductor line 412 is a continuous line that curves to form two partial loops - one partial loop is labeled in FIG. 4A as a loop 414a (the loop with a cross symbol inside) and the other partial loop is labeled in FIG. 4A as a loop 414b (the loop with a dot symbol inside), similar to the center conductor line 312 shown in FIGS. 3A- 3B.
  • the center conductor line 412 terminates with a signal connection 420 (i.e. the connection 420 is the output for the signal current flowing along the loops 414a and 414b).
  • the center conductor line 412 has to cross over a portion 418 of itself, which could be implemented via e.g. an air bridge 424, schematically illustrated in FIG. 4A. In other embodiments, the air bridge 424 could be substituted by an electrical connection made under the surface.
  • FIG. 4A generates a magnetic field Ba with an average direction perpendicular to and pointing into the page of the drawing in the loop 414a and generates a magnetic field Bb with an average direction perpendicular to and pointing out the page of the drawing in the loop 414b, as labeled with a cross and a dot in the loops 414a and 414b, respectively.
  • the SQUID 304 is provided near the loop 414a so that the magnetic field Ba extends to the SQUID 304 causing the current in the SQUID loop and generation of the magnetic field ⁇ inside the SQUID 304 in the direction that is perpendicular to and points out of the page of the drawing, as shown a dot inside the SQUID 304 in FIG. 4A.
  • the SQUID 304 may be provided at a distance d from the loop 414a, as was described above with reference to FIG. 3A. Discussions provided above regarding geometry and sizes of the loops 314a and 314b shown in FIGS. 3A-3B are applicable to the loops 414a and 414b shown in FIGS. 4A-4B and, therefore, in the interests of brevity, are not repeated.
  • FIG. 4B provides an illustration of the SQUID portion 302 and the flux bias line 412 as shown in FIG. 4A, except that in FIG. 4B the SQUID loop 304 is provided near the loop 414b.
  • this would result in generation of the of magnetic field Bi inside the SQUID 304 in the direction that is perpendicular to and points into the page of the drawing, as shown a cross inside the SQUID 304 in FIG. 4B.
  • Other discussions provided for FIG. 4A are applicable to FIG. 4B and, therefore, in the interests of brevity, are not repeated.
  • FIGS. 5A-5B provide schematic illustrations of alternative exemplary physical layouts 500A and 500B (top views) of a SQUID portion 302 of a quantum circuit and a flux bias line structure with a single center conductor line split into two center conductor lines each forming a partial loop and including an inductor, according to some embodiments of the present disclosure.
  • the SQUID portion 302 of FIGS. 5A-5B is substantially the same as that shown in FIGS. 3A-3B and described above, which descriptions are not repeated here.
  • the physical layouts 500A and 500B as shown in FIGS. 5A-5B, respectively could be used in any of the quantum circuits employing flux bias lines, e.g. in any of the quantum circuits as described above with reference to FIGS. 1A-1C.
  • FIG. 5A illustrates a flux bias line structure that includes a single center conductor line 512 originating from an external source, e.g. from a wirebonding pad or any other electrical connection to the die that houses the quantum circuit.
  • the center conductor line 512 splits into two branches - center conductor lines 512a and 512b - each branch being curved to form a partial loop - the partial loop formed by the branch 512a is labeled in FIG. 5A as a loop 514a (the loop with a dot symbol inside) and the partial loop formed by the branch 512b is labeled in FIG. 5A as a loop 514b (the loop with a cross symbol inside).
  • Each of the branches 512a and 512b terminates with a ground connection, shown in FIG. 5A as ground connections 516a and 516b, respectively. Discussions provided above for the ground connection 316 are applicable to the ground connections 516a and 516b and, therefore, in the interests of brevity, are not repeated.
  • each of the branches 512a and 512b includes a respective inductor 526a and 526b.
  • an inductor refers to a passive two-terminal electrical component with as inductance of value L.
  • the inductor could include the entire length of the line 512a/b, or a fraction of the line 512a/b, or be distributed along the line 512a/b.
  • the branches 512a and 512b have the same inductance, so that the current in one branch will be equal to the current in the other branch.
  • kinetic inductance arises because electrons have mass, so it takes time for an electric field to accelerate them, and for an opposing field to change their direction.
  • Kinetic inductance represents the inertia of electrons to change their direction when the direction of the electric field changes.
  • a superconducting wire With an alternating current of frequency ⁇ , a superconducting wire can be treated as two parallel conductors: one having the "normal'' (i.e. not superconducting) electrons with a resistance R, and the other one with the superconducting electrons with a kinetic inductance L k .
  • each of the branches 512a and 512b by the kinetic inductance of each of the branches 512a and 512b.
  • the kinetic inductance increases with increasing magnetic penetration depth and wire length, and decreases with increasing cross- sectional wire area.
  • these branches may be designed to have a desired inductance, e.g. the same inductance.
  • the length of each of the branches 512a and 512b may be greater than about 100 microns, which is sufficiently large to ensure the current is split equally between the two paths (e.g.
  • each of the inductors 526a and 526b may be implemented as an electrically conductive line, e.g. a wire (e.g. a portion of the respective split center conductor line 512a or 512b), of a given length and cross sectional area.
  • each of the inductors 526a and 526b may be implemented as wires with higher and well-controlled kinetic inductance, by either increasing the length, decreasing the area, or inserting materials with higher magnetic penetration depths.
  • the line width of the line implementing each of the inductors 526a and 526b may be between 50 nm and 15 micron, including all values and ranges therein, e.g.
  • the thickness of the line implementing each of the inductors 526a and 526b could be between 5 nm and 500 nm, including all values and ranges therein, e.g. between 10 nm and 30 nm.
  • the thickness of the line could be reduced by protecting the rest of the circuit with patterned photoresist, then applying a wet chemical etch or a dry plasma etch.
  • the current b-l in the center conductor line branch 512b generates a magnetic field Bb with an average direction perpendicular to and pointing into the page of the drawing in the loop 514b, as labeled with a cross in the loop 514b.
  • the SQUID 304 is provided near the loop 514b so that the magnetic field Bb extends to the SQUID 304 causing the current in the SQUID loop and generation of the magnetic field ⁇ inside the SQUID 304 in the direction that is perpendicular to and points out of the page of the drawing, as shown a dot inside the SQUID 304 in FIG. 5A.
  • the SQUID 304 may be provided at a distance d from the loop 514b, as was described above with reference to FIG. 3A. Discussions provided above regarding geometry and sizes of the loops 314a and 314b shown in FIGS. 3A-3B are applicable to the loops 514a and 514b shown in FIGS. 5A-5B and, therefore, in the interests of brevity, are not repeated.
  • FIG. 5B provides an illustration of the SQUID portion 302 and the flux bias line 512 as shown in FIG. 5A, except that in FIG. 5B the SQUID loop 304 is provided near the loop 514a. As can be seen by comparison of FIGS. 5A and 5B, this would result in generation of the of magnetic field Bl inside the SQUID 304 in the direction that is perpendicular to and points into the page of the drawing, as shown a cross inside the SQUID 304 in FIG. 5B. Other discussions provided for FIG. 5 A are applicable to FIG. 5B and, therefore, in the interests of brevity, are not repeated.
  • FIGS. 6A-6B provide schematic illustrations of alternative exemplary physical layouts 600A and 600B (top views) of a SQUID portion 302 of a quantum circuit and a flux bias line structure with two separately driven center conductor lines each forming a partial loop, according to some embodiments of the present disclosure.
  • the SQUID portion 302 of FIGS. 6A-6B is substantially the same as that shown in FIGS. 3A-3B and described above, which descriptions are not repeated here.
  • the physical layouts 600A and 600B as shown in FIGS. 6A-6B respectively, could be used in any of the quantum circuits employing flux bias lines, e.g. in any of the quantum circuits as described above with reference to FIGS. 1A-1C
  • FIG. 6A illustrates a flux bias line structure that includes two separately driven center conductor lines - lines 612-1 and 612-2 - originating from two respective external sources, e.g. from wirebonding pads or any other electrical connection to the die that houses the quantum circuit.
  • the first center conductor line 612-1 curves to form a partial loop labeled in FIG. 6A as a loop 614a (the loop with a dot symbol inside), while the second center conductor line 612-2 curves to form a partial loop labeled in FIG. 6A as a loop 614b (the loop with a cross symbol inside).
  • Each of the separate lines 612-1 and 612-2 terminates with a ground connection, shown in FIG. 6A as ground connections 616-1 and 616-1, respectively. Discussions provided above for the ground connection 316 are applicable to the ground connections 616-1 and 616-2 and, therefore, in the interests of brevity, are not repeated.
  • Currents l 1 and l 2 flowing through the center conductor lines 612-1 and 612-2, respectively, in the direction shown in FIG. 6A may be individually controlled to generate magnetic fields Ba and Bb of desired magnitude so that the desired Bi is generated while net magnetic field at a desired distance is minimized (to reduce unwanted crosstalk).
  • the current in the center conductor line 612-1 generates a magnetic field Ba with an average direction perpendicular to and pointing out of the page of the drawing in the loop 614a, as labeled with a dot in the loop 614a.
  • the current in the center conductor line 612-2 generates a magnetic field Bb with an average direction perpendicular to and pointing into the page of the drawing in the loop 614b, as labeled with a cross in the loop 614b.
  • the SQUID 304 is provided near the loop 614b so that the magnetic field Bb extends to the SQUID 304 causing the current in the SQUID loop and generation of the magnetic field Bi inside the SQUID 304 in the direction that is perpendicular to and points out of the page of the drawing, as shown a dot inside the SQUID 304 in FIG. 6A.
  • the SQUID 304 may be provided at a distance d from the loop 614b, as was described above with reference to FIG. 3A. Discussions provided above regarding geometry and sizes of the loops 314a and 314b shown in FIGS. 3A-3B are applicable to the loops 614a and 614b shown in FIGS. 6A-6B and, therefore, in the interests of brevity, are not repeated.
  • FIG. 6B provides an illustration of the SQUID portion 302 and the flux bias line structure comprising two separately driven center conductor lines 612-1 and 612-2 as shown in FIG. 6A, except that in FIG. 6B the SQUID loop 304 is provided near the loop 614a. As can be seen by comparison of FIGS. 6A and B, this would result in generation of the of magnetic field Bi inside the SQUID 304 in the direction that is perpendicular to and points into the page of the drawing, as shown a cross inside the SQUID 304 in FIG. 6B. Other discussions provided for FIG. 6A are applicable to FIG. 6B and, therefore, in the interests of brevity, are not repeated.
  • FIGS. 7A-7B provide schematic illustrations of alternative exemplary physical layouts 700A and 700B (top views) of a SQUID portion 302 of a quantum circuit and a flux bias line structure with a single center conductor line forming a single partial loop, according to some embodiments of the present disclosure.
  • the SQUID portion 302 of FIGS. 7A-7B is substantially the same as that shown in FIGS. 3A-3B and described above, which descriptions are not repeated here.
  • the physical layouts 700A and 700B as shown in FIGS. 7A-7B, respectively could be used in any of the quantum circuits employing flux bias lines, e.g. in any of the quantum circuits as described above with reference to FIGS. 1A-1C.
  • FIG. 7A illustrates a flux bias line structure that includes a single center conductor line 712 originating from an external source, e.g. from a wirebonding pad or any other electrical connection to the die that houses the quantum circuit.
  • the center conductor line 712 is a continuous line that curves to form a single loop labeled in FIG. 7A as a loop 714 (the loop with a cross symbol inside).
  • the center conductor line 712 terminates with a signal connection 720, similar to the signal connection 420 described above.
  • FIG. 7A Current / flowing through the center conductor line 712 in the direction shown in FIG. 7A generates a magnetic field Ba with an average direction perpendicular to and pointing into the page of the drawing in the loop 714, labeled with a cross.
  • the SQUID 304 is provided near the loop 714 so that the magnetic field Ba extends to the SQUID 304 causing the current in the SQUID loop and generation of the magnetic field Bi inside the SQUID 304 in the direction that is perpendicular to and points out of the page of the drawing, as shown a dot inside the SQUID 304 in FIG. 7A.
  • the SQUID 304 may be provided at a distance d from the loop 714, as was described above with reference to FIG. 3A.
  • FIG. 7B provides an illustration of the SQUID portion 302 and the flux bias line 712 as shown in FIG. 7 A, except that FIG. 7B illustrates an example of the flux bias line 712 being shaped differently (triangle vs. rectangle) and also illustrates that the flux bias line 712 may, alternatively, be terminated with a ground connection 716 instead of the signal connection 720 as shown in FIG. 7A.
  • the ground connection 716 may be implemented similar to the ground connection 316, described above.
  • the flux bias line structures proposed herein allow to generate precise local magnetic field to control SQUID frequency based on the absolute current magnitude and coils(s) geometry and not on other, poorly controllable, parameters such as e.g. non-ideal ground impedance, while still preserving magnetic field cancellation at farther distances to minimize unwanted crosstalk to other quantum circuits.
  • the embodiments with a single partial loop may provide the advantage of simpler fabrication.
  • the currents provided in the center line conductors proposed herein to generate magnetic fields which are used to tune (change) the qubit frequency may be low frequency pulses, e.g. with a frequency lower than 1 GHz.
  • quantum circuits with flux bias line structures as described above may be fabricated using any suitable fabrication techniques.
  • FIG. 8 provides a flow chart of a method 800 for fabricating a quantum circuit assembly with any of the flux bias line structures disclosed herein, according to some embodiments of the present disclosure.
  • the operations of the method 800 are illustrated in a particular order and depicted once each, these operations may be repeated or performed in a different order (e.g., in parallel), as suitable. Additionally, various operations may be omitted, as suitable.
  • Various operations of the method 800 may be illustrated with reference to one or more of the embodiments discussed above, but the method 800 may be used to manufacture any suitable quantum circuit component comprising one or more flux bias line structures according to any embodiments disclosed herein.
  • the method 800 may begin with providing, over a substrate, flux bias line structures as described herein, i.e. providing the one or more center conductor lines and whichever ground plane(s) may be present (process 802 shown in FIG. 8).
  • the substrate used in the process 802 may comprise any substrate suitable for realizing quantum circuit components described herein.
  • the substrate may be a crystalline substrate such as, but not limited to a silicon or a sapphire substrate, and may be provided as a wafer or a portion thereof.
  • the substrate may be noncrystalline.
  • any material that provides sufficient advantages e.g. sufficiently good electrical isolation and/or ability to apply known fabrication and processing techniques
  • to outweigh the possible disadvantages e.g. negative effects of spurious TLS's
  • Additional examples of substrates include silicon-on-insulator (SOI) substrates, lll-V substrates, and quartz substrates.
  • the substrate may be cleaned prior to or/and after any of the processes for forming flux bias line structures described herein, e.g. to remove surface-bound organic and metallic contaminants, as well as subsurface contamination.
  • cleaning may be carried out using e.g. a chemical solutions (such as peroxide), and/or with UV radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g. using HF).
  • any suitable deposition and patterning techniques may be used for forming the flux bias line structures in the process 802.
  • the conductive portions of the flux bias line structures such as e.g. the center conductor line(s) and ground plane(s) may comprise any conducting or superconducting material suitable for serving as an interconnect in a quantum circuit, such as e.g.
  • niobium aluminum (Al), niobium (Nb), niobum nitride (NbN), niobium titanium nitride (NbTiN), titanium nitride (TIN), niobium titanium (NbTi), molybdenum rhenium (MoRe), etc, or any alloy of two or more superconducting/conducting materials. These materials may be deposited over the substrate using any known techniques for depositing
  • conducting/superconducting materials such as e.g. atomic layer deposition (ALD), physical vapor deposition (PVD) (e.g. evaporative deposition, magnetron sputtering, or e-beam deposition), chemical vapor deposition (CVD), or electroplating, and patterned using any known patterning techniques, e.g. photolithographic patterning.
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • electroplating electroplating
  • the conducting or superconducting materials for forming the center conductor line(s) and ground plane(s) in the process 802 could, first, be deposited and then subtractively patterned.
  • openings in the substrate may be formed in accordance with the desired locations and geometry of the center conductor line(s) and ground plane(s), and then the openings may be filled with the conducting or superconducting materials as known in the art, thus forming the center conductor line(s) and ground plane(s) in the process 802.
  • the center conductor line(s) and ground plane(s) may be formed in the process 802 using dopant implantation and subsequent activation of dopants.
  • the process 802 may begin with depositing a mask for the subsequent dopant implantation to form the center conductor line(s) and ground plane(s).
  • a silicon (Si) or a silicon germanium (SGe) substrate it may be particularly advantageous to use a silicon (Si) or a silicon germanium (SGe) substrate in the process 802, because of the established techniques for dopant implantation and epitaxial growth on such substrates and because such substrates may be suitably low-loss in terms of spurious TLS's.
  • any standard processing cleaning techniques as known in the art may be applied to obtain single crystal silicon surface that is either as received from a supplier or has an intrinsic (i.e. non-doped or low- doped, where doping is either unintentional or deliberate) epitaxially grown silicon region in the upper 0.5 to 8 micrometers (microns).
  • this thin epitaxially grown region may comprise silicon that is sufficiently pure so that it can behave as a low-loss insulator at qubits operating temperatures (i.e. either no dopants or sufficiently low-level of dopants) or might be isotopically enriched 28Si (i.e. sufficiently few atoms with nuclear moments to ensure a low loss).
  • non-doped or low-doped silicon implies a non-conductive silicon at temperatures at which qubits operate (i.e. cryogenic temperatures).
  • CTL cryogenic temperatures
  • unintentional impurities e.g., oxygen, residual dopants in the chamber, etc.
  • unintentional impurities e.g., oxygen, residual dopants in the chamber, etc.
  • dopants may be deliberately added to materials for reasons such as e.g. thermal or mechanical stability.
  • silicon may be referred to as intrinsic or non-doped silicon.
  • the mask may be provided over the substrate in any manner known in the art for providing suitable ion implantation masks, e.g. using photoresist and patterning of the photoresist in a manner similar to that described above.
  • Dimensions and shape/geometry of the openings in the mask may be the same or comparable to the dimensions and shape/geometry of the center conductor line(s) and ground plane(s) to be formed, and could be as described above with reference to the dimensions and shape/geometry of the flux bias lines shown in FIGS. 3A-3B, 4A-4B, 5A-5B, 6A- 6B, and 7A-7B described above.
  • dopants are implanted into the substrate through the openings in the mask, which results in dopants implanting in portions of the substrate exposed by the openings. Dopants may also be implanted into the mask, but dopants implanted into mask do not reach the substrate below it.
  • Dopant implantation may be performed by any known dopant implantation techniques.
  • a Si or SiGe substrate may be doped with phosphorus (P) or arsenic (As) to doping concentrations ranging lel8 to le21, including all values and ranges therein, e.g. to about le20.
  • the mask may be removed and the substrate may be annealed to activate the dopants.
  • Annealing to activate dopants may, for example, be performed at temperatures in the range of 900" C to 1100" C, including all values and ranges therein, for a time period in the range of 1 nanoseconds to 1 minute, including all values and ranges therein.
  • doped regions of the substrate are made conductive or superconductive, as suitable for forming the signal line, ground plane(s) and perpendicular conductive elements of a flux bias line structure employed in a quantum circuit.
  • the substrate comprising implanted and activated dopants may then, optionally, be cleaned again, using any suitable cleaning techniques as known in the art.
  • the center conductor line(s) and ground plane(s) could be formed in the process 802 using a combination of metal deposition and patterning and dopant implantation.
  • some or all of the electrically conductive/superconductive materials used to implement the center conductor line(s) and ground plane(s) in the process 802 could be the same or different materials.
  • the method 800 may further include providing the qubits (process 804 shown in FIG. 8). Any of the known methods could be used for providing the qubits in the process 804, all of which being within the scope of the present disclosure. In some embodiments, at least some of the processes of forming the center conductor line(s) and ground plane(s) could also be used to fabricate at least parts of the qubits (i.e. qubits and parts of the flux bias line structures described herein could be fabricated in some shared process steps).
  • qubits may be fabricated after all of most of the fabrication processes used for forming the flux bias line structures are finished, in order to eliminate or reduce potential negative impacts due to the fabrication processes used for forming the flux bias line structures on the integrity and performance of the qubits.
  • the quantum circuits with flux bias line structures illustrated in these FIGS may, optionally, be covered (i.e. encapsulated) with a dielectric material which is a low-loss material in terms of spurious TLS's, with controlled interfaces between the conductive materials of the flux bias lines and the cover dielectric material.
  • a dielectric material which is a low-loss material in terms of spurious TLS's
  • Such encapsulation of the flux bias line structures in quantum circuits may help with reducing qubit decoherence problems because it could eliminate superconductor-air interfaces above the conductive materials of the flux bias line structures.
  • the encapsulation may be carried out as follows (not shown in FIGS.).
  • a layer of dielectric material e.g. a suitable inter layer dielectric (ILD)
  • ILD inter layer dielectric
  • Some considerations in selecting a suitable dielectric material may include e.g. possibilities of smooth film formation, low shrinkage and outgassing, and good dielectric properties (such as e.g. low electrical leakage, suitable value of a dielectric constant, and thermal stability).
  • dielectric materials examples include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as peril uorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.
  • the dielectric material used for encapsulation may include an oxide deposited over the conductive elements of the quantum circuit using e.g. chemical vapor deposition or/and plasma-enhanced chemical vapor deposition, as typically done in conventional processing.
  • the dielectric material used for encapsulation may include a dielectric material formed over the conductive elements of the quantum circuit using coating techniques involving cross-linking of liquid precursors into solid dielectric materials.
  • planarization may be performed in order to achieve a relatively smooth, plane surface of the dielectric layer used for the encapsulation.
  • a thickness of the dielectric layer used for the encapsulation could depend on e.g. the desired distance to the surface of the device from the flux bias line structure.
  • the dielectric layer used for the encapsulation may have a thickness between e.g. 20 and 3000 nm, including all values and ranges therein, typically for qubit applications between 50 and 100 nm.
  • one or more first via openings are formed in the dielectric material used for the encapsulation to connect to the center conductor line(s) and one or more second via openings are formed to connect to the ground planes of the flux bias line structure.
  • Number, dimensions and a shape of the via openings could depend on e.g. the conductive/superconductive material used to fill the via openings, dimensions and shape of the ground planes and the center conductor line(s), and the etching process used to form these via openings.
  • one via opening could be used as a first via opening and one via opening could be used as a second via opening.
  • the first and second via openings extend from the surface of the dielectric layer used for the encapsulation to the respective conductors of the flux bias line structure structure.
  • the dielectric layer used for the encapsulation at least partially surrounds each of the via openings, isolating them from one another and from other openings that may be formed in that layer, both physically and electrically.
  • largest dimensions of the first and second via openings could be between 5 and 40 nm for both the x-axis and y-axis, including all values and ranges therein.
  • any kind of etching techniques may be used to form the first and second via openings.
  • both the first and second via openings are formed in a single etching step. For example, once patterning has been done to expose portions of the underlying dielectric layer used for the encapsulation in a patterned mask that defines location and arrangement of future first and second vias, exposed portions of the underlying dielectric layer are then chemically etched.
  • the method may then proceed with filling the one or more first via openings and one or more second via openings in the dielectric layer used for the encapsulation with a conducting or superconducting material suitable to provide electrical connectivity to, respectively, the center conductor line(s) and the ground plane(s) of the flux bias line structure.
  • FIGS The different views of the flux bias line structures as described herein are shown in the FIGS, with precise right angles and straight lines, which does not reflect example real world process limitations which may cause the features to not look so ideal when any of the structures described above are examined using e.g. scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images.
  • SEM scanning electron microscopy
  • TEM transmission electron microscope
  • possible processing defects could also be visible, such as e.g. tapered vias, occasional screw, edge, or combination dislocations within the crystalline region, occasional dislocation defects of single atoms or clusters of atoms.
  • FIGS. 9A-9B are top views of a wafer 2000 and dies 2002 that may be formed from the wafer 2000, according to some embodiments of the present disclosure.
  • the dies 2002 may include any of the quantum circuits/devices disclosed herein, e.g., the quantum circuit 100, and may include any of the flux bias line structures described herein, such as e.g. the flux bias line structures shown in FIGS. 3A-3B, FIGS. 4A-4B, FIGS. 5A-5B, FIGS. 6A-6B, FIGS. 7A-7B, or any combinations of these flux bias line structures.
  • the wafer 2000 may include semiconductor material and may include one or more dies 2002 having conventional and quantum circuit device elements formed on a surface of the wafer 2000. Each of the dies 2002 may be a repeating unit of a semiconductor product that includes any suitable conventional and/or quantum circuit qubit device.
  • the wafer 2000 may undergo a singulation process in which each of the dies 2002 is separated from one another to provide discrete "chips" of the
  • a die 2002 may include one or more quantum circuits 100 and/or supporting circuitry to route electrical signals to the quantum circuits 100 (e.g., interconnects connected to the conductive contacts of the flux bias line structures described herein, and other conductive vias and lines), as well as any other IC components.
  • the wafer 2000 or the die 2002 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 2002.
  • SRAM static random access memory
  • logic device e.g., AND, OR, NAND, or NOR gate
  • a memory array formed by multiple memory devices may be formed on a same die 2002 as a processing device (e.g., the processing device 2202 of FIG. 11) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.
  • a processing device e.g., the processing device 2202 of FIG. 11
  • other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.
  • FIG. 10 is a cross-sectional side view of a device assembly 2100 that may include any of the embodiments of the quantum circuits employing flux bias line structures disclosed herein.
  • the device assembly 2100 includes a number of components disposed on a circuit board 2102.
  • the device assembly 2100 may include components disposed on a first face 2140 of the circuit board 2102 and an opposing second face 2142 of the circuit board 2102; generally, components may be disposed on one or both faces 2140 and 2142.
  • the circuit board 2102 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2102.
  • the circuit board 2102 may be a package substrate or flexible board.
  • the IC device assembly 2100 illustrated in FIG. 10 includes a package-on-interposer structure 2136 coupled to the first face 2140 of the circuit board 2102 by coupling components 2116.
  • the coupling components 2116 may electrically and mechanically couple the package-on-interposer structure 2136 to the circuit board 2102, and may include solder balls (as shown in FIG. 10), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.
  • the package-on-interposer structure 2136 may include a package 2120 coupled to an interposer 2104 by coupling components 2118.
  • the coupling components 2118 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2116. Although a single package 2120 is shown in FIG. 10, multiple packages may be coupled to the interposer 2104; indeed, additional interposers may be coupled to the interposer 2104.
  • the interposer 2104 may provide an intervening substrate used to bridge the circuit board 2102 and the package 2120.
  • the package 2120 may be a quantum circuit device package as described herein, e.g.
  • the interposer 2104 may spread a connection to a wider pitch or reroute a connection to a different connection.
  • the interposer 2104 may couple the package 2120 (e.g., a die) to a ball grid array (BGA) of the coupling components 2116 for coupling to the circuit board 2102.
  • BGA ball grid array
  • the package 2120 and the circuit board 2102 are attached to opposing sides of the interposer 2104; in other embodiments, the package 2120 and the circuit board 2102 may be attached to a same side of the interposer 2104.
  • three or more components may be interconnected by way of the interposer 2104.
  • the interposer 2104 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 2104 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials.
  • the interposer 2104 may include metal interconnects 2108 and vias 2110, including but not limited to through-silicon vias (TSVs) 2106.
  • TSVs through-silicon vias
  • the interposer 2104 may further include embedded devices 2114, including both passive and active devices.
  • Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2104.
  • RF radio-frequency
  • MEMS microelectromechanical systems
  • the package-on-interposer structure 2136 may take the form of any of the package-on-interposer structures known in the art.
  • the device assembly 2100 may include a package 2124 coupled to the first face 2140 of the circuit board 2102 by coupling components 2122.
  • the coupling components 2122 may take the form of any of the embodiments discussed above with reference to the coupling components 2116
  • the package 2124 may take the form of any of the embodiments discussed above with reference to the package 2120.
  • the package 2124 may be a package including one or more quantum circuits with qubits as described herein or may be a conventional IC package, for example. In some embodiments, the package 2124 may take the form of any of the embodiments of the quantum circuit 100 with any of the flux bias line structures described herein.
  • the device assembly 2100 illustrated in FIG. 10 includes a package-on-package structure 2134 coupled to the second face 2142 of the circuit board 2102 by coupling components 2128.
  • the package-on-package structure 2134 may include a package 2126 and a package 2132 coupled together by coupling components 2130 such that the package 2126 is disposed between the circuit board 2102 and the package 2132.
  • the coupling components 2128 and 2130 may take the form of any of the embodiments of the coupling components 2116 discussed above, and the packages 2126 and 2132 may take the form of any of the embodiments of the package 2120 discussed above.
  • Each of the packages 2126 and 2132 may be a qubit device package as described herein or may be a conventional IC package, for example.
  • one or both of the packages 2126 and 2132 may take the form of any of the embodiments of the quantum circuit 100 with any of the flux bias line structures described herein, or a combination thereof.
  • FIG. 11 is a block diagram of an example quantum computing device 2200 that may include any of the quantum circuits with flux bias line structures disclosed herein.
  • a number of components are illustrated in FIG. 11 as included in the quantum computing device 2200, but any one or more of these components may be omitted or duplicated, as suitable for the application.
  • some or all of the components included in the quantum computing device 2200 may be attached to one or more printed circuit boards (e.g., a motherboard), and may be included in, or include, any of the quantum circuits with flux bias line structures described herein.
  • various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die.
  • SoC system-on-a-chip
  • the quantum computing device 2200 may not include one or more of the components illustrated in FIG. 11, but the quantum computing device 2200 may include interface circuitry for coupling to the one or more components.
  • the quantum computing device 2200 may not include a display device 2206, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2206 may be coupled.
  • the quantum computing device 2200 may not include an audio input device 2224 or an audio output device 2208, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2224 or audio output device 2208 may be coupled.
  • the quantum computing device 2200 may include a processing device 2202 (e.g., one or more processing devices).
  • processing device or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the processing device 2202 may include a quantum processing device 2226 (e.g., one or more quantum processing devices), and a non-quantum processing device 2228 (e.g., one or more non-quantum processing devices).
  • the quantum processing device 2226 may include one or more of the quantum circuits 100 with flux bias line structures disclosed herein, and may perform data processing by performing operations on the qubits that may be generated in the quantum circuits 100, and monitoring the result of those operations. For example, as discussed above, different qubits may be allowed to interact, the quantum states of different qubits may be set or transformed, and the quantum states of different qubits may be read.
  • the quantum processing device 2226 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device 2226 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc.
  • the quantum processing device 2226 may also include support circuitry to support the processing capability of the quantum processing device 2226, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to- digital converters.
  • the processing device 2202 may include a non-quantum processing device 2228.
  • the non-quantum processing device 2228 may provide peripheral logic to support the operation of the quantum processing device 2226.
  • the non-quantum processing device 2228 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc.
  • the non-quantum processing device 2228 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2226.
  • the non-quantum processing device 2228 may interface with one or more of the other components of the quantum computing device 2200 (e.g., the communication chip 2212 discussed below, the display device 2206 discussed below, etc) in a conventional manner, and may serve as an interface between the quantum processing device 2226 and conventional components.
  • the non-quantum processing device 2228 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.
  • DSPs digital signal processors
  • ASICs application-specific integrated circuits
  • CPUs central processing units
  • GPUs graphics processing units
  • cryptoprocessors specialized processors that execute cryptographic algorithms within hardware
  • server processors or any other suitable processing devices.
  • the quantum computing device 2200 may include a memory 2204, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory. and/or a hard drive.
  • volatile memory e.g., dynamic random access memory (DRAM)
  • nonvolatile memory e.g., read-only memory (ROM)
  • flash memory solid state memory. and/or a hard drive.
  • solid state memory solid state memory.
  • the states of qubits in the quantum processing device 2226 may be read and stored in the memory 2204.
  • the memory 2204 may include memory that shares a die with the non-quantum processing device 2228. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).
  • eDRAM embedded dynamic random access memory
  • STT-MRAM spin transfer torque magnetic random-access memory
  • the quantum computing device 2200 may include a cooling apparatus 2230.
  • the cooling apparatus 2230 may maintain the quantum processing device 2226, in particular the quantum circuits 100 as described herein, at a predetermined low temperature during operation to avoid qubit decoherence and to reduce the effects of scattering in the quantum processing device 2226.
  • This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 degrees Kelvin or less.
  • the non-quantum processing device 2228 (and various other components of the quantum computing device 2200) may not be cooled by the cooling apparatus 2230, and may instead operate at room temperature.
  • the cooling apparatus 2230 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.
  • the quantum computing device 2200 may include a communication chip 2212 (e.g., one or more communication chips).
  • the communication chip 2212 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 2200.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 2212 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2”), etc.).
  • IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and
  • the communication chip 2212 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network.
  • GSM Global System for Mobile Communication
  • GPRS General Packet Radio Service
  • UMTS Universal Mobile Telecommunications System
  • High Speed Packet Access HSPA
  • E-HSPA Evolved HSPA
  • LTE LTE network.
  • the communication chip 2212 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN).
  • EDGE Enhanced Data for GSM Evolution
  • GERAN GSM EDGE Radio Access Network
  • UTRAN Universal Terrestrial Radio Access Network
  • E-UTRAN Evolved UTRAN
  • the communication chip 2212 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • CDMA Code Division Multiple Access
  • TDMA Time Division Multiple Access
  • DECT Digital Enhanced Cordless Telecommunications
  • EV-DO Evolution-Data Optimized
  • the communication chip 2212 may operate in accordance with other wireless protocols in other embodiments.
  • the quantum computing device 2200 may include an antenna 2222 to facilitate wireless communications and/or to receive other wireless
  • the communication chip 2212 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2212 may include multiple communication chips. For instance, a first communication chip 2212 may be dedicated to shorter-range wireless
  • a second communication chip 2212 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others.
  • a first communication chip 2212 may be dedicated to wireless communications
  • a second communication chip 2212 may be dedicated to wired communications.
  • the quantum computing device 2200 may include battery/power circuitry 2214.
  • the battery/power circuitry 2214 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2200 to an energy source separate from the quantum computing device 2200 (e.g., AC line power).
  • the quantum computing device 2200 may include a display device 2206 (or corresponding interface circuitry, as discussed above).
  • the display device 2206 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
  • LCD liquid crystal display
  • the quantum computing device 2200 may include an audio output device 2208 (or corresponding interface circuitry, as discussed above).
  • the audio output device 2208 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
  • the quantum computing device 2200 may include an audio input device 2224 (or corresponding interface circuitry, as discussed above).
  • the audio input device 2224 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
  • the quantum computing device 2200 may include a global positioning system (GPS) device 2218 (or corresponding interface circuitry, as discussed above).
  • GPS global positioning system
  • the GPS device 2218 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2200, as known in the art.
  • the quantum computing device 2200 may include an other output device 2210 (or corresponding interface circuitry, as discussed above).
  • Examples of the other output device 2210 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
  • the quantum computing device 2200 may include an other input device 2220 (or corresponding interface circuitry, as discussed above).
  • Examples of the other input device 2220 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
  • RFID radio frequency identification
  • the quantum computing device 2200 may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.
  • a hand-held or mobile computing device e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.
  • PDA personal digital assistant
  • a desktop computing device e.g.,
  • Example 1 provides a quantum integrated circuit assembly/device, including a substrate; a qubit disposed over or in the substrate, the qubit including a superconducting quantum interference device (SQUID); and a flux bias line structure for applying a magnetic field to the SQUID to control qubit' s frequency and proximate to the SQUID, the flux bias line structure including a single center conductor line forming two partial loops.
  • SQUID superconducting quantum interference device
  • Example 2 provides the quantum circuit assembly according to Example 1, where the single center conductor line terminates with a connection to ground.
  • Example 3 provides the quantum circuit assembly according to Example 2, where the connection to ground includes a connection to one of ground planes of the flux bias line structure.
  • Example 4 provides the quantum circuit assembly according to Example 2, where the connection to ground includes a ground connection of a device package in which the quantum circuit assembly is included.
  • Example 5 provides the quantum circuit assembly according to Example 1, where the single center conductor line includes one input signal connection and one output signal connection.
  • Example 6 provides the quantum circuit assembly according to any one of the preceding Examples, where the two partial loops are arranged so that a current flowing through the signal center conductor line generates magnetic fields of opposite directions within the two partial loops (i.e. a magnetic field of a first direction is generated within the first loop, e.g. in a direction perpendicular to the plane of the loop and pointing out of the loop, and a magnetic field of a direction opposite to the first direction is generated within the second loop).
  • a current flowing through the signal center conductor line generates magnetic fields of opposite directions within the two partial loops (i.e. a magnetic field of a first direction is generated within the first loop, e.g. in a direction perpendicular to the plane of the loop and pointing out of the loop, and a magnetic field of a direction opposite to the first direction is generated within the second loop).
  • Example 7 provides the quantum circuit assembly according to any one of the preceding Examples, where a portion of one of the two partial loops is provided at a distance between about 100 and 15,000 nanometers from a portion of the SQUID, e.g. between 5 and 15 micron, or between 1 and 10 micron.
  • the distance between a portion of one partial loops of the flux bias line structure and the SQUID should be such so that the magnetic field generated because of the current flowing through that portion can reach the SQUID and generate a magnetic field in the SQUID, thereby controlling the frequency of the qubit.
  • Example 8 provides the quantum circuit assembly according to any one of the preceding Examples, where an area enclosed by each of the two partial loops is between about 10,000 square nanometers and 2500 square micrometers, e.g. between 100 micron 2 and 1500 micron 2 or between 100 micron 2 and 900 micron 2 .
  • Example 9 provides the quantum circuit assembly according to any one of the preceding Examples, where a perimeter of each of the two partial loops is between about 600 and 250,000 nanometers, e.g. between 80 micron and 220 micron or between 100 micron and 200 micron.
  • Example 10 provides the quantum circuit assembly according to any one of the preceding Examples, where the SQUID includes two Josephson Junctions and a loop of one or more superconductive materials.
  • Example 11 provides the quantum circuit assembly according to any one of the preceding Examples, where the single center conductor line includes one or more superconductive materials.
  • Example 12 provides the quantum circuit assembly according to Example 11, where the one or more superconductive materials include one or more of aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), niobium titanium (NbTi), and niobium titanium nitride (NbTiN).
  • the one or more superconductive materials include one or more of aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), niobium titanium (NbTiN).
  • Example 13 provides a quantum integrated circuit assembly/device, including a substrate; a qubit disposed over or in the substrate, the qubit including a superconducting quantum interference device (SQUID); and a flux bias line structure for applying a magnetic field to the SQUID to control qubit' s frequency and proximate to the SQUID, the flux bias line structure including two separately driven center conductor lines, each of the two center conductor lines forming a respective partial loop.
  • SQUID superconducting quantum interference device
  • Example 14 provides the quantum circuit assembly according to Example 13, where the each of the two center conductor lines terminates with a connection to ground.
  • the connection to ground may be in a form of a connection to one of ground planes of the flux bias line structure.
  • the connection to ground may be in a form of a ground connection of a device package in which the quantum circuit assembly is included.
  • Example 15 provides the quantum circuit assembly according to Examples 13 or 14, where the two center conductor lines are arranged so that a current flowing through a first one of the two center conductor lines generates a magnetic field in a first direction within the partial loop formed by the first center conductor line and a current flowing through a second one of the two center conductor lines generates a magnetic field in a second direction within the partial loop formed by the second center conductor line, the second direction being opposite to the first direction.
  • Example 16 provides the quantum circuit assembly according to any one of Examples 13-15, where a portion of the partial loop formed by the first center conductor line or by the second center conductor line is provided at a distance between 100 and 15,000 nanometers from a portion of the SQUID, e.g. between 5 and 15 micron, or between 1 and 10 micron.
  • Example 17 provides a quantum integrated circuit assembly/device, including a substrate; a qubit disposed over or in the substrate, the qubit including a superconducting quantum interference device (SQUID); and a flux bias line structure for applying a magnetic field to the SQUID to control qubit's frequency and proximate to the SQUID, the flux bias line structure including a single center conductor line split into two center conductor lines, each of the two center conductor lines forming a respective partial loop and including a respective inductor.
  • SQUID superconducting quantum interference device
  • Example 18 provides the quantum circuit assembly according to Example 17, where the inductor in one of the two center conductor lines has a kinetic inductance equal to that of the inductor in another one of the two center conductor lines.
  • Example 19 provides the quantum circuit assembly according to Examples 17 or 18, where the each of the two center conductor lines terminates with a connection to ground.
  • the connection to ground may be in a form of a connection to one of ground planes of the flux bias line structure.
  • the connection to ground may be in a form of a ground connection of a device package in which the quantum circuit assembly is included.
  • Example 20 provides the quantum circuit assembly according to any one of Examples 17-19, where the two center conductor lines are arranged so that a current flowing through a first one of the two center conductor lines generates a magnetic field in a first direction within the partial loop formed by the first center conductor line and a current flowing through a second one of the two center conductor lines generates a magnetic field in a second direction within the partial loop formed by the second center conductor line, the second direction being opposite to the first direction.
  • Example 21 provides the quantum circuit assembly according to any one of Examples 17-20, where a portion of the partial loop formed by the first center conductor line or by the second center conductor line is provided at a distance between 100 and 15,000 nanometers from a portion of the SQUID, e.g. between 5 and 15 micron, or between 1 and 10 micron.
  • a quantum integrated circuit assembly/device may include a substrate; a qubit disposed over or in the substrate, the qubit including a superconducting quantum interference device (SQUID); and a flux bias line structure for applying a magnetic field to the SQUID to control qubit's frequency, the flux bias line structure including a single center conductor line forming a single partial loop.
  • the single center conductor line of such a quantum circuit assembly may terminate with a connection to ground.
  • the connection to ground may be in a form of a connection to one of ground planes of the flux bias line structure.
  • the connection to ground may be in a form of a ground connection of a device package in which the quantum circuit assembly is included.
  • Example 22 provides a method of manufacturing a quantum device, the method including providing a plurality of qubits over or in a substrate, at least one qubit including a superconducting quantum interference device (SQUID); and providing one or more center conductor lines over or in the substrate, the one or more center conductor lines forming two partial loops, at least one partial loop proximate to the SQUID.
  • SQUID superconducting quantum interference device
  • Example 23 provides the method according to Example 22, where the substrate is a silicon substrate and where providing the one or more center conductor lines includes implanting dopants in a portion of a top layer of the substrate and activating the implanted dopants.
  • Example 24 provides the method according to Example 23, where the top layer of the substrate includes an uppermost layer of intrinsic or low-doped epitaxially grown silicon.
  • Example 25 provides the method according to any one of Examples 22-24, where the plurality of qubits include superconducting qubits and are provided over the substrate after the flux bias line structure is formed.
  • Example 26 provides a quantum computing device that includes a quantum processing device that includes a plurality of qubits; a non-quantum processing device coupled to the quantum processing device; and a memory device to store data generated by the plurality of qubits during operation of the quantum processing device.
  • the quantum processing device may include a quantum integrated circuit assembly according to any one of the preceding Examples.
  • Example 27 provides the quantum computing device according to Example 26, further including a cooling apparatus configured to maintain a temperature of the quantum processing device below 5 degrees Kelvin.
  • Example 28 provides the quantum computing device according to Examples 26 or 27, where the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

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Abstract

Selon certains modes de réalisation, la présente invention concerne de nouvelles configurations de ligne de polarisation de flux pour commander des fréquences de bits quantiques supraconducteurs. Une structure de ligne de polarisation de flux proposée donnée à titre d'exemple comprend une seule ligne de conducteur central formant deux boucles partielles. Une autre structure donnée à titre d'exemple comprend deux lignes de conducteur central entraînées séparément, chacune des deux lignes de conducteur central formant une boucle partielle respective. Une autre structure de ligne de polarisation de flux donné à titre d'exemple comprend une ligne de conducteur central unique divisée en deux lignes de conducteur central, chacune des deux lignes de conducteur central formant une boucle partielle respective et comprenant une boucle d'induction respective. De telles structures fournissent des améliorations par rapport à des lignes de polarisation de flux classiques dans la génération d'un champ magnétique qui peut accorder la fréquence d'un bit quantique avec un degré de commande suffisant tout en garantissant que le champ magnétique n'affecte pas sensiblement d'autres composants d'un circuit quantique.
PCT/US2017/024396 2017-03-28 2017-03-28 Lignes de polarisation de flux de courant commandé dans des dispositifs à bits quantiques WO2018182571A1 (fr)

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Cited By (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190044051A1 (en) * 2018-08-14 2019-02-07 Intel Corporation Vertical flux bias lines coupled to vertical squid loops in superconducting qubits
WO2020150348A1 (fr) 2019-01-17 2020-07-23 Yale University Circuit josephson non linéaire
CN111731517A (zh) * 2020-07-02 2020-10-02 北京卫星环境工程研究所 一种多层隔热组件内部放气泄放装置
US10810506B1 (en) 2020-03-02 2020-10-20 International Business Machines Corporation Qubit biasing scheme using non-volatile devices
US10847705B2 (en) 2018-02-15 2020-11-24 Intel Corporation Reducing crosstalk from flux bias lines in qubit devices
US10910488B2 (en) 2018-06-26 2021-02-02 Intel Corporation Quantum dot devices with fins and partially wrapped gates
US11011693B2 (en) 2019-06-24 2021-05-18 Intel Corporation Integrated quantum circuit assemblies for cooling apparatus
US11038021B2 (en) 2017-06-24 2021-06-15 Intel Corporation Quantum dot devices
US11063138B2 (en) 2017-06-24 2021-07-13 Intel Corporation Quantum dot devices
US11114530B2 (en) 2017-12-17 2021-09-07 Intel Corporation Quantum well stacks for quantum dot devices
US11158731B2 (en) 2017-09-28 2021-10-26 Intel Corporation Quantum well stacks for quantum dot devices
KR20210131410A (ko) * 2019-04-25 2021-11-02 인터내셔널 비지네스 머신즈 코포레이션 초전도 루프들을 위한 지속적인 자속 바이어싱 방법
US11177912B2 (en) 2018-03-06 2021-11-16 Intel Corporation Quantum circuit assemblies with on-chip demultiplexers
US11183564B2 (en) 2018-06-21 2021-11-23 Intel Corporation Quantum dot devices with strain control
CN113761334A (zh) * 2020-11-13 2021-12-07 北京沃东天骏信息技术有限公司 一种可视化推荐方法、装置、设备和存储介质
US11322591B2 (en) 2017-06-24 2022-05-03 Intel Corporation Quantum dot devices
US11335778B2 (en) 2018-06-26 2022-05-17 Intel Corporation Quantum dot devices with overlapping gates
US11355623B2 (en) 2018-03-19 2022-06-07 Intel Corporation Wafer-scale integration of dopant atoms for donor- or acceptor-based spin qubits
US11387324B1 (en) 2019-12-12 2022-07-12 Intel Corporation Connectivity in quantum dot devices
US11417765B2 (en) 2018-06-25 2022-08-16 Intel Corporation Quantum dot devices with fine-pitched gates
US11417755B2 (en) 2018-01-08 2022-08-16 Intel Corporation Differentially strained quantum dot devices
US11424324B2 (en) 2018-09-27 2022-08-23 Intel Corporation Multi-spacers for quantum dot device gates
US11450765B2 (en) 2018-09-27 2022-09-20 Intel Corporation Quantum dot devices with diodes for electrostatic discharge protection
US11494682B2 (en) 2017-12-29 2022-11-08 Intel Corporation Quantum computing assemblies
WO2022269121A1 (fr) * 2021-06-22 2022-12-29 Iqm Finland Oy Circuit supraconducteur à éléments accordables par flux magnétiques et procédés de limitation de diaphonie de flux entre des éléments accordables par flux magnétiques dans des circuits supraconducteurs
US11557630B2 (en) 2017-09-28 2023-01-17 Intel Corporation Quantum dot devices with selectors
US11616126B2 (en) 2018-09-27 2023-03-28 Intel Corporation Quantum dot devices with passive barrier elements in a quantum well stack between metal gates
US11658212B2 (en) 2019-02-13 2023-05-23 Intel Corporation Quantum dot devices with conductive liners
US11682701B2 (en) 2019-03-27 2023-06-20 Intel Corporation Quantum dot devices
CN116324822A (zh) * 2020-09-24 2023-06-23 国际商业机器公司 电流偏置可调谐量子位
US11699747B2 (en) 2019-03-26 2023-07-11 Intel Corporation Quantum dot devices with multiple layers of gate metal
US20230246321A1 (en) * 2017-09-07 2023-08-03 Amherst College Loop Gap Resonators for Spin Resonance Spectroscopy
US11737376B2 (en) 2017-12-11 2023-08-22 Yale University Superconducting nonlinear asymmetric inductive element and related systems and methods
US11749721B2 (en) 2018-09-28 2023-09-05 Intel Corporation Gate walls for quantum dot devices
US11937516B2 (en) 2020-03-04 2024-03-19 International Business Machines Corporation Fabrication of a flux bias line local heating device
US11957066B2 (en) 2019-09-04 2024-04-09 Intel Corporation Stackable in-line filter modules for quantum computing
US12022749B2 (en) 2020-03-04 2024-06-25 International Business Machines Corporation Flux bias line local heating device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4176290A (en) * 1976-10-27 1979-11-27 Nippon Telegraph And Telephone Public Corporation Superconductive Josephson circuit device
US8610453B2 (en) * 2007-12-13 2013-12-17 Northrop Grumman Systems Corporation Single flux quantum circuits
US8654578B2 (en) * 2011-06-17 2014-02-18 Northrop Grumman Systems Corporation Phase qubit cell having enhanced coherence
US20140235450A1 (en) * 2012-07-30 2014-08-21 International Business Machines Corporation Multi-tunable superconducting circuits
US20160148112A1 (en) * 2014-11-25 2016-05-26 Samsung Electronics Co., Ltd. Multi-qubit coupling structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4176290A (en) * 1976-10-27 1979-11-27 Nippon Telegraph And Telephone Public Corporation Superconductive Josephson circuit device
US8610453B2 (en) * 2007-12-13 2013-12-17 Northrop Grumman Systems Corporation Single flux quantum circuits
US8654578B2 (en) * 2011-06-17 2014-02-18 Northrop Grumman Systems Corporation Phase qubit cell having enhanced coherence
US20140235450A1 (en) * 2012-07-30 2014-08-21 International Business Machines Corporation Multi-tunable superconducting circuits
US20160148112A1 (en) * 2014-11-25 2016-05-26 Samsung Electronics Co., Ltd. Multi-qubit coupling structure

Cited By (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11038021B2 (en) 2017-06-24 2021-06-15 Intel Corporation Quantum dot devices
US11721748B2 (en) 2017-06-24 2023-08-08 Intel Corporation Quantum dot devices
US11721723B2 (en) 2017-06-24 2023-08-08 Intel Corporation Quantum dot devices
US11322591B2 (en) 2017-06-24 2022-05-03 Intel Corporation Quantum dot devices
US11063138B2 (en) 2017-06-24 2021-07-13 Intel Corporation Quantum dot devices
US20230246321A1 (en) * 2017-09-07 2023-08-03 Amherst College Loop Gap Resonators for Spin Resonance Spectroscopy
US11158731B2 (en) 2017-09-28 2021-10-26 Intel Corporation Quantum well stacks for quantum dot devices
US11557630B2 (en) 2017-09-28 2023-01-17 Intel Corporation Quantum dot devices with selectors
US11737376B2 (en) 2017-12-11 2023-08-22 Yale University Superconducting nonlinear asymmetric inductive element and related systems and methods
US11721724B2 (en) 2017-12-17 2023-08-08 Intel Corporation Quantum well stacks for quantum dot devices
US11114530B2 (en) 2017-12-17 2021-09-07 Intel Corporation Quantum well stacks for quantum dot devices
US11494682B2 (en) 2017-12-29 2022-11-08 Intel Corporation Quantum computing assemblies
US11417755B2 (en) 2018-01-08 2022-08-16 Intel Corporation Differentially strained quantum dot devices
US10847705B2 (en) 2018-02-15 2020-11-24 Intel Corporation Reducing crosstalk from flux bias lines in qubit devices
US11177912B2 (en) 2018-03-06 2021-11-16 Intel Corporation Quantum circuit assemblies with on-chip demultiplexers
US11355623B2 (en) 2018-03-19 2022-06-07 Intel Corporation Wafer-scale integration of dopant atoms for donor- or acceptor-based spin qubits
US11183564B2 (en) 2018-06-21 2021-11-23 Intel Corporation Quantum dot devices with strain control
US11417765B2 (en) 2018-06-25 2022-08-16 Intel Corporation Quantum dot devices with fine-pitched gates
US10910488B2 (en) 2018-06-26 2021-02-02 Intel Corporation Quantum dot devices with fins and partially wrapped gates
US11335778B2 (en) 2018-06-26 2022-05-17 Intel Corporation Quantum dot devices with overlapping gates
US20190044051A1 (en) * 2018-08-14 2019-02-07 Intel Corporation Vertical flux bias lines coupled to vertical squid loops in superconducting qubits
US10879446B2 (en) 2018-08-14 2020-12-29 Intel Corporation Vertical flux bias lines coupled to vertical squid loops in superconducting qubits
US11450765B2 (en) 2018-09-27 2022-09-20 Intel Corporation Quantum dot devices with diodes for electrostatic discharge protection
US11616126B2 (en) 2018-09-27 2023-03-28 Intel Corporation Quantum dot devices with passive barrier elements in a quantum well stack between metal gates
US11424324B2 (en) 2018-09-27 2022-08-23 Intel Corporation Multi-spacers for quantum dot device gates
US11749721B2 (en) 2018-09-28 2023-09-05 Intel Corporation Gate walls for quantum dot devices
EP3912200A4 (fr) * 2019-01-17 2022-10-05 Yale University Circuit josephson non linéaire
WO2020150348A1 (fr) 2019-01-17 2020-07-23 Yale University Circuit josephson non linéaire
US11791818B2 (en) 2019-01-17 2023-10-17 Yale University Josephson nonlinear circuit
US11658212B2 (en) 2019-02-13 2023-05-23 Intel Corporation Quantum dot devices with conductive liners
US11699747B2 (en) 2019-03-26 2023-07-11 Intel Corporation Quantum dot devices with multiple layers of gate metal
US11682701B2 (en) 2019-03-27 2023-06-20 Intel Corporation Quantum dot devices
KR20210131410A (ko) * 2019-04-25 2021-11-02 인터내셔널 비지네스 머신즈 코포레이션 초전도 루프들을 위한 지속적인 자속 바이어싱 방법
KR102551937B1 (ko) * 2019-04-25 2023-07-06 인터내셔널 비지네스 머신즈 코포레이션 초전도 루프들을 위한 지속적인 자속 바이어싱 방법
CN113748435A (zh) * 2019-04-25 2021-12-03 国际商业机器公司 用于超导环路的持续通量偏置方法
US11011693B2 (en) 2019-06-24 2021-05-18 Intel Corporation Integrated quantum circuit assemblies for cooling apparatus
US11957066B2 (en) 2019-09-04 2024-04-09 Intel Corporation Stackable in-line filter modules for quantum computing
US11387324B1 (en) 2019-12-12 2022-07-12 Intel Corporation Connectivity in quantum dot devices
US10810506B1 (en) 2020-03-02 2020-10-20 International Business Machines Corporation Qubit biasing scheme using non-volatile devices
US12022749B2 (en) 2020-03-04 2024-06-25 International Business Machines Corporation Flux bias line local heating device
US11937516B2 (en) 2020-03-04 2024-03-19 International Business Machines Corporation Fabrication of a flux bias line local heating device
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CN111731517B (zh) * 2020-07-02 2021-10-08 北京卫星环境工程研究所 一种多层隔热组件内部放气泄放装置
CN116324822A (zh) * 2020-09-24 2023-06-23 国际商业机器公司 电流偏置可调谐量子位
CN113761334A (zh) * 2020-11-13 2021-12-07 北京沃东天骏信息技术有限公司 一种可视化推荐方法、装置、设备和存储介质
CN117337635A (zh) * 2021-06-22 2024-01-02 Iqm芬兰公司 具有磁通量可调谐元件的超导电路以及用于最小化超导电路中磁通量可调谐元件之间的磁通串扰的方法
WO2022269121A1 (fr) * 2021-06-22 2022-12-29 Iqm Finland Oy Circuit supraconducteur à éléments accordables par flux magnétiques et procédés de limitation de diaphonie de flux entre des éléments accordables par flux magnétiques dans des circuits supraconducteurs
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