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WO2018180235A1 - Semiconductor package device and manufacturing method therefor - Google Patents

Semiconductor package device and manufacturing method therefor Download PDF

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Publication number
WO2018180235A1
WO2018180235A1 PCT/JP2018/008270 JP2018008270W WO2018180235A1 WO 2018180235 A1 WO2018180235 A1 WO 2018180235A1 JP 2018008270 W JP2018008270 W JP 2018008270W WO 2018180235 A1 WO2018180235 A1 WO 2018180235A1
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WO
WIPO (PCT)
Prior art keywords
transistor
package
wiring
semiconductor package
insulating layer
Prior art date
Application number
PCT/JP2018/008270
Other languages
French (fr)
Japanese (ja)
Inventor
細美　英一
Original Assignee
日本電産株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電産株式会社 filed Critical 日本電産株式会社
Priority to CN201880021991.8A priority Critical patent/CN110462825B/en
Priority to JP2019509079A priority patent/JPWO2018180235A1/en
Publication of WO2018180235A1 publication Critical patent/WO2018180235A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in subclass H10D
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits

Definitions

  • the present invention relates to a semiconductor package device and a manufacturing method thereof.
  • Patent Document 1 An example of a conventional package device is disclosed in Patent Document 1.
  • a first integrated circuit die is fixed on a package substrate by adhesion.
  • the first integrated circuit die and the package substrate are connected by wire bonding.
  • the adhesive spacer is disposed between the first integrated circuit die and the integrated circuit package system.
  • the integrated circuit package system includes a second integrated circuit die, a terminal, and a sealing resin.
  • the second integrated circuit die is connected to the terminal by a bonding wire.
  • the second integrated circuit die and the terminal are sealed with a sealing resin.
  • the terminals and the package substrate are connected by bonding wires.
  • the package substrate, the first integrated circuit die, the adhesive spacer, and the integrated circuit package system are packaged by sealing with a sealing resin, thereby forming an integrated circuit package-in-package system.
  • the integrated circuit package system having the second integrated circuit die is disposed above the first integrated circuit die, so that the integrated circuit package system and the first integrated circuit die are electrically connected. Therefore, it is necessary to connect the terminals of the integrated circuit package system to the package substrate by wire bonding. When wire bonding is performed, a corresponding space is required for routing the wire.
  • Patent Document 1 when a similar package device is further stacked above the integrated circuit package system, the length of the bonding wire for connecting to the package substrate becomes longer as the upper package device is formed. . Therefore, in Patent Document 1, the number of package devices to be packaged is greatly limited. *
  • an object of the present invention is to provide a semiconductor package device that eliminates the need for wire bonding for wiring and reduces the number of semiconductor packages to be mounted.
  • An exemplary semiconductor package device of the present invention includes a wiring layer having an insulating part and a conductive part, a plurality of semiconductor packages arranged in contact with the upper surface of the wiring layer, a resin part for sealing the semiconductor package, It is set as the structure provided with.
  • the exemplary method for manufacturing a semiconductor package device of the present invention includes a first step of disposing a plurality of semiconductor packages on an adhesive disposed on a support substrate, and a second step of sealing the semiconductor package with a resin.
  • the exemplary semiconductor package device of the present invention it is not necessary to use wire bonding for wiring, and the number of semiconductor packages to be mounted is reduced.
  • FIG. 1 is a diagram showing a circuit configuration of a semiconductor package device according to an embodiment of the present invention.
  • FIG. 2A is a schematic cross-sectional side view showing one step in the manufacturing process of the semiconductor package device.
  • FIG. 2B is a schematic cross-sectional side view showing one step in the manufacturing process of the semiconductor package device.
  • FIG. 2C is a schematic side cross-sectional view showing one step in the manufacturing process of the semiconductor package device.
  • FIG. 2D is a schematic side cross-sectional view showing one step in the manufacturing process of the semiconductor package device.
  • FIG. 2E is a schematic cross-sectional side view showing one step in the manufacturing process of the semiconductor package device.
  • FIG. 2F is a schematic side cross-sectional view showing one step in the manufacturing process of the semiconductor package device.
  • FIG. 2A is a schematic cross-sectional side view showing one step in the manufacturing process of the semiconductor package device.
  • FIG. 2B is a schematic cross-sectional side view showing one step in the manufacturing process of
  • FIG. 2G is a schematic side cross-sectional view showing one step in the manufacturing process of the semiconductor package device.
  • FIG. 3A is a bottom view showing one process in the manufacturing process of the semiconductor package device.
  • FIG. 3B is a bottom view showing one process in the manufacturing process of the semiconductor package device.
  • FIG. 3C is a bottom view showing one process in the manufacturing process of the semiconductor package device.
  • FIG. 3D is a bottom view showing one process in a manufacturing process of the semiconductor package device.
  • FIG. 1 shows a circuit configuration of a semiconductor package device 50 according to an embodiment of the present invention.
  • the semiconductor package device 50 has a function of driving the motor 60.
  • the semiconductor package device 50 includes a first package 1, a second package 2, a third package 3, a fourth package 4, a fifth package 5, a sixth package 6, 7 package 7.
  • the semiconductor package device 50 according to the present embodiment is configured by packaging a plurality of semiconductor packages that are the first package 1 to the seventh package 7 into one. *
  • the first package 1 includes a microcomputer 1A and a gate driver 1B.
  • the second package 2 includes a first transistor M1 configured by an n-channel MOSFET (metal-oxide-semiconductor field-effect transistor).
  • the third package 3 includes a second transistor M2 configured with a p-channel MOSFET.
  • the fourth package 4 includes a third transistor M3 configured with an n-channel MOSFET.
  • the fifth package 5 includes a fourth transistor M4 configured by a p-channel MOSFET.
  • the sixth package 6 includes a fifth transistor M5 configured with an n-channel MOSFET.
  • the seventh package 7 includes a sixth transistor M6 configured by a p-channel MOSFET. *
  • the first transistor M1 to the sixth transistor M6 constitute an inverter IV. *
  • the application terminal of the input voltage Vin which is a DC voltage is connected to the source of the second transistor M2.
  • the drain of the second transistor M2 is connected to the drain of the first transistor M1.
  • the source of the first transistor M1 is connected to a ground potential application terminal. That is, the first transistor M1 and the second transistor M2 are connected in series.
  • the application terminal of the input voltage Vin is connected to the source of the fourth transistor M4.
  • the drain of the fourth transistor M4 is connected to the drain of the third transistor M3.
  • the source of the third transistor M3 is connected to a ground potential application terminal. That is, the third transistor M3 and the fourth transistor M4 are connected in series.
  • the application terminal of the input voltage Vin is connected to the source of the sixth transistor M6.
  • the drain of the sixth transistor M6 is connected to the drain of the fifth transistor M5.
  • the source of the fifth transistor M5 is connected to a ground potential application terminal. That is, the fifth transistor M5 and the sixth transistor M6 are connected in series.
  • the motor 60 that is the driving target of the semiconductor package device 50 is a three-phase brushless DC motor.
  • a connection node P1 to which the fifth transistor M5 and the sixth transistor M6 are connected is connected to the U-phase input terminal of the motor 60.
  • a connection node P2 to which the third transistor M3 and the fourth transistor M4 are connected is connected to a V-phase input terminal of the motor 60.
  • a connection node P3 to which the first transistor M1 and the second transistor M2 are connected is connected to the W-phase input terminal of the motor 60.
  • the gate driver 1B switches the transistors M1 to M6 by applying a driving voltage to the gates of the transistors M1 to M6 based on a command from the microcomputer 1A.
  • the motor 60 is driven by, for example, sinusoidal driving.
  • the upper transistor (for example, the second transistor M2) and the lower transistor (for example, the first transistor M1) constituting one arm are p-channel MOSFET and n-channel MOSFET, respectively.
  • both the upper transistor and the lower transistor may be constituted by n-channel MOSFETs.
  • a bootstrap capacitor for driving the upper transistor is included in the semiconductor package device.
  • FIGS. 2A to 2G are schematic side sectional views in each step. *
  • a support substrate 52 having an adhesive 51 disposed on the upper surface is prepared, and seven semiconductor packages, which are the first package 1 to the seventh package 7, are arranged on the adhesive 51.
  • the fourth package 4 to the seventh package 7 are not shown in FIG. 2A, they are actually arranged on the back side of the sheet of FIG. 2A.
  • a glass substrate or a silicon substrate is used as the support substrate 52. *
  • the process proceeds to the step shown in FIG. 2B.
  • the resin part (mold resin) 501 is sealed so as to cover the whole of the first package 1 to the seventh package 7. *
  • the process proceeds to the step shown in FIG. 2D, and the first insulating layer 502 is formed on the lower surface side of the first package 1 to the seventh package 7.
  • a via 502A is formed by laser processing or the like.
  • the via 502A is a through-hole penetrating in the thickness direction of the first insulating layer 502, and is formed at a position corresponding to each terminal of the first package 1 to the seventh package.
  • the first wiring pattern portion 503 is formed by plating on the inside of the via 502A and the lower surface of the first insulating layer 502.
  • the plating for example, copper plating is used.
  • a conductive material (such as copper) used for plating may be filled inside the via, or the conductive material may be formed only along the inner wall of the via.
  • the process proceeds to the step shown in FIG. 2F, and the second insulating layer 504 is formed on the lower surface side of the first insulating layer 502. Then, a via 504A is formed in the second insulating layer 504. The via 504A is formed at a position corresponding to a predetermined location of the first wiring pattern portion 503. Then, as shown in FIG. 2F, the second wiring pattern portion 505 is formed by plating on the inside of the via 504A and the lower surface of the second insulating layer 504. *
  • the process proceeds to the step shown in FIG. 2G, and the semiconductor package device 50 is completed by forming the resist layer 506 on the lower surface side of the second insulating layer 504.
  • the resist layer 506 is laminated so as not to be formed at a position corresponding to a portion exposed downward in the second wiring pattern portion 505.
  • the portion exposed below is a terminal portion that is electrically connected to a printed board on which the semiconductor package device 50 is mounted.
  • solder ball can be provided at the lower exposed portion of the second wiring pattern portion 505.
  • an insulating portion 5001A is configured from the first insulating layer 502 and the second insulating layer 504.
  • the first wiring pattern portion 503 and the second wiring pattern portion 505 constitute a conductor portion 5001B. That is, the semiconductor package device 50 includes a wiring layer 5001 including an insulating part 5001A and a conductor part 5001B.
  • the semiconductor package device 50 according to the present embodiment manufactured by such a manufacturing process can perform wiring by forming the conductor portion 5001B by plating the insulating portion 5001A, wire bonding is not necessary. . Further, compared to the conventional configuration in which the above-described package devices are stacked in the vertical direction (vertical direction), the number of semiconductor packages to be mounted is less likely to be limited. *
  • wiring is performed on a plurality of stacked insulating layers such as the first insulating layer 502 and the second insulating layer 504, so that the degree of freedom of wiring can be increased in a limited space. . *
  • the semiconductor package device 50 is a wide variety when dealing with various motors. However, since a prepackaged device is used, the semiconductor package device 50 is compatible with a wide variety. It is easy. *
  • FIG. 3A shows a plan view seen from below in the state shown in FIG. 2C in the manufacturing process described above.
  • 3A is a bottom view of the first package 1 to the seventh package sealed by the resin portion 501.
  • FIG. 3A the plurality of terminals 10 of the first package 1 are arranged on each side of the outer edge of the rectangular lower surface of the first package 1 and exposed downward.
  • the terminal 10 includes driving terminals 10A to 10F described later. *
  • the second package 2 has a control terminal 2A, a current outflow terminal 2B, and a current inflow terminal 2C, and these terminals are exposed downward.
  • the second package 2 has a chip of the first transistor M1 inside.
  • the control terminal 2A is connected to the gate of the first transistor M1.
  • the current outflow terminal 2B is connected to the source of the first transistor M1.
  • the current inflow terminal 2C is connected to the drain of the first transistor M1.
  • the third package 3 has a control terminal 3A, a current outflow terminal 3B, and a current inflow terminal 3C, and these terminals are exposed downward.
  • the third package 3 has a chip of the second transistor M2 inside.
  • the control terminal 3A is connected to the gate of the second transistor M2.
  • the current outflow terminal 3B is connected to the drain of the second transistor M2.
  • the current inflow terminal 3C is connected to the source of the second transistor M2. *
  • the fourth package 4 has a control terminal 4A, a current outflow terminal 4B, and a current inflow terminal 4C, and these terminals are exposed downward.
  • the fourth package 4 has a third transistor M3 chip inside.
  • the control terminal 4A is connected to the gate of the third transistor M3.
  • the current outflow terminal 4B is connected to the source of the third transistor M3.
  • the current inflow terminal 4C is connected to the drain of the third transistor M3. *
  • the fifth package 5 has a control terminal 5A, a current outflow terminal 5B, and a current inflow terminal 5C, and these terminals are exposed downward.
  • the fifth package 5 has a chip of a fourth transistor M4 inside.
  • the control terminal 5A is connected to the gate of the fourth transistor M4.
  • the current outflow terminal 5B is connected to the drain of the fourth transistor M4.
  • the current inflow terminal 5C is connected to the source of the fourth transistor M4. *
  • the sixth package 6 has a control terminal 6A, a current outflow terminal 6B, and a current inflow terminal 6C, and these terminals are exposed downward.
  • the sixth package 6 has a chip of a fifth transistor M5 inside.
  • the control terminal 6A is connected to the gate of the fifth transistor M5.
  • the current outflow terminal 6B is connected to the source of the fifth transistor M5.
  • the current inflow terminal 6C is connected to the drain of the fifth transistor M5. *
  • the seventh package 7 has a control terminal 7A, a current outflow terminal 7B, and a current inflow terminal 7C, and these terminals are exposed downward.
  • the seventh package 7 has a sixth transistor M6 chip inside.
  • the control terminal 7A is connected to the gate of the sixth transistor M6.
  • the current outflow terminal 7B is connected to the drain of the sixth transistor M6.
  • the current inflow terminal 7C is connected to the source of the sixth transistor M6. *
  • FIG. 3B is a plan view of the state of the process shown in FIG. 2D described above viewed from below. That is, FIG. 3B shows a state in which the first insulating layer 502 is formed and the via 502A is formed in the first insulating layer 502 with respect to the state of FIG. 3A. *
  • vias 502 ⁇ / b> A are formed at positions corresponding to the terminals 10 of the first package 1.
  • vias 502A are formed at positions corresponding to the control terminals 2A to 7A, the current outflow terminals 2B to 7B, and the current inflow terminals 2C to 7C of the second package 2 to the seventh package 7, respectively.
  • four vias 502A are formed for each of the current inflow terminals 2C to 7C.
  • FIG. 3C is a plan view of the state of the process shown in FIG. 2E described above as viewed from below. That is, FIG. 3C shows a state in which the first wiring pattern portion 503 is formed by plating on the inside of the via 502A and the lower surface of the first insulating layer 502 in the state of FIG. 3B. *
  • the first wiring pattern portion 503 includes control wiring portions 503A to 503F, connection wiring portions 503G to 503I, a common connection wiring portion 503J, and a wiring portion 503K. *
  • the control wiring portions 503A to 503F electrically connect the driving terminals 10A to 10F of the first package 1 and the control terminals 2A to 7A, respectively.
  • the first package 1 can apply a driving voltage to the control terminals 2A to 7A via the control wiring portions 503A to 503F.
  • connection wiring portions 503G to 503I are respectively connected to the current outflow terminals 3B, 5B, and 7B of the third, fifth, and seventh packages, and the current inflow terminals 2C, 4C, and 6C of the second, fourth, and sixth packages, respectively. , Connect electrically. *
  • the common connection wiring portion 503J electrically connects the current inflow terminals 3C, 5C, and 7C of the third, fifth, and seventh packages in common. *
  • wiring portions 503K are electrically connected to the terminals 10 other than the driving terminals 10A to 10F of the first package 1, respectively.
  • FIG. 3D is a plan view of the state of the process shown in FIG. 2F described above viewed from below. That is, FIG. 3D shows the state of FIG. 3C in which the second insulating layer 504 is formed, the via 504A is formed in the second insulating layer 504, and the inside of the via 504A and the lower surface of the second insulating layer 504 are plated. A state in which the second wiring pattern portion 505 is formed is shown. *
  • the second wiring pattern portion 505 includes ground wiring portions 505A to 505C, output wiring portions 505D to 505F, an input voltage application wiring portion 505G, and a circular wiring portion 505H.
  • the ground wiring portion 505A is electrically connected to the current outflow terminal 2B of the second package 2 through the via 504A and the via 502A.
  • the ground wiring portion 505B is electrically connected to the current outflow terminal 4B of the fourth package 4 through the via 504A and the via 502A.
  • the ground wiring portion 505C is electrically connected to the current outflow terminal 6B of the sixth package 6 through the via 504A and the via 502A.
  • a ground potential is applied to the ground wiring portions 505A to 505C when the semiconductor package device 50 is mounted. *
  • the ground wiring portion 505B overlaps with the control wiring portion 503B in plan view.
  • the ground wiring portion 505C overlaps with the control wiring portions 503A to 503F in plan view.
  • the ground wiring portions 505B and 505C are formed in different layers from the control wiring portions 503A to 503F, it is possible to avoid interference between the control wiring of each transistor and the ground wiring in a limited wiring space. it can. *
  • Output wiring portions 505D to 505F are electrically connected to connection wiring portions 503G to 503I through vias 504A, respectively.
  • the output wiring portions 505D to 505F are electrically connected to the input terminals of the respective phases of the motor 60. *
  • the input voltage application wiring portion 505G is electrically connected to the common connection wiring portion 503J through the via 504A.
  • the input voltage Vin is applied to the input voltage application wiring portion 505G by mounting the semiconductor package device 50.
  • the input voltage Vin is, for example, 200V to 300V. *
  • the output wiring portions 505D to 505F overlap with the common connection wiring portion 503J in plan view. However, since the output wiring portions 505D to 505F are formed in different layers from the common connection wiring portion 503J, it is possible to avoid interference between the output wiring and the input voltage application wiring in a limited wiring space. *
  • the circular wiring portion 505H is electrically connected to the connection terminal portion Tc via the via 504A, the wiring portion 503K, and another via 504A.
  • the connection terminal portion Tc is disposed at a position corresponding to each circular wiring portion 505H.
  • the connection terminal portion Tc is included in the second wiring pattern portion 505.
  • the circular wiring portion 505H is connected to the circular wiring portion 503K via the via 504A, and the circular wiring portion 505H and the connection terminal portion Tc are connected to each other by a wiring (not shown) in the second wiring pattern portion 505. Also good. *
  • the semiconductor package device 50 is completed by forming the resist layer 506 as in the step shown in FIG. 2G.
  • Input terminals Tin1 and Tin2 are formed at the ends of the input voltage application wiring portion 505G.
  • Output terminals Tout1 to Tout3 are formed at the end portions of the output wiring portions 505D to 505F, respectively.
  • Ground terminals Tg1 to Tg3 are formed at respective end portions of the ground wiring portions 505A to 505C.
  • the resist layer 506 is formed so that the input terminals Tin1, Tin2, Tout1 to Tout3, Tg1 to Tg3, and the connection terminal portion Tc are exposed downward. *
  • connection terminal portion Tc is on one side of the first side of the rectangular outer edge of the semiconductor package device 50, one side of the second side opposite to the first side, and a third side sandwiched between the first side and the second side. Arranged along.
  • the input terminal Tin1 is disposed along the other side of the second side.
  • the output terminals Tout1 to Tout3 and the input terminal Tin2 are arranged along the fourth side opposite to the third side.
  • the output terminals Tout1 to Tout3 and the input terminals Tin1 and Tin2 are adjacent to each other to form the first group G1.
  • the connection terminal portions Tc are adjacent to each other to form the second group G2. Since the first group G1 and the second group G2 are arranged at positions far apart from each other, the high voltage connected to the output terminals Tout1 to Tout3 and the input terminals Tin1 and Tin2 when the semiconductor package device 50 is mounted on the printed board. The insulation between the system wiring and the low voltage system wiring connected to the connection terminal portion Tc can be ensured.
  • the third group G3 including the ground terminals Tg1 to Tg3 is arranged along the first side as in the second group G2, but the third group G3 and the second group G2 are arranged apart from each other. Therefore, it is possible to ensure insulation between the ground wiring connected to the ground terminals Tg1 to Tg3 and the wiring connected to the connection terminal portion Tc when the semiconductor package device 50 is mounted.
  • the semiconductor package device (50) of the present embodiment is in contact with the wiring layer (5001) having the insulating portion (5001A) and the conductive portion (5001B), and the upper surface of the wiring layer. And a plurality of semiconductor packages (1 to 7) disposed in a row, and a resin portion (501) for sealing the semiconductor package.
  • wiring can be performed by forming a conductive portion by plating the insulating portion, and wire bonding is not necessary.
  • the limitation on the number of semiconductor packages to be mounted can be reduced.
  • the insulating portion includes a plurality of insulating layers (502, 504) stacked in the vertical direction, and the conductive portion is a wiring pattern portion (503, 503) disposed on the lower surface of the insulating layer. 505).
  • the freedom degree of wiring can be made high in the limited wiring space.
  • the said structure WHEREIN The resist layer (506) arrange
  • the semiconductor package includes a first package (1) having a microcomputer (1A) and a gate driver (1B), a second package (2) including a first transistor (M1), and the first transistor in series. And a third package (3) including a second transistor (M2) to be connected. Since the required transistor capacity varies depending on the motor to be driven by the semiconductor package device, there are many types of semiconductor package devices to support various motors. It is easy to respond. *
  • the semiconductor package includes a fourth package (4) including a third transistor (M3) and a fifth package (5) including a fourth transistor (M4) connected in series to the third transistor. ), A sixth package (6) including a fifth transistor (M5), and a seventh package (7) including a sixth transistor (M6) connected in series to the fifth transistor.
  • the insulating part includes a first insulating layer (502) and a second insulating layer (504) located below the first insulating layer.
  • the conductive portion is disposed on the lower surface of the first insulating layer, and electrically connects the terminals (10A to 10F) of the first package and the control terminals (2A to 7A) of the second to seventh packages.
  • Control wiring portions (503A to 503F) connected to the second insulation layer, and the current outflow terminals (2B, 4B, 6B) of the second package, the fourth package, and the sixth package. And at least one of the control wiring portions overlaps at least one of the ground wiring portions in a plan view.
  • the conductive portion is disposed on the lower surface of the first insulating layer, and the current outflow terminals (3B, 5B, 7B) of the third, fifth, and seventh packages and the second and second 4.
  • the connection wiring portions (503G to 503I) that electrically connect the current inflow terminals (2C, 4C, 6C) of the sixth package and the lower surface of the first insulating layer are disposed, and the third, third, 5, common connection wiring part (503J) for electrically connecting the current inflow terminals (3C, 5C, 7C) of the seventh package, and the connection wiring part disposed on the lower surface of the second insulating layer,
  • the common connection wiring portion is for each output Overlap in the line portion in plan view.
  • the semiconductor package device for driving a motor including the inverter it is possible to avoid interference between the output wiring and the input voltage application wiring by forming the insulating layer with two layers in a limited wiring space.
  • the conductive portion includes the current outflow terminals (3B, 5B, and 7B) of the third, fifth, and seventh packages and the current inflow terminals of the second, fourth, and sixth packages ( 2C, 4C, and 6C), each output wiring portion (505D to 505F) electrically connected to each connection point, and each current inflow terminal (3C, 5C, 7C) and a voltage application wiring portion (505G) electrically connected to each terminal, and each connection terminal portion (Tc) for electrical connection to each terminal (10) of the first package.
  • Each end (Tout1 to Tout3, Tin1, Tin2) of the output wiring section and the voltage applying wiring section is located on the outer edge of the wiring layer and constitutes the first group (G1) adjacent to each other.
  • Each of the connection terminal portions is located on the outer edge of the wiring layer and is adjacent to each other to form a second group (G2), and the first group and the second group are located at positions separated from each other.
  • each end of the output wiring portion and the voltage applying wiring portion which is a high voltage system and each connection terminal portion which is a low voltage system are different from each other. Since the group is formed and located at positions separated from each other, insulation between the high voltage system wiring and the low voltage system wiring can be ensured in the substrate on which the semiconductor package device is mounted.
  • the manufacturing method of the semiconductor package device (50) of the present embodiment includes a first step of disposing a plurality of semiconductor packages (1-7) on an adhesive (51) disposed on a support substrate (52). A second step of sealing the semiconductor package with a resin (501); a third step of removing the support substrate and the adhesive from the resin; and an insulating layer (502, 504) on the lower surface side of the resin. Forming a via (502A, 504A) in the insulating layer, and forming a wiring pattern portion (503, 505) by plating on the via and the lower surface of the insulating layer at least once. And including. *
  • the semiconductor package device has an inverter composed of six transistors, but the semiconductor package device for driving a motor is not limited to having an inverter, but only two transistors connected in series. It is good also as a structure to have.
  • the use of the semiconductor package device is not limited to motor driving.
  • a package including components such as a chip capacitor may be included.
  • the present invention can be suitably used for a semiconductor package device for driving a motor, for example.
  • 50 Semiconductor package device, 60 ... Motor, 1 ... 1st package, 2 ... 2nd package, 3 ... 3rd package, 4 ... 4th package, 5 ... 5th package, 6 ... 6th package, 7 ... 7th package, 1A ... microcomputer, 1B ... gate driver, M1 ... 1st transistor, M2 ... 2nd transistor, M3 ... 3rd transistor, M4 ... 4th transistor, M5 ... 5th transistor, M6 ... 6th transistor, IV ... Inverter, P1-P3 ... Connection node, 51 ... Support substrate, 52... Adhesive, 501... Resin part, 502... First insulating layer, 502 A... Via, 503...
  • First wiring pattern part 504. 504A ... via 505 ..Second wiring pattern part, 506... Resist layer, 5001 .. wiring layer, 5001A .. insulating part, 5001B .. conductor part, 10 .. terminal, 10A to 10F. Terminals, 2A-7A ... Control terminals, 2B-7B ... Current outflow terminals, 2C-7C ... Current inflow terminals, 503A-503F ... Control wiring, 503G-503I ...
  • Connection wiring 503J Common connection wiring section
  • 503K Wiring section
  • 505A to 505C Ground wiring section
  • 505D to 505F Output wiring section
  • 505G Input voltage applying wiring section
  • 505H Circular wiring section
  • Tg1 to Tg3 Ground terminal
  • Tin1, Tin2 Input terminal
  • Tout1 to Tout3 Output terminal
  • Tc Connection terminal section
  • G1 First group , 2,... The second group, G3 ⁇ third group

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Inverter Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

Provided is a semiconductor package device comprising: a wiring layer that has an insulative section and a conductive section; a plurality of semiconductor packages disposed in contact with the upper surface of the wiring layer; and a resin section for sealing the semiconductor packages.

Description

半導体パッケージ装置、およびその製造方法Semiconductor package device and manufacturing method thereof
本発明は、半導体パッケージ装置、およびその製造方法に関する。 The present invention relates to a semiconductor package device and a manufacturing method thereof.
従来のパッケージ装置の一例は、特許文献１に開示される。特許文献１の集積回路パッケージインパッケージシステムでは、パッケージ基板上に第１集積回路ダイが接着により固定される。第１集積回路ダイとパッケージ基板は、ワイヤボンディングにより接続される。接着スペーサは、第１集積回路ダイと集積回路パッケージシステムとの間に配置される。　 An example of a conventional package device is disclosed in Patent Document 1. In the integrated circuit package-in-package system of Patent Document 1, a first integrated circuit die is fixed on a package substrate by adhesion. The first integrated circuit die and the package substrate are connected by wire bonding. The adhesive spacer is disposed between the first integrated circuit die and the integrated circuit package system. *
集積回路パッケージシステムは、第２集積回路ダイと、端子と、封止用樹脂とを有する。第２集積回路ダイは、ボンディングワイヤにより端子と接続される。第２集積回路ダイと端子は、封止用樹脂により封止される。端子とパッケージ基板とは、ボンディングワイヤにより接続される。　 The integrated circuit package system includes a second integrated circuit die, a terminal, and a sealing resin. The second integrated circuit die is connected to the terminal by a bonding wire. The second integrated circuit die and the terminal are sealed with a sealing resin. The terminals and the package substrate are connected by bonding wires. *
パッケージ基板、第１集積回路ダイ、接着スペーサ、および集積回路パッケージシステムが封止用樹脂により封止されることでパッケージ化され、集積回路パッケージインパッケージシステムが構成される。 The package substrate, the first integrated circuit die, the adhesive spacer, and the integrated circuit package system are packaged by sealing with a sealing resin, thereby forming an integrated circuit package-in-package system.
特開２０１２－１６９６６４号公報JP 2012-169664 A
しかしながら、上記特許文献１では、第２集積回路ダイを有する集積回路パッケージシステムは、第１集積回路ダイの上方に配置されるので、集積回路パッケージシステムと第１集積回路ダイとを電気的に接続するために、集積回路パッケージシステムの端子をパッケージ基板にワイヤボンディングにより接続する必要がある。ワイヤボンディングを行うと、その分、ワイヤを取回すためのスペースが必要となる。　 However, in Patent Document 1, the integrated circuit package system having the second integrated circuit die is disposed above the first integrated circuit die, so that the integrated circuit package system and the first integrated circuit die are electrically connected. Therefore, it is necessary to connect the terminals of the integrated circuit package system to the package substrate by wire bonding. When wire bonding is performed, a corresponding space is required for routing the wire. *
また、上記特許文献１において、集積回路パッケージシステムの上方にさらに同様のパッケージデバイスを積層する場合、上方のパッケージデバイスになる程、パッケージ基板と接続するためのボンディングワイヤの長さが長くなってしまう。従って、上記特許文献１では、パッケージ化するパッケージデバイスの個数の制限が大きい。　 Further, in Patent Document 1, when a similar package device is further stacked above the integrated circuit package system, the length of the bonding wire for connecting to the package substrate becomes longer as the upper package device is formed. . Therefore, in Patent Document 1, the number of package devices to be packaged is greatly limited. *
上記状況に鑑み、本発明は、配線にワイヤボンディングを用いることが不要となり、且つ、搭載する半導体パッケージの個数の制限が少なくなる半導体パッケージ装置を提供することを目的とする。 In view of the above situation, an object of the present invention is to provide a semiconductor package device that eliminates the need for wire bonding for wiring and reduces the number of semiconductor packages to be mounted.
本発明の例示的な半導体パッケージ装置は、絶縁部と導電部を有する配線層と、前記配線層の上面に接して配置される複数の半導体パッケージと、前記半導体パッケージを封止する樹脂部と、を備える構成としている。　 An exemplary semiconductor package device of the present invention includes a wiring layer having an insulating part and a conductive part, a plurality of semiconductor packages arranged in contact with the upper surface of the wiring layer, a resin part for sealing the semiconductor package, It is set as the structure provided with. *
また、本発明の例示的な半導体パッケージ装置の製造方法は、支持基板上に配置された接着剤上に複数の半導体パッケージを配置する第１ステップと、前記半導体パッケージを樹脂で封止する第２ステップと、前記支持基板と前記接着剤を前記樹脂から取り外す第３ステップと、前記樹脂の下面側において、絶縁層を形成し、前記絶縁層にビアを形成し、前記ビアおよび前記絶縁層の下面に対してめっきにより配線パターン部を形成するステップを少なくとも１回行う第４ステップと、を含む。 The exemplary method for manufacturing a semiconductor package device of the present invention includes a first step of disposing a plurality of semiconductor packages on an adhesive disposed on a support substrate, and a second step of sealing the semiconductor package with a resin. A step of removing the support substrate and the adhesive from the resin; forming an insulating layer on the lower surface side of the resin; forming a via in the insulating layer; and lower surfaces of the via and the insulating layer And a fourth step of performing the step of forming the wiring pattern portion by plating at least once.
本発明の例示的な半導体パッケージ装置によれば、配線にワイヤボンディングを用いることが不要となり、且つ、搭載する半導体パッケージの個数の制限が少なくなる。 According to the exemplary semiconductor package device of the present invention, it is not necessary to use wire bonding for wiring, and the number of semiconductor packages to be mounted is reduced.
図１は、本発明の一実施形態に係る半導体パッケージ装置の回路構成を示す図である。FIG. 1 is a diagram showing a circuit configuration of a semiconductor package device according to an embodiment of the present invention. 図２Ａは、半導体パッケージ装置の製造工程における一工程を示す概略側面断面図である。FIG. 2A is a schematic cross-sectional side view showing one step in the manufacturing process of the semiconductor package device. 図２Ｂは、半導体パッケージ装置の製造工程における一工程を示す概略側面断面図である。FIG. 2B is a schematic cross-sectional side view showing one step in the manufacturing process of the semiconductor package device. 図２Ｃは、半導体パッケージ装置の製造工程における一工程を示す概略側面断面図である。FIG. 2C is a schematic side cross-sectional view showing one step in the manufacturing process of the semiconductor package device. 図２Ｄは、半導体パッケージ装置の製造工程における一工程を示す概略側面断面図である。FIG. 2D is a schematic side cross-sectional view showing one step in the manufacturing process of the semiconductor package device. 図２Ｅは、半導体パッケージ装置の製造工程における一工程を示す概略側面断面図である。FIG. 2E is a schematic cross-sectional side view showing one step in the manufacturing process of the semiconductor package device. 図２Ｆは、半導体パッケージ装置の製造工程における一工程を示す概略側面断面図である。FIG. 2F is a schematic side cross-sectional view showing one step in the manufacturing process of the semiconductor package device. 図２Ｇは、半導体パッケージ装置の製造工程における一工程を示す概略側面断面図である。FIG. 2G is a schematic side cross-sectional view showing one step in the manufacturing process of the semiconductor package device. 図３Ａは、半導体パッケージ装置の製造工程における一工程を示す下面図である。FIG. 3A is a bottom view showing one process in the manufacturing process of the semiconductor package device. 図３Ｂは、半導体パッケージ装置の製造工程における一工程を示す下面図である。FIG. 3B is a bottom view showing one process in the manufacturing process of the semiconductor package device. 図３Ｃは、半導体パッケージ装置の製造工程における一工程を示す下面図である。FIG. 3C is a bottom view showing one process in the manufacturing process of the semiconductor package device. 図３Ｄは、半導体パッケージ装置の製造工程における一工程を示す下面図である。FIG. 3D is a bottom view showing one process in a manufacturing process of the semiconductor package device.
以下に本発明の例示的な実施形態について図面を参照して説明する。　 Hereinafter, exemplary embodiments of the present invention will be described with reference to the drawings. *
＜１．半導体パッケージの回路構成＞　図１は、本発明の一実施形態に係る半導体パッケージ装置５０の回路構成を示す。半導体パッケージ装置５０は、モータ６０を駆動する機能を有する。図１に示すように、半導体パッケージ装置５０は、第１パッケージ１と、第２パッケージ２と、第３パッケージ３と、第４パッケージ４と、第５パッケージ５と、第６パッケージ６と、第７パッケージ７と、を備える。本実施形態に係る半導体パッケージ装置５０では、第１パッケージ１～第７パッケージ７である複数の半導体パッケージを一つにパッケージ化して構成される。　 <1. Circuit Configuration of Semiconductor Package> FIG. 1 shows a circuit configuration of a semiconductor package device 50 according to an embodiment of the present invention. The semiconductor package device 50 has a function of driving the motor 60. As shown in FIG. 1, the semiconductor package device 50 includes a first package 1, a second package 2, a third package 3, a fourth package 4, a fifth package 5, a sixth package 6, 7 package 7. The semiconductor package device 50 according to the present embodiment is configured by packaging a plurality of semiconductor packages that are the first package 1 to the seventh package 7 into one. *
第１パッケージ１は、マイコン１Ａと、ゲートドライバ１Ｂと、を有する。第２パッケージ２は、ｎチャネルＭＯＳＦＥＴ（metal-oxide-semiconductor field-effect transistor）で構成される第１トランジスタＭ１を有する。第３パッケージ３は、ｐチャネルＭＯＳＦＥＴで構成される第２トランジスタＭ２を有する。第４パッケージ４は、ｎチャネルＭＯＳＦＥＴで構成される第３トランジスタＭ３を有する。第５パッケージ５は、ｐチャネルＭＯＳＦＥＴで構成される第４トランジスタＭ４を有する。第６パッケージ６は、ｎチャネルＭＯＳＦＥＴで構成される第５トランジスタＭ５を有する。第７パッケージ７は、ｐチャネルＭＯＳＦＥＴで構成される第６トランジスタＭ６を有する。　 The first package 1 includes a microcomputer 1A and a gate driver 1B. The second package 2 includes a first transistor M1 configured by an n-channel MOSFET (metal-oxide-semiconductor field-effect transistor). The third package 3 includes a second transistor M2 configured with a p-channel MOSFET. The fourth package 4 includes a third transistor M3 configured with an n-channel MOSFET. The fifth package 5 includes a fourth transistor M4 configured by a p-channel MOSFET. The sixth package 6 includes a fifth transistor M5 configured with an n-channel MOSFET. The seventh package 7 includes a sixth transistor M6 configured by a p-channel MOSFET. *
第１トランジスタＭ１～第６トランジスタＭ６により、インバータＩＶが構成される。　 The first transistor M1 to the sixth transistor M6 constitute an inverter IV. *
第２トランジスタＭ２のソースには、直流電圧である入力電圧Ｖｉｎの印加端が接続される。第２トランジスタＭ２のドレインは、第１トランジスタＭ１のドレインに接続される。第１トランジスタＭ１のソースは、グランド電位の印加端に接続される。すなわち、第１トランジスタＭ１と第２トランジスタＭ２は、直列に接続される。　 The application terminal of the input voltage Vin which is a DC voltage is connected to the source of the second transistor M2. The drain of the second transistor M2 is connected to the drain of the first transistor M1. The source of the first transistor M1 is connected to a ground potential application terminal. That is, the first transistor M1 and the second transistor M2 are connected in series. *
第４トランジスタＭ４のソースには、入力電圧Ｖｉｎの印加端が接続される。第４トランジスタＭ４のドレインは、第３トランジスタＭ３のドレインに接続される。第３トランジスタＭ３のソースは、グランド電位の印加端に接続される。すなわち、第３トランジスタＭ３と第４トランジスタＭ４は、直列に接続される。　 The application terminal of the input voltage Vin is connected to the source of the fourth transistor M4. The drain of the fourth transistor M4 is connected to the drain of the third transistor M3. The source of the third transistor M3 is connected to a ground potential application terminal. That is, the third transistor M3 and the fourth transistor M4 are connected in series. *
第６トランジスタＭ６のソースには、入力電圧Ｖｉｎの印加端が接続される。第６トランジスタＭ６のドレインは、第５トランジスタＭ５のドレインに接続される。第５トランジスタＭ５のソースは、グランド電位の印加端に接続される。すなわち、第５トランジスタＭ５と第６トランジスタＭ６は、直列に接続される。　 The application terminal of the input voltage Vin is connected to the source of the sixth transistor M6. The drain of the sixth transistor M6 is connected to the drain of the fifth transistor M5. The source of the fifth transistor M5 is connected to a ground potential application terminal. That is, the fifth transistor M5 and the sixth transistor M6 are connected in series. *
半導体パッケージ装置５０の駆動対象であるモータ６０は、３相ブラシレスＤＣモータである。第５トランジスタＭ５と第６トランジスタＭ６とが接続される接続ノードＰ１は、モータ６０のＵ相入力端子に接続される。第３トランジスタＭ３と第４トランジスタＭ４とが接続される接続ノードＰ２は、モータ６０のＶ相入力端子に接続される。第１トランジスタＭ１と第２トランジスタＭ２とが接続される接続ノードＰ３は、モータ６０のＷ相入力端子に接続される。　 The motor 60 that is the driving target of the semiconductor package device 50 is a three-phase brushless DC motor. A connection node P1 to which the fifth transistor M5 and the sixth transistor M6 are connected is connected to the U-phase input terminal of the motor 60. A connection node P2 to which the third transistor M3 and the fourth transistor M4 are connected is connected to a V-phase input terminal of the motor 60. A connection node P3 to which the first transistor M1 and the second transistor M2 are connected is connected to the W-phase input terminal of the motor 60. *
ゲートドライバ１Ｂは、マイコン１Ａからの指令に基づき、各トランジスタＭ１～Ｍ６の各ゲートに駆動電圧を印加することで、各トランジスタＭ１～Ｍ６をスイッチ制御する。これにより、モータ６０は、例えば正弦波駆動により駆動される。　 The gate driver 1B switches the transistors M1 to M6 by applying a driving voltage to the gates of the transistors M1 to M6 based on a command from the microcomputer 1A. Thereby, the motor 60 is driven by, for example, sinusoidal driving. *
なお、上記実施形態では、一つのアームを構成する上側トランジスタ（例えば第２トランジスタＭ２）と下側トランジスタ（例えば第１トランジスタＭ１）は、それぞれｐチャネルＭＯＳＦＥＴとｎチャネルＭＯＳＦＥＴを用いたが、これに限らず、例えば上側トランジスタ、下側トランジスタともにｎチャネルＭＯＳＦＥＴにより構成してもよい。この場合、上側トランジスタを駆動するためのブートストラップ用のコンデンサを半導体パッケージ装置に含めることとなる。　 In the above-described embodiment, the upper transistor (for example, the second transistor M2) and the lower transistor (for example, the first transistor M1) constituting one arm are p-channel MOSFET and n-channel MOSFET, respectively. For example, both the upper transistor and the lower transistor may be constituted by n-channel MOSFETs. In this case, a bootstrap capacitor for driving the upper transistor is included in the semiconductor package device. *
また、各トランジスタをＭＯＳＦＥＴに限らず、例えばＩＧＢＴ（insulated gate bipolar transistor）により構成してもよい。　 In addition, each transistor is not limited to a MOSFET, but may be composed of, for example, an IGBT (insulated gate bipolar transistor). *
＜２．半導体パッケージ装置の製造工程＞　次に、図２Ａ～図２Ｇを参照して、本実施形態に係る半導体パッケージ装置５０の製造工程について説明する。図２Ａ～図２Ｇは、各工程における概略側面断面図を示す。　 <2. Manufacturing Process of Semiconductor Package Device> Next, a manufacturing process of the semiconductor package device 50 according to the present embodiment will be described with reference to FIGS. 2A to 2G. 2A to 2G are schematic side sectional views in each step. *
まず、図２Ａに示す工程において、接着剤５１が上面に配置された支持基板５２を準備し、第１パッケージ１～第７パッケージ７である７つの半導体パッケージを接着剤５１上に配列する。なお、第４パッケージ４～第７パッケージ７は、図２Ａでは不図示であるが、実際には図２Ａの紙面奥側に配置される。支持基板５２としては、例えばガラス基板またはシリコン基板などが用いられる。　 First, in the step shown in FIG. 2A, a support substrate 52 having an adhesive 51 disposed on the upper surface is prepared, and seven semiconductor packages, which are the first package 1 to the seventh package 7, are arranged on the adhesive 51. Although the fourth package 4 to the seventh package 7 are not shown in FIG. 2A, they are actually arranged on the back side of the sheet of FIG. 2A. For example, a glass substrate or a silicon substrate is used as the support substrate 52. *
次に、図２Ｂに示す工程に進み、接着剤５１上において、樹脂部（モールド樹脂）５０１によって第１パッケージ１～第７パッケージ７の全体を覆うように封止する。　 Next, the process proceeds to the step shown in FIG. 2B. On the adhesive 51, the resin part (mold resin) 501 is sealed so as to cover the whole of the first package 1 to the seventh package 7. *
そして、図２Ｃに示す工程に進み、樹脂部５０１によって封止された第１パッケージ１～第７パッケージ７から、支持基板５２を接着剤５１とともに取り外す。これにより、図２Ｃに示すように、第１パッケージ１～第７パッケージの下面は露出する。すなわち、各パッケージが有する各端子が下方に露出する。なお、当該各端子のより具体的な構成については、後述する。　 Then, the process proceeds to the step shown in FIG. 2C, and the support substrate 52 is removed together with the adhesive 51 from the first package 1 to the seventh package 7 sealed by the resin portion 501. As a result, as shown in FIG. 2C, the lower surfaces of the first package 1 to the seventh package are exposed. That is, each terminal of each package is exposed downward. A more specific configuration of each terminal will be described later. *
次に、図２Ｄに示す工程に進み、第１パッケージ１～第７パッケージ７の下面側に、第１絶縁層５０２が形成される。そして、第１絶縁層５０２において、レーザ加工等によってビア５０２Ａが形成される。ビア５０２Ａは、第１絶縁層５０２の厚み方向に貫通する貫通孔であり、第１パッケージ１～第７パッケージの各端子に対応する位置に形成される。　 Next, the process proceeds to the step shown in FIG. 2D, and the first insulating layer 502 is formed on the lower surface side of the first package 1 to the seventh package 7. In the first insulating layer 502, a via 502A is formed by laser processing or the like. The via 502A is a through-hole penetrating in the thickness direction of the first insulating layer 502, and is formed at a position corresponding to each terminal of the first package 1 to the seventh package. *
そして、図２Ｅに示す工程に進み、ビア５０２Ａ内部および第１絶縁層５０２の下面に対して、めっきにより、第１配線パターン部５０３が形成される。めっきは、例えば銅めっきが用いられる。また、ビア内部のめっきについては、めっきに用いる導電材（銅など）をビア内部に充填してもよいし、導電材をビアの内壁のみに沿って形成してもよい。　 2E, the first wiring pattern portion 503 is formed by plating on the inside of the via 502A and the lower surface of the first insulating layer 502. For the plating, for example, copper plating is used. As for plating inside the via, a conductive material (such as copper) used for plating may be filled inside the via, or the conductive material may be formed only along the inner wall of the via. *
次に、図２Ｆに示す工程に進み、第１絶縁層５０２の下面側に第２絶縁層５０４を形成する。そして、第２絶縁層５０４において、ビア５０４Ａを形成する。ビア５０４Ａは、第１配線パターン部５０３の所定箇所に対応する位置に形成する。そして、図２Ｆに示すように、ビア５０４Ａ内部および第２絶縁層５０４の下面に対して、めっきにより、第２配線パターン部５０５が形成される。　 Next, the process proceeds to the step shown in FIG. 2F, and the second insulating layer 504 is formed on the lower surface side of the first insulating layer 502. Then, a via 504A is formed in the second insulating layer 504. The via 504A is formed at a position corresponding to a predetermined location of the first wiring pattern portion 503. Then, as shown in FIG. 2F, the second wiring pattern portion 505 is formed by plating on the inside of the via 504A and the lower surface of the second insulating layer 504. *
そして、図２Ｇに示す工程に進み、第２絶縁層５０４の下面側にレジスト層５０６を形成することで、半導体パッケージ装置５０が完成される。レジスト層５０６は、第２配線パターン部５０５における下方に露出させる箇所に対応した位置には形成されないように積層される。当該下方に露出される箇所は、半導体パッケージ装置５０を実装させるプリント基板と電気的に接続される端子部分となる。レジスト層５０６を設けることにより、半導体パッケージ装置５０を半田付けによりプリント基板に実装する際に、半田によって端子部分同士がショートす
ることを抑制できる。また、レジスト層５０６は、熱、埃、湿気などの外部環境から半導体パッケージ装置５０内部の回路を保護する機能も有する。　 Then, the process proceeds to the step shown in FIG. 2G, and the semiconductor package device 50 is completed by forming the resist layer 506 on the lower surface side of the second insulating layer 504. The resist layer 506 is laminated so as not to be formed at a position corresponding to a portion exposed downward in the second wiring pattern portion 505. The portion exposed below is a terminal portion that is electrically connected to a printed board on which the semiconductor package device 50 is mounted. By providing the resist layer 506, when the semiconductor package device 50 is mounted on a printed circuit board by soldering, it is possible to suppress short circuit between the terminal portions due to solder. The resist layer 506 also has a function of protecting the circuit inside the semiconductor package device 50 from an external environment such as heat, dust, and moisture.
なお、第２配線パターン部５０５における上記下方に露出される箇所には、半田ボールを設けることも可能である。　 Note that a solder ball can be provided at the lower exposed portion of the second wiring pattern portion 505. *
図２Ｇに示すように構成される半導体パッケージ装置５０において、第１絶縁層５０２と第２絶縁層５０４から絶縁部５００１Ａが構成される。また、第１配線パターン部５０３と第２配線パターン部５０５から導体部５００１Ｂが構成される。すなわち、半導体パッケージ装置５０は、絶縁部５００１Ａと導体部５００１Ｂとを含む配線層５００１を有する。　 In the semiconductor package device 50 configured as shown in FIG. 2G, an insulating portion 5001A is configured from the first insulating layer 502 and the second insulating layer 504. The first wiring pattern portion 503 and the second wiring pattern portion 505 constitute a conductor portion 5001B. That is, the semiconductor package device 50 includes a wiring layer 5001 including an insulating part 5001A and a conductor part 5001B. *
このような製造工程により製造される本実施形態に係る半導体パッケージ装置５０は、絶縁部５００１Ａに対してめっきによって導体部５００１Ｂを形成することで配線を行うことができるので、ワイヤボンディングが不要となる。また、先述したパッケージデバイスを縦方向（上下方向）に積層する従来の構成に比べ、搭載する半導体パッケージの個数の制限を受けにくい。　 Since the semiconductor package device 50 according to the present embodiment manufactured by such a manufacturing process can perform wiring by forming the conductor portion 5001B by plating the insulating portion 5001A, wire bonding is not necessary. . Further, compared to the conventional configuration in which the above-described package devices are stacked in the vertical direction (vertical direction), the number of semiconductor packages to be mounted is less likely to be limited. *
また、半導体パッケージ装置５０では、第１絶縁層５０２、第２絶縁層５０４といった複数に積層された絶縁層に対して配線を行うので、限られたスペースにおいて配線の自由度を高くすることができる。　 In the semiconductor package device 50, wiring is performed on a plurality of stacked insulating layers such as the first insulating layer 502 and the second insulating layer 504, so that the degree of freedom of wiring can be increased in a limited space. . *
また、駆動対象のモータによって必要なトランジスタ能力が異なるので、各種モータに対応する場合に半導体パッケージ装置５０としては多品種となるが、予めパッケージ化されているデバイスを用いるので、多品種に対応することは容易である。　 In addition, since the required transistor capacity differs depending on the motor to be driven, the semiconductor package device 50 is a wide variety when dealing with various motors. However, since a prepackaged device is used, the semiconductor package device 50 is compatible with a wide variety. It is easy. *
＜３．半導体パッケージ装置の配線構造＞　次に、本実施形態に係る半導体パッケージ装置５０における配線構造について、図３Ａ～図３Ｄを参照して説明する。　 <3. Wiring Structure of Semiconductor Package Device> Next, a wiring structure in the semiconductor package device 50 according to the present embodiment will be described with reference to FIGS. 3A to 3D. *
図３Ａは、先述した製造工程における図２Ｃに示す工程における状態での下方から視た平面図を示す。すなわち、図３Ａは、樹脂部５０１によって第１パッケージ１～第７パッケージを封止した状態の下面図である。図３Ａに示すように、第１パッケージ１の有する複数の端子１０は、第１パッケージ１の矩形状下面の外縁の各辺に配列され、下方に露出する。なお、端子１０には、後述する駆動用端子１０Ａ～１０Ｆが含まれる。　 FIG. 3A shows a plan view seen from below in the state shown in FIG. 2C in the manufacturing process described above. 3A is a bottom view of the first package 1 to the seventh package sealed by the resin portion 501. FIG. As shown in FIG. 3A, the plurality of terminals 10 of the first package 1 are arranged on each side of the outer edge of the rectangular lower surface of the first package 1 and exposed downward. The terminal 10 includes driving terminals 10A to 10F described later. *
第２パッケージ２は、制御端子２Ａと、電流流出端子２Ｂと、電流流入端子２Ｃと、を有し、これらの各端子は下方に露出する。第２パッケージ２は、内部に第１トランジスタＭ１のチップを有する。制御端子２Ａは、第１トランジスタＭ１のゲートに接続される。電流流出端子２Ｂは、第１トランジスタＭ１のソースに接続される。電流流入端子２Ｃは、第１トランジスタＭ１のドレインに接続される。　 The second package 2 has a control terminal 2A, a current outflow terminal 2B, and a current inflow terminal 2C, and these terminals are exposed downward. The second package 2 has a chip of the first transistor M1 inside. The control terminal 2A is connected to the gate of the first transistor M1. The current outflow terminal 2B is connected to the source of the first transistor M1. The current inflow terminal 2C is connected to the drain of the first transistor M1. *
第３パッケージ３は、制御端子３Ａと、電流流出端子３Ｂと、電流流入端子３Ｃと、を有し、これらの各端子は下方に露出する。第３パッケージ３は、内部に第２トランジスタＭ２のチップを有する。制御端子３Ａは、第２トランジスタＭ２のゲートに接続される。電流流出端子３Ｂは、第２トランジスタＭ２のドレインに接続される。電流流入端子３Ｃは、第２トランジスタＭ２のソースに接続される。　 The third package 3 has a control terminal 3A, a current outflow terminal 3B, and a current inflow terminal 3C, and these terminals are exposed downward. The third package 3 has a chip of the second transistor M2 inside. The control terminal 3A is connected to the gate of the second transistor M2. The current outflow terminal 3B is connected to the drain of the second transistor M2. The current inflow terminal 3C is connected to the source of the second transistor M2. *
第４パッケージ４は、制御端子４Ａと、電流流出端子４Ｂと、電流流入端子４Ｃと、を有し、これらの各端子は下方に露出する。第４パッケージ４は、内部に第３トランジスタＭ３のチップを有する。制御端子４Ａは、第３トランジスタＭ３のゲートに接続される。電流流出端子４Ｂは、第３トランジスタＭ３のソースに接続される。電流流入端子４Ｃは、第３トランジスタＭ３のドレインに接続される。　 The fourth package 4 has a control terminal 4A, a current outflow terminal 4B, and a current inflow terminal 4C, and these terminals are exposed downward. The fourth package 4 has a third transistor M3 chip inside. The control terminal 4A is connected to the gate of the third transistor M3. The current outflow terminal 4B is connected to the source of the third transistor M3. The current inflow terminal 4C is connected to the drain of the third transistor M3. *
第５パッケージ５は、制御端子５Ａと、電流流出端子５Ｂと、電流流入端子５Ｃと、を有し、これらの各端子は下方に露出する。第５パッケージ５は、内部に第４トランジスタＭ４のチップを有する。制御端子５Ａは、第４トランジスタＭ４のゲートに接続される。電流流出端子５Ｂは、第４トランジスタＭ４のドレインに接続される。電流流入端子５Ｃは、第４トランジスタＭ４のソースに接続される。　 The fifth package 5 has a control terminal 5A, a current outflow terminal 5B, and a current inflow terminal 5C, and these terminals are exposed downward. The fifth package 5 has a chip of a fourth transistor M4 inside. The control terminal 5A is connected to the gate of the fourth transistor M4. The current outflow terminal 5B is connected to the drain of the fourth transistor M4. The current inflow terminal 5C is connected to the source of the fourth transistor M4. *
第６パッケージ６は、制御端子６Ａと、電流流出端子６Ｂと、電流流入端子６Ｃと、を有し、これらの各端子は下方に露出する。第６パッケージ６は、内部に第５トランジスタＭ５のチップを有する。制御端子６Ａは、第５トランジスタＭ５のゲートに接続される。電流流出端子６Ｂは、第５トランジスタＭ５のソースに接続される。電流流入端子６Ｃは、第５トランジスタＭ５のドレインに接続される。　 The sixth package 6 has a control terminal 6A, a current outflow terminal 6B, and a current inflow terminal 6C, and these terminals are exposed downward. The sixth package 6 has a chip of a fifth transistor M5 inside. The control terminal 6A is connected to the gate of the fifth transistor M5. The current outflow terminal 6B is connected to the source of the fifth transistor M5. The current inflow terminal 6C is connected to the drain of the fifth transistor M5. *
第７パッケージ７は、制御端子７Ａと、電流流出端子７Ｂと、電流流入端子７Ｃと、を有し、これらの各端子は下方に露出する。第７パッケージ７は、内部に第６トランジスタＭ６のチップを有する。制御端子７Ａは、第６トランジスタＭ６のゲートに接続される。電流流出端子７Ｂは、第６トランジスタＭ６のドレインに接続される。電流流入端子７Ｃは、第６トランジスタＭ６のソースに接続される。　 The seventh package 7 has a control terminal 7A, a current outflow terminal 7B, and a current inflow terminal 7C, and these terminals are exposed downward. The seventh package 7 has a sixth transistor M6 chip inside. The control terminal 7A is connected to the gate of the sixth transistor M6. The current outflow terminal 7B is connected to the drain of the sixth transistor M6. The current inflow terminal 7C is connected to the source of the sixth transistor M6. *
図３Ｂは、先述した図２Ｄに示す工程の状態を下方から視た平面図である。すなわち、図３Ｂは、図３Ａの状態に対して第１絶縁層５０２を形成し、第１絶縁層５０２にビア５０２Ａを形成した状態を示す。　 FIG. 3B is a plan view of the state of the process shown in FIG. 2D described above viewed from below. That is, FIG. 3B shows a state in which the first insulating layer 502 is formed and the via 502A is formed in the first insulating layer 502 with respect to the state of FIG. 3A. *
図３Ｂに示すように、第１パッケージ１の各端子１０に対応する位置にビア５０２Ａが形成される。また、第２パッケージ２～第７パッケージ７の各制御端子２Ａ～７Ａ、各電流流出端子２Ｂ～７Ｂ、および各電流流入端子２Ｃ～７Ｃに対応する位置にビア５０２Ａが形成される。なお、各電流流入端子２Ｃ～７Ｃについては、一例として４つのビア５０２Ａを形成している。　 As shown in FIG. 3B, vias 502 </ b> A are formed at positions corresponding to the terminals 10 of the first package 1. In addition, vias 502A are formed at positions corresponding to the control terminals 2A to 7A, the current outflow terminals 2B to 7B, and the current inflow terminals 2C to 7C of the second package 2 to the seventh package 7, respectively. For example, four vias 502A are formed for each of the current inflow terminals 2C to 7C. *
図３Ｃは、先述した図２Ｅに示す工程の状態を下方から視た平面図である。すなわち、図３Ｃは、図３Ｂの状態において、ビア５０２Ａの内部および第１絶縁層５０２の下面に対してめっきによって第１配線パターン部５０３を形成した状態を示す。　 FIG. 3C is a plan view of the state of the process shown in FIG. 2E described above as viewed from below. That is, FIG. 3C shows a state in which the first wiring pattern portion 503 is formed by plating on the inside of the via 502A and the lower surface of the first insulating layer 502 in the state of FIG. 3B. *
図３Ｃに示すように、第１配線パターン部５０３は、制御用配線部５０３Ａ～５０３Ｆと、接続配線部５０３Ｇ～５０３Ｉと、共通接続配線部５０３Ｊと、配線部５０３Ｋと、を含む。　 As shown in FIG. 3C, the first wiring pattern portion 503 includes control wiring portions 503A to 503F, connection wiring portions 503G to 503I, a common connection wiring portion 503J, and a wiring portion 503K. *
制御用配線部５０３Ａ～５０３Ｆはそれぞれ、第１パッケージ１の駆動用端子１０Ａ～１０Ｆと各制御端子２Ａ～７Ａとを電気的に接続する。第１パッケージ１は、制御用配線部５０３Ａ～５０３Ｆを介して駆動電圧を各制御端子２Ａ～７Ａに印加することができる。　 The control wiring portions 503A to 503F electrically connect the driving terminals 10A to 10F of the first package 1 and the control terminals 2A to 7A, respectively. The first package 1 can apply a driving voltage to the control terminals 2A to 7A via the control wiring portions 503A to 503F. *
接続配線部５０３Ｇ～５０３Ｉはそれぞれ、第３、第５、第７パッケージの各電流流出端子３Ｂ、５Ｂ、７Ｂと、第２、第４、第６パッケージの各電流流入端子２Ｃ、４Ｃ、６Ｃと、を電気的に接続する。　 The connection wiring portions 503G to 503I are respectively connected to the current outflow terminals 3B, 5B, and 7B of the third, fifth, and seventh packages, and the current inflow terminals 2C, 4C, and 6C of the second, fourth, and sixth packages, respectively. , Connect electrically. *
共通接続配線部５０３Ｊは、第３、第５、第７パッケージの各電流流入端子３Ｃ、５Ｃ、７Ｃを電気的に共通接続する。　 The common connection wiring portion 503J electrically connects the current inflow terminals 3C, 5C, and 7C of the third, fifth, and seventh packages in common. *
また、第１パッケージ１の駆動用端子１０Ａ～１０Ｆ以外の各端子１０にはそれぞれ、配線部５０３Ｋが電気的に接続される。　 Further, the wiring portions 503K are electrically connected to the terminals 10 other than the driving terminals 10A to 10F of the first package 1, respectively. *
図３Ｄは、先述した図２Ｆに示す工程の状態を下方から視た平面図である。すなわち、図３Ｄは、図３Ｃの状態において、第２絶縁層５０４を形成し、第２絶縁層５０４にビア５０４Ａを形成し、ビア５０４Ａの内部および第２絶縁層５０４の下面に対してめっきによって第２配線パターン部５０５を形成した状態を示す。　 FIG. 3D is a plan view of the state of the process shown in FIG. 2F described above viewed from below. That is, FIG. 3D shows the state of FIG. 3C in which the second insulating layer 504 is formed, the via 504A is formed in the second insulating layer 504, and the inside of the via 504A and the lower surface of the second insulating layer 504 are plated. A state in which the second wiring pattern portion 505 is formed is shown. *
図３Ｄに示すように、第２配線パターン部５０５は、グランド配線部５０５Ａ～５０５Ｃと、出力用配線部５０５Ｄ～５０５Ｆと、入力電圧印加用配線部５０５Ｇと、円形配線部５０５Ｈと、を含む。　 As shown in FIG. 3D, the second wiring pattern portion 505 includes ground wiring portions 505A to 505C, output wiring portions 505D to 505F, an input voltage application wiring portion 505G, and a circular wiring portion 505H. *
グランド配線部５０５Ａは、ビア５０４Ａおよびビア５０２Ａを介して第２パッケージ２の電流流出端子２Ｂに電気的に接続される。グランド配線部５０５Ｂは、ビア５０４Ａおよびビア５０２Ａを介して第４パッケージ４の電流流出端子４Ｂに電気的に接続される。グランド配線部５０５Ｃは、ビア５０４Ａおよびビア５０２Ａを介して第６パッケージ６の電流流出端子６Ｂに電気的に接続される。グランド配線部５０５Ａ～５０５Ｃには、半導体パッケージ装置５０の実装によりグランド電位が印加される。　 The ground wiring portion 505A is electrically connected to the current outflow terminal 2B of the second package 2 through the via 504A and the via 502A. The ground wiring portion 505B is electrically connected to the current outflow terminal 4B of the fourth package 4 through the via 504A and the via 502A. The ground wiring portion 505C is electrically connected to the current outflow terminal 6B of the sixth package 6 through the via 504A and the via 502A. A ground potential is applied to the ground wiring portions 505A to 505C when the semiconductor package device 50 is mounted. *
グランド配線部５０５Ｂは、平面視において、制御用配線部５０３Ｂと重なる。また、グランド配線部５０５Ｃは、平面視において、制御用配線部５０３Ａ～５０３Ｆと重なる。しかしながら、グランド配線部５０５Ｂ、５０５Ｃは、制御用配線部５０３Ａ～５０３Ｆと形成される層が異なるので、限られた配線スペースにおいて、各トランジスタの制御用配線とグランド用配線とが干渉することを回避できる。　 The ground wiring portion 505B overlaps with the control wiring portion 503B in plan view. The ground wiring portion 505C overlaps with the control wiring portions 503A to 503F in plan view. However, since the ground wiring portions 505B and 505C are formed in different layers from the control wiring portions 503A to 503F, it is possible to avoid interference between the control wiring of each transistor and the ground wiring in a limited wiring space. it can. *
出力用配線部５０５Ｄ～５０５Ｆはそれぞれ、ビア５０４Ａを介して接続配線部５０３Ｇ～５０３Ｉと電気的に接続される。出力用配線部５０５Ｄ～５０５Ｆは、モータ６０の各相の入力端子に電気的に接続される。　 Output wiring portions 505D to 505F are electrically connected to connection wiring portions 503G to 503I through vias 504A, respectively. The output wiring portions 505D to 505F are electrically connected to the input terminals of the respective phases of the motor 60. *
入力電圧印加用配線部５０５Ｇは、ビア５０４Ａを介して共通接続配線部５０３Ｊに電気的に接続される。入力電圧印加用配線部５０５Ｇには、半導体パッケージ装置５０の実装により入力電圧Ｖｉｎが印加される。入力電圧Ｖｉｎは、例えば２００Ｖ～３００Ｖである。　 The input voltage application wiring portion 505G is electrically connected to the common connection wiring portion 503J through the via 504A. The input voltage Vin is applied to the input voltage application wiring portion 505G by mounting the semiconductor package device 50. The input voltage Vin is, for example, 200V to 300V. *
出力用配線部５０５Ｄ～５０５Ｆは、平面視において、共通接続配線部５０３Ｊと重なる。しかしながら、出力用配線部５０５Ｄ～５０５Ｆは、共通接続配線部５０３Ｊと形成される層が異なるので、限られた配線スペースにおいて、出力配線と入力電圧印加配線とが干渉することを回避できる。　 The output wiring portions 505D to 505F overlap with the common connection wiring portion 503J in plan view. However, since the output wiring portions 505D to 505F are formed in different layers from the common connection wiring portion 503J, it is possible to avoid interference between the output wiring and the input voltage application wiring in a limited wiring space. *
また、円形配線部５０５Ｈは、ビア５０４Ａ、配線部５０３Ｋ、および別のビア５０４Ａを介して接続端子部Ｔｃに電気的に接続される。各円形配線部５０５Ｈに対応する位置に接続端子部Ｔｃが配置される。接続端子部Ｔｃは、第２配線パターン部５０５に含まれる。なお、円形配線部５０５Ｈが円形とした配線部５０３Ｋとビア５０４Ａを介して接続され、円形配線部５０５Ｈと接続端子部Ｔｃとが第２配線パターン部５０５において不図示の配線により接続される構成としてもよい。　 The circular wiring portion 505H is electrically connected to the connection terminal portion Tc via the via 504A, the wiring portion 503K, and another via 504A. The connection terminal portion Tc is disposed at a position corresponding to each circular wiring portion 505H. The connection terminal portion Tc is included in the second wiring pattern portion 505. The circular wiring portion 505H is connected to the circular wiring portion 503K via the via 504A, and the circular wiring portion 505H and the connection terminal portion Tc are connected to each other by a wiring (not shown) in the second wiring pattern portion 505. Also good. *
図３Ｄの状態において、図２Ｇに示す工程のようにレジスト層５０６を形成することにより、半導体パッケージ装置５０が完成される。入力電圧印加用配線部５０５Ｇの端部には、入力端子Ｔｉｎ１、Ｔｉｎ２が形成される。出力用配線部５０５Ｄ～５０５Ｆのそれぞれの端部には、出力端子Ｔｏｕｔ１～Ｔｏｕｔ３が形成される。グランド配線部５０５Ａ～５０５Ｃのそれぞれの端部には、グランド端子Ｔｇ１～Ｔｇ３が形成される。レジスト層５０６は、入力端子Ｔｉｎ１、Ｔｉｎ２、Ｔｏｕｔ１～Ｔｏｕｔ３、Ｔｇ１～Ｔｇ３、および接続端子部Ｔｃを下方へ露出させるように形成される。　 In the state of FIG. 3D, the semiconductor package device 50 is completed by forming the resist layer 506 as in the step shown in FIG. 2G. Input terminals Tin1 and Tin2 are formed at the ends of the input voltage application wiring portion 505G. Output terminals Tout1 to Tout3 are formed at the end portions of the output wiring portions 505D to 505F, respectively. Ground terminals Tg1 to Tg3 are formed at respective end portions of the ground wiring portions 505A to 505C. The resist layer 506 is formed so that the input terminals Tin1, Tin2, Tout1 to Tout3, Tg1 to Tg3, and the connection terminal portion Tc are exposed downward. *
接続端子部Ｔｃは、半導体パッケージ装置５０の矩形状外縁における第１辺の一方側、第１辺に対向する第２辺の一方側、および第１辺と第２辺に挟まれる第３辺に沿って配列される。入力端子Ｔｉｎ１は、第２辺の他方側に沿って配置される。出力端子Ｔｏｕｔ１～Ｔｏｕｔ３と入力端子Ｔｉｎ２は、第３辺と対向する第４辺に沿って配列される。　 The connection terminal portion Tc is on one side of the first side of the rectangular outer edge of the semiconductor package device 50, one side of the second side opposite to the first side, and a third side sandwiched between the first side and the second side. Arranged along. The input terminal Tin1 is disposed along the other side of the second side. The output terminals Tout1 to Tout3 and the input terminal Tin2 are arranged along the fourth side opposite to the third side. *
すなわち、出力端子Ｔｏｕｔ１～Ｔｏｕｔ３と入力端子Ｔｉｎ１、Ｔｉｎ２は、互いに隣り合って、第１群Ｇ１を構成する。接続端子部Ｔｃは、互いに隣り合って第２群Ｇ２を構成する。第１群Ｇ１と第２群Ｇ２は、大きく離れた位置に配置されるので、半導体パッケージ装置５０のプリント基板への実装時に出力端子Ｔｏｕｔ１～Ｔｏｕｔ３と入力端子Ｔｉｎ１、Ｔｉｎ２にそれぞれ接続される高電圧系の配線と、接続端子部Ｔｃに接続される低電圧系の配線との絶縁を確保することができる。　 That is, the output terminals Tout1 to Tout3 and the input terminals Tin1 and Tin2 are adjacent to each other to form the first group G1. The connection terminal portions Tc are adjacent to each other to form the second group G2. Since the first group G1 and the second group G2 are arranged at positions far apart from each other, the high voltage connected to the output terminals Tout1 to Tout3 and the input terminals Tin1 and Tin2 when the semiconductor package device 50 is mounted on the printed board. The insulation between the system wiring and the low voltage system wiring connected to the connection terminal portion Tc can be ensured. *
また、グランド端子Ｔｇ１～Ｔｇ３から構成される第３群Ｇ３は、第２群Ｇ２と同様に第１辺に沿って配置されるが、第３群Ｇ３と第２群Ｇ２は離れて配置されるので、半導体パッケージ装置５０の実装時にグランド端子Ｔｇ１～Ｔｇ３に接続されるグランド用の配線と、接続端子部Ｔｃに接続される配線との絶縁を確保することができる。　 The third group G3 including the ground terminals Tg1 to Tg3 is arranged along the first side as in the second group G2, but the third group G3 and the second group G2 are arranged apart from each other. Therefore, it is possible to ensure insulation between the ground wiring connected to the ground terminals Tg1 to Tg3 and the wiring connected to the connection terminal portion Tc when the semiconductor package device 50 is mounted. *
＜４．本実施形態の作用効果＞　以上のように本実施形態の半導体パッケージ装
置（５０）は、絶縁部（５００１Ａ）と導電部（５００１Ｂ）を有する配線層（５００１）と、前記配線層の上面に接して配置される複数の半導体パッケージ（１～７）と、前記半導体パッケージを封止する樹脂部（５０１）と、を備える。　 <4. Operational Effects of Present Embodiment> As described above, the semiconductor package device (50) of the present embodiment is in contact with the wiring layer (5001) having the insulating portion (5001A) and the conductive portion (5001B), and the upper surface of the wiring layer. And a plurality of semiconductor packages (1 to 7) disposed in a row, and a resin portion (501) for sealing the semiconductor package.
このような構成によれば、絶縁部に対してめっきにより導電部を形成することで配線を行うことができ、ワイヤボンディングが不要となる。また、搭載する半導体パッケージの個数の制限を少なくできる。　 According to such a configuration, wiring can be performed by forming a conductive portion by plating the insulating portion, and wire bonding is not necessary. In addition, the limitation on the number of semiconductor packages to be mounted can be reduced. *
また、上記構成において、前記絶縁部は、上下方向に積層される複数の絶縁層（５０２、５０４）を有し、前記導電部は、前記絶縁層の下面に配置される配線パターン部（５０３、５０５）を有する。これにより、限られた配線スペースにおいて、配線の自由度を高くすることができる。　 In the above configuration, the insulating portion includes a plurality of insulating layers (502, 504) stacked in the vertical direction, and the conductive portion is a wiring pattern portion (503, 503) disposed on the lower surface of the insulating layer. 505). Thereby, the freedom degree of wiring can be made high in the limited wiring space. *
また、上記構成において、前記配線層の下面に配置されるレジスト層（５０６）をさらに備える。これにより、配線層の下面において半田付け等により導電部がショートすることを抑制することができる。　 Moreover, the said structure WHEREIN: The resist layer (506) arrange | positioned at the lower surface of the said wiring layer is further provided. Thereby, it is possible to suppress a short circuit of the conductive portion due to soldering or the like on the lower surface of the wiring layer. *
また、前記半導体パッケージは、マイコン（１Ａ）およびゲートドライバ（１Ｂ）を有する第１パッケージ（１）と、第１トランジスタ（Ｍ１）を含む第２パッケージ（２）と、前記第１トランジスタに直列に接続される第２トランジスタ（Ｍ２）を含む第３パッケージ（３）と、を含む。半導体パッケージ装置により駆動する対象のモータによって必要なトランジスタ能力が異なるため、種々のモータに対応するには半導体パッケージ装置として多品種となるが、パッケージ化されているデバイスから構成するため、多品種に対応することは容易となる。　 The semiconductor package includes a first package (1) having a microcomputer (1A) and a gate driver (1B), a second package (2) including a first transistor (M1), and the first transistor in series. And a third package (3) including a second transistor (M2) to be connected. Since the required transistor capacity varies depending on the motor to be driven by the semiconductor package device, there are many types of semiconductor package devices to support various motors. It is easy to respond. *
また、上記構成において、前記半導体パッケージは、第３トランジスタ（Ｍ３）を含む第４パッケージ（４）と、前記第３トランジスタに直列に接続される第４トランジスタ（Ｍ４）を含む第５パッケージ（５）と、第５トランジスタ（Ｍ５）を含む第６パッケージ（６）と、前記第５トランジスタに直列に接続される第６トランジスタ（Ｍ６）を含む第７パッケージ（７）と、をさらに含む。前記絶縁部は、第１絶縁層（５０２）と、前記第１絶縁層の下方に位置する第２絶縁層（５０４）を有する。　 In the above configuration, the semiconductor package includes a fourth package (4) including a third transistor (M3) and a fifth package (5) including a fourth transistor (M4) connected in series to the third transistor. ), A sixth package (6) including a fifth transistor (M5), and a seventh package (7) including a sixth transistor (M6) connected in series to the fifth transistor. The insulating part includes a first insulating layer (502) and a second insulating layer (504) located below the first insulating layer. *
そして、前記導電部は、前記第１絶縁層の下面に配置され、前記第１パッケージの各端子（１０Ａ～１０Ｆ）と前記第２～第７パッケージの各制御端子（２Ａ～７Ａ）を電気的に接続する各制御用配線部（５０３Ａ～５０３Ｆ）と、前記第２絶縁層の下面に配置され、前記第２パッケージ、第４パッケージ、および第６パッケージの各電流流出端子（２Ｂ、４Ｂ、６Ｂ）に電気的に接続される各グランド配線部（５０５Ａ～５０５Ｃ）と、を有し、前記各制御用配線部の少なくともいずれかは、前記各グランド配線部の少なくともいずれかと平面視において重なる。　 The conductive portion is disposed on the lower surface of the first insulating layer, and electrically connects the terminals (10A to 10F) of the first package and the control terminals (2A to 7A) of the second to seventh packages. Control wiring portions (503A to 503F) connected to the second insulation layer, and the current outflow terminals (2B, 4B, 6B) of the second package, the fourth package, and the sixth package. And at least one of the control wiring portions overlaps at least one of the ground wiring portions in a plan view. *
これにより、インバータを含むモータ駆動用の半導体パッケージ装置において、限られた配線スペースにおいて絶縁層を２層で構成することで、各トランジスタの制御用配線とグランド用配線の干渉を回避することが可能となる。　 As a result, in the semiconductor package device for driving the motor including the inverter, it is possible to avoid interference between the control wiring and the ground wiring of each transistor by forming the insulating layer with two layers in a limited wiring space. It becomes. *
また、上記構成において、前記導電部は、前記第１絶縁層の下面に配置され、前記第３、第５、第７パッケージの各電流流出端子（３Ｂ、５Ｂ、７Ｂ）と前記第２、第４、第６パッケージの各電流流入端子（２Ｃ、４Ｃ、６Ｃ）を電気的に接続する各接続配線部（５０３Ｇ～５０３Ｉ）と、前記第１絶縁層の下面に配置され、前記第３、第５、第７パッケージの各電流流入端子（３Ｃ、５Ｃ、７Ｃ）を電気的に共通接続する共通接続配線部（５０３Ｊ）と、前記第２絶縁層の下面に配置され、前記各接続配線部と電気的に接続される各出力用配線部（５０５Ｄ～５０５Ｆ）と、前記第２絶縁層の下面に配置され、前記共通接続配線部と電気的に接続される入力電圧印加用配線部（５０５Ｇ）と、を有し、前記共通接続配線部は、前記各出力用配線部と平面視において重なる。　 Further, in the above configuration, the conductive portion is disposed on the lower surface of the first insulating layer, and the current outflow terminals (3B, 5B, 7B) of the third, fifth, and seventh packages and the second and second 4. The connection wiring portions (503G to 503I) that electrically connect the current inflow terminals (2C, 4C, 6C) of the sixth package and the lower surface of the first insulating layer are disposed, and the third, third, 5, common connection wiring part (503J) for electrically connecting the current inflow terminals (3C, 5C, 7C) of the seventh package, and the connection wiring part disposed on the lower surface of the second insulating layer, Each output wiring portion (505D to 505F) to be electrically connected, and an input voltage application wiring portion (505G) disposed on the lower surface of the second insulating layer and electrically connected to the common connection wiring portion And the common connection wiring portion is for each output Overlap in the line portion in plan view. *
これにより、インバータを含むモータ駆動用の半導体パッケージ装置において、限られた配線スペースにおいて絶縁層を２層で構成することで、出力配線と入力電圧印加配線の干渉を回避することが可能となる。　 Thereby, in the semiconductor package device for driving a motor including the inverter, it is possible to avoid interference between the output wiring and the input voltage application wiring by forming the insulating layer with two layers in a limited wiring space. *
また、上記構成において、前記導電部は、前記第３、第５、第７パッケージの各電流流出端子（３Ｂ、５Ｂ、７Ｂ）と前記第２、第４、第６パッケージの各電流流入端子（２Ｃ、４Ｃ、６Ｃ）との各接続点に電気的に接続される各出力用配線部（５０５Ｄ～５０５Ｆ）と、前記第３、第５、第７パッケージの各電流流入端子（３Ｃ、５Ｃ、７Ｃ）と電気的に接続される電圧印加用配線部（５０５Ｇ）と、前記第１パッケージの各端子（１０）と電気的に接続するための各接続端子部（Ｔｃ）と、を有する。そして、前記出力用配線部および前記電圧印加用配線部の各端部（Ｔｏｕｔ１～Ｔｏｕｔ３、Ｔｉｎ１、Ｔｉｎ２）は、前記配線層の外縁に位置し、互いに隣り合って第１群（Ｇ１）を構成し、前記各接続端子部は、前記配線層の外縁に位置し、互いに隣り合って第２群（Ｇ２）を構成し、前記第１群と前記第２群は、離れた位置に位置する。　 In the above configuration, the conductive portion includes the current outflow terminals (3B, 5B, and 7B) of the third, fifth, and seventh packages and the current inflow terminals of the second, fourth, and sixth packages ( 2C, 4C, and 6C), each output wiring portion (505D to 505F) electrically connected to each connection point, and each current inflow terminal (3C, 5C, 7C) and a voltage application wiring portion (505G) electrically connected to each terminal, and each connection terminal portion (Tc) for electrical connection to each terminal (10) of the first package. Each end (Tout1 to Tout3, Tin1, Tin2) of the output wiring section and the voltage applying wiring section is located on the outer edge of the wiring layer and constitutes the first group (G1) adjacent to each other. Each of the connection terminal portions is located on the outer edge of the wiring layer and is adjacent to each other to form a second group (G2), and the first group and the second group are located at positions separated from each other. *
これにより、インバータを含むモータ駆動用の半導体パッケージ装置において、高電圧系である出力用配線部および電圧印加用配線部の各端部と、低電圧系である各接続端子部は、それぞれ別の群を構成し、互いに離れた位置に位置するので、半導体パッケージ装置を実装する基板において、高電圧系と低電圧系の配線間の絶縁を確保することができる。　 As a result, in the semiconductor package device for driving a motor including the inverter, each end of the output wiring portion and the voltage applying wiring portion which is a high voltage system and each connection terminal portion which is a low voltage system are different from each other. Since the group is formed and located at positions separated from each other, insulation between the high voltage system wiring and the low voltage system wiring can be ensured in the substrate on which the semiconductor package device is mounted. *
また、本実施形態の半導体パッケージ装置（５０）の製造方法は、支持基板（５２）上に配置された接着剤（５１）上に複数の半導体パッケージ（１～７）を配置する第１ステップと、前記半導体パッケージを樹脂（５０１）で封止する第２ステップと、前記支持基板と前記接着剤を前記樹脂から取り外す第３ステップと、前記樹脂の下面側において、絶縁層（５０２、５０４）を形成し、前記絶縁層にビア（５０２Ａ、５０４Ａ）を形成し、前記ビアおよび前記絶縁層の下面に対してめっきにより配線パターン部（５０３、５０５）を形成するステップを少なくとも１回行う第４ステップと、を含む。　 Further, the manufacturing method of the semiconductor package device (50) of the present embodiment includes a first step of disposing a plurality of semiconductor packages (1-7) on an adhesive (51) disposed on a support substrate (52). A second step of sealing the semiconductor package with a resin (501); a third step of removing the support substrate and the adhesive from the resin; and an insulating layer (502, 504) on the lower surface side of the resin. Forming a via (502A, 504A) in the insulating layer, and forming a wiring pattern portion (503, 505) by plating on the via and the lower surface of the insulating layer at least once. And including. *
これにより、配線にワイヤボンディングが不要となり、搭載する半導体パッケージの個数の制限を抑えて、容易に半導体パッケージ装置を製造することができる。　 This eliminates the need for wire bonding in the wiring, makes it possible to easily manufacture a semiconductor package device while limiting the number of semiconductor packages to be mounted. *
＜５．その他＞　以上、本発明の実施形態について説明したが、本発明の趣旨の範囲内であれば、実施形態は種々の変更が可能である。　 <5. Others> The embodiment of the present invention has been described above, but the embodiment can be variously modified within the scope of the gist of the present invention. *
例えば、上記実施形態では、６つのトランジスタから構成されるインバータを有する半導体パッケージ装置としたが、モータ駆動用の半導体パッケージ装置として、インバータを備えることに限らず、直列接続された２つのトランジスタのみを有する構成などとしてもよい。なお、半導体パッケージ装置の用途は、モータ駆動用に限ることはない。　 For example, in the above embodiment, the semiconductor package device has an inverter composed of six transistors, but the semiconductor package device for driving a motor is not limited to having an inverter, but only two transistors connected in series. It is good also as a structure to have. The use of the semiconductor package device is not limited to motor driving. *
また、半導体パッケージ装置において、トランジスタを有する半導体パッケージ以外に、チップコンデンサなどの部品も含めてパッケージ化してもよい。 Further, in the semiconductor package device, in addition to the semiconductor package having a transistor, a package including components such as a chip capacitor may be included.
本発明は、例えばモータ駆動用の半導体パッケージ装置に好適に利用することができる。 The present invention can be suitably used for a semiconductor package device for driving a motor, for example.
５０・・・半導体パッケージ装置、６０・・・モータ、１・・・第１パッケージ、２・・・第２パッケージ、３・・・第３パッケージ、４・・・第４パッケージ、５・・・第５パッケージ、６・・・第６パッケージ、７・・・第７パッケージ、１Ａ・・・マイコン、１Ｂ・・・ゲートドライバ、Ｍ１・・・第１トランジスタ、Ｍ２・・・第２トランジスタ、Ｍ３・・・第３トランジスタ、Ｍ４・・・第４トランジスタ、Ｍ５・・・第５トランジスタ、Ｍ６・・・第６トランジスタ、ＩＶ・・・インバータ、Ｐ１～Ｐ３・・・接続ノード、５１・・・支持基板、５２・・・接着剤、５０１・・・樹脂部、５０２・・・第１絶縁層、５０２Ａ・・・ビア、５０３・・・第１配線パターン部、５０４・・・第２絶縁層、５０４Ａ・・・ビア、５０５・・・第２配線パターン部、５０６・・・レジスト層、５００１・・・配線層、５００１Ａ・・・絶縁部、５００１Ｂ・・・導体部、１０・・・端子、１０Ａ～１０Ｆ・・・駆動用端子、２Ａ～７Ａ・・・制御端子、２Ｂ～７Ｂ・・・電流流出端子、２Ｃ～７Ｃ・・・電流流入端子、５０３Ａ～５０３Ｆ・・・制御用配線部、５０３Ｇ～５０３Ｉ・・・接続配線部、５０３Ｊ・・・共通接続配線部、５０３Ｋ・・・配線部、５０５Ａ～５０５Ｃ・・・グランド配線部、５０５Ｄ～５０５Ｆ・・・出力用配線部、５０５Ｇ・・・入力電圧印加用配線部、５０５Ｈ・・・円形配線部、Ｔｇ１～Ｔｇ３・・・グランド端子、Ｔｉｎ１、Ｔｉｎ２・・・入力端子、Ｔｏｕｔ１～Ｔｏｕｔ３・・・出力端子、Ｔｃ・・・接続端子部、Ｇ１・・・第１群、Ｇ２・・・第２群、Ｇ３・・・第３群 50 ... Semiconductor package device, 60 ... Motor, 1 ... 1st package, 2 ... 2nd package, 3 ... 3rd package, 4 ... 4th package, 5 ... 5th package, 6 ... 6th package, 7 ... 7th package, 1A ... microcomputer, 1B ... gate driver, M1 ... 1st transistor, M2 ... 2nd transistor, M3 ... 3rd transistor, M4 ... 4th transistor, M5 ... 5th transistor, M6 ... 6th transistor, IV ... Inverter, P1-P3 ... Connection node, 51 ... Support substrate, 52... Adhesive, 501... Resin part, 502... First insulating layer, 502 A... Via, 503... First wiring pattern part, 504. 504A ... via 505 ..Second wiring pattern part, 506... Resist layer, 5001 .. wiring layer, 5001A .. insulating part, 5001B .. conductor part, 10 .. terminal, 10A to 10F. Terminals, 2A-7A ... Control terminals, 2B-7B ... Current outflow terminals, 2C-7C ... Current inflow terminals, 503A-503F ... Control wiring, 503G-503I ... Connection wiring 503J: Common connection wiring section, 503K: Wiring section, 505A to 505C: Ground wiring section, 505D to 505F: Output wiring section, 505G: Input voltage applying wiring section, 505H: Circular wiring section, Tg1 to Tg3: Ground terminal, Tin1, Tin2: Input terminal, Tout1 to Tout3: Output terminal, Tc: Connection terminal section, G1: First group , 2,... The second group, G3 ··· third group

Claims (8)

  1. 絶縁部と導電部を有する配線層と、　前記配線層の上面に接して配置される複数の半導体パッケージと、　前記半導体パッケージを封止する樹脂部と、　を備える、半導体パッケージ装置。 A semiconductor package device comprising: a wiring layer having an insulating part and a conductive part; a plurality of semiconductor packages arranged in contact with an upper surface of the wiring layer; and a resin part for sealing the semiconductor package.
  2. 前記絶縁部は、上下方向に積層される複数の絶縁層を有し、　前記導電部は、前記絶縁層の下面に配置される配線パターン部を有する、請求項１に記載の半導体パッケージ装置。 2. The semiconductor package device according to claim 1, wherein the insulating portion includes a plurality of insulating layers stacked in a vertical direction, and the conductive portion includes a wiring pattern portion disposed on a lower surface of the insulating layer.
  3. 前記配線層の下面に配置されるレジスト層をさらに備える、請求項１または請求項２に記載の半導体パッケージ装置。 The semiconductor package device according to claim 1, further comprising a resist layer disposed on a lower surface of the wiring layer.
  4. 前記半導体パッケージは、マイコンおよびゲートドライバを有する第１パッケージと、第１トランジスタを含む第２パッケージと、前記第１トランジスタに直列に接続される第２トランジスタを含む第３パッケージと、を含む、請求項１から請求項３のいずれか１項に記載の半導体パッケージ装置。 The semiconductor package includes a first package having a microcomputer and a gate driver, a second package including a first transistor, and a third package including a second transistor connected in series to the first transistor. The semiconductor package device according to any one of claims 1 to 3.
  5. 前記半導体パッケージは、第３トランジスタを含む第４パッケージと、前記第３トランジスタに直列に接続される第４トランジスタを含む第５パッケージと、第５トランジスタを含む第６パッケージと、前記第５トランジスタに直列に接続される第６トランジスタを含む第７パッケージと、をさらに含み、　前記絶縁部は、第１絶縁層と、前記第１絶縁層の下方に位置する第２絶縁層を有し、　前記導電部は、　前記第１絶縁層の下面に配置され、前記第１パッケージの各端子と前記第２～第７パッケージの各制御端子を電気的に接続する各制御用配線部と、　前記第２絶縁層の下面に配置され、前記第２パッケージ、第４パッケージ、および第６パッケージの各電流流出端子に電気的に接続される各グランド配線部と、を有し、　前記各制御用配線部の少なくともいずれかは、前記各グランド配線部の少なくともいずれかと平面視において重なる、請求項４に記載の半導体パッケージ装置。 The semiconductor package includes a fourth package including a third transistor, a fifth package including a fourth transistor connected in series to the third transistor, a sixth package including a fifth transistor, and the fifth transistor. A seventh package including a sixth transistor connected in series, wherein the insulating portion includes a first insulating layer and a second insulating layer located below the first insulating layer, and the conductive layer The parts are arranged on the lower surface of the first insulating layer, electrically connect each terminal of the first package and each control terminal of the second to seventh packages, and the second insulation. Each ground wiring portion disposed on the lower surface of the layer and electrically connected to each current outflow terminal of the second package, the fourth package, and the sixth package. At least one of use wiring portion overlaps at least one in plan view of each of the ground wiring portion, the semiconductor package device according to claim 4.
  6. 前記半導体パッケージは、第３トランジスタを含む第４パッケージと、前記第３トランジスタに直列に接続される第４トランジスタを含む第５パッケージと、第５トランジスタを含む第６パッケージと、前記第５トランジスタに直列に接続される第６トランジスタを含む第７パッケージと、をさらに含み、　前記絶縁部は、第１絶縁層と、前記第１絶縁層の下方に位置する第２絶縁層を有し、　前記導電部は、　前記第１絶縁層の下面に配置され、前記第３、第５、第７パッケージの各電流流出端子と前記第２、第４、第６パッケージの各電流流入端子を電気的に接続する各接続配線部と、　前記第１絶縁層の下面に配置され、前記第３、第５、第７パッケージの各電流流入端子を電気的に共通接続する共通接続配線部と、　前記第２絶縁層の下面に配置され、前記各接続配線部と電気的に接続される各出力用配線部と、　前記第２絶縁層の下面に配置され、前記共通接続配線部と電気的に接続される入力電圧印加用配線部と、を有し、　前記共通接続配線部は、前記各出力用配線部と平面視において重なる、請求項４または請求項５に記載の半導体パッケージ装置。 The semiconductor package includes a fourth package including a third transistor, a fifth package including a fourth transistor connected in series to the third transistor, a sixth package including a fifth transistor, and the fifth transistor. A seventh package including a sixth transistor connected in series, wherein the insulating portion includes a first insulating layer and a second insulating layer located below the first insulating layer, and the conductive layer The portion is disposed on the lower surface of the first insulating layer, and electrically connects the current outflow terminals of the third, fifth, and seventh packages to the current inflow terminals of the second, fourth, and sixth packages. Connecting wiring portions that are arranged on the lower surface of the first insulating layer and electrically connecting the current inflow terminals of the third, fifth, and seventh packages in common, and the second insulation layer Each output wiring portion disposed on the lower surface and electrically connected to each connection wiring portion, and input voltage application disposed on the lower surface of the second insulating layer and electrically connected to the common connection wiring portion 6. The semiconductor package device according to claim 4, wherein the common connection wiring portion overlaps the output wiring portions in a plan view.
  7. 前記半導体パッケージは、第３トランジスタを含む第４パッケージと、前記第３トランジスタに直列に接続される第４トランジスタを含む第５パッケージと、第５トランジス
    タを含む第６パッケージと、前記第５トランジスタに直列に接続される第６トランジスタを含む第７パッケージと、をさらに含み、　前記導電部は、　前記第３、第５、第７パッケージの各電流流出端子と前記第２、第４、第６パッケージの各電流流入端子との各接続点に電気的に接続される各出力用配線部と、　前記第３、第５、第７パッケージの各電流流入端子と電気的に接続される電圧印加用配線部と、　前記第１パッケージの各端子と電気的に接続するための各接続端子部と、を有し、　前記出力用配線部および前記電圧印加用配線部の各端部は、前記配線層の外縁に位置し、互いに隣り合って第１群を構成し、　前記各接続端子部は、前記配線層の外縁に位置し、互いに隣り合って第２群を構成し、　前記第１群と前記第２群は、離れた位置に位置する、請求項４から請求項６のいずれか１項に記載の半導体パッケージ装置。     The semiconductor package includes a fourth package including a third transistor, a fifth package including a fourth transistor connected in series to the third transistor, a sixth package including a fifth transistor, and the fifth transistor. A seventh package including a sixth transistor connected in series, wherein the conductive portion includes the current outflow terminals of the third, fifth, and seventh packages and the second, fourth, and sixth packages. Output wiring portions electrically connected to connection points with the respective current inflow terminals, and voltage application wires electrically connected to the respective current inflow terminals of the third, fifth and seventh packages. And each connection terminal portion for electrically connecting to each terminal of the first package, and each end of the output wiring portion and the voltage application wiring portion is formed on the wiring layer. Outer edge The first group is located adjacent to each other, and each of the connection terminal portions is located at an outer edge of the wiring layer and is adjacent to each other to constitute a second group. The first group and the second group The semiconductor package device according to claim 4, which is located at a distant position.
  8. 支持基板上に配置された接着剤上に複数の半導体パッケージを配置する第１ステップと、　前記半導体パッケージを樹脂で封止する第２ステップと、　前記支持基板と前記接着剤を前記樹脂から取り外す第３ステップと、　前記樹脂の下面側において、絶縁層を形成し、前記絶縁層にビアを形成し、前記ビアおよび前記絶縁層の下面に対してめっきにより配線パターン部を形成するステップを少なくとも１回行う第４ステップと、　を含む、半導体パッケージ装置の製造方法。 A first step of disposing a plurality of semiconductor packages on an adhesive disposed on a support substrate; a second step of sealing the semiconductor package with a resin; and a step of removing the support substrate and the adhesive from the resin. And at least one step of forming an insulating layer on the lower surface side of the resin, forming a via in the insulating layer, and forming a wiring pattern portion on the via and the lower surface of the insulating layer by plating. A semiconductor package device manufacturing method, comprising: a fourth step to be performed.
PCT/JP2018/008270 2017-03-29 2018-03-05 Semiconductor package device and manufacturing method therefor WO2018180235A1 (en)

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