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WO2018177195A1 - Pompe de charge, procédé de traitement et circuit bouclé à verrouillage de phase basés sur la pompe de charge, et support de stockage - Google Patents

Pompe de charge, procédé de traitement et circuit bouclé à verrouillage de phase basés sur la pompe de charge, et support de stockage Download PDF

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Publication number
WO2018177195A1
WO2018177195A1 PCT/CN2018/080067 CN2018080067W WO2018177195A1 WO 2018177195 A1 WO2018177195 A1 WO 2018177195A1 CN 2018080067 W CN2018080067 W CN 2018080067W WO 2018177195 A1 WO2018177195 A1 WO 2018177195A1
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WO
WIPO (PCT)
Prior art keywords
pmos transistor
voltage
charge pump
resistor
source
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Application number
PCT/CN2018/080067
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English (en)
Chinese (zh)
Inventor
程武
谢梦琳
Original Assignee
深圳市中兴微电子技术有限公司
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Publication of WO2018177195A1 publication Critical patent/WO2018177195A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0893—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses

Definitions

  • the present application relates to integrated circuit technology, and in particular, to a charge pump, a charge pump based processing method, a phase locked loop circuit, and a storage medium.
  • phase-locked loop using a charge pump structure
  • existing phase-locked loops using a charge pump structure generally include a Frequency Phase Detector (FPD), a Charge Pump (CP), a Low Pass Filter (LPF), and a Voltage Controlled Oscillator. (VCO, Voltage Control Oscillator) and other components.
  • FPD Frequency Phase Detector
  • CP Charge Pump
  • LPF Low Pass Filter
  • VCO Voltage Controlled Oscillator
  • the role of the charge pump is to amplify the signal output by the FPD and charge and discharge the capacitance of the LPF.
  • a charge pump also known as a switched-capacitor voltage converter, is a DC-DC converter that uses so-called “flying” or “pumping” capacitors (rather than inductors or transformers) to store energy.
  • the charge pump uses an internal FET transistor switch array to control the transfer of charge on the capacitor in a certain way.
  • the charge and discharge of the capacitor in the charge pump is controlled by a clock signal, so that the input voltage is raised or lowered in a certain manner to achieve The required output voltage.
  • phase-locked loop circuits existing charge pumps are difficult to meet the requirements of the phase-locked loop circuit.
  • the existing charge pump does not have high stability and matching due to the differential output voltage generated in a low voltage environment, which cannot meet the requirements of the inductor-capacitor voltage-controlled oscillator. The performance of the inductor-capacitor phase-locked loop circuit is degraded.
  • the embodiments of the present application provide a charge pump, a charge pump-based processing method, a phase-locked loop circuit, and a storage medium, which are capable of generating a differential output voltage with high stability and matching in a low voltage environment.
  • the embodiment of the present application provides a charge pump, the charge pump includes: a charge pump main circuit, a common mode feedback circuit, and a voltage bias circuit; wherein
  • the charge pump main circuit is configured to generate a differential output voltage of the charge pump by using the input differential control signal
  • the common mode feedback circuit is configured to generate a feedback voltage signal based on the differential output voltage and a common mode bias voltage provided by the voltage bias circuit, and output the feedback voltage signal to the charge pump main circuit And adjusting a common mode voltage of the differential output voltage generated by the charge pump main circuit based on the feedback voltage signal.
  • the charge pump further includes: a zero point compensation circuit configured to compensate a phase of the common mode feedback circuit.
  • the charge pump main circuit includes a first branch, a second branch connected to the first branch, and a third branch connected to the second branch;
  • the first branch as a discharge current source, is configured to provide a discharge current for the second branch;
  • the third branch as a charging current source, is configured to provide a charging current for the second branch; and receive a feedback voltage signal output by the common mode feedback circuit to adjust the charging current;
  • the second branch is configured to determine a differential output voltage of the charge pump based on the input differential control signal, the charging current, and the discharging current.
  • the common mode feedback circuit includes a fourth branch and a fifth branch;
  • the fourth branch is configured to acquire a voltage to be detected by means of a resistor divider according to the differential output voltage; the voltage to be detected is greater than a half of a sum of the differential output voltages;
  • the fifth branch is configured to compare the to-be-detected voltage and a common mode bias voltage provided by the voltage bias circuit, generate a feedback voltage signal according to the comparison result, and output the feedback voltage signal to the charge Pump main circuit.
  • the first branch includes a first NMOS transistor and a second NMOS transistor
  • the second branch includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor.
  • the third branch includes a fifth PMOS transistor and a sixth PMOS transistor;
  • the gate of the first NMOS transistor is connected to the gate of the second NMOS transistor, and the gate of the first NMOS transistor and the gate of the second NMOS transistor are connected to the first voltage source, the source of the first NMOS transistor, and the second NMOS.
  • the source of the tube is grounded; the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor and the drain of the third PMOS transistor; the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor and the fourth PMOS transistor.
  • the drain of the first PMOS transistor is connected to the first control signal, the source of the first PMOS transistor is connected to the source of the second PMOS transistor, and the source of the first PMOS transistor and the source of the second PMOS transistor Connected to the drain of the fifth PMOS transistor; the gate of the second PMOS transistor is connected to the second control signal; the gate of the third PMOS transistor is connected to the third control signal, and the source of the third PMOS transistor is connected to the fourth PMOS transistor.
  • the source, the source of the third PMOS transistor and the source of the fourth PMOS transistor are both connected to the drain of the sixth PMOS transistor; the gate of the fourth PMOS transistor is connected to the fourth control signal; the source of the fifth PMOS transistor a source of the sixth PMOS transistor is connected
  • the fourth branch includes a first resistor, a second resistor, and a third resistor
  • the fifth branch includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a seventh PMOS transistor.
  • One end of the first resistor is connected to the drain of the first NMOS transistor, the drain of the first PMOS transistor and the drain of the third PMOS transistor, and the other end is connected to the second resistor; one end of the second resistor is connected to the drain of the second NMOS transistor, a drain of the second PMOS transistor and a drain of the fourth PMOS transistor, and the other end is connected to the first resistor; one end of the third resistor is connected to the gate of the fourth NMOS transistor, the first resistor and the second resistor, and the other end is connected to the third a voltage source; a drain of the third NMOS transistor is connected to a source of the fourth NMOS transistor and a source of the fifth NMOS transistor, a gate of the third NMOS transistor is connected to the first voltage source, and a source of the third NMOS transistor is grounded; The gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor, and the drain of the seventh PMOS transistor is connected to the gate of the seventh PMOS transistor,
  • the drain of the tube; the gate of the tenth PMOS transistor is connected to the gate of the ninth PMOS transistor, and the drain of the tenth PMOS transistor is connected to the gate of the tenth PMOS transistor, the gate of the ninth PMOS transistor, and the eighth PMOS transistor a drain, a drain of the fifth NMOS transistor, a gate of the fifth PMOS transistor, a gate of the sixth PMOS transistor, a source of the seventh PMOS transistor, a source of the eighth PMOS transistor, and a ninth
  • the source of the PMOS transistor and the source of the tenth PMOS transistor are all connected to the second voltage source.
  • the voltage bias circuit includes a fourth resistor and a fifth resistor
  • One end of the fourth resistor is connected to the gate of the fifth NMOS transistor and the fifth resistor, and the other end is connected to the fourth voltage source; one end of the fifth resistor is connected to the gate of the fifth NMOS transistor and the fourth resistor, and the other end is grounded.
  • the zero point compensation circuit includes a sixth resistor and a capacitor
  • One end of the sixth resistor is connected to the gate of the fourth NMOS transistor, the first resistor, the second resistor, and the third resistor, and the other end is connected to the capacitor; one end of the capacitor is connected to the sixth resistor, and the other end is grounded.
  • the resistance of the first resistor is equal to the resistance of the second resistor.
  • the aspect ratio of the first NMOS transistor is equal to the aspect ratio of the second NMOS transistor;
  • the width to length ratio of the third NMOS transistor is equal to the aspect ratio of the first NMOS transistor;
  • the width to length ratio of the fourth NMOS transistor is equal to the width to length ratio of the fifth NMOS transistor;
  • the aspect ratio of the first PMOS transistor is equal to the aspect ratio of the second PMOS transistor, the aspect ratio of the third PMOS transistor, and the width to length ratio of the fourth PMOS transistor;
  • the width to length ratio of the fifth PMOS transistor is equal to a width to length ratio of the sixth PMOS transistor;
  • a width to length ratio of the seventh PMOS transistor is equal to a width to length ratio of the eighth PMOS transistor, a width to length ratio of the ninth PMOS transistor, and a width to length ratio of the tenth PMOS transistor.
  • the embodiment of the present application further provides a charge pump based processing method, the method comprising:
  • the method further includes:
  • a zero point is introduced in the feedback function to perform phase compensation.
  • the differential output voltage of the charge pump is generated by using the input differential control signal, including:
  • the charging current includes: adjusting the charging current generated by the charging current source according to the feedback voltage signal Current.
  • Generating a feedback voltage signal based on the differential output voltage and the common mode bias voltage including:
  • the differential output voltage a voltage to be detected by using a voltage division method; the voltage to be detected is greater than a half of a sum of the differential output voltages;
  • the voltage to be detected and the common mode bias voltage are compared, and a feedback voltage signal is generated according to the comparison result.
  • the embodiment of the present application further provides a phase locked loop circuit, the phase locked loop circuit includes: a frequency discrimination phase detector, a charge pump connected to the phase frequency detector, and a low pass filter connected to the charge pump And a voltage controlled oscillator connected to the low pass filter; wherein
  • the charge pump includes a charge pump main circuit, a common mode feedback circuit, and a voltage bias circuit;
  • the charge pump main circuit is configured to generate a differential output voltage of the charge pump by using the input differential control signal
  • the common mode feedback circuit is configured to generate a feedback voltage signal based on the differential output voltage and a common mode bias voltage provided by the voltage bias circuit, and output the feedback voltage signal to the charge pump main circuit And adjusting a common mode voltage of the differential output generated by the charge pump main circuit based on the feedback voltage signal.
  • the charge pump is specifically any one of the charge pumps described above.
  • the embodiment of the present application further provides a storage medium storing computer executable instructions, and when the computer executable instructions are executed, implementing the charge pump based processing method according to any one of the foregoing aspects.
  • the charge pump, the charge pump-based processing method and the phase-locked loop circuit provided by the embodiment of the present application include: a charge pump main circuit, a common mode feedback circuit, and a voltage bias circuit; and the charge pump main circuit is used for Generating a differential output voltage of the charge pump using the input differential control signal; the common mode feedback circuit for generating a feedback voltage signal based on the differential output voltage and a common mode bias voltage provided by the voltage bias circuit, And outputting the feedback voltage signal to the charge pump main circuit to adjust a common mode voltage of the differential output voltage generated by the charge pump main circuit based on the feedback voltage signal.
  • the charge pump provided by the embodiment of the present application can convert the differential output voltage into a feedback voltage signal to adjust the output differential output voltage based on the feedback voltage signal, thereby ensuring that the charge pump is generated in a low voltage environment. Differential output voltage for stability and matching.
  • FIG. 1 is a schematic structural diagram of a charge pump provided in Embodiment 1 of the present application.
  • FIG. 2 is a schematic diagram showing an implementation flow of a charge pump-based processing method according to Embodiment 1 of the present application;
  • FIG. 3 is a schematic structural diagram of a specific structure of a charge pump according to Embodiment 1 of the present application;
  • FIG. 4 is a schematic structural diagram of a phase locked loop circuit according to Embodiment 2 of the present application.
  • the charge pump 1 is a schematic structural diagram of a charge pump according to Embodiment 1 of the present application.
  • the charge pump 1 includes a charge pump main circuit 11, a common mode feedback circuit 12, and a voltage bias circuit 13;
  • the charge pump main circuit 11 is configured to generate a differential output voltage of the charge pump by using the input differential control signal;
  • the common mode feedback circuit 12 is configured to generate a feedback voltage signal based on the differential output voltage and a common mode bias voltage provided by the voltage bias circuit 13, and output the feedback voltage signal to the charge pump a main circuit to adjust a common mode voltage of a differential output voltage generated by the charge pump main circuit based on the feedback voltage signal.
  • the charge pump main circuit 11 includes a first branch 111, a second branch 112 connected to the first branch 111, and a third branch 113 connected to the second branch 112;
  • the first branch 111 as a discharge current source, is configured to provide a discharge current for the second branch 112;
  • the third branch 113 as a charging current source, is configured to provide a charging current for the second branch 112; and receive a feedback voltage signal output by the common mode feedback circuit 12 to adjust the charging current;
  • the second branch 112 is configured to determine a differential output voltage of the charge pump based on the input differential control signal, the charging current, and the discharging current.
  • the second branch 112 is specifically configured to determine a differential output voltage of the charge pump according to the input differential control signal, the charging current provided by the third branch 113, and the discharge current provided by the first branch 111.
  • the differential output voltage is adjusted based on the input differential control signal, the adjusted charging current provided by the third branch 113, and the discharge current provided by the first branch 111.
  • the second branch 112 adjusts the differential output voltage according to the input differential control signal, the adjusted charging current and the discharging current, in order to realize the charge pump by adjusting the differential output voltage of the charge pump.
  • the differential output voltage is adjusted for the common mode voltage.
  • the common mode feedback circuit 12 includes a fourth branch 121 and a fifth branch 122;
  • the fourth branch 121 is configured to acquire a voltage to be detected by means of a resistor divider according to the differential output voltage; the voltage to be detected is greater than a half of a sum of the differential output voltages;
  • the fifth branch 122 is configured to compare the voltage to be detected and the common mode bias voltage provided by the voltage bias circuit 13, generate a feedback voltage signal according to the comparison result, and output the feedback voltage signal to the The charge pump main circuit 11 is described.
  • the common mode feedback circuit 12 generates a feedback voltage signal by using the common mode bias voltage supplied from the voltage bias circuit 13 as a reference, so that the charge pump main circuit 11 adjusts the differential output voltage according to the feedback voltage signal. To ensure the stability and matching of the differential output voltage.
  • the charge pump 1 further includes a zero point compensation circuit 14 configured to compensate a phase of the common mode feedback circuit 13.
  • the zero point compensation circuit 14 compensates the phase of the common mode feedback circuit 13 by introducing a zero point, which can further improve the stability of the charge pump, that is, further improve the stability of the differential output voltage.
  • FIG. 2 is a schematic flowchart of an implementation process of a charge pump-based processing method according to Embodiment 1 of the present application, where the method includes:
  • Step 101 Generate a differential output voltage of the charge pump by using the input differential control signal
  • Step 102 Generate a feedback voltage signal based on the differential output voltage and the common mode bias voltage.
  • a voltage to be detected is obtained by using a voltage division method; the voltage to be detected is greater than a half of a sum of the differential output voltages; and the voltage to be detected and the common mode offset are compared.
  • the voltage is set, and a feedback voltage signal is generated according to the comparison result.
  • Step 103 Adjust a common mode voltage of the differential output voltage according to the feedback voltage signal.
  • the method further includes:
  • a zero point is introduced in the feedback function to perform phase compensation.
  • charge pump based processing method provided by the embodiment of the present application can be implemented by the above charge pump.
  • the charge pump includes: a first NMOS transistor M1, a second NMOS transistor M2, a first PMOS transistor M3, a second PMOS transistor M4, and a third PMOS.
  • the NMOS transistor M1 and the second NMOS transistor M2 form a first branch
  • the first PMOS transistor M3, the second PMOS transistor M4, the third PMOS transistor M5, and the fourth PMOS transistor M6 form a second branch
  • the sixth PMOS transistor M8 constitutes a third branch, that is, the first NMOS transistor M1, the second NMOS transistor M2, the first PMOS transistor M3, the second PMOS transistor M4, the third PMOS transistor M5, the fourth PM
  • the OS tube M12, the eighth PMOS tube M13, the ninth PMOS tube M14, and the tenth PMOS tube M15 form a fifth branch, that is, the first resistor R1, the second resistor R2, the third resistor R3, and the third NMOS transistor M9
  • the four NMOS transistors M10, the fifth NMOS transistor M11, the seventh PMOS transistor M12, the eighth PMOS transistor M13, the ninth PMOS transistor M14, and the tenth PMOS transistor M15 form a common mode feedback circuit;
  • the fourth resistor R4 and the fifth resistor R5 constitute a voltage bias circuit;
  • a sixth resistor R6 and a capacitor C constitute a zero point compensation circuit;
  • connection relationship in the charge pump shown in Figure 3 is:
  • the gate of the first NMOS transistor M1 is connected to the gate of the second NMOS transistor M2, and the gate of the first NMOS transistor M1 and the gate of the second NMOS transistor M2 are connected to the first voltage source VDD1.
  • the source of the first NMOS transistor M1 and the source of the second NMOS transistor M2 are grounded; the drain of the first NMOS transistor M1 is connected to the drain of the first PMOS transistor M3 and the drain of the third PMOS transistor M5; the second NMOS The drain of the tube M2 is connected to the drain of the second PMOS transistor M4 and the drain of the fourth PMOS transistor M6; the gate of the first PMOS transistor M3 is connected to the first control signal UP, and the source of the first PMOS transistor M3 is connected.
  • the source of the second PMOS transistor M4, and the source of the first PMOS transistor M3 and the source of the second PMOS transistor M4 are connected to the drain of the fifth PMOS transistor M7; the gate of the second PMOS transistor M4 is connected to the second control The signal UPB; the gate of the third PMOS transistor M5 is connected to the third control signal DNB, the source of the third PMOS transistor M5 is connected to the source of the fourth PMOS transistor M6, and the source of the third PMOS transistor M5 and the fourth PMOS
  • the source of the tube M6 is connected to the drain of the sixth PMOS transistor M8; the gate of the fourth PMOS transistor M6 is connected to the fourth control signal DN; the source of the fifth PMOS transistor M7 and the source of the sixth PMOS transistor M8 are connected.
  • Second voltage source VDD2, fifth PMOS transistor M7 The gate is connected to the gate of the sixth PMOS transistor M8; the first control signal UP, the second control signal UPB, the third control signal DNB and the fourth control signal DN are the input differential control signals;
  • the second control signal UPB is a differential signal of the first control signal UP;
  • the fourth control signal DN is a differential signal of the third control signal DNB.
  • one end of the first resistor R1 is connected to the drain of the first NMOS transistor M1, the drain of the first PMOS transistor M3 and the drain of the third PMOS transistor M5, and the other end is connected to the second resistor R2;
  • One end of the two resistor R2 is connected to the drain of the second NMOS transistor M2, the drain of the second PMOS transistor M4 and the drain of the fourth PMOS transistor M6, and the other end is connected to the first resistor R1;
  • one end of the third resistor R3 is connected to the fourth NMOS
  • the gate of the tube M6, the first resistor R1 and the second resistor R2, and the other end is connected to the third voltage source VDD3;
  • the drain of the third NMOS transistor M5 is connected to the source of the fourth NMOS transistor M10 and the source of the fifth NMOS transistor M11
  • the gate of the third NMOS transistor M9 is connected to the first voltage source VDD1, the source of the third NMOS transistor M9 is grounded; the gate of the
  • the gate of the nine PMOS transistor M14, the drain of the tenth PMOS transistor M15 is connected to the gate of the tenth PMOS transistor M15, the gate of the ninth PMOS transistor M14, the drain of the eighth PMOS transistor M13, and the fifth NMOS transistor M11.
  • the source of the PMOS transistor M15 is connected to the second voltage source VDD2.
  • one end of the fourth resistor R4 is connected to the gate of the fifth NMOS transistor M11 and the fifth resistor R5, and the other end is connected to the fourth voltage source VDD4; one end of the fifth resistor R5 is connected to the gate of the fifth NMOS transistor M11.
  • the pole and the fourth resistor R4 are grounded at the other end.
  • one end of the sixth resistor R6 is connected to the gate of the fourth NMOS transistor M10, the first resistor R1, the second resistor R2, and the third resistor R3, and the other end is connected to the capacitor C; one end of the capacitor C is connected to the sixth resistor. R6, the other end is grounded.
  • the main circuit of the charge pump composed of M8 is a completely symmetrical structure.
  • the charge pump main circuit converts the charge and discharge signals outputted by the PFD into a charge and discharge current to the charge pump output capacitor, and then converts it into a voltage signal through the LPF, thereby performing LCVCO on the LCVCO.
  • the first branch formed by the first NMOS transistor M1 and the second NMOS transistor M2 acts as a discharge current source under the action of the first voltage source VDD1 Providing a pull-down current for the charge pump, that is, providing a discharge current by the second branch formed by the first PMOS transistor M3, the second PMOS transistor M4, the third PMOS transistor M5, and the fourth PMOS transistor M6; the first PMOS transistor M3, The second PMOS transistor M4, the third PMOS transistor M5, and the fourth PMOS transistor M6 serve as input terminals of the charge pump, and are connected to the charge and discharge control signals of the PFD output; however, it should be noted that the width to length ratio of the first NMOS transistor M1 should be Equal to the aspect ratio of the second NMOS transistor M2, the aspect ratio of the first PMOS transistor M3 and the second P The width-to-length ratio of the MOS transistor is equal to the width-to-length ratio of the third PMOS transistor
  • the differential signals UPB and DNB of the UP and DN respectively control the second PMOS transistor M4 and the third PMOS transistor M5, and the drains of the second PMOS transistor M4 and the third PMOS transistor M5 are cross-connected to the output nodes of VOUTP and VOUTN.
  • the charging and discharging speed is fully accelerated during charging and discharging.
  • the first control signal UP is the charging control signal
  • the fourth control signal DN is the discharging control signal
  • the second control signal UPB is the differential signal of the first control signal UP
  • the third control signal DNB is the first
  • the differential signal of the four control signals DN is taken as an example for description.
  • the common mode feedback circuit formed by the PMOS transistor M14 and the tenth PMOS transistor M15 provides a stable common mode operating point for the charge pump, ensuring the stability of the charge pump operation.
  • the resistance of the first resistor R1 should be equal to the resistance of the second resistor R2; the magnitude of the third voltage source VDD3 may need to be based on actual conditions such as the resistance of the first resistor R1 and the charge pump output common mode voltage VCMOUT.
  • the width to length ratio of the third NMOS transistor M9 is equal to the width to length ratio of the first NMOS transistor M1; the aspect ratio of the seventh PMOS transistor M12 to the width to length ratio of the eighth PMOS transistor, and the ninth PMOS
  • the width to length ratio of the tube and the width to length ratio of the tenth PMOS transistor are equal;
  • the width to length ratio of the fourth NMOS transistor M10 is equal to the width to length ratio of the fifth NMOS transistor M11;
  • the third NMOS transistor M9 forms a mirror image relationship with the first NMOS transistor M1.
  • the width and length ratios of the two are equal, and N times mirroring is achieved by finger or M.
  • the resistance of the fourth resistor R4 and the resistance of the fifth resistor R5 may be equal or not equal; the third voltage source VDD3 and the fourth voltage source VDD4 may be the same voltage source or different voltages.
  • the source that is, the voltages provided by the third voltage source VDD3 and the fourth voltage source VDD4 may be the same or different; in practical applications, the third voltage source VDD3 and the appropriate size may be selected according to actual needs.
  • the charge pump output common mode voltage VCMOUT remains stable, so that the input voltage VCM of the gate of the fourth NMOS transistor M10 is equal to the fifth NMOS transistor M11.
  • the input voltage VB of the gate is the common mode bias voltage provided by the voltage bias circuit.
  • the feedback voltage signal VFB generated by the common mode feedback circuit does not adjust the output of the fifth PMOS transistor M7 and the sixth PMOS transistor M8.
  • the charging current that is, maintains the balance between the differential output voltages VOUTP and VOUTN; when the differential output voltages VOUTP and VOUTN change due to changes in UP and DN, the fourth NMOS transistor is caused by the differential output voltages VOUTP and VOUTN.
  • the input voltage VCM of the gate of M10 changes, and the input voltage VB of the gate of the fifth NMOS transistor M11 is stable, which will cause the input voltage VCM of the gate of the fourth NMOS transistor M10 and the fifth NMOS transistor.
  • the imbalance between the input voltage VB of the gate of M11 causes the common mode feedback circuit to output the VCM change to the charge pump main circuit through the feedback voltage signal VFB, so that the charge pump main circuit adjusts the fifth PMOS transistor M7, sixth.
  • PMOS M8 charging current changing the differential output voltage VOUTP, VOUTN, to re-enable gate input of the fourth NMOS transistor M10 is equal to the gate voltage VCM fifth NMOS transistor M11 of the input voltage VB
  • the first NMOS transistor M1, the second NMOS transistor M2, the first PMOS transistor M3, the second PMOS transistor M4, the third PMOS transistor M5, the fourth PMOS transistor M6, the fifth PMOS transistor M7, and the sixth PMOS transistor The charge pump main circuit composed of M8 converts the differential input control signal pair UP and UPB, DN and DNB into differential output signals VOUTP and VOUTN, and the first resistor R1, the second resistor R2, the third resistor R3, and the third NMOS transistor M9.
  • the common mode feedback circuit formed by the fourth NMOS transistor M10, the fifth NMOS transistor M11, the seventh PMOS transistor M12, the eighth PMOS transistor M13, the ninth PMOS transistor M14, and the tenth PMOS transistor M15 is obtained according to the differential output signals VOUTP and VOUTN.
  • the detection voltage is the input voltage VCM of the gate of the fourth NMOS transistor M10, and the change of the VCM is converted into the feedback voltage signal VFB and fed back to the main circuit of the charge pump for common mode adjustment, so that the differential output signal has high stability. It also has a good match.
  • the charge pump provided in this embodiment can be applied to an integrated circuit such as a phase locked loop circuit, a clock data recovery circuit, a memory circuit read/write circuit, or the like.
  • phase-locked loop circuit includes: a charge pump 1, a phase frequency detector, a low-pass filter 3, and a voltage-controlled oscillator 4; ,
  • the phase frequency detector 2 is configured to compare the input reference signal with the output signal of the voltage controlled oscillator 4 to generate a comparison result
  • the charge pump 1 is configured to adjust an output voltage according to a comparison result of the phase frequency detector 2;
  • the low pass filter 3 is configured to filter an output voltage of the charge pump 1;
  • the voltage controlled oscillator 4 is configured to adjust the frequency of the output signal in accordance with the output voltage filtered by the low pass filter 3.
  • the phase-locked loop circuit shown in FIG. 4 operates on the principle that when the phase frequency detector 2 detects that the frequency of the output signal of the voltage-controlled oscillator 4 is less than the frequency of the reference signal, The charge pump 1 raises an output voltage of the charge pump 1, and the output voltage is filtered by the low-pass filter 3 to output a DC voltage portion, and the frequency of the output signal of the voltage controlled oscillator 4 is at the rise The frequency of the output signal is increased under the control of the high voltage.
  • the charge pump 1 lowers the output voltage of the charge pump 1, after After filtering, the voltage controlled oscillator 4 reduces the frequency of the output signal according to the reduced voltage; after repeated adjustments until the frequency of the output signal of the voltage controlled oscillator 4 is equal to the frequency of the reference signal, the voltage control The output signal of the oscillator 4 is locked.
  • the output signal of the voltage controlled oscillator 4 may be a signal obtained by dividing a signal output by the voltage controlled oscillator 4
  • the charge pump 1 may be any one of the above-described first embodiment.
  • a storage medium provided by an embodiment of the present application stores a computer executable instruction, and when the computer executable instruction is executed, the charge pump based processing method according to any one of the above embodiments is implemented.
  • the charge pump can ensure the high stability of the charge pump in a low voltage environment by converting the differential output voltage into a feedback voltage signal to adjust the output differential output voltage based on the feedback voltage signal. And matching differential output voltage.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

L'invention concerne une pompe de charge (1), un procédé de traitement et un circuit bouclé à verrouillage de phase basés sur la pompe de charge, et un support de stockage. La pompe de charge comprend un circuit principal de pompe de charge (11), un circuit de rétroaction en mode commun (12) et un circuit de polarisation de tension (13). Le circuit principal de pompe de charge génère une tension de sortie différentielle de la pompe de charge au moyen d'un signal de commande différentiel d'entrée. Le circuit de rétroaction en mode commun génère un signal de tension de rétroaction sur la base de la tension de sortie différentielle et d'une tension de polarisation en mode commun fournie par le circuit de polarisation de tension, et délivre le signal de tension de rétroaction au circuit principal de pompe de charge, de manière à régler la tension en mode commun de la tension de sortie différentielle générée par le circuit principal de pompe de charge sur la base du signal de tension de rétroaction. La pompe de charge peut générer une tension de sortie différentielle ayant une stabilité élevée et une propriété d'adaptation élevée dans un environnement basse tension.
PCT/CN2018/080067 2017-03-28 2018-03-22 Pompe de charge, procédé de traitement et circuit bouclé à verrouillage de phase basés sur la pompe de charge, et support de stockage WO2018177195A1 (fr)

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CN201710194256.4A CN108667456A (zh) 2017-03-28 2017-03-28 一种电荷泵、基于电荷泵的处理方法及锁相环电路

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CN110943738B (zh) * 2019-10-15 2023-05-26 芯创智（北京）微电子有限公司 一种输出时钟共模电压可调的电感电容压控振荡器

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW531965B (en) * 2001-12-07 2003-05-11 Mediatek Inc Differential charge pump
CN104201880A (zh) * 2014-07-15 2014-12-10 浙江大学 用于锁相环低电压下抗工艺涨落的低电流失配电荷泵电路
CN104811189A (zh) * 2015-05-14 2015-07-29 东南大学 一种电荷泵锁相环中的电荷泵电路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201515362U (zh) * 2009-09-11 2010-06-23 安凯(广州)微电子技术有限公司 一种锁相环泄漏电流补偿电路及锁相环电路
CN103166627B (zh) * 2013-04-03 2016-08-03 中国科学院微电子研究所 一种带有共模反馈的低电压差分信号驱动器
CN104796136B (zh) * 2014-01-17 2018-01-26 苏州芯动科技有限公司 锁相环时钟数据恢复器用电荷泵装置
CN104993817B (zh) * 2015-08-12 2017-12-19 电子科技大学 一种用于电荷泵锁相环的快速启动电路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW531965B (en) * 2001-12-07 2003-05-11 Mediatek Inc Differential charge pump
CN104201880A (zh) * 2014-07-15 2014-12-10 浙江大学 用于锁相环低电压下抗工艺涨落的低电流失配电荷泵电路
CN104811189A (zh) * 2015-05-14 2015-07-29 东南大学 一种电荷泵锁相环中的电荷泵电路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HUANG, SHUI LONG ET AL.: "Design of an improved high performance differential charge pump", CHINESE JOURNAL OF ELECTRON DEVICES, vol. 29, no. 4, 31 December 2006 (2006-12-31), pages 1054 - 1055, ISSN: 1005-9490 *

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