+

WO2018174267A1 - Circuit d'attaque de charge, système l'utilisant, et procédé de commande de circuit d'attaque - Google Patents

Circuit d'attaque de charge, système l'utilisant, et procédé de commande de circuit d'attaque Download PDF

Info

Publication number
WO2018174267A1
WO2018174267A1 PCT/JP2018/011851 JP2018011851W WO2018174267A1 WO 2018174267 A1 WO2018174267 A1 WO 2018174267A1 JP 2018011851 W JP2018011851 W JP 2018011851W WO 2018174267 A1 WO2018174267 A1 WO 2018174267A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
control input
state
drive circuit
bridge circuit
Prior art date
Application number
PCT/JP2018/011851
Other languages
English (en)
Japanese (ja)
Inventor
裕樹 菅本
Original Assignee
ローム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2018054900A external-priority patent/JP7228335B2/ja
Application filed by ローム株式会社 filed Critical ローム株式会社
Priority to CN201880020633.5A priority Critical patent/CN110476349B/zh
Publication of WO2018174267A1 publication Critical patent/WO2018174267A1/fr
Priority to US16/580,303 priority patent/US10992244B2/en

Links

Images

Definitions

  • the present invention relates to a drive circuit for driving a load such as a motor.
  • FIG. 1 is a block diagram of a DC motor drive circuit.
  • the drive circuit 100R includes a logic circuit 110, a pre-driver 120, and an H bridge circuit 130.
  • the drive target motor 202 is connected to the output terminals (pins) OUTA and OUTB of the drive circuit 100R.
  • Driving circuit 100R receives the control instruction S 1 from an external controller 204 drives the motor 202 in response to the control instruction S 1.
  • control instruction S 1 is the torque command and speed command, rather than such position command includes data indicating the state of the H-bridge circuit 130.
  • the H bridge circuit 130 can take four states ⁇ 1 to ⁇ 4 .
  • H represents a high voltage
  • L represents a low voltage
  • Z represents a high impedance state.
  • ⁇ 1 OUTA Z
  • OUTB L ⁇ 3
  • OUTA L
  • OUTB H
  • OUTB H
  • OUTA L
  • the drive circuit 100R includes, in addition to the two output pins OUTA and OUTB, a power supply pin VM and a ground pin PGND of the H bridge circuit 130, a power supply pin VCC for the previous circuit (110 and 120), and a ground pin GND. If you want to accommodate the drive circuit 100R in 8-pin package, the reception of the control command S CNT from the controller 204, two control pins INA, it is possible to assign the INB. When each control pin can be controlled in the high and low 2 states, the four states ⁇ 1 to ⁇ 4 can be switched using the two control pins INA and INB.
  • a general IC includes an enable pin, and is configured to shift to a standby mode by setting the enable pin to a predetermined state.
  • the present invention has been made in view of these problems, and one of the exemplary purposes of an aspect thereof is to provide a drive circuit that can be set to a standby mode without increasing the number of pins.
  • the drive circuit has an H bridge circuit, one or two control input pins for receiving one or two control input signals indicating the state of the H bridge circuit from the outside, and one or two control input signals. And a logic circuit that generates an internal signal that indicates the state of the transistors that constitute the H-bridge circuit, and a pre-driver that drives the H-bridge circuit based on the internal signal.
  • the drive circuit shifts to the standby mode when one or two control input signals maintain a predetermined state for a predetermined determination time.
  • the predetermined state may correspond to a high impedance state of the H bridge circuit.
  • the predetermined state may correspond to a short brake state of the H bridge circuit.
  • the determination time may be longer than 50 ⁇ s.
  • the state of the control input pin changes in the PWM cycle.
  • the state of the control input pin changes with the frequency (cycle) of the control pulse that defines the rotation speed.
  • the PWM frequency and the frequency of the control pulse are set outside the audio band, that is, 20 kHz or more. Therefore, by defining the determination time longer than 50 ⁇ s, it is possible to distinguish between an intentional transition instruction to the standby state and a specific state during PWM drive or stepping motor control.
  • the control method includes a step in which the processor changes one or two control input signals that specify the state of the H-bridge circuit in a time shorter than a predetermined period in order to rotate the motor, and one or two controls. Controlling the H-bridge circuit in response to the input signal; and fixing the one or two control input signals to a predetermined state for a predetermined time in order for the processor to shift the drive circuit to a standby mode; A step of transitioning the drive circuit to a standby mode when it is detected that one or two control input signals have maintained the predetermined state for a predetermined time in the drive circuit.
  • FIG. 1 is a circuit diagram of a system including a drive circuit according to a first embodiment.
  • FIG. 3 is a diagram illustrating an example of correspondence between states of control input pins INA and INB, and internal and output states of the drive circuit in the drive circuit of FIG. 2.
  • FIG. 3 is an operation waveform diagram of the drive circuit of FIG. 2.
  • It is a circuit diagram of a system provided with the drive circuit which concerns on 2nd Example.
  • FIGS. 7A to 7C are diagrams showing some examples of correspondence between the state of the control input pin IN in the drive circuit of FIG. 6 and the internal and output states of the drive circuit.
  • FIG. 9 is a circuit diagram of the system which concerns on 4th Example. It is a circuit diagram of a system provided with the drive circuit which concerns on 5th Example. 10 is a time chart showing an example of the operation of the system of FIG. 9.
  • 14 is a circuit diagram of a drive circuit according to Modification 4.
  • FIG. 14 is a circuit diagram of a drive circuit according to Modification 4.
  • FIG. 10 is a circuit diagram of a system including a drive circuit according to Modification Example 5.
  • FIGS. 14A to 14H are views showing the appearance of the package of the drive circuit.
  • the state in which the member A is connected to the member B means that the member A and the member B are electrically connected to each other in addition to the case where the member A and the member B are physically directly connected. It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.
  • the state in which the member C is provided between the member A and the member B refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as their electric It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.
  • FIG. 2 is a circuit diagram of a system 200 including the drive circuit 100 according to the first embodiment.
  • the drive circuit 100 includes two control input pins INA and INB, and two control input signals are supplied from the external controller 204 to the control input pins INA and INB.
  • the drive circuit 100 drives a load (for example, the motor 202) connected to the two output terminals OUTA and OUTB according to the two control input signals INA and INB.
  • the drive circuit 100 includes a logic circuit 110, a pre-driver 120, an H bridge circuit 130, a BGR (bandgap reference) circuit 140, a protection circuit 150, and a standby circuit 160, and is accommodated in one package.
  • the drive circuit 100 may be a functional IC integrated on one semiconductor substrate.
  • the H bridge circuit 130 may be integrated on a separate chip from the other blocks (110, 120, 140, 150, 160).
  • the H bridge circuit 130 can take four states ⁇ 1 to ⁇ 4 according to the control input pins INA and INB.
  • the logic circuit 110 monitors the states (control input signals) of the control input pins INA and INB, and determines which of the states ⁇ 1 to ⁇ 4 is in effect. Then, an internal signal S INT corresponding to the determined state is generated.
  • the internal signal S INT may be a signal instructing on / off of each of the four transistors M1 to M4 constituting the H-bridge circuit 130.
  • the pre-driver 120 controls the gate voltages of the transistors M1 to M4 of the H bridge circuit 130 based on the internal signal S INT .
  • the BGR circuit 140 generates a reference voltage.
  • the protection circuit 150 includes a thermal shutdown (TSD) circuit, an undervoltage lockout (UVLO) circuit, and the like.
  • TSD thermal shutdown
  • UVLO undervoltage lockout
  • the protection circuit 150 includes a voltage comparator.
  • the standby circuit 160 shifts the drive circuit 100 to the standby mode when the two control input signals INA and INB maintain the predetermined state ⁇ for the predetermined determination time ⁇ .
  • the standby mode supply of the bias current, bias voltage, and power supply voltage to other circuit blocks other than the logic circuit 110 is stopped, and the current consumption of the drive circuit 100 is reduced to a level of several ⁇ A.
  • the standby circuit 160 is shown outside the logic circuit 110, but the function of the standby circuit 160 can actually be implemented as a part of the logic circuit 110.
  • FIG. 3 is a diagram showing an example of the correspondence between the states of the control input pins INA and INB and the internal and output states of the drive circuit 100.
  • the predetermined state ⁇ is the high impedance state ⁇ 1 of the H bridge circuit 130.
  • Standby circuit 160 measures the time that the logic circuit 110 detects a high impedance state phi 1, reaches the determination time tau, to shift the driving circuit 100 to the standby mode.
  • the determination time ⁇ is preferably defined to be longer than 50 ⁇ s, for example, set between 50 and 500 ⁇ s.
  • FIG. 4 is an operation waveform diagram of the drive circuit 100 of FIG.
  • the power supply voltage VCC and VM stand up to time t 0.
  • the standby mode is set, and the operating current I CC is very small.
  • the control input signal INA the INB changes, the transition to the normal mode.
  • the state transitions sequentially to the states ⁇ 3 , ⁇ 4 , and ⁇ 2 corresponding to the levels of the control input signals INA and INB.
  • the output is high impedance.
  • the state ⁇ 4 continues for the determination time ⁇ at time t 3 , the standby mode is entered and the operating current I CC decreases.
  • the state transitions sequentially to states ⁇ 2 , ⁇ 3 , ⁇ 2 , and ⁇ 3 corresponding to the levels of the control input signals INA and INB.
  • Supply voltage V CC is below the threshold UVLO circuit at time t 5, becomes undervoltage lockout, the output of the H-bridge circuit 130 becomes a high impedance.
  • the four states of the H-bridge circuit 130 are controlled from the outside by using only the two control input pins INA and INB without adding an enable pin, and further shifted to the standby mode. Can do.
  • a torque command (speed command) of zero is understood as an explicit instruction to stop the motor. Therefore, after waiting for the time required for the motor to completely stop after the torque command (speed command) becomes zero, it is sufficient to shift to the standby mode.
  • the drive circuit 100 supports pulse driving with a cycle shorter than the determination time ⁇ .
  • the controller 204 by switching alternately shorter than the determination time ⁇ period, while the motor 202 is stopped, without migrating the driving circuit 100 in the standby mode It is also possible to continue to maintain the normal mode. Such control cannot be realized by a drive circuit that receives a torque command or a speed command.
  • the bias circuit stops, so it takes a few ⁇ s to return to normal mode.
  • PWM drive there is a case where the output voltage of the H bridge circuit is desired to be changed at a slew rate of several tens ns. If control that shifts to standby immediately when a high-impedance control input is detected, the rounding of the waveform of the output voltage of the H-bridge circuit during PWM driving becomes large, and the usable applications are limited. In the embodiment, since the waveform of the output voltage of the H-bridge circuit does not occur, it can be applied to a wide range of applications.
  • FIG. 5 is a circuit diagram of a system 200A including a drive circuit 100A according to the second embodiment.
  • the drive circuit 100A includes a PWM (Pulse Width Modulation) circuit 170 for switching the drive signal during the energization period to the motor.
  • a shunt resistor Rs is provided on the path of the drive current, specifically between the PGND pin and the external ground, and a voltage drop (current detection signal) Vs corresponding to the drive current flowing through the motor 202 is provided in the shunt resistor Rs. Will occur.
  • the shunt resistor Rs may be built in the drive circuit 100A.
  • the PWM circuit 170 is a pulse-by-pulse current limiting circuit, and generates the PWM signal S PWM based on the current detection signal Vs.
  • the PWM circuit 170 operates in synchronization with the clock generated by the oscillator 172.
  • the PWM circuit 170 changes the PWM signal S PWM to the first level (for example, high) in response to the positive edge of the clock CK generated by the oscillator 172.
  • the PWM circuit 170 compares the current detection signal Vs with a limit value V CL that defines the upper limit of the drive current, and detects V S > V CL , that is, when the drive current reaches the limit value, the PWM signal S PWM To the second level (eg, low).
  • the PWM signal S PWM is supplied to the pre-driver 120.
  • the pre-driver 120 logically synthesizes the PWM signal S PWM with the internal signal S INT and controls the H bridge circuit 130.
  • the logic synthesis function may be implemented in the logic circuit 110.
  • the standby circuit 160 may stop the PWM circuit 170 in the standby state. Specifically, current consumption can be reduced by cutting off the current of the comparator included in the PWM circuit 170. Further, the oscillator 172 that generates the clock CK may be stopped in the standby state. This can further reduce current consumption.
  • FIG. 6 is a circuit diagram of a system 200B including a drive circuit 100B according to the third embodiment.
  • the drive circuit 100B includes one control pin IN.
  • a high / low binary control input signal IN is input to the control pin IN.
  • the logic circuit 110 transitions the state of the bridge circuit 130 in response to the transition of the state of the control input pin IN. Further, when the control input pin IN remains in a predetermined state for a predetermined time, the standby circuit 160 shifts the drive circuit 100B to the standby state.
  • FIGS. 7A to 7C are diagrams showing some examples of the correspondence between the state of the control input pin IN in the drive circuit 100B of FIG. 6 and the internal and output states of the drive circuit.
  • the H bridge circuit 130 can take two states ⁇ 1 and ⁇ 2 according to the control input pin IN.
  • ⁇ 1 OUT1 L
  • OUT2 H
  • ⁇ 2 OUT1 H
  • OUT2 L
  • the logic circuit 110 monitors the state (control input signal) of the control input pin IN, and determines whether the state is ⁇ 1 or ⁇ 2 . Then, an internal signal S INT corresponding to the determined state is generated.
  • the standby circuit 160 shifts the drive circuit 100B to the standby mode when the first state ⁇ 1 (that is, the IN pin is low) lasts for a predetermined time.
  • the logic circuit 110 changes the internal signal S INT so that the H bridge circuit 130 is in a state ⁇ s (short brake state) different from the first state ⁇ 1 and the second state ⁇ 3 .
  • the motor 202 can be fixed in the standby mode.
  • ⁇ s may be in a high impedance state.
  • FIG. 8 is a circuit diagram of a system 200C according to the fourth embodiment.
  • the system 200C includes two drive circuits 100B shown in FIG.
  • the output of one drive circuit 100B_A is connected to one coil of the stepping motor 202C, and the output of the other drive circuit 100B_B is connected to the other coil of the stepping motor 202C.
  • the controller 204 controls the stepping motor 202C by supplying the control input signal INA to the drive circuit 100B_A and the control input signal INB to the drive circuit 100B_B.
  • the waveforms of the control input signals INA and INB are selected according to the driving method of the stepping motor (one-phase example, 1-2-phase excitation, 2-phase excitation, etc.).
  • FIG. 9 is a circuit diagram of a system 200D including a drive circuit 100D according to the fifth embodiment.
  • the drive circuit 100D can be understood as a circuit in which the drive circuits 100B_A and 100B_B in FIG. 8 are integrated.
  • the outputs OUTA and OUTB can take four states ⁇ 11 to ⁇ 14 depending on the combination of INA and INB.
  • INA L
  • OUTA2 H
  • OUTB1 L
  • OUTB2 H ⁇ ⁇ 12
  • OUTA2 L
  • OUTB1 L
  • OUTB2 H ⁇ ⁇ 13
  • OUTA2 H
  • OUTB1 H
  • OUTA2 L
  • FIG. 10 is a time chart showing an example of the operation of the system 200D of FIG.
  • 1-2 phase excitation is taken as an example.
  • the standby circuit 160 of the drive circuit 100D monitors all edges of the two control input signals INA and INB. When the edge interval exceeds a predetermined determination time ⁇ , the standby mode is entered. In other words, when any one of the four states ⁇ 11 to ⁇ 14 is maintained for a predetermined time, the standby mode is entered.
  • the bridge circuits 130A and 130B are fixed to a predetermined state ⁇ s (for example, a high impedance state or a short brake state). Alternatively, the predetermined state ⁇ s may be the immediately preceding state ( ⁇ 13 in the example of FIG. 10).
  • the standby mode is canceled, and then the state transitions to the states ⁇ 11 and ⁇ 12 corresponding to the two control inputs INA and INB.
  • Modification 2 In the embodiment, a single-phase DC motor is used as a load.
  • the present invention is also applicable to a three-phase inverter and a stepping motor drive circuit.
  • the load is not limited to the motor, and the drive circuit 100 may be a part of a flyback converter, a forward converter, a DC / DC converter, or the like.
  • FIG. 11 is a circuit diagram of a drive circuit 100E according to the fourth modification.
  • the drive circuit 100E has two power supply pins common to the drive circuit 100 of FIG. 2, and two ground pins.
  • FIG. 12 is a circuit diagram of the drive circuit 100F according to the fourth modification.
  • the drive circuit 100F is obtained by sharing the two power pins of the drive circuit 100B of FIG. 6 and sharing the two ground pins.
  • FIG. 13 is a circuit diagram of a system 200G including a drive circuit 100G according to Modification 5.
  • the drive circuit 100G includes a half-bridge circuit 130G at its output stage instead of the H-bridge circuit 130.
  • the output pin of the half bridge circuit 130G is connected to one end of a motor 130G (coil), and a predetermined voltage (power supply voltage or ground voltage) is applied to the other end of the motor 130G.
  • FIG. 14A to 14H are views showing the appearance of the package of the drive circuit 100.
  • FIG. FIG. 14A shows an 8-pin package.
  • the drive circuit 100 of FIG. 2 can be accommodated in this package.
  • Each pin of the drive circuit 100 in FIG. 2 may be arranged as follows. Name Pin number VM 2 PGND 8 VCC 4 GND 5 INA 3 INB 6 OUTA 1 OUTB 7
  • FIG. 14B shows a 6-pin package.
  • the drive circuit 100E of FIG. 11 can be accommodated in this package.
  • Each pin of the drive circuit 100E of FIG. 11 may be arranged as follows. Name Pin No. VCC 2 GND 5 INA 3 INB 4 OUTA 1 OUTB 6
  • FIG. 14C shows a 5-pin package.
  • the drive circuit 100F of FIG. 12 can be accommodated in this package.
  • Each pin of the drive circuit 100F may be arranged as follows. Name Pin number VM 5 PGND 2 IN 4 OUTA 1 OUTB 3
  • FIG. 14 (d) shows a 4-pin package.
  • the drive circuit 100G of FIG. 13 can be accommodated in this package.
  • Each pin of the drive circuit 100G may be arranged as follows. Name Pin No. VCC 1 GND 2 IN 3 OUT 4
  • FIGS. 14E to 14F show 8-pin, 6-pin, 5-pin, and 4-pin CSP (Chip Size Package).
  • the present invention can be used for motor driving technology.

Landscapes

  • Control Of Stepping Motors (AREA)

Abstract

Selon l'invention, deux broches d'entrée de commande INA, INB reçoivent, de l'extérieur, deux signaux d'entrée de commande. Un circuit logique (110), correspondant aux deux signaux d'entrée de commande INA, INB, génère un signal interne S INT qui commande l'état d'un circuit en pont H 130. Un pré-circuit d'attaque 120 attaque le circuit en pont H 130 sur la base du signal interne S INT. Lorsque les deux signaux d'entrée de commande INA, INB sont maintenus dans un état prédéterminé pendant un temps de détermination prédéterminé, un circuit de mise en veille 160 décale un circuit d'attaque 100 pour que celui-ci se mette en mode veille.
PCT/JP2018/011851 2017-03-24 2018-03-23 Circuit d'attaque de charge, système l'utilisant, et procédé de commande de circuit d'attaque WO2018174267A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201880020633.5A CN110476349B (zh) 2017-03-24 2018-03-23 负载的驱动电路、使用该驱动电路的系统、驱动电路的控制方法
US16/580,303 US10992244B2 (en) 2017-03-24 2019-09-24 Load driving circuit

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2017-059452 2017-03-24
JP2017059452 2017-03-24
JP2018-054900 2018-03-22
JP2018054900A JP7228335B2 (ja) 2017-03-24 2018-03-22 負荷の駆動回路、それを用いたシステム、駆動回路の制御方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/580,303 Continuation US10992244B2 (en) 2017-03-24 2019-09-24 Load driving circuit

Publications (1)

Publication Number Publication Date
WO2018174267A1 true WO2018174267A1 (fr) 2018-09-27

Family

ID=63585490

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2018/011851 WO2018174267A1 (fr) 2017-03-24 2018-03-23 Circuit d'attaque de charge, système l'utilisant, et procédé de commande de circuit d'attaque

Country Status (1)

Country Link
WO (1) WO2018174267A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0614587A (ja) * 1992-06-29 1994-01-21 Toshiba Corp 高負荷ドライブ回路
JP2008263733A (ja) * 2007-04-12 2008-10-30 Rohm Co Ltd モータ駆動装置、ロック保護方法およびそれを用いた冷却装置
JP2012065470A (ja) * 2010-09-16 2012-03-29 On Semiconductor Trading Ltd モータ駆動回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0614587A (ja) * 1992-06-29 1994-01-21 Toshiba Corp 高負荷ドライブ回路
JP2008263733A (ja) * 2007-04-12 2008-10-30 Rohm Co Ltd モータ駆動装置、ロック保護方法およびそれを用いた冷却装置
JP2012065470A (ja) * 2010-09-16 2012-03-29 On Semiconductor Trading Ltd モータ駆動回路

Similar Documents

Publication Publication Date Title
JP2018164253A (ja) 負荷の駆動回路、それを用いたシステム、駆動回路の制御方法
JP3890906B2 (ja) ブラシレスモータの駆動装置およびそれを使用するモータ
US8669790B2 (en) Control circuit arrangement for pulse-width modulated DC/DC converters and method for controlling a pulse-width modulated converter
US7402975B2 (en) Motor drive device and drive method
JP4486888B2 (ja) モータ駆動装置
JP2008043171A (ja) 負荷駆動装置及びこれを用いた電気機器
JP5345764B2 (ja) モータ制御用マイクロコンピュータ及びその制御方法
JP5337533B2 (ja) モータ駆動回路
TWI699961B (zh) 馬達驅動電路及方法
WO2005085879A1 (fr) Stockage, entrainement de charge, circuit de detection de courant
JP4001562B2 (ja) モータ及びディスク装置
US10594238B2 (en) Driving circuit for stepping motor
JP7144190B2 (ja) ステッピングモータの駆動回路、それを用いたシステム
WO2018174267A1 (fr) Circuit d'attaque de charge, système l'utilisant, et procédé de commande de circuit d'attaque
JP5650399B2 (ja) 加減速検出回路
JPWO2005067136A1 (ja) 電流制限回路およびモータドライブ回路
JP3874290B2 (ja) モータ駆動装置
JP7129366B2 (ja) スイッチング電源装置
TWI424677B (zh) 啟動電路及馬達驅動晶片
JP5399085B2 (ja) ブラシレスモータの駆動回路、モータユニット、ならびにそれを用いた電子機器
JP4034278B2 (ja) 電流検出回路、負荷駆動回路、及び記憶装置
TW202218313A (zh) 三相馬達驅動電路及方法
JP6117389B1 (ja) モータ駆動装置
CN101562419B (zh) 马达的驱动装置及方法
JP4248619B2 (ja) モータ駆動回路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18770917

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18770917

Country of ref document: EP

Kind code of ref document: A1

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载