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WO2018171099A1 - Procédé d'encapsulation pour structure d'encapsulation à puce de transmission de puissance intégrée - Google Patents

Procédé d'encapsulation pour structure d'encapsulation à puce de transmission de puissance intégrée Download PDF

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Publication number
WO2018171099A1
WO2018171099A1 PCT/CN2017/095406 CN2017095406W WO2018171099A1 WO 2018171099 A1 WO2018171099 A1 WO 2018171099A1 CN 2017095406 W CN2017095406 W CN 2017095406W WO 2018171099 A1 WO2018171099 A1 WO 2018171099A1
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Prior art keywords
chip
power transmission
power
layer
transmission chip
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PCT/CN2017/095406
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English (en)
Chinese (zh)
Inventor
林章申
林正忠
何志宏
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中芯长电半导体（江阴）有限公司
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Publication of WO2018171099A1 publication Critical patent/WO2018171099A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Definitions

  • the invention belongs to the technical field of semiconductor packaging, and relates to a packaging method of a package structure integrated with a power transmission chip.
  • Power transfer systems are required for all computing and communication systems.
  • the power transfer system converts the high voltage of the power supply into many different low voltages required for discrete devices in the system.
  • the efficiency of the power transfer system determines the power loss of the down-conversion, and the number of power transfer rails determines the number of discrete voltage supplies or devices that can be supported.
  • adding more power transmission tracks requires copying more power transmission components, which will increase the number of components, increase the size of the board, increase the number of layers of the board, increase the system size, cost and weight.
  • an object of the present invention is to provide a packaging method of a package structure integrated with a power transmission chip for solving the problem of low power transmission efficiency and available voltage of different voltage tracks in the existing power transmission system. Less problem.
  • the present invention provides a packaging method of a package structure integrated with a power transmission chip, the package structure including an electrical chip and a power transmission chip connected under the power chip;
  • the power transmission chip is configured to convert a voltage of the external power source into a plurality of voltages required by the power chip, and provide a plurality of power supply tracks that are connected to the power chip;
  • the packaging method includes the following steps:
  • An active component and a passive component of the power transmission chip are placed on the adhesion layer, wherein the active component and the passive component have one side of the pad in contact with the adhesion layer;
  • a conductive portion of the rewiring layer is connected to the conductive pillar and the pad to achieve the An electrical connection between the active component and the passive component, and providing a plurality of power supply tracks that are connected to the power chip;
  • a plurality of second bump structures connected to the conductive pillars are formed on a surface of the plastic sealing layer on a side opposite to the pads.
  • the voltage of the external power source is higher than the voltage required by the power chip.
  • the active component comprises a controller and a buck converter
  • the passive component comprises a capacitor, an inductor and a resistor.
  • the method further includes filling the gap between the power chip and the wiring layer by using an underfill. a step, and a step of wrapping the surrounding electrical chip with a molding material.
  • the rewiring layer includes a dielectric layer and at least one metal wiring and at least one layer of conductive plugs formed in the dielectric layer; the metal wiring is implemented by the conductive plug An electrical connection of the active component, the passive component, and the conductive pillar, and when a plurality of metal wirings are formed in the dielectric layer, the interlayer electrical connection is realized by the conductive plug between the multiple metal wirings.
  • the first bump structure comprises microbumps.
  • the second bump structure comprises a ball grid array solder ball.
  • the power chip is an application specific integrated circuit.
  • the method of forming the plastic seal layer includes any one or more of compression molding, transfer molding, liquid sealing molding, vacuum lamination, and spin coating.
  • the method of forming the through hole includes any one or more of laser drilling, mechanical drilling, reactive ion etching, and nano imprinting.
  • the method of forming the conductive pillars comprises one or more of electroplating, electroless plating, silk screen printing, wire bonding.
  • the present invention provides a new packaging method in which a three-dimensional chip stacking technology is used to integrate a power chip and a power transfer chip in a package structure, which has the following beneficial effects:
  • the power-on chip may be an Application Specific Integrated Circuit (ASIC).
  • ASIC Application Specific Integrated Circuit
  • the active 2.5D interposer acts as a power transmission power chip, which is tightly integrated under the power chip, solving the problem of power transmission.
  • the power transmission system of the entire system circuit board is implemented by the power transmission chip, which includes a controller, a buck converter, a capacitor (CAP (3T)), and an inductor (L (2T) )) and resistors, thus eliminating all passive components on the system board.
  • the power transmission chip which includes a controller, a buck converter, a capacitor (CAP (3T)), and an inductor (L (2T) )) and resistors, thus eliminating all passive components on the system board.
  • the buck converter in the power transfer chip can generate thousands of low voltage power transmission tracks (power supply tracks) that are connected to the power chips through the micro bumps.
  • the package structure of the present invention can eliminate parasitic resistance on a package substrate such as a PCB due to integration of a power transfer chip including passive components, thereby improving power transmission efficiency and improving response time of power control.
  • FIG. 1 is a process flow diagram showing a packaging method of a package structure integrated with a power transmission chip of the present invention.
  • FIG. 2 is a schematic view showing a carrier for a package method of a package structure integrated with a power transmission chip of the present invention.
  • FIG. 3 is a schematic view showing an encapsulation method of a package structure integrated with a power transmission chip of the present invention forming an adhesion layer on the carrier.
  • FIG. 4 is a schematic diagram showing a packaging method of a power transmission chip-integrated package structure of the present invention, in which an active component and a passive component of the power transmission chip are placed on the adhesion layer.
  • FIG. 5 is a schematic view showing a method of packaging a package structure integrated with a power transmission chip of the present invention to form a plastic seal layer on the adhesion layer.
  • FIG. 6 is a schematic view showing the encapsulation method of the package structure integrated with the power transmission chip of the present invention for removing the carrier and the adhesion layer.
  • FIG. 7 is a schematic view showing a method of packaging a package structure integrated with a power transmission chip of the present invention to form a conductive pillar in the plastic seal layer.
  • FIG. 8 is a schematic view showing a method of packaging a package structure integrated with a power transmission chip of the present invention to form a rewiring layer of the power transmission chip.
  • FIG. 9 shows a packaging method of a package structure integrated with a power transmission chip of the present invention through a plurality of first bump structures
  • the power chip is connected to the rewiring layer, and a schematic diagram of the gap between the power chip and the wiring layer is filled by an underfill.
  • FIG. 10 is a schematic view showing a packaging method of a package structure integrated with a power transmission chip of the present invention, which is wrapped around a periphery of the power chip by a molding material.
  • FIG. 11 is a schematic view showing a packaging method of a package structure integrated with a power transmission chip of the present invention, and forming a plurality of second bump structures connected to the conductive pillars.
  • the invention provides a packaging method of a package structure integrated with a power transmission chip.
  • the package structure includes an electrical chip 5 and a power transmission chip 3 connected under the power chip 5 .
  • the power transmission chip 3 is configured to convert a voltage of an external power source into the power chip. 5 required multiple voltages, and providing a plurality of power supply tracks that are connected to the power chip 5.
  • the packaging method of the present invention utilizes the power transmission chip 3 as an active 2.5D interposer, and integrates the power chip 5 on an active 2.5D interposer through microbumps or other bump structures to obtain a three-dimensional stacked chip structure.
  • the power transmission system of the entire system circuit board is implemented by the power transmission chip, which can eliminate parasitic resistance on the package substrate, thereby improving power transmission efficiency, improving power control response time, and improving fidelity.
  • the power transmission chip includes an active component 301, a passive component 302, a plastic encapsulation layer 304, a conductive pillar 305, and a rewiring layer 306.
  • FIG. 1 is a process flow diagram of a packaging method of a package structure integrated with a power transmission chip according to the present invention, including the following steps:
  • S6 forming a rewiring layer of the power transmission chip on a surface of the plastic sealing layer on the same side as the pad; and electrically connecting the conductive portion of the rewiring layer to the conductive pillar and the pad to realize Electrical connection between the active component and the passive component, and providing a plurality of power supply tracks that are connected to the power chip;
  • step S1 is performed: a carrier 1 is provided, and an adhesion layer 2 is formed on the carrier 1.
  • the material of the carrier may be selected from one or more of glass, silicon, silicon oxide, metal or ceramic, or the like.
  • the carrier 1 may be of a flat type, for example, a glass circular plate having a certain thickness.
  • the adhesive layer 2 functions to adhere and fix the components placed thereon, and when the carrier 1 is subsequently removed, the adhesive layer 2 is also removed.
  • the adhesive layer 2 may be a UV tape or a thermal material, wherein the UV tape may have a reduced adhesive strength under illumination of a specific wavelength, so that the carrier is easily peeled off. When the hot material is heated at a certain temperature, the adhesion strength is lowered, so that the carrier is easily peeled off.
  • the adhesive layer 2 can also be combined with a UV adhesive and a thermal material.
  • step S2 is performed to place the active component 301 and the passive component 302 of the power transmission chip 3 on the adhesion layer 2, wherein the active component 301 and the passive component 302 One side having the pad 303 is in contact with the adhesion layer.
  • one side of the active element 301 having the pad 303 is referred to as a front side, and the other side opposite thereto is referred to as a back side.
  • the passive component 302. the active component 301 and the passive component 302 are placed face down on the adhesive layer 2 so as to be adhered and fixed to the carrier.
  • a Die Attach Film (DFA) is attached to the back surface of the wafer including a plurality of Dies, or the adhesive film is not attached, and then dicing to obtain a plurality of independent dies (ie, The active component 301 or the passive component 302) is then picked up and placed on the adhesive layer 2 to temporarily fix the die on the carrier 1.
  • the adhesive film may be a UV film, and the use of a specific wavelength of light/heating of the film after cutting the wafer may reduce the adhesion strength of the film, so that the chip is easily removed from the film.
  • the function of the power transmission chip 3 is to convert the voltage of the external power source into a plurality of voltages required by the power chip 5, and provide a plurality of power supply tracks that are connected to the power chip 5.
  • the voltage of the external power source is higher than the voltage required by the power chip, and the voltage of the external power source is hereinafter referred to as a high voltage, and the voltage required for the power chip is a low voltage.
  • the active component 301 includes a controller and a buck converter;
  • the passive component 302 includes a capacitor 3021, an inductor 3021, and a resistor (not shown).
  • the buck converter can be converted into tens of thousands of low voltages by high voltage, and the low voltage can form a plurality of power supply tracks through the subsequently formed conductive pillars and rewiring layers, and is formed by subsequent The first bump structure is docked with the top power chip.
  • step S3 is performed: forming the active component 301 and the passive element on the adhesion layer 2
  • the plastic seal layer 304 of the member 302 and the plastic seal layer are ground to thin the plastic seal layer.
  • the method of forming the plastic sealing layer 304 includes any one or more of compression molding, transfer molding, liquid sealing molding, vacuum lamination, spin coating, or other suitable methods.
  • the molding material includes suitable materials such as epoxy resin, liquid thermosetting epoxy resin, and plastic.
  • the plastic sealing layer is thinned until the back surface of the active component and the passive component is exposed. Since the active component and the passive component have no pads on the back side, a certain thickness of the molding material may be retained on the back side of the active component and the passive component, and the scope of protection of the present invention should not be unduly limited herein.
  • the grinding process can employ a mechanical grinding process, a chemical polishing process, an etching process, any combination thereof, and/or the like.
  • step S4 is performed to remove the carrier 1 and the adhesion layer 2 to expose the pad 303.
  • the carrier 1 may be removed by one or more of mechanical grinding, chemical polishing, etching, ultraviolet peeling, and mechanical peeling; preferably, in the embodiment, the adhesive layer 2 may be removed by The carrier 1 was peeled off.
  • step S5 is performed: forming a plurality of through holes penetrating the plastic sealing layer up and down, and filling the through holes with a conductive material to obtain a conductive pillar 305.
  • the Through Active-interposer Via may be fabricated by any one or more of laser drilling, mechanical drilling, reactive ion etching, nanoimprinting, or other suitable methods.
  • the via fill material can be solder or copper.
  • the TAV fill can be formed by any one or more of electroplating, electroless plating, silk screen printing, wire bonding, or other suitable metal deposition process.
  • step S6 is performed to form a rewiring layer 306 of the power transmission chip 3 on the same side of the molding layer 304 as the pad 303; a conductive portion of the rewiring layer 306.
  • the conductive pillar 305 and the pad 303 are connected to realize electrical connection between the active component 301 and the passive component 302, and a plurality of power supply tracks that are connected to the power chip 5 are provided.
  • the rewiring layer includes a dielectric layer 3061 and at least one metal connection 3062 and at least one layer of conductive plugs 3063 formed in the dielectric layer; the metal connection 3062 passes through the conductive plug 3063 Electrical connection with the active component 301, the passive component 302, and the conductive pillar 305 is achieved, and when the multilayer metal wiring 3062 is formed in the dielectric layer 3061, the multilayer metal wiring 3062 passes between The conductive plugs 3063 implement interlayer electrical connections.
  • the material of the metal wiring 3062 includes one or more of Cu, Al, Ag, Au, Sn, Ni, Ti, Ta, or other suitable conductive metal materials.
  • the metal wiring 3062 may be a Cu wire, and the seed layer of the Cu wire may be a Ti/Cu layer.
  • the method of forming the metal wiring 182 may include one or more of electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process.
  • a through hole may be formed in the dielectric layer 3061 by laser drilling, mechanical drilling, reactive ion etching, nanoimprinting, or other suitable opening method, and then the through hole
  • the conductive plug 3063 can be formed by filling a metal material; the material of the conductive plug 3063 can be solder or Cu, and the filling method can be electrolytic plating, electroless plating, screen printing, wire bonding or other suitable in the through hole. A method of filling a conductive material.
  • step S7 is performed to connect the power chip 5 and the rewiring layer through a plurality of first bump structures 4 to realize docking of the power chip 5 and the plurality of power supply tracks. .
  • the power chip includes, but is not limited to, an ASIC Die.
  • the first bump structure 4 may adopt a mico-bump or other suitable bump structure.
  • the power chip 5 may be soldered to the rewiring layer 306 via a plurality of first bump structures 4 by processes such as ultrasonic bonding, thermocompression bonding, or conventional reflow soldering.
  • the method further includes filling the power chip 5 and the wiring layer 306 with an underfill.
  • the step of the gap is simply the meaning of underfill.
  • the conventional definition is to use a chemical glue (the main component is epoxy resin) to underfill the chip.
  • the bottom of the chip has a large gap (generally covering 80). Filled more than %) to achieve the purpose of reinforcement and enhance the drop resistance of the package structure.
  • the underfill method may be a capillary underfill or a Molding UnderFill (MUF).
  • capillary filling is the use of capillary action to make the glue flow rapidly through the bottom of the chip, and the minimum space for capillary flow is 10um. This also meets the minimum electrical characteristics between the pad and the solder ball in the soldering process, because the glue does not flow through the gap below 4um, thus ensuring the electrical safety characteristics of the soldering process.
  • a step of wrapping the periphery of the power chip 5 by a molding material 7 is also included.
  • step S8 is performed to form a plurality of second bump structures 8 connected to the conductive pillars on a surface of the plastic sealing layer on the side opposite to the pads.
  • the second bump structure includes a Ball Grid Array (BGA) solder ball.
  • BGA Ball Grid Array
  • the package structure may be combined with the package substrate by using the second bump structure, and the package substrate may be a printed circuit board (PCB) or other suitable package.
  • An external power supply voltage can be applied to the power transmission chip through the package substrate, and converted into a plurality of voltages required by the power chip by the power transmission chip, and the converted voltage is further passed through the power transmission chip A plurality of power supply tracks are applied to the power chip. Since the package structure of the present invention integrates a power transmission chip including passive components, parasitic resistance on a package substrate such as a PCB can be eliminated, thereby improving power transmission efficiency, improving response time of power control, and improving fidelity.
  • the present invention provides a new packaging method for integrating a power chip and a power transmission chip into a package structure using a three-dimensional chip stacking technology, which has the following beneficial effects: (1) using an existing active device Components and passive components Forming an active 2.5D interposer, and then integrating the power chip on the active 2.5D interposer through microbumps or other bump structures to obtain a three-dimensional stacked structure; wherein the power chip may be an application specific integrated circuit ( Application Specific Integrated Circuit (ASIC). (2) In the three-dimensional stack structure, the active 2.5D interposer acts as a power transmission power chip, which is tightly integrated under the power chip, solving the problem of power transmission.
  • ASIC Application Specific Integrated Circuit
  • the power transmission system of the entire system circuit board is implemented by the power transmission chip, which includes a controller, a buck converter, a capacitor (CAP (3T)), and an inductor (L (2T) )) and resistors, thus eliminating all passive components on the system board.
  • the buck converter in the power transfer chip can generate thousands of low voltage power transmission tracks (power supply tracks) that are connected to the power chips through the micro bumps.
  • the package structure of the present invention can eliminate parasitic resistance on a package substrate such as a PCB due to integration of a power transfer chip including passive components, thereby improving power transmission efficiency and improving response time of power control.
  • (6) Improves fidelity by reducing voltage drop and noise, thereby improving response time. Better fidelity performance improvements are achieved due to the need for less design margin. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

L'invention concerne un procédé d'encapsulation pour une structure d'encapsulation avec une puce de transmission de puissance intégrée. La structure d'encapsulation comprend une puce électrique (5) et une puce de transmission de puissance (3) connectée au-dessous de la puce électrique (5). La puce de transmission de puissance (3) est utilisée pour convertir une tension d'une source d'alimentation externe en une pluralité de tensions requises pour la puce électrique (5) et fournir une pluralité de rails d'alimentation électrique s'accouplant à la puce électrique (5). La puce de transmission de puissance (3) est utilisée en tant que plaque intermédiaire 2,5D active et la puce électrique (5) est intégrée sur la plaque intermédiaire 2,5D active au moyen d'une micro-bosse ou d'autres structures de bosse, de façon à obtenir une structure de puce empilée tridimensionnelle. Un système de transmission de puissance de toute la carte de circuit de système est réalisé grâce à la puce de transmission de puissance (3) et une résistance parasite sur un substrat d'encapsulation peut être éliminée, de sorte que l'efficacité de transmission de puissance puisse être améliorée, le temps de réponse pour la commande de puissance puisse être amélioré et la fidélité soit améliorée.
PCT/CN2017/095406 2017-03-22 2017-08-01 Procédé d'encapsulation pour structure d'encapsulation à puce de transmission de puissance intégrée WO2018171099A1 (fr)

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