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WO2018159309A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
WO2018159309A1
WO2018159309A1 PCT/JP2018/005301 JP2018005301W WO2018159309A1 WO 2018159309 A1 WO2018159309 A1 WO 2018159309A1 JP 2018005301 W JP2018005301 W JP 2018005301W WO 2018159309 A1 WO2018159309 A1 WO 2018159309A1
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Prior art keywords
semiconductor chip
substrate
spacer
back surface
semiconductor
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PCT/JP2018/005301
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English (en)
French (fr)
Inventor
和明 馬渡
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株式会社デンソー
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Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Priority to CN201880013574.9A priority Critical patent/CN110326092B/zh
Priority to DE112018001137.2T priority patent/DE112018001137B4/de
Publication of WO2018159309A1 publication Critical patent/WO2018159309A1/ja
Priority to US16/545,141 priority patent/US11183480B2/en

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    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Definitions

  • the present disclosure relates to a semiconductor device and a manufacturing method thereof.
  • Patent Document 1 For a semiconductor device having a configuration in which a semiconductor chip is fixed to a substrate with an adhesive, for example, in Patent Document 1, in order to prevent the semiconductor chip from being inclined with respect to the substrate, the semiconductor chip is bonded using an adhesive containing spherical particles. A method of fixing to a substrate has been proposed.
  • a semiconductor device includes a substrate, a semiconductor chip disposed on a front surface side of the substrate, and an adhesive that fixes a back surface of the semiconductor chip to the front surface of the substrate. And a plurality of spacers that define the distance between the substrate and the semiconductor chip, the spacers being bonded to the front surface of the substrate or the back surface of the semiconductor chip, and in the in-plane direction of the back surface of the semiconductor chip, the semiconductor chip It is located at each vertex of the polygon surrounding the center of gravity.
  • the spacer so as to surround the center of gravity of the semiconductor chip, the semiconductor chip is supported on both sides of the center of gravity, and the semiconductor chip is prevented from being inclined with respect to the substrate by its own weight.
  • a method for manufacturing a semiconductor device comprising a substrate, a semiconductor chip disposed on the front surface side of the substrate, and an adhesive that fixes the back surface of the semiconductor chip to the surface of the substrate, Forming a spacer so as to be positioned at each vertex of a polygon which is bonded to the front surface of the substrate or the back surface of the semiconductor chip and surrounds the center of gravity of the semiconductor chip in the in-plane direction of the back surface of the semiconductor chip; Applying an adhesive to the front surface or the back surface of the semiconductor chip; and fixing the back surface of the semiconductor chip to the front surface of the substrate with an adhesive so that the distance between the substrate and the semiconductor chip is defined by the spacer.
  • the spacer so as to surround the center of gravity of the semiconductor chip, the semiconductor chip is supported on both sides of the center of gravity, and the semiconductor chip is prevented from being inclined with respect to the substrate by its own weight.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment.
  • 1 is a plan view of a semiconductor device according to a first embodiment.
  • FIG. 2 is a cross-sectional view showing a manufacturing process of the semiconductor device of FIG. 1.
  • FIG. 3B is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 3A;
  • FIG. 3B is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 3B.
  • It is sectional drawing of the modification of 1st Embodiment. It is a top view which shows the manufacturing process of the modification of 1st Embodiment.
  • It is sectional drawing of the semiconductor device concerning 2nd Embodiment.
  • It is sectional drawing of the semiconductor device concerning 3rd Embodiment.
  • It is sectional drawing of the semiconductor device concerning 4th Embodiment.
  • It is sectional drawing of the semiconductor device concerning 5th Embodiment.
  • It is a top view
  • the semiconductor device of this embodiment includes a substrate 1, a semiconductor chip 2, an adhesive 3, a plurality of spacers 4, bonding wires 5, and a sealing resin 6.
  • the substrate 1 is composed of a printed circuit board based on a resin such as epoxy resin or glass epoxy resin.
  • the semiconductor chip 2 is obtained by forming a semiconductor element on a substrate made of Si or the like, and is disposed on the surface side of the substrate 1.
  • the semiconductor chip 2 has a rectangular plate shape, and the back surface is fixed to the surface of the substrate 1 with an adhesive 3.
  • the adhesive 3 is made of, for example, a silicon resin or an epoxy resin.
  • An adhesive 3 and a spacer 4 are disposed between the substrate 1 and the semiconductor chip 2.
  • the spacer 4 defines the distance between the substrate 1 and the semiconductor chip 2.
  • the spacer 4 is bonded to the back surface of the semiconductor chip 2.
  • the spacer 4 is located at each vertex of a polygon surrounding the center of gravity of the semiconductor chip 2 in the in-plane direction of the back surface of the semiconductor chip 2.
  • the spacers 4 may be arranged at the apexes of a triangle surrounding the center of gravity of the semiconductor chip 2 in the in-plane direction of the back surface of the semiconductor chip 2. Further, the center of gravity of the semiconductor chip 2 may be surrounded by some of the plurality of spacers 4.
  • the plurality of spacers 4 are arranged symmetrically with respect to the center of the semiconductor chip 2 in the in-plane direction of the back surface of the semiconductor chip 2. By disposing the spacer 4 in this way, deformation of the semiconductor chip 2 due to the difference in linear expansion coefficient between the substrate 1 and the semiconductor chip 2 can be reduced.
  • FIG. 2 is a plan view of the semiconductor chip 2 on which the spacer 4 is formed as seen from the back side.
  • spacers 4 are formed at four corners on the back surface of the semiconductor chip 2, respectively, and are positioned at the vertices of a rectangle surrounding the center of gravity of the semiconductor chip 2.
  • the other four spacers 4 are formed on the inner peripheral portion of the back surface of the semiconductor chip 2, and are positioned at each vertex of a quadrangle surrounding the center of gravity of the semiconductor chip 2.
  • the spacer 4 is made of a resin that is cured by heat or ultraviolet rays.
  • the spacer 4 is preferably made of a material having a low stress and a low linear expansion coefficient depending on the application of the semiconductor device.
  • the spacer 4 may be made of a metal such as Ag paste or solder ball, or a material similar to the adhesive.
  • Each of the plurality of spacers 4 is applied to a circular area on the back surface of the semiconductor chip 2, and the height of the spacer 4 can be increased by increasing the diameter of the area.
  • the diameter of the region to which the spacer 4 is applied and the height of the spacer 4 are controlled by the viscosity and thixo value of the material.
  • the bonding wire 5 is for electrically connecting the semiconductor chip 2 to the substrate 1 and is connected to a pad (not shown) formed on the surface of the semiconductor chip 2. As shown in FIG. 1, the bonding wire 5 is connected to the semiconductor chip 2 at a position corresponding to the spacer 4. When the bonding wire 5 is arranged in this manner, a portion of the semiconductor chip 2 to which a load is applied at the time of wire bonding is supported by the spacer 4, so that stable wire bonding can be performed even when the adhesive 3 is soft. it can.
  • the sealing resin 6 is formed on the surface of the substrate 1 so as to cover the semiconductor chip 2, the adhesive 3, the spacer 4, and the bonding wire 5.
  • a resin is applied to the back surface of the semiconductor chip 2 using a jet dispenser or the like. Specifically, in the in-plane direction of the back surface of the semiconductor chip 2, the resin is applied in a dot shape so as to be positioned at each vertex of a polygon surrounding the center of gravity of the semiconductor chip 2. Then, the applied resin is cured by heat or ultraviolet rays. Thereby, the spacer 4 joined to the back surface of the semiconductor chip 2 is formed.
  • the spacer 4 is formed after the wafer on which the semiconductor element is formed is divided into chips by dicing cut. However, the spacer 4 is formed on the wafer on which the semiconductor element is formed, and then dicing is performed.
  • the semiconductor chip 2 may be formed by cutting.
  • the back surface of the semiconductor chip 2 is fixed to the front surface of the substrate 1 using an adhesive 3.
  • the tips of the spacers 4 formed on the back surface of the semiconductor chip 2 are brought into contact with the substrate 1.
  • the distance between the substrate 1 and the semiconductor chip 2 becomes equal to the height of the spacer 4. That is, the distance between the substrate 1 and the semiconductor chip 2 is defined by the spacer 4.
  • the semiconductor chip 2 may be fixed to the substrate 1 after applying the adhesive 3 to the substrate 1, or the semiconductor chip 2 is attached to the substrate 1 after applying the adhesive 3 to the semiconductor chip 2. It may be fixed to.
  • wire bonding for electrically connecting a pad (not shown) formed on the surface of the semiconductor chip 2 and the substrate 1 is performed.
  • a pad not shown
  • stable wire bonding can be performed even when the adhesive 3 is soft.
  • a resin is applied so as to cover the semiconductor chip 2, the adhesive 3, the spacer 4, and the bonding wire 5, and the sealing resin 6 is formed. In this way, the semiconductor device of this embodiment shown in FIG. 1 is manufactured.
  • the semiconductor chip 2 is supported from both sides of the center of gravity by the spacers 4, so that the semiconductor chip 2 is prevented from being inclined with respect to the substrate 1 due to its own weight. .
  • the spacer 4 is bonded to the back surface of the semiconductor chip 2, but the spacer 4 may be bonded to the surface of the substrate 1 as shown in FIG. 4. Even in such a configuration, the semiconductor chip 2 can be prevented from being inclined with respect to the substrate 1 as in the present embodiment. In FIG. 4 and FIGS. 6 to 9 described later, the sealing resin 6 is not shown.
  • FIG. 5 is a plan view of the substrate 1 on which the spacers 4 are formed as viewed from the front side.
  • the semiconductor chip 2 is arranged in a region surrounded by a one-dot chain line.
  • the spacer 4 when the spacer 4 is bonded to the surface of the substrate 1, the spacer 4 can be used as an alignment mark when the semiconductor chip 2 is fixed to the substrate 1.
  • the spacer 4 of this embodiment is composed of a first layer 4a formed on the back surface of the semiconductor chip 2 and a second layer 4b formed on the surface of the first layer 4a.
  • the first layer 4a and the second layer 4b are made of resin.
  • Such a spacer 4 forms the first layer 4a by applying the resin constituting the first layer 4a on the back surface of the semiconductor chip 2 and curing it, and then forming the second layer 4b on the surface of the first layer 4a. It is formed by applying and curing resin.
  • the height of the spacer 4 formed by applying the resin once is determined by the surface tension or the like, but by applying the resin to the surface of the first layer 4a to form the second layer 4b,
  • the spacer 4 can be made higher than the case where the spacer 4 is formed by applying the resin. This also makes it possible to reduce stress due to the difference in linear expansion coefficient between the substrate 1 and the semiconductor chip 2.
  • some spacers 4 are formed on the surface of the substrate 1, and other spacers 4 are formed on the back surface of the semiconductor chip 2.
  • the spacers 4 formed on the front surface of the substrate 1 and the back surface of the semiconductor chip 2 are bonded to the front surface of the substrate 1 and the back surface of the semiconductor chip 2, respectively.
  • the distance between the substrate 1 and the semiconductor chip 2 is defined by stacking the spacer 4 formed on the front surface of the substrate 1 and the spacer 4 formed on the back surface of the semiconductor chip 2.
  • the spacers 4 formed on both the substrate 1 and the semiconductor chip 2 are stacked, so that the distance between the substrate 1 and the semiconductor chip 2 can be increased. In addition, it is possible to reduce stress due to the difference in linear expansion coefficient between the substrate 1 and the semiconductor chip 2.
  • vias 7 that are TSVs (through silicon vias) penetrating the semiconductor chip 2 in the thickness direction are formed in the semiconductor chip 2.
  • the spacer 4 includes a metal layer 8 formed on the inside of the via 7 and the back surface of the semiconductor chip 2. Note that the via 7 and the metal layer 8 do not electrically connect the semiconductor chip 2 and the circuit formed on the substrate 1 but are formed separately from the wiring that electrically connects them.
  • a semiconductor element is formed on the surface of a Si substrate, a via 7 penetrating the Si substrate is formed, a metal layer 8 is embedded in the via 7 by plating, and then Si The metal layer 8 is protruded by removing a part of the back side of the substrate by etching. Then, as in the first embodiment, bonding, wire bonding, and resin sealing are performed.
  • the semiconductor chip 2 is suppressed from being inclined with respect to the substrate 1 as in the first embodiment.
  • the semiconductor device of this embodiment includes a plurality of semiconductor chips 2 arranged in a stacked manner.
  • One back surface of two adjacent semiconductor chips 2 is fixed to the other surface by the adhesive 3
  • one back surface of the plurality of semiconductor chips 2 is fixed to the surface of the substrate 1 by the adhesive 3.
  • the adhesive 3 that fixes the semiconductor chip 2 to the substrate 1 corresponds to the first adhesive
  • the adhesive 3 that fixes one of the two adjacent semiconductor chips 2 to the other corresponds to the second adhesive.
  • some of the plurality of spacers 4 are bonded to the surface of the substrate 1, and the other spacers 4 are arranged between two adjacent semiconductor chips 2.
  • the spacer 4 disposed between two adjacent semiconductor chips 2 is bonded to one surface of the two semiconductor chips 2 close to the substrate 1, and the center of gravity of the other back surface is in the in-plane direction of the other back surface. Located at each vertex of the enclosing polygon.
  • the spacer 4 defines a distance between two adjacent semiconductor chips 2.
  • the spacer 4 disposed between the substrate 1 and the semiconductor chip 2 corresponds to a first spacer, and the spacer 4 disposed between two adjacent semiconductor chips 2 corresponds to a second spacer.
  • one of the two adjacent semiconductor chips 2 is arranged by arranging the spacer 4 between the two adjacent semiconductor chips 2 in the same manner as in the first embodiment. Is suppressed from tilting with respect to the other.
  • the spacer 4 may be formed on the surface of the substrate 1 in the second embodiment.
  • the spacer 4 that defines the distance between the substrate 1 and the semiconductor chip 2 may be bonded to the back surface of the semiconductor chip 2.
  • the spacer 4 may be bonded to the back surface of the semiconductor chip 2 far from the substrate 1 among the two adjacent semiconductor chips 2.
  • the spacer 4 may be composed of the first layer 4a and the second layer 4b as in the second embodiment.
  • the spacer 4 may be formed at another position in the in-plane direction of the back surface of the semiconductor chip 2.
  • the spacer 4 may be formed at another position in the in-plane direction of the back surface of the semiconductor chip 2.
  • six spacers 4 are formed on the back surface of the semiconductor chip 2, and the six spacers 4 each have a rectangular vertex surrounding the center of gravity of the semiconductor chip 2 and two opposing sides. It may be located at the midpoint.
  • FIG. 10 is a plan view of the semiconductor chip 2 on which the spacer 4 is formed as seen from the back side.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

半導体装置は、基板（１）と、基板（１）の表面側に配置された半導体チップ（２）と、半導体チップ（２）の裏面を基板（１）の表面に固定する接着剤（３）と、基板（１）と半導体チップ（２）との距離を規定する複数のスペーサ（４）と、を備え、スペーサ（４）は、基板（１）の表面、または、半導体チップ（２）の裏面に接合され、半導体チップ（２）の裏面の面内方向において、半導体チップ（２）の重心を囲む多角形の各頂点に位置している。

Description

半導体装置およびその製造方法 関連出願への相互参照
　本出願は、２０１７年３月３日に出願された日本特許出願番号２０１７－４０６７０号に基づくもので、ここにその記載内容が参照により組み入れられる。
　本開示は、半導体装置およびその製造方法に関するものである。
　半導体チップが接着剤で基板に固定された構成の半導体装置について、例えば特許文献１では、半導体チップが基板に対して傾くことを抑制するために、球状粒子を含む接着剤を用いて半導体チップを基板に固定する方法が提案されている。
特許第４２９９６８５号公報
　接着剤の粘度が高い場合には、接着剤と球状粒子との攪拌が困難であるため、接着剤中の球状粒子の分布に偏りが生じることがある。そのため、特許文献１に記載の方法では、半導体チップが球状粒子によって十分に支持されず、基板に対して傾くおそれがある。
　本開示は上記点に鑑みて、半導体チップが基板に対して傾くことを抑制することができる半導体装置およびその製造方法を提供することを目的とする。
　上記目的を達成するため、本開示の１つの観点によれば、半導体装置であって、基板と、基板の表面側に配置された半導体チップと、半導体チップの裏面を基板の表面に固定する接着剤と、基板と半導体チップとの距離を規定する複数のスペーサと、を備え、スペーサは、基板の表面、または、半導体チップの裏面に接合され、半導体チップの裏面の面内方向において、半導体チップの重心を囲む多角形の各頂点に位置している。
　このように、半導体チップの重心を囲むようにスペーサを配置することにより、半導体チップが重心の両側で支持されるようになり、半導体チップが自身の重さによって基板に対して傾くことが抑制される。
　また、別の観点によれば、基板と、基板の表面側に配置された半導体チップと、半導体チップの裏面を基板の表面に固定する接着剤と、を備える半導体装置の製造方法であって、基板の表面、または、半導体チップの裏面に接合され、半導体チップの裏面の面内方向において、半導体チップの重心を囲む多角形の各頂点に位置するように、スペーサを形成することと、基板の表面、または、半導体チップの裏面に接着剤を塗布することと、スペーサによって基板と半導体チップとの距離が規定されるように、接着剤によって、半導体チップの裏面を基板の表面に固定することと、を備える。
　このように、半導体チップの重心を囲むようにスペーサを配置することにより、半導体チップが重心の両側で支持されるようになり、半導体チップが自身の重さによって基板に対して傾くことが抑制される。
第１実施形態にかかる半導体装置の断面図である。 第１実施形態にかかる半導体装置の平面図である。 図１の半導体装置の製造工程を示す断面図である。 図３Ａに続く半導体装置の製造工程を示す断面図である。 図３Ｂに続く半導体装置の製造工程を示す断面図である。 第１実施形態の変形例の断面図である。 第１実施形態の変形例の製造工程を示す平面図である。 第２実施形態にかかる半導体装置の断面図である。 第３実施形態にかかる半導体装置の断面図である。 第４実施形態にかかる半導体装置の断面図である。 第５実施形態にかかる半導体装置の断面図である。 他の実施形態にかかる半導体装置の平面図である。
　以下、本開示の実施形態について図に基づいて説明する。なお、以下の各実施形態相互において、互いに同一もしくは均等である部分には、同一符号を付して説明を行う。
　（第１実施形態）
　第１実施形態について説明する。図１に示すように、本実施形態の半導体装置は、基板１と、半導体チップ２と、接着剤３と、複数のスペーサ４と、ボンディングワイヤ５と、封止樹脂６とを備えている。
　基板１は、エポキシ樹脂やガラスエポキシ樹脂等の樹脂をベースとするプリント基板で構成されている。半導体チップ２は、Ｓｉ等で構成された基板に半導体素子が形成されたものであり、基板１の表面側に配置されている。半導体チップ２は、矩形板状とされており、裏面が接着剤３によって基板１の表面に固定されている。接着剤３は、例えばシリコン樹脂、エポキシ樹脂等で構成される。基板１と半導体チップ２との間には、接着剤３と、スペーサ４とが配置されている。
　スペーサ４は、基板１と半導体チップ２との距離を規定するものである。本実施形態では、スペーサ４は、半導体チップ２の裏面に接合されている。また、スペーサ４は、半導体チップ２の裏面の面内方向において、半導体チップ２の重心を囲む多角形の各頂点に位置している。このような構成により、半導体チップ２が自身の重さで傾くことが抑制され、基板１と半導体チップ２との間の距離が一定に保たれる。
　なお、スペーサ４は少なくとも３つあればよい。半導体装置がスペーサ４を３つ備える場合には、半導体チップ２の裏面の面内方向において、半導体チップ２の重心を囲む三角形の各頂点にスペーサ４を配置すればよい。また、複数のスペーサ４の一部によって半導体チップ２の重心が囲まれていてもよい。
　また、複数のスペーサ４は、半導体チップ２の裏面の面内方向において、半導体チップ２の中心に対して対称に配置されている。スペーサ４をこのように配置することで、基板１と半導体チップ２との線膨張係数の差による半導体チップ２の変形を緩和することができる。
　本実施形態では、図２に示すように、スペーサ４は、半導体チップ２の裏面に８つ形成されている。なお、図２は、スペーサ４が形成された半導体チップ２を裏面側から見た平面図である。
　８つのスペーサ４のうち４つは、それぞれ、半導体チップ２の裏面の４つの角部に形成されており、半導体チップ２の重心を囲む四角形の各頂点に位置している。そして、他の４つのスペーサ４は、半導体チップ２の裏面の内周部に形成されており、半導体チップ２の重心を囲む四角形の各頂点に位置している。
　また、本実施形態では、スペーサ４は、熱や紫外線によって硬化する樹脂で構成されている。なお、スペーサ４の材料は、半導体装置の用途によっては、低応力、低線膨張係数のものが望ましい。また、スペーサ４をＡｇペースト、ハンダボール等の金属、または、接着剤と同様の材料で構成してもよい。
　複数のスペーサ４は、それぞれ、半導体チップ２の裏面における円形状の領域に塗布されており、この領域の径を大きくすることにより、スペーサ４の高さを大きくすることができる。スペーサ４を塗布する領域の径、および、スペーサ４の高さは、材料の粘度やチクソ値により制御される。
　ボンディングワイヤ５は、半導体チップ２を基板１に電気的に接続するためのものであり、半導体チップ２の表面に形成された図示しないパッドに接続されている。図１に示すように、ボンディングワイヤ５は、スペーサ４に対応する位置において半導体チップ２に接続されている。ボンディングワイヤ５をこのように配置すると、半導体チップ２のうちワイヤボンディングの際に荷重が加わる部分がスペーサ４によって支持されるので、接着剤３が軟らかい場合にも、安定したワイヤボンディングを行うことができる。
　封止樹脂６は、基板１の表面において、半導体チップ２、接着剤３、スペーサ４、ボンディングワイヤ５を覆うように形成されている。
　本実施形態の半導体装置の製造方法について図３Ａ～図３Ｃを用いて説明する。図３Ａに示す工程では、ジェットディスペンサ等を用いて、半導体チップ２の裏面に樹脂を塗布する。具体的には、半導体チップ２の裏面の面内方向において、半導体チップ２の重心を囲む多角形の各頂点に位置するように樹脂を点状に塗布する。そして、塗布した樹脂を熱や紫外線によって硬化させる。これにより、半導体チップ２の裏面に接合されたスペーサ４が形成される。
　なお、本実施形態では、半導体素子が形成されたウェハをダイシングカットによってチップ単位に分割した後にスペーサ４を形成しているが、半導体素子が形成されたウェハにスペーサ４を形成し、その後にダイシングカットを行って半導体チップ２を形成してもよい。
　図３Ｂに示す工程では、接着剤３を用いて、半導体チップ２の裏面を基板１の表面に固定する。このとき、半導体チップ２の裏面に形成されたスペーサ４の先端が基板１に接触するようにする。これにより、基板１と半導体チップ２との距離がスペーサ４の高さと等しくなる。すなわち、スペーサ４によって基板１と半導体チップ２との距離が規定される。半導体チップ２を基板１に固定する際には、半導体チップ２に接合されたスペーサ４をアライメントマークとして使用することが可能である。
　なお、図３Ｂに示す工程では、基板１に接着剤３を塗布した後に半導体チップ２を基板１に固定してもよいし、半導体チップ２に接着剤３を塗布した後に半導体チップ２を基板１に固定してもよい。
　図３Ｃに示す工程では、半導体チップ２の表面に形成された図示しないパッドと基板１とを電気的に接続するワイヤボンディングを行う。このとき、ボンディングワイヤ５を、スペーサ４に対応する位置において半導体チップ２に接続することにより、接着剤３が軟らかい場合にも、安定したワイヤボンディングを行うことができる。
　図３Ｃに示す工程の後、半導体チップ２、接着剤３、スペーサ４、ボンディングワイヤ５を覆うように樹脂を塗布し、封止樹脂６を形成する。このようにして、図１に示す本実施形態の半導体装置が製造される。
　スペーサ４が上記のように配置された本実施形態では、半導体チップ２がスペーサ４によって重心の両側から支えられるため、半導体チップ２が自身の重さによって基板１に対して傾くことが抑制される。
　また、特許文献１に記載の方法では、接着剤と球状粒子とを攪拌する工程が必要であるが、本実施形態では、この攪拌工程が必要でないため、半導体装置の製造工程を簡略化することができる。また、接着剤の粘度が高い場合には、接着剤と球状粒子との攪拌が困難になるが、本実施形態では、接着剤３として粘度が高い材料を用いても、粘度が低い材料を用いる場合と同様に半導体装置を製造することができる。
　なお、本実施形態では、スペーサ４は半導体チップ２の裏面に接合されているが、図４に示すように、スペーサ４が基板１の表面に接合されていてもよい。このような構成においても、本実施形態と同様に、半導体チップ２が基板１に対して傾くことを抑制することができる。なお、図４、および、後述する図６～図９では、封止樹脂６の図示を省略している。
　また、このような構成では、図３Ｂに示す工程において基板１に接着剤３を塗布する場合に、半導体チップ２を基板１に固定する際に、接着剤３が過度に広がることをスペーサ４によって抑制することができる。例えば、接着剤３を半導体チップ２が置かれる領域の中央部に塗布することで、図５の破線で囲まれた領域、すなわち、半導体チップ２が配置される領域のうち、スペーサ４の近傍およびスペーサ４よりも内周側の部分に接着剤３を留まらせることができる。なお、図５はスペーサ４が形成された基板１を表面側から見た平面図であり、一点鎖線で囲まれた領域に半導体チップ２が配置される。
　また、スペーサ４を基板１の表面に接合する場合にも、半導体チップ２を基板１に固定する際に、スペーサ４をアライメントマークとして使用することが可能である。
　（第２実施形態）
　第２実施形態について説明する。第２実施形態は、第１実施形態に対してスペーサ４の構成を変更したものであり、その他については第１実施形態と同様であるため、第１実施形態と異なる部分についてのみ説明する。
　図６に示すように、本実施形態のスペーサ４は、半導体チップ２の裏面に形成された第１層４ａと、第１層４ａの表面に形成された第２層４ｂとで構成されている。第１層４ａ、第２層４ｂは、樹脂で形成されている。
　このようなスペーサ４は、半導体チップ２の裏面に第１層４ａを構成する樹脂を塗布し、硬化させて第１層４ａを形成した後、第１層４ａの表面に第２層４ｂを構成する樹脂を塗布し、硬化させることにより形成される。
　一度の樹脂の塗布で形成されるスペーサ４の高さは表面張力等で定まるが、このように、第１層４ａの表面にさらに樹脂を塗布して第２層４ｂを形成することにより、一度の樹脂の塗布でスペーサ４を形成する場合に比べて、スペーサ４を高くすることができる。また、これにより、基板１と半導体チップ２との線膨張係数の差による応力を低減することが可能となる。
　（第３実施形態）
　第３実施形態について説明する。第３実施形態は、第１実施形態に対してスペーサ４の構成を変更したものであり、その他については第１実施形態と同様であるため、第１実施形態と異なる部分についてのみ説明する。
　図７に示すように、本実施形態では、一部のスペーサ４は基板１の表面に形成されており、他のスペーサ４は半導体チップ２の裏面に形成されている。基板１の表面、半導体チップ２の裏面に形成されたスペーサ４は、それぞれ、基板１の表面、半導体チップ２の裏面に接合されている。そして、基板１の表面に形成されたスペーサ４と、半導体チップ２の裏面に形成されたスペーサ４とが積み重なることにより、基板１と半導体チップ２との距離が規定されている。
　このように、基板１と半導体チップ２の両方に形成されたスペーサ４が積み重なることにより、基板１と半導体チップ２との距離を大きくすることができる。また、基板１と半導体チップ２との線膨張係数の差による応力を低減することが可能となる。
　（第４実施形態）
　第４実施形態について説明する。第４実施形態は、第１実施形態に対してスペーサ４の構成を変更したものであり、その他については第１実施形態と同様であるため、第１実施形態と異なる部分についてのみ説明する。
　図８に示すように、本実施形態では、半導体チップ２に、半導体チップ２を厚さ方向に貫通するＴＳＶ（シリコン貫通ビア）であるビア７が形成されている。そして、スペーサ４は、ビア７の内部および半導体チップ２の裏面に形成された金属層８で構成されている。なお、ビア７および金属層８は、半導体チップ２と基板１に形成された回路等とを電気的に接続するものではなく、これらを電気的に接続する配線等とは別に形成される。
　このような半導体装置を製造するには、例えばＳｉ基板の表面に半導体素子を形成し、Ｓｉ基板を貫通するビア７を形成し、メッキによってビア７の内部に金属層８を埋め込んだ後、Ｓｉ基板の裏面側の一部をエッチングにより除去して金属層８を突出させる。そして、第１実施形態と同様に接着、ワイヤボンディング、樹脂封止を行う。
　このように、スペーサ４を金属層８で構成した本実施形態においても、第１実施形態と同様に、半導体チップ２が基板１に対して傾くことが抑制される。
　（第５実施形態）
　第５実施形態について説明する。第５実施形態は、第１実施形態に対して半導体チップ２の数を変更したものであり、その他については第１実施形態と同様であるため、第１実施形態と異なる部分についてのみ説明する。
　図９に示すように、本実施形態の半導体装置は、積層配置された複数の半導体チップ２を備えている。隣り合う２つの半導体チップ２のうち一方の裏面は、接着剤３によって他方の表面に固定されており、複数の半導体チップ２のうち１つの裏面は、接着剤３によって基板１の表面に固定されている。半導体チップ２を基板１に固定する接着剤３は第１接着剤に相当し、隣り合う２つの半導体チップ２のうち一方を他方に固定する接着剤３は第２接着剤に相当する。
　また、複数のスペーサ４の一部が基板１の表面に接合されており、他のスペーサ４は、隣り合う２つの半導体チップ２の間に配置されている。隣り合う２つの半導体チップ２の間に配置されたスペーサ４は、２つの半導体チップ２のうち基板１に近い一方の表面に接合されており、他方の裏面の面内方向において、他方の重心を囲む多角形の各頂点に位置している。そして、スペーサ４は、隣り合う２つの半導体チップ２の間の距離を規定している。基板１と半導体チップ２との間に配置されたスペーサ４は第１スペーサに相当し、隣り合う２つの半導体チップ２の間に配置されたスペーサ４は第２スペーサに相当する。
　このように複数の半導体チップ２が積層された構成では、隣り合う２つの半導体チップ２の間に第１実施形態と同様にスペーサ４を配置することにより、隣り合う２つの半導体チップ２のうち一方が他方に対して傾くことが抑制される。
　（他の実施形態）
　なお、本開示は上記した実施形態に限定されるものではなく、適宜変更が可能である。また、上記各実施形態は、互いに無関係なものではなく、組み合わせが明らかに不可な場合を除き、適宜組み合わせが可能である。また、上記各実施形態において、実施形態を構成する要素は、特に必須であると明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではないことは言うまでもない。また、上記各実施形態において、実施形態の構成要素の個数、数値、量、範囲等の数値が言及されている場合、特に必須であると明示した場合および原理的に明らかに特定の数に限定される場合等を除き、その特定の数に限定されるものではない。また、上記各実施形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に特定の形状、位置関係等に限定される場合等を除き、その形状、位置関係等に限定されるものではない。
　例えば、上記第２実施形態において、スペーサ４を基板１の表面に形成してもよい。また、上記第５実施形態において、基板１と半導体チップ２との距離を規定するスペーサ４を半導体チップ２の裏面に接合させてもよい。また、上記第５実施形態において、隣り合う２つの半導体チップ２のうち基板１から遠い方の半導体チップ２の裏面にスペーサ４を接合させてもよい。
　また、上記第３、第５実施形態において、第２実施形態と同様に、スペーサ４を第１層４ａと第２層４ｂで構成してもよい。
　また、上記第１実施形態において、スペーサ４を半導体チップ２の裏面の面内方向において他の位置に形成してもよい。例えば、図１０に示すように、スペーサ４が、半導体チップ２の裏面に６つ形成されており、６つのスペーサ４が、半導体チップ２の重心を囲む長方形の各頂点と、対向する２つの辺の中点に位置していてもよい。なお、図１０は、スペーサ４が形成された半導体チップ２を裏面側から見た平面図である。

Claims (11)

  1. 　半導体装置であって、
    　基板（１）と、
    　前記基板の表面側に配置された半導体チップ（２）と、
    　前記半導体チップの裏面を前記基板の表面に固定する接着剤（３）と、
    　前記基板と前記半導体チップとの距離を規定する複数のスペーサ（４）と、を備え、
    　前記スペーサは、前記基板の表面、または、前記半導体チップの裏面に接合され、前記半導体チップの裏面の面内方向において、前記半導体チップの重心を囲む多角形の各頂点に位置している半導体装置。
  2. 　前記スペーサは、前記半導体チップの裏面の面内方向において、前記半導体チップの重心を囲む三角形の各頂点に位置している請求項１に記載の半導体装置。
  3. 　前記スペーサは、前記半導体チップの裏面の面内方向において、前記半導体チップの中心に対して対称に配置されている請求項１または２に記載の半導体装置。
  4. 　前記半導体チップの表面に接続されたボンディングワイヤ（５）を備え、
    　前記ボンディングワイヤは、前記スペーサに対応する位置において前記半導体チップに接続されている請求項１ないし３のいずれか１つに記載の半導体装置。
  5. 　前記スペーサは、樹脂で構成された第１層（４ａ）と、前記第１層の表面に形成された第２層（４ｂ）とで構成されている請求項１ないし４のいずれか１つに記載の半導体装置。
  6. 　一部の前記スペーサは、前記基板の表面に接合されており、他の前記スペーサは、前記半導体チップの裏面に接合されており、
    　前記基板の表面に接合された前記スペーサと、前記半導体チップの裏面に接合された前記スペーサとが積み重なることにより、前記基板と前記半導体チップとの距離が規定されている請求項１ないし５のいずれか１つに記載の半導体装置。
  7. 　前記半導体チップには、前記半導体チップを貫通するビア（７）が形成されており、
    　前記スペーサは、前記ビアの内部および前記半導体チップの裏面に形成された金属層（８）で構成されている請求項１ないし４のいずれか１つに記載の半導体装置。
  8. 　積層配置された複数の前記半導体チップを備え、
    　前記接着剤を第１接着剤として、
    　隣り合う２つの前記半導体チップのうち一方の裏面を他方の表面に固定する第２接着剤（３）を備え、
    　前記スペーサを第１スペーサとして、
    　隣り合う２つの前記半導体チップのうち一方の表面、または、他方の裏面に接合され、他方の裏面の面内方向において、他方の重心を囲む多角形の各頂点に位置しており、隣り合う２つの前記半導体チップの間の距離を規定する第２スペーサ（４）を備える請求項１ないし７のいずれか１つに記載の半導体装置。
  9. 　基板（１）と、前記基板の表面側に配置された半導体チップ（２）と、前記半導体チップの裏面を前記基板の表面に固定する接着剤（３）と、を備える半導体装置の製造方法であって、
    　前記基板の表面、または、前記半導体チップの裏面に接合され、前記半導体チップの裏面の面内方向において、前記半導体チップの重心を囲む多角形の各頂点に位置するように、スペーサ（４）を形成することと、
    　前記基板の表面、または、前記半導体チップの裏面に前記接着剤を塗布することと、
    　前記スペーサによって前記基板と前記半導体チップとの距離が規定されるように、前記接着剤によって、前記半導体チップの裏面を前記基板の表面に固定することと、を備える半導体装置の製造方法。
  10. 　前記固定することでは、前記スペーサをアライメントマークとして、前記半導体チップの裏面を前記基板の表面に固定する請求項９に記載の半導体装置の製造方法。
  11. 　前記スペーサは、樹脂で構成された第１層（４ａ）と、前記第１層の表面に形成された第２層（４ｂ）とで構成されており、
    　前記スペーサを形成することでは、前記基板の表面、または、前記半導体チップの裏面に、前記第１層を構成する樹脂を塗布し、該樹脂が硬化した後、前記第２層を構成する樹脂を前記第１層の表面に塗布する請求項９または１０に記載の半導体装置の製造方法。
PCT/JP2018/005301 2017-03-03 2018-02-15 半導体装置およびその製造方法 WO2018159309A1 (ja)

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