+

WO2018151029A1 - Condensateur - Google Patents

Condensateur Download PDF

Info

Publication number
WO2018151029A1
WO2018151029A1 PCT/JP2018/004530 JP2018004530W WO2018151029A1 WO 2018151029 A1 WO2018151029 A1 WO 2018151029A1 JP 2018004530 W JP2018004530 W JP 2018004530W WO 2018151029 A1 WO2018151029 A1 WO 2018151029A1
Authority
WO
WIPO (PCT)
Prior art keywords
capacitor
metal
cavity
substrate
dielectric layer
Prior art date
Application number
PCT/JP2018/004530
Other languages
English (en)
Japanese (ja)
Inventor
晃 白鳥
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Publication of WO2018151029A1 publication Critical patent/WO2018151029A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors (thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)

Definitions

  • the present invention relates to a capacitor.
  • Patent Document 1 has a conductive metal base material having a porous portion, a dielectric layer located on the porous portion, and an upper electrode located on the dielectric layer.
  • a capacitor having a capacitance forming portion only on one main surface side is disclosed.
  • ⁇ Capacitors as described above are usually manufactured as a collective substrate and divided into individual elements. At this time, if a metal part is present in the cut part, the upper electrode and the lower electrode may be short-circuited due to flash generated by the cutting. Further, since the metal has high ductility and viscosity, it is easily stretched in the cutting direction during cutting. The extended metal may cause a short circuit between the upper electrode and the lower electrode at the end face of the capacitor.
  • a conductive metal base material is a main constituent member, and a collective substrate is manufactured from a single metal substrate. Therefore, this metal substrate exists on the cut surface. Therefore, there is a problem that the short circuit between the upper electrode and the lower electrode is likely to occur.
  • an object of the present invention is to provide a capacitor that has a high capacitance and can be easily separated from the collective substrate.
  • the present inventors have found that a capacitor made of a conductive material such as metal is not disposed at a location where the material is cut from the collective substrate.
  • the present inventors have found that a short circuit at the end face of the film can be suppressed, and have reached the present invention.
  • the present invention An insulating substrate; A conductive porous substrate having a porous portion; A dielectric layer located on the porous portion; An upper electrode located on the dielectric layer; A capacitor in which the insulating substrate has a cavity, and the conductive porous substrate, the dielectric layer, and the upper electrode are provided in the cavity. To do.
  • a capacitor comprising an insulating substrate, a conductive porous substrate having a porous part, a dielectric layer located on the porous part, and an upper electrode located on the dielectric layer
  • FIG. 1 is a schematic cross-sectional view of a capacitor 1a according to one embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view of the capacitance forming portion 4 of the capacitor 1a shown in FIG.
  • FIG. 3 is a schematic plan view of the insulating sheet 21 used for manufacturing the capacitor 1a.
  • FIG. 4 is a schematic plan view of one surface of the insulating sheet 22 used for manufacturing the capacitor 1a.
  • FIG. 5 is a schematic plan view of another surface of the insulating sheet 22 used for manufacturing the capacitor 1a.
  • FIG. 6 is a schematic plan view of the insulating sheet 23 used for manufacturing the capacitor 1a.
  • FIG. 1 is a schematic cross-sectional view of a capacitor 1a according to one embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view of the capacitance forming portion 4 of the capacitor 1a shown in FIG.
  • FIG. 3 is a schematic plan view of the insulating sheet 21 used for manufacturing the capacitor 1
  • FIG. 7 is a schematic cross-sectional view of the substrate before the capacitance forming portion 4 is formed in the cavity 3 of the insulating base 2.
  • FIG. 8 is a view showing a cutting part of the collective substrate 29.
  • FIG. 9 is a schematic cross-sectional view of a capacitor 1b according to another embodiment of the present invention.
  • FIG. 10 is a schematic cross-sectional view for explaining the state of the substrate during firing.
  • the capacitor 1 a includes an insulating base 2 and a capacitance forming portion 4 provided in the cavity 3 of the insulating base 2.
  • a first external electrode 5 is provided on the capacitance forming portion 4.
  • a cavity electrode 6 is provided at the bottom of the cavity 3.
  • a second external electrode 7 is provided on the bottom surface of the insulating substrate 2, and a metal layer 8 is provided on the second external electrode 7.
  • a via 9 is provided between the cavity electrode 6 and the second external electrode 7 so as to penetrate the insulating substrate 2 and electrically connect them.
  • the capacitance forming unit 4 includes a conductive porous substrate 11 functioning as a lower electrode, a dielectric layer 12 positioned on the conductive porous substrate 11, and an upper electrode 13 positioned on the dielectric layer 12. Consists of The first external electrode 5 is provided on the upper electrode 13. No metal material is present at the end of the capacitor 1a, and the capacitor 1a is entirely composed of the insulating substrate 2. In the capacitor 1 a, by applying a voltage between the first external electrode 5 and the metal layer 8, a voltage is applied between the lower electrode, that is, the conductive porous substrate 11 and the upper electrode 13, and the dielectric layer 12 is applied. Charge can be accumulated.
  • the capacitor 1a as described above is manufactured as follows, for example.
  • insulating sheets 21, 22, 23, and 24 constituting the insulating base 2 are prepared.
  • the insulating sheet 21 has a plurality of openings 25 corresponding to the cavities 3 of the capacitor 1a.
  • the insulating sheet 22 has a metal layer 26 corresponding to the cavity electrode 6 of the capacitor 1 a on one main surface and a through metal layer 27 corresponding to the via 9.
  • the insulating sheet 23 has a through metal layer 27 corresponding to the via 9 of the capacitor 1a, as shown in FIG.
  • the insulating sheet 24 is the same as the insulating sheet 22 except that the cavity electrode 6 is replaced with the second external electrode 7, and has a metal layer 26 corresponding to the second external electrode 7 on one main surface, and a via 9 has a through metal layer 27 corresponding to 9.
  • each insulating sheet is not particularly limited as long as it is an insulating material, and examples thereof include various ceramic materials, glass ceramic materials, resin materials, and the like.
  • the insulating material is preferably a ceramic material, particularly a glass ceramic material.
  • Examples of the ceramic material include alumina and zirconia.
  • Examples of the glass ceramic material include a mixture of CaO—Al 2 O 3 —SiO 2 glass and alumina.
  • glass ceramic materials include CaO—Al 2 O 3 —SiO 2 —B 2 O 3 glass, Na 2 O—SiO 2 glass, Na 2 O—CaO—SiO 2 glass, Na 2 O—CaO. —SiO 2 —Al 2 O 3 glass, Na 2 O—CaO—SiO 2 —Al 2 O 3 —B 2 O 3 glass, Na 2 O—B 2 O 3 —SiO 2 glass, Na 2 O— Examples thereof include B 2 O 3 —CaO—SiO 2 glass, B 2 O 3 —Al 2 O 3 —SiO 2 glass, and the like.
  • the resin material is preferably a heat-resistant resin, and examples thereof include polyimide, polybenzoxazole, polyethylene terephthalate, benzocyclobutene resin, and epoxy resin.
  • the resin material may contain a filler for adjusting the linear expansion coefficient, such as a Si filler.
  • each insulating sheet is not particularly limited, but may be, for example, 1 ⁇ m or more and 1.0 mm or less, preferably 10 ⁇ m or more and 200 ⁇ m or less, for example, 20 ⁇ m or more and 100 ⁇ m or less.
  • the material constituting the cavity electrode 6 is not particularly limited, and examples thereof include metals such as Au, Pb, Pd, Ag, Sn, Ni, and Cu, and alloys thereof.
  • the material constituting the cavity electrode 6 is Cu.
  • the thickness of the cavity electrode 6 is not particularly limited, but is preferably 0.1 ⁇ m to 100 ⁇ m, more preferably 0.5 ⁇ m to 50 ⁇ m, still more preferably 0.5 ⁇ m to 10 ⁇ m, for example, 1 ⁇ m to 5 ⁇ m. .
  • the material constituting the via 9 is not particularly limited, and examples thereof include metals and alloys such as Au, Pb, Pd, Ag, Sn, Ni, and Cu. Preferably, the material constituting the via 9 is Cu.
  • the material constituting the second external electrode 7 is not particularly limited, and examples thereof include metals and alloys such as Au, Pb, Pd, Ag, Sn, Ni, and Cu. Preferably, the material constituting the second external electrode 7 is Cu.
  • the thickness of the second external electrode 7 is not particularly limited, but is preferably 0.1 ⁇ m or more and 100 ⁇ m or less, more preferably 0.5 ⁇ m or more and 50 ⁇ m or less, further preferably 0.5 ⁇ m or more and 10 ⁇ m or less, for example, 1 ⁇ m or more and 5 ⁇ m or less. possible.
  • the insulating sheets 21, 22, 23, and 24 are laminated as shown in FIG. 7 and integrated by thermocompression bonding or the like to obtain a laminated body 28.
  • the number of each insulating sheet is not specifically limited, It can set suitably according to the size etc. of a desired capacitor
  • the laminate 28 is fired.
  • the firing is performed while applying pressure in the thickness direction.
  • the cavity 3 is filled with a ceramic slurry 33 (for example, Al 2 O 3 slurry), and further separately prepared green sheets 31 and 32 (for example, Al 2 O 3 green sheets). Are disposed on the upper and lower surfaces of the insulating substrate 2.
  • the green sheets 31 and 32 are fired while a pressure is applied.
  • the magnitude of the pressure may be, for example, from 0.1 MPa to 10 MPa, preferably from 0.3 MPa to 1 MPa.
  • the sintered body in the cavity 3 and the layers derived from the green sheets 31 and 32 are removed.
  • a metal layer 8 is formed on the second external electrode 7.
  • the material constituting the metal layer 8 is not particularly limited, and examples thereof include metals such as Au, Pb, Pd, Ag, Sn, Ni, and Cu, and alloys thereof.
  • the material constituting the metal layer 8 is Cu.
  • the method for forming the metal layer 8 is not particularly limited, and for example, chemical vapor deposition (CVD: Chemical Vapor Deposition), electrolytic plating, electroless plating, vapor deposition, sputtering, conductive paste baking, or the like can be used. Electroless plating, vapor deposition, sputtering and the like are preferable. Moreover, you may use combining these methods. By using electrolytic plating, electroless plating, vapor deposition, or sputtering, a dense metal layer 8 can be obtained.
  • CVD Chemical Vapor Deposition
  • electrolytic plating electroless plating
  • vapor deposition vapor deposition
  • sputtering conductive paste baking
  • the metal layer 8 By forming the metal layer 8 as a dense layer, when the dielectric layer 12 and the upper electrode 13 are later formed by a vapor phase method, the upper electrode 13 penetrates the via 9 and the like and is exposed to the bottom surface of the capacitor, It is possible to prevent a short circuit between the upper electrode and the lower surface of the capacitor.
  • the thickness of the metal layer 8 is not particularly limited, but is preferably 0.1 ⁇ m to 100 ⁇ m, more preferably 0.5 ⁇ m to 50 ⁇ m, and even more preferably 0.5 ⁇ m to 10 ⁇ m, for example, 1 ⁇ m to 5 ⁇ m. .
  • the conductive porous substrate 11 is formed in the cavity 3 of the laminate 28.
  • the conductive porous substrate 11 is a metal sintered body.
  • the metal sintered body can be obtained by firing one or more metal powders.
  • the metal sintered body may be formed by firing metal powder in the cavity 3, or a metal sintered body obtained by separately firing metal powder may be placed in the cavity 3.
  • the metal sintered body is formed by firing metal powder in the cavity 3.
  • the metal powder added into the cavity may be either liquid phase synthetic powder or gas phase synthetic powder.
  • the said metal powder can be added to a cavity as a dispersion liquid, and this dispersion liquid may contain the 1 type (s) or 2 or more types of dispersing agent, a plasticizer, a solvent, and a binder component.
  • metal powder in the present specification means an aggregate of metal particles, which means that the particle size distribution substantially shows one peak. That is, even metal powders made of the same constituent element, such as Ni, are regarded as different metal powders if their particle size distributions are different.
  • the shape of the metal powder is not particularly limited, and may be spherical, elliptical, needle-like, rod-like, wire-like, or the like. Further, the metal powder may be subjected to a treatment for increasing the surface area.
  • the metal material constituting the metal powder is not particularly limited as long as it is conductive.
  • Al, Ti, Ta, Nb, Ni, Cu, W, Mo, Au, Ir, Ag, Rh, Ru, Co, Fe or an alloy thereof may be used.
  • the metal material constituting the metal powder is Ni, Cu, W, Mo, Au, Ir, Ag, Rh, Ru, Co or Fe.
  • the equivalent series resistance of the sintered metal body can be reduced.
  • these materials have a low specific resistance and a high melting point, they can be annealed at a high temperature, and a high-quality dielectric film can be obtained in the following steps.
  • the average particle diameter of the metal powder is not particularly limited, but may be, for example, 10 nm to 600 nm, preferably 30 nm to 400 nm, and more preferably 50 nm to 200 nm. By setting the average particle size within this range, the effective area that functions as a capacitor can be increased.
  • the metal sintered body can be obtained by mixing and firing at least two kinds of metal powders.
  • strength can be obtained, and high electrostatic capacitance density and high intensity
  • the mixture of metal powders includes at least 2, for example, 2, 3, or 4 metal powders having different average particle sizes.
  • the “average particle size” of the metal powder means the average particle size D50 (particle size equivalent to a volume-based cumulative percentage of 50%).
  • the average particle diameter D50 can be measured by, for example, a dynamic light scattering particle size analyzer (manufactured by Nikkiso Co., Ltd., UPA).
  • the average particle size of the sintered metal is obtained by processing the sintered metal into a thin piece by focused ion beam (FIB) processing, and a predetermined region (for example, 5 ⁇ m ⁇ 5 ⁇ m) of the thin piece sample, It can be obtained by photographing using a transmission electron microscope (TEM) and analyzing the obtained image.
  • FIB focused ion beam
  • TEM transmission electron microscope
  • the mixture of metal powders includes at least two metal powders having different melting points, such as two, three, or four metal powders.
  • the combination of the metal powder that is the main component of the metal sintered body and the metal powder having a low melting point is not particularly limited, and examples thereof include a combination of Ni and Cu.
  • the metal sintered body has a high gap.
  • the porosity of the sintered metal body may be preferably 30% or more, more preferably 40% or more.
  • 90% or less is preferable and 80% or less is more preferable.
  • porosity means the ratio of voids in the porous portion.
  • the porosity can be measured as follows.
  • the voids in the porous portion can be finally filled with a dielectric layer and an upper electrode in the process of manufacturing a capacitor.
  • the “porosity” does not take into account the material filled in this way.
  • the filled portion is also calculated as a void.
  • the porous portion is processed into a thin piece by focused ion beam (FIB) processing.
  • a predetermined region for example, 5 ⁇ m ⁇ 5 ⁇ m
  • TEM transmission electron microscope
  • the thickness of the metal sintered body, that is, the conductive porous substrate is not particularly limited and can be appropriately selected according to the purpose.
  • the thickness is 5 ⁇ m or more and 200 ⁇ m or less, preferably 10 ⁇ m or more and 100 ⁇ m or less, more preferably 20 ⁇ m or more. It can be 100 ⁇ m or less.
  • the thickness of the conductive porous substrate means the thickness of the porous portion when it is assumed that all the pores are filled.
  • the dielectric layer 12 and the upper electrode 13 are formed on the conductive porous substrate 11.
  • the material for forming the dielectric layer 12 is not particularly limited as long as it is insulative, but preferably, AlO x (eg, Al 2 O 3 ), SiO x (eg, SiO 2 ), AlTiO x , SiTiO x , HfO x, TaO x, ZrO x , LaO x, HfSiO x, ZrSiO x, TiZrO x, TiZrWO x, TiO x, SrTiO x, PbTiO x, BaTiO x, BaSrTiO x, BaCaTiO x, metal oxides such as SiAlO x; Metal nitrides such as AlN x , SiN x , AlScN x ; or metal oxynitrides such as AlO x N y , SiO x N y , HfSiO x N y , SiC x O
  • x, y, and z attached to O and N may be any value greater than 0, and the abundance ratio of each element including a metal element is arbitrary. Further, a layered compound composed of a plurality of layers having different dielectric layers may be used.
  • the thickness of the dielectric layer 12 is not particularly limited, but is preferably 3 nm to 100 nm, for example, and more preferably 5 nm to 50 nm. By setting the thickness of the dielectric layer to 3 nm or more, it is possible to increase the insulation and to reduce the leakage current. Further, by setting the thickness of the dielectric layer to 100 nm or less, it is possible to obtain a larger capacitance.
  • the dielectric layer 12 may be a single layer or a multilayer.
  • the dielectric layer 12 is preferably formed by a vapor phase method such as a vacuum evaporation method, a CVD method, a sputtering method, an atomic layer deposition method (ALD), a pulsed laser deposition method (PLD: Pulsed Laser Deposition), or the like. It is formed by a method using a supercritical fluid.
  • the ALD method is more preferable because a more uniform and dense film can be formed in the fine pores of the high porosity portion.
  • the material constituting the upper electrode 13 is not particularly limited as long as it is conductive, but Ni, Cu, Al, W, Ti, Ag, Au, Pt, Zn, Sn, Pb, Fe, Cr, Mo, Ru, Pd, Ta and alloys thereof such as CuNi, AuNi, AuSn, and metal nitrides such as TiN, TiAlN, TiON, TiAlON, and TaN, metal oxynitrides, conductive polymers (eg, PEDOT (poly (3,4) -Ethylenedioxythiophene))), polypyrrole, polyaniline) and the like, and TiN and TiON are preferred.
  • PEDOT poly (3,4) -Ethylenedioxythiophene
  • the thickness of the upper electrode 13 is not particularly limited, but is preferably 3 nm or more, for example, and more preferably 10 nm or more. By setting the thickness of the upper electrode to 3 nm or more, the resistance of the upper electrode itself can be reduced.
  • the upper electrode 13 may be a single layer or a multilayer.
  • the upper electrode 13 may be formed by an ALD method. By using the ALD method, the capacitance of the capacitor can be increased.
  • the top electrode may be coated by a method such as CVD, plating, bias sputtering, Sol-Gel method, or conductive polymer filling that can cover the dielectric layer and substantially fill the pores of the substrate. It may be formed.
  • a conductive film is formed on the dielectric layer by the ALD method, and the upper electrode is formed by filling the pores with a conductive material, preferably a substance having a lower electrical resistance, by another method. May be. With such a configuration, a higher capacity density and a lower equivalent series resistance (ESR: Equivalent Series Resistance) can be obtained efficiently.
  • ESR Equivalent Series Resistance
  • the first external electrode 5 is formed on the upper electrode 13.
  • the material constituting the first external electrode 5 is not particularly limited, and examples thereof include metals and alloys such as Au, Pb, Pd, Ag, Sn, Ni, and Cu, and conductive polymers.
  • the material constituting the first external electrode 5 is Cu.
  • the method for forming the first external electrode 5 is not particularly limited, and for example, CVD, electrolytic plating, electroless plating, vapor deposition, sputtering, baking of conductive paste, and the like can be used. Electrolytic plating, electroless plating, vapor deposition Sputtering or the like is preferable. Moreover, you may use combining these methods.
  • the thickness of the first external electrode 5 is not particularly limited, but it is preferably 0.1 ⁇ m or more and 100 ⁇ m or less, more preferably 0.5 ⁇ m or more and 50 ⁇ m or less, and still more preferably 0.00 on the basis of the upper surface of the conductive porous substrate. It may be 5 ⁇ m or more and 10 ⁇ m or less, for example, 1 ⁇ m or more and 5 ⁇ m or less.
  • the collective substrate 29 including the plurality of capacitors 1a is manufactured by the above process.
  • the collective substrate 29 is divided into each element.
  • the collective substrate 29 can be cut along a straight line indicated by x and y and divided into each element. That is, in the capacitor of the present invention, at least one of the side surfaces, preferably the entire side surface may be a cut surface.
  • the division of the aggregate substrate can be performed using a scriber, a dicing blade, various laser devices, various blades, and a mold.
  • the capacitor of the present invention can be manufactured as a collective substrate, the size and capacitance of the entire capacitor can be easily adjusted by adjusting the size of each block.
  • FIG. 9 shows a schematic cross-sectional view of a capacitor 1b according to another embodiment of the present invention.
  • the capacitor 1 b of the present embodiment is characterized in that the cavity 43 of the insulating base 42 is provided so as to penetrate the insulating base 42.
  • the capacitor 1b includes an insulating base 42 having a through-cavity 43, a cavity electrode 46 that seals the bottom of the through-cavity 43, a capacitance forming portion 44 provided in the cavity, and capacitance formation.
  • a first external electrode 45 on the portion 44 is provided.
  • the capacitance forming portion 44 includes a conductive porous substrate that functions as a lower electrode, a dielectric layer positioned on the conductive porous substrate, and a dielectric And an upper electrode located on the layer.
  • the capacitor 1b by applying a voltage between the first external electrode 45 and the cavity electrode 46, a voltage is applied between the conductive porous substrate of the capacitance forming portion 44 and the upper electrode, and the dielectric layer is applied to the dielectric layer. Charge can be accumulated.
  • the thickness of the capacitor can be reduced.
  • the capacitor of the present invention has been described based on the capacitors 1a and 1b.
  • the capacitor of the present invention is not limited to the above-described embodiment and manufacturing method, and the design can be changed without departing from the gist of the present invention. is there.
  • the capacitor 1a has a cavity electrode at the bottom of the cavity
  • the capacitor of the present invention may not have a cavity electrode.
  • the conductive porous substrate and the via are directly electrically connected.
  • the capacitor 1a has three vias 9.
  • the number of vias may be one or two, or four or more. Increasing the number of vias increases the contact area between the via, the cavity electrode, and the second external electrode, and reduces the ESR of the capacitor. Further, contact failure between the via, the cavity electrode, and the second external electrode can be suppressed.
  • the opening of the cavity extends over the entire cavity.
  • the opening may be a part of the bottom of the cavity.
  • the capacitors 1a and 1b have only one capacitance forming portion, but the present invention is not limited to this.
  • the number of capacitance forming units may be two or more, for example, two, three, or four.
  • the capacitance can be easily adjusted.
  • the strength of the capacitor can be increased.
  • the cavity electrode or via of the capacitor of the present invention may have a dense structure or a coarse structure.
  • the dense structure means a dense structure in which a gas, for example, a gas used when manufacturing a dielectric layer or an upper electrode by a vapor phase method does not penetrate
  • the coarse structure means a coarse structure through which the gas penetrates. To do.
  • the strength of the capacitor can be increased.
  • the cavity electrode or the via can also function as the capacitance forming portion, and the capacitance of the entire capacitor can be increased.
  • the method of manufacturing the capacitor aggregate substrate of the present invention is not limited to the above.
  • the insulating substrate does not need to be obtained as a laminate, and the cavity or the through hole may be formed by scraping the insulating substrate with a laser or the like.
  • Examples of the conductive porous substrate include a conductive porous substrate in addition to the above-described sintered metal.
  • the conductive porous substrate has a porous structure, and its material and configuration are not limited as long as the surface is conductive.
  • examples of the conductive porous substrate include a porous metal substrate, a substrate in which a conductive layer is formed on the surface of a porous silica material, a porous carbon material, or a porous ceramic sintered body.
  • the conductive porous substrate is a porous metal substrate.
  • the metal constituting the porous metal substrate examples include aluminum, tantalum, nickel, copper, titanium, niobium and iron metals, and alloys such as stainless steel and duralumin.
  • the porous metal substrate is an aluminum porous substrate.
  • a separately manufactured capacitor may be incorporated in the cavity.
  • Such a capacitor is not particularly limited, and various capacitors can be used.
  • a multilayer capacitor, a winding capacitor, a film capacitor, an electrolytic capacitor, or the like can be used.
  • a glass ceramic powder obtained by mixing a CaO—Al 2 O 3 —SiO 2 —B 2 O 3 glass powder (50 wt%) and an Al 2 O 3 powder (50 wt%) as a glass ceramic raw material powder.
  • a body was prepared (average particle size: about 2 ⁇ m).
  • a dioxyl phthalate plasticizer, an acrylic resin binder, and a solvent are added to the glass ceramic powder, and the mixture is thoroughly kneaded to prepare a slurry having a viscosity of 2,000 mPa ⁇ s.
  • the thickness is 0.1 mm by the doctor blade method.
  • a glass ceramic green sheet was formed.
  • the glass ceramic green sheet was processed into a predetermined shape using a punching machine.
  • a plurality of via holes (0.3 mm ⁇ ) were punched and formed at predetermined positions, and each via hole was filled with Cu paste.
  • Cu paste was screen-printed in the predetermined location.
  • the obtained glass ceramic green sheets were laminated as shown in FIG. 7 to obtain a green sheet laminate.
  • the obtained green sheet laminate was integrated by thermocompression bonding under conditions of 110 ° C. and 10 MPa.
  • the outer dimensions of the obtained green sheet laminate were 100 ⁇ 100 mm square, and the dimensions of the cavity were 1.4 ⁇ 0.6 mm.
  • the green sheet laminate had 6438 cavities.
  • Al 2 O 3 powder having an average particle size of about 0.3 [mu] m was added a mixture of ethyl cellulose resin dissolved in alcohol, Al 2 O 3 solid content of the powder is 69% Al 2 O A paste containing 3 powders was prepared.
  • an organic solvent, an acrylic binder, a plasticizer, and a dispersant are added to the Al 2 O 3 powder, mixed with a ball mill to form a slurry, and this slurry is used to form an Al 2 O 3 green sheet by a doctor blade method. Formed.
  • the obtained Al 2 O 3 green sheets were arranged on both the upper and lower surfaces of the green sheet laminate (see FIG. 10).
  • the green sheet laminate and the Al 2 O 3 and Al 2 O 3 green sheets in the cavity were used in an electric continuous belt furnace. Then, it was calcined by holding at 900 ° C. for 20 minutes in the reduction. Next, the Al 2 O 3 powder on the upper and lower surfaces of the obtained sintered laminate was removed by blasting glass beads. As a result, a multilayer substrate having a structure as shown in FIG. 7 was obtained.
  • a Cu layer was formed by electroless plating so as to cover the second external electrode of the obtained multilayer substrate.
  • Ni metal powder having an average particle diameter of 200 nm was dispersed in a ball mill using 1 mm ⁇ zirconia balls in ethanol.
  • Polyvinyl alcohol was added to this dispersion to prepare a metal powder slurry.
  • This slurry was added into each cavity using a dispenser and dried.
  • the thickness of the metal powder layer after drying was about 30 ⁇ m.
  • the metal substrate on which the metal powder layer was formed in the cavity was degreased at 200 to 300 ° C. in a firing furnace and then heat-treated at 300 to 650 ° C. for 5 minutes in an N 2 atmosphere to obtain a sintered metal body.
  • an ALD method was used to form an AlOx film (25 nm) on the metal sintered body to form a dielectric layer.
  • a Ru film (20 nm) was formed by ALD to form an upper electrode.
  • a first external electrode was formed on the upper electrode by Cu plating. As a result, a capacitor aggregate substrate of the present invention was obtained.
  • the capacitor of the present invention has a high capacitance, it is suitably used for various electronic devices.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

La présente invention concerne un condensateur qui est configuré pour comprendre un substrat isolant, un matériau de base poreux conducteur comprenant une partie poreuse, une couche diélectrique qui est positionnée sur la partie poreuse, et une électrode supérieure qui est positionnée sur la couche diélectrique. Le substrat isolant est pourvu d'une cavité ; et le matériau de base poreux conducteur, la couche diélectrique et l'électrode supérieure sont disposés à l'intérieur de la cavité.
PCT/JP2018/004530 2017-02-14 2018-02-09 Condensateur WO2018151029A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017025274 2017-02-14
JP2017-025274 2017-02-14

Publications (1)

Publication Number Publication Date
WO2018151029A1 true WO2018151029A1 (fr) 2018-08-23

Family

ID=63169419

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2018/004530 WO2018151029A1 (fr) 2017-02-14 2018-02-09 Condensateur

Country Status (1)

Country Link
WO (1) WO2018151029A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115039190A (zh) * 2020-03-24 2022-09-09 株式会社村田制作所 电容器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001203455A (ja) * 1999-11-12 2001-07-27 Matsushita Electric Ind Co Ltd コンデンサ搭載金属箔およびその製造方法、ならびに回路基板およびその製造方法
US20090122460A1 (en) * 2007-11-12 2009-05-14 Alexander Gschwandtner Semiconductor Device and Method for Producing the Same
US20100283122A1 (en) * 2009-05-05 2010-11-11 Pulugurtha Markondeyaraj Systems and methods for providing high-density capacitors
US20150028449A1 (en) * 2013-07-25 2015-01-29 International Business Machines Corporation Nanoparticles for making supercapacitor and diode structures

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001203455A (ja) * 1999-11-12 2001-07-27 Matsushita Electric Ind Co Ltd コンデンサ搭載金属箔およびその製造方法、ならびに回路基板およびその製造方法
US20090122460A1 (en) * 2007-11-12 2009-05-14 Alexander Gschwandtner Semiconductor Device and Method for Producing the Same
US20100283122A1 (en) * 2009-05-05 2010-11-11 Pulugurtha Markondeyaraj Systems and methods for providing high-density capacitors
US20150028449A1 (en) * 2013-07-25 2015-01-29 International Business Machines Corporation Nanoparticles for making supercapacitor and diode structures

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115039190A (zh) * 2020-03-24 2022-09-09 株式会社村田制作所 电容器
CN115039190B (zh) * 2020-03-24 2023-08-25 株式会社村田制作所 电容器

Similar Documents

Publication Publication Date Title
US10622152B2 (en) Multi-layer ceramic capacitor and method of producing the same
US9136058B2 (en) Laminated ceramic electronic component and manufacturing method therefor
JP2018107239A (ja) 積層セラミックコンデンサ及びその製造方法
JP2017011172A (ja) 積層セラミックコンデンサ及びその製造方法
JP7310709B2 (ja) 積層型電子部品および積層型電子部品の製造方法
US20180158611A1 (en) Capacitor and method for manufacturing the same
TWI596630B (zh) 電容器
KR20190131424A (ko) 도전성 페이스트
WO2016181865A1 (fr) Condensateur et son procédé de fabrication
JP2021019100A (ja) 積層型電子部品
TWI597747B (zh) Capacitor and its manufacturing method
JP6954325B2 (ja) コンデンサおよびその製造方法
WO2018151029A1 (fr) Condensateur
JP7283440B2 (ja) 積層型電子部品および積層型電子部品の製造方法
JP7215459B2 (ja) 積層型電子部品
WO2018151028A1 (fr) Condensateur
JP7338310B2 (ja) 積層型電子部品
WO2018151025A1 (fr) Condensateur
JP4826881B2 (ja) 導電性ペースト、及び積層セラミック電子部品の製造方法、並びに積層セラミック電子部品
JP2016192477A (ja) 積層セラミック電子部品
WO2018174132A1 (fr) Condensateur
TW201711069A (zh) 電容器
WO2020174836A1 (fr) Condensateur
JP2023098834A (ja) 積層型電子部品
KR20210052252A (ko) 도전성 페이스트 및 적층형 전자부품

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18753541

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18753541

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载