WO2018148909A1 - Method for fabricating tunneling field effect transistor - Google Patents

Abstract

A method for fabricating a tunneling field effect transistor comprises: fabricating a main spindle (202) on a substrate (201); covering a first passivation protective layer (203) onto a sidewall surface of the main spindle (202); forming a doped region (204) of a first doping type in an area that is not covered by the first passivation protective layer (203) and the main spindle (202); covering a second passivation protective layer (205) onto the first passivation protective layer (203); forming a source region (206) of a second doping type in an area of the doped region (204) that is not covered by the second passivation protective layer (205), the second doping type being opposite to the first doping type; removing the main spindle (202), and forming a drain region (209) of the first doping type in an area previously occupied by the removed main spindle (202); and removing the first passivation protective layer (203) and the second passivation protective layer (205), and fabricating a metal gate (210) in an area previously occupied by the removed first passivation protective layer (203) and the second passivation protective layer (205). In this way, the limitation of a photolithographic process can be overcome to realize a small gate width, and a flexible design of a doping pocket can be realized, making it possible to be compatible with conventional semiconductor processes.

Description

Method of making tunneling field effect transistor Technical field

The present application relates to the field of semiconductor device technologies, and in particular, to a method for fabricating a tunneling field effect transistor.

Background technique

With the development of integrated circuit technology, the size of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is continuously reduced according to "Moore's Law". For example, the gate length of MOSFET is reduced to below 45 nm. . Since the Subthreshold Swing (SS) of the MOSFET is limited by the Boltzmann heat distribution of the carrier and cannot be synchronously reduced as the device size shrinks, the power consumption of the MOSFET circuit is continuously increased. The energy consumption continues to rise, and the power consumption density of the chip increases sharply, which seriously hinders the application of the chip in system integration.

In order to adapt to the development trend of integrated circuits, Tunneling Field Effect Transistor (TFET) has been proposed as a potential replacement for MOSFETs. The TFET is a gate-controlled reverse-biased P-type doped-intrinsic-n-type doped junction (p-i-n junction) device with opposite source and drain doping types. For N-type TFETs, the source region is heavily P-doped and the drain region is heavily doped with N-type; for P-type TFETs, the source region is heavily doped with N-type and the drain region is doped with P-type. The source and drain doping types are different such that the TFET is formed to be different from the MOSFET's operating mechanism, ie, the carrier quantum tunneling mechanism, which may also be referred to as band tunneling. Due to the different working mechanism of the MOSFET, the subthreshold swing of the TFET is not limited by the carrier thermal distribution. In theory, the TFET can achieve a subthreshold swing of less than 60mV/dec and can operate at a lower driving voltage. The static power consumption of the device can be reduced.

TFETs are roughly classified into point tunneling and line tunneling in terms of tunneling. A TFET in which the tunneling mode is a line tunneling is characterized in that a doping pocket (Pocket) of a type opposite to that of the source region is inserted in the source region of the TFET. Since the line tunneling provides a larger tunneling area, the tunneling probability can be increased, and the turn-on current can be increased without significantly increasing the leakage current.

At present, there is a lack of a scheme for fabricating a TFET having a doped pocket structure, and in the prior art, a conventional lithography technique is generally used to fabricate a TFET, but when the gate width of the TFET requires a small size, the source is implemented according to a photolithography process. Different doping with the drain is very difficult.

Summary of the invention

The present application provides a method for fabricating a tunneling field effect transistor. By using a self-aligned process to fabricate a tunneling field effect transistor, the gate width of a smaller size can be overcome by the limitation of the photolithography process, and the doping can also be achieved. The flexible design of the miscellaneous pockets is compatible with traditional semiconductor processes and has good feasibility and repeatability, which can be applied to the actual manufacturing process of tunneling field effect transistors.

In a first aspect, a method of fabricating a tunneling field effect transistor is provided, the method comprising: fabricating a spindle on a first surface of a substrate, the axis of the spindle being perpendicular to the first surface; Covering a first passivation protective layer on a sidewall surface; forming a doped region having a first doping type in a region where the first surface is not covered by the first passivation protective layer and the main axis; The surface of the first passivation protective layer is covered with a second passivation protective layer; a source region having a second doping type is formed in a region where the doped region is not covered by the second passivation protective layer, a region of the doped region covered by the second passivation protective layer is a doped pocket having the first doping type in close proximity to the source region, the second doping type and the first doping region One doping type is reversed; the spindle is removed and removed Forming a drain region having the first doping type on a region of the main shaft; removing the first passivation protective layer and the second passivation protective layer, and removing the first passivation protection A metal gate is formed on the region of the layer and the second passivation protective layer.

As can be seen from the above, in the method for fabricating a tunneling field effect transistor provided by the present application, the position and size of the main shaft and the thickness of the first passivation protective layer determine the position of the doping pocket, and the thickness of the second passivation protective layer determines The size of the doped pocket; the position and size of the spindle determine the position of the metal gate. The thickness of the first passivation protective layer and the second passivation protective layer determine the size of the metal gate; the position and size of the spindle, and The thickness of a passivation protective layer and a second passivation protective layer determines the position of the source region; the position and size of the spindle determine the position and size of the drain region. In other words, the present application realizes a more precise positioning of the source region (source), the drain region (drain), and the metal gate of the tunneling field effect transistor through the self-aligned process, and realizes the tunneling field. The doped pocket is inserted into the effect transistor so that a smaller size of the gate width can be realized without being limited by the photolithography process, and a flexible design of the doped pocket can also be achieved. It will be appreciated that by inserting a doped pocket (also referred to as a Pocket layer) of opposite doping type in the source region of the tunneling field effect transistor, the tunneling probability and the turn-on current can be increased.

In practical applications, the doping pocket conforming to the application requirement can be designed by controlling the position and size of the main shaft, the thickness of the first passivation protective layer and the second passivation protective layer; by controlling the first passivation protective layer and the second blunt The thickness of the protective layer can achieve a smaller gate width.

Therefore, the method for fabricating a tunneling field effect transistor provided by the present application can achieve a smaller size gate width by overcoming the limitation of the photolithography process by using a self-aligned process to form a tunneling field effect transistor, and can also realize The flexible design of the doped pockets is compatible with traditional semiconductor processes and has good feasibility and repeatability for use in the actual fabrication of tunneling field effect transistors.

In conjunction with the first aspect, in a possible implementation manner of the first aspect, the fabricting the metal gate on the region where the first passivation protective layer and the second passivation protective layer are removed, including: And removing the region of the first passivation protective layer and the second passivation protective layer for etching; forming the metal gate on the region after the etching.

Specifically, the means of etching may be wet etching using hydrofluoric acid or a similar solution, or dry etching of a CF series. It should be understood that by etching the region where the first passivation protective layer and the second passivation layer are removed, the overlapping area of the gate and the source region can be increased, thereby increasing the tunneling area and thereby increasing the turn-on current.

In conjunction with the first aspect, in a possible implementation of the first aspect, before the removing the spindle, the method further comprises: covering the region of the source region on the first surface with an oxide; Before the removing the first passivation protective layer and the second passivation protective layer, the method further comprises: covering an oxide on a region of the drain region located on the first surface.

It should be understood that the region where the source region is located on the first surface covers the oxide in order to protect the source region from the subsequent doping step; the region where the drain region is located on the first surface is covered with oxide to protect the drain region from being protected. The effect of subsequent doping steps.

In conjunction with the first aspect, in a possible implementation of the first aspect, the spindle is made of polysilicon.

In combination with the first aspect, in a possible implementation manner of the first aspect, the passivation protective layer is made of any one of the following materials: silicon nitride, silicon dioxide or silicon oxynitride.

In conjunction with the first aspect, in some possible implementations of the first aspect, the passivation protective layer is formed in an isotropic deposition and etching.

In a second aspect, a method of fabricating a tunneling field effect transistor is provided, the method comprising: on a first substrate Making a first major axis on the first surface and a second main axis on the second surface of the second substrate, the first surface being parallel to the second surface, the first main axis and the axis of the second main axis The core is perpendicular to the first surface; covering the first passivation protective layer on the sidewall surfaces of the first main axis and the second main axis respectively; the first passivation is not performed on the first surface The protective layer is N-type doped on the region covered by the first main axis to form a first doped region; the second passivation protective layer is covered on the surface of the first passivation protective layer; P-doping is performed on the doped region not covered by the second passivation protective layer to form a first source region, and the region of the first doped region covered by the second passivation protective layer is N a doped first doped pocket, P-doped on the second surface not covered by the first passivation layer, the second passivation protective layer and the second main axis, Forming a second drain region; removing the first major axis and the second major axis, and removing the region of the second major axis at the second surface Performing P-type doping on the domain to form a second doped region; covering a surface of the first passivation protective layer away from the second passivation protective layer with a third passivation protective layer; The region not covered by the third passivation protective layer is N-type doped to form a second source region, and the region of the second doped region covered by the third passivation protective layer is P-type doped a second doping pocket, performing N-type doping on a region of the first surface from which the first major axis is removed to form a first drain region; removing the first passivation protective layer, the second passivation protection a layer and the third passivation protective layer, and forming a metal gate on a region where the first passivation protective layer, the second passivation protective layer and the third passivation protective layer are removed, wherein The type of tunneling field effect transistor formed on the first substrate is pnin, and the type of tunneling field effect transistor formed on the second substrate is npip.

As can be seen from the above, in the method for fabricating a tunneling field effect transistor having a doped pocket structure provided by the present application, the position and size of the first major axis and the thickness of the first passivation protective layer determine the position of the first doped pocket. The thickness of the second passivation protective layer determines the size of the first doped pocket; the position and size of the first major axis, and the thickness of the first, second and third passivation protective layers determine the metal gate on the first substrate Position and size; the position and size of the second spindle determine the position of the second doping pocket, the thickness of the third passivation layer determines the size of the second doping pocket; the position and size of the second spindle, first The thickness of the second and third passivation protective layers determines the position and size of the metal gate on the second substrate.

In practical applications, the gate width of the smaller size can be realized by controlling the position and size of the first main shaft and the second main shaft, and the thicknesses of the first, second and third passivation protective layers; by controlling the second passivation protection The thickness of the layer is designed to design a doping pocket of a pnin tunneling field effect transistor; the doping pocket of the npip type tunneling field effect transistor is designed by controlling the thickness of the third passivation protective layer.

The method provided by the present application can simultaneously realize the tunneling field effect transistors of the pnin type and the npip type, can realize the gate width of a smaller size by overcoming the limitation of the photolithography process, and can also realize the flexible design of the doping pocket, and can The traditional semiconductor process is compatible, has good feasibility and repeatability, and can be applied to the actual manufacturing process of tunneling field effect transistors.

With reference to the second aspect, in a possible implementation manner of the second aspect, the removing the first passivation protective layer, the second passivation protective layer, and the third passivation protective layer Fabricating a metal gate, comprising: etching on the region where the first passivation protective layer, the second passivation protective layer, and the third passivation protective layer are removed; after the etching A metal gate is fabricated on the area.

With reference to the second aspect, in a possible implementation manner of the second aspect, before the removing the first main axis and the second main axis, the method further includes: the first source area is located in the first a region of a surface is covered with an oxide, and an oxide is covered on a region of the second drain region on the second surface; and the first passivation protective layer and the second passivation protective layer are removed Before the third passivation protective layer, the method further includes: at the A drain region is overlying the oxide on the region of the first surface and overlying the region of the second source region on the second surface.

In conjunction with the second aspect, in a possible implementation manner of the second aspect, the material of the first main shaft and the second main shaft is polysilicon.

In combination with the second aspect, in a possible implementation manner of the second aspect, the passivation protective layer is made of any one of the following materials: silicon nitride, silicon dioxide or silicon oxynitride.

In conjunction with the second aspect, in some possible implementations of the second aspect, the passivation protective layer is formed in an isotropic deposition and etching.

DRAWINGS

FIG. 1 is a schematic flowchart of a method for fabricating a tunneling field effect transistor according to an embodiment of the present invention.

FIG. 2 to FIG. 10 are schematic diagrams showing processes of fabricating a tunneling field effect transistor according to an embodiment of the present invention.

FIG. 11 is a schematic flowchart of a method for simultaneously fabricating p-n-i-n type and n-p-i-p type tunneling field effect transistors according to an embodiment of the present invention.

FIG. 12 to FIG. 22 are schematic diagrams showing processes of simultaneously fabricating p-n-i-n type and n-p-i-p type tunneling field effect transistors according to an embodiment of the present invention.

detailed description

The technical solutions of the embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a schematic flowchart of a method 100 for fabricating a tunneling field effect transistor according to an embodiment of the present invention. The method 100 includes the following steps:

110. A spindle is fabricated on the first surface of the substrate, the axis of the spindle being perpendicular to the first surface.

120, covering a first passivation protective layer on a sidewall surface of the main shaft.

130. Form a doped region having a first doping type in a region where the first surface is not covered by the first passivation protective layer and the main axis.

140, covering a surface of the first passivation protective layer with a second passivation protective layer.

150. Form a source region having a second doping type in a region where the doping region is not covered by the second passivation protective layer, and the region covered by the second passivation protective layer is adjacent to the source A doped pocket of the first doping type is opposite to the first doping type.

Specifically, the doped region formed in step 130 is transformed into a source region having the second doping type and a doping pocket having the first doping type adjacent to the source region after step 140 and step 150. (Pocket).

160, removing the spindle, and forming a drain region having the first doping type on a region where the spindle is removed

It should be understood that the doping type of the doping pocket is opposite to the type of the source region, the doping type of the doping pocket is consistent with the doping type of the drain region, and the doping pocket is adjacent to the source region.

170. The first passivation protective layer and the second passivation protective layer are removed, and a metal gate is formed on a region where the first passivation protective layer and the second passivation protective layer are removed.

It should be understood that the method 100 further includes forming a source on the source region and forming a drain on the drain region.

It should also be understood that the tunneling field effect transistor fabricated by the method 100 includes: an insulating substrate, a source region, a doping pocket, a drain region, and a metal gate adjacent to the source region and having opposite doping types to the source region, it being understood The tunneling field effect transistor further includes a source on the source region and a drain on the drain region.

As described above, in the method for fabricating a tunneling field effect transistor having a doped pocket structure provided by the embodiment of the present invention, the position and size of the main shaft and the thickness of the first passivation protective layer determine the position of the doped pocket, and second The thickness of the passivation protective layer determines the size of the doped pocket; the position and size of the main axis determine the position of the metal gate, and the thickness of the first passivation protective layer and the second passivation protective layer determine the size of the metal gate; The position and size of the main shaft, and the thickness of the first passivation protective layer and the second passivation protective layer determine the position of the source region; the position and size of the main shaft determine the position and size of the drain region.

In other words, in the embodiment of the present invention, the source region (source), the drain region (drain), and the metal gate of the tunneling field effect transistor are accurately positioned by a self-aligned process. In practical applications, By controlling the thickness of the first passivation protective layer and the second passivation protective layer, a gate size of a smaller size can be realized, which can be controlled by controlling the position and size of the main shaft, the first passivation protective layer and the second passivation protective layer. Thickness, designed to meet the application requirements of the doping pocket.

Therefore, the method for fabricating a tunneling field effect transistor provided by the embodiment of the present invention can achieve a smaller size of the gate width by overcoming the limitation of the photolithography process by using a self-aligned process to fabricate a tunneling field effect transistor. The flexible design of the doping pocket can be realized, it is compatible with the traditional semiconductor process, and has good feasibility and repeatability, so that it can be applied to the actual manufacturing process of the tunneling field effect transistor.

Optionally, in the above embodiment, the step 170 is performed on the area where the first passivation protective layer and the second passivation protective layer are removed, and the method includes:

Etching is performed on a region where the first passivation protective layer and the second passivation layer are removed;

A metal gate is formed on the area after etching.

Specifically, the means of etching may be wet etching using hydrofluoric acid or a similar solution, or dry etching of a CF series. It should be understood that by etching the region where the first passivation protective layer and the second passivation layer are removed, the overlapping area of the gate and the source region can be increased, thereby increasing the tunneling area and thereby increasing the turn-on current.

Optionally, in the above embodiment, before removing the spindle in step 160, the method 100 further includes: covering the region of the source region on the first surface with an oxide;

Before removing the first passivation protective layer and the second passivation protective layer in step 170, the method 100 further includes: covering the oxide on the region of the drain region on the first surface.

It should be understood that the region where the source region is located on the first surface covers the oxide in order to protect the source region from the subsequent doping step; the region where the drain region is located on the first surface is covered with oxide to protect the drain region from being protected. The effect of subsequent doping steps.

Specifically, the oxide is, for example, silicon dioxide (SiO 2 ), or the oxide may be FCVD (Flowable CVD), SOG (Spin on Glass), HDP (High Density Plasma CVD), or HARP (High-Aspect- Ratio Process CVD) is a similar material.

Specifically, assuming that the first doping type is an N type and the second doping type is a P type, in the step S130, the first surface is not covered by the first passivation protective layer and the main axis (denoted as The specific manner of forming the doped region having the first doping type is: ion implantation of the region 1 by using an N+ mask, or etching and epitaxy of the region 1 by a hard film method to form an N-type doping. Doped region

In step 160, on the region where the main axis is removed (referred to as region 2), a specific manner of forming the drain region having the first doping type is: ion implantation of region 2 using an N+ mask, or utilization Etching and epitaxy of region 2 in a hard film manner to form an N-doped drain region;

In step 150, a specific way of forming a source region having a second doping type in a region where the doped region is not covered by the second passivation protective layer (referred to as region 3) is: using a P+ reticle pair region 3 do ion implantation, or use The region 3 is etched and epitaxially formed in a hard film manner to form a P-doped source region.

Specifically, the material of the main shaft is polysilicon.

Specifically, the material of the first passivation protective layer, the second passivation protective layer and the third passivation protective layer is any one of the following materials: silicon nitride, silicon dioxide or silicon oxynitride.

Specifically, the passivation protective layer is formed in an isotropic deposition and etching.

FIG. 2 to FIG. 10 are schematic diagrams showing a process of a method 100 for fabricating a tunneling field effect transistor according to an embodiment of the present invention.

Step 110, as shown in FIG. 2, a spindle 202 is formed on the first surface of the substrate 201, the axis of the spindle 202 being perpendicular to the first surface.

Specifically, the substrate 201 may be a substrate of a Fin structure. For example, the material of the substrate 201 may be poly-silicon or the like. The surface of the substrate may be covered with a thin oxide layer.

The main axis 202 is formed on the substrate 201 by depositing on the first surface of the substrate 201 to form the spindle 202. The material of the main shaft 202 may be polysilicon.

Step 120, as shown in FIG. 3, covers the first passivation protective layer 203 on the sidewall surface of the main shaft 202.

Specifically, the first passivation protective layer 203 is made of a nitride, and may be, for example, silicon nitride (Si 3 N 4 ), silicon dioxide (SiO 2 ), or silicon oxynitride (SiON).

Taking the material of the first passivation protective layer 203 as silicon nitride as an example, the first passivation protective layer 203 is covered on the sidewall surface of the main shaft 202 by depositing silicon nitride on the sidewall surface of the main shaft 202. Then, an isotropic etch is used to create a spacer or sidewall (ie, a first passivation protective layer).

In the embodiment of the present invention, the first passivation protective layer may also be referred to as a first nitride spacer.

Step 130, as shown in FIG. 4, forming a doping having a first doping type on a region of the first surface of the substrate 201 that is not covered by the main axis 202 and the first passivation protective layer 203 (referred to as region 1). Area 204.

It should be noted that the first doping type mentioned in the embodiment of the present invention may be N-type or P-type, and if the first doping type is N-type, the second doping type appearing below For the P type, if the first doping type is P type, the second doping type appearing below is N type.

Specifically, taking the first doping type as the N-type as an example, the specific manner of forming the doping region 204 is: using the existing N+ mask to ion-implant the region 1 to form an N-type doping, or to utilize The Hard mask method etches and epitaxes the region 1 to form an N-type hetero doping.

It should be noted that the doped region 204 formed in this step will subsequently form a doped pocket (Pocket layer) adjacent to the source region.

When the doping region 204 is formed by ion implantation, the energy of the ion implantation can control the depth of doping of the doping region 204. If the doping depth is deep, a "Full Pocket layer" is formed later, if the doping depth is shallow The follow-up will form the "Split Pocket Layer".

Step 140, as shown in FIG. 5, covers the second passivation protective layer 205 on the surface of the first passivation protective layer 203.

Specifically, the material of the second passivation protective layer 205 is also a nitride such as silicon nitride (Si3N4), silicon dioxide (SiO2) or silicon oxynitride (SiON).

Taking the material of the second passivation protective layer 205 as silicon nitride as an example, the second passivation protective layer 205 is formed by depositing silicon nitride on the sidewall of the first passivation protective layer 203 away from the main axis 202. A spacer or sidewall (i.e., second passivation protective layer 205) is then created using an isotropic etch.

In the embodiment of the present invention, the second passivation protective layer 205 may also be referred to as a “second nitride spacer”.

Step 150, as shown in FIG. 6, in the region where the doping region 204 is not covered by the second passivation protective layer 205 (denoted as a region) Domain 2) forms a source region 206 having a second doping type, the second doping type being opposite to the first doping type, and the remaining portion of the doping region 204 not formed as the source region 206 is defined as being in close proximity to the source region A doped pocket 207 of the first doping type is provided.

Taking the first doping type as N-type and the second doping type as P-type as an example, the specific way of forming the source region 206 is to use the existing P+ reticle to implant the region 2 into the P-type doping. The P-type hetero-doping is formed by etching and epitaxy of the region 2 by a Hard mask method to form a P-type doped source region 206.

If the first doping type is P-type and the second doping type is N-type, an N-doped source region 206 is formed in this step.

As can be seen from FIG. 6, the thickness of the second passivation protective layer 205 determines the size of the doped pocket 207. Specifically, the thickness of the second passivation protective layer 205 is the width of the doped pocket 207 in the view shown in FIG.

Step 160, as shown in Figures 7 and 8, removes the spindle 202 and forms a drain region 209 having a first doping type on the region where the spindle 202 is removed (denoted as region 3).

Specifically, as shown in FIG. 7, first, the oxide region 208 is overlaid on the region of the source region 206 on the first surface of the substrate 201, in other words, the oxide 208 is filled in the second passivation protective layer 205 and the source region. 206 is located in a space enclosed by the area of the first surface to protect the source region 206. The oxide 208 may be, for example, silicon dioxide (SiO2), or may be a similar material such as FCVD, SOG, HDP or HARP. It should be understood that after the oxide 208 is filled over the source region 206, the surface of the entire article can then be planarized by a planarization process, for example, etching and chemical mechanical polishing can be used to achieve a planarization process.

As shown in FIG. 8, after the oxide 208 is filled over the source region 206, the spindle 202 is removed such that the region of the substrate 201 that was originally covered by the spindle 202 (ie, region 3) is exposed, and the region 3 is first The doping type is doped to form a drain region 209 having a first doping type.

Specifically, taking the first doping type as the N-type as an example, the specific manner of forming the drain region 209 is: using the existing N+ mask to ion-implant the region 3 to form an N-type doping, or using a Hard mask. The region 3 is etched and epitaxially formed to form an N-type hetero-doping to form an N-doped drain region 208.

Step 207, as shown in FIG. 9 and FIG. 10, removing the first passivation protective layer 203 and the second passivation protective layer 205, and removing the regions of the first passivation protective layer 203 and the second passivation protective layer 205 ( A metal gate 210 is formed on the region 4).

Specifically, as shown in FIG. 9, first, the oxide 208 is overlaid on the region of the drain region 209 on the first surface of the substrate 201, in other words, the oxide 208 is filled in the first passivation protective layer 203 away from the second. The surface of the passivation protective layer 205 and the region of the drain region 209 located at the first surface are protected to protect the drain region 209. It should also be understood that after the oxide 208 is filled over the drain region 209, the surface of the entire article can then be planarized by a planarization process, for example, etching and chemical mechanical polishing can be used to achieve a planarization process.

As shown in FIG. 10, after the oxide 208 is filled over the drain region 209, the first passivation protective layer 203 and the second passivation protective layer 205 are removed, so that the substrate 201 is originally protected by the first passivation protective layer 203 and The area covered by the two passivation protective layer 205 (ie, the area 4) is exposed, and the metal gate 210 is formed on the area 4.

It should be understood that the region of the substrate 201 that was originally covered by the first passivation protection layer 203 and the second passivation protection layer 205 is the gate underlayer of the tunneling field effect transistor.

Preferably, in some embodiments, after removing the first passivation protective layer 203 and the second passivation protective layer 205, the region 4 may be first etched, for example, wet etching using hydrofluoric acid or a similar solution. Or a dry etch of the CF series; then a metal gate 210 is formed over the area after etching.

It should also be understood that etching the region where the first passivation protective layer 203 and the second passivation protective layer 205 are removed can enlarge the underlying area of the gate, thereby increasing the overlapping area of the gate and the source region (source), thereby further The on-state current can be increased.

It should also be understood that oxide 208 for protecting source region 206 and drain region 209 may be removed after fabrication of metal gate 210 is completed.

Thus, the fabrication of the tunneling field effect transistor is completed. As can be seen from FIG. 10, the field effect transistor fabricated by the method provided by the embodiment of the present invention includes an insulating substrate 201, a source region 206 (source), an adjacent source region, and a source region. Doping pockets 207 of opposite doping type, drain region 209 (drain), and metal gate 210.

It can be seen from the process preparation flow of FIG. 2 to FIG. 10 that the position and size of the main shaft 202 and the thickness of the first passivation protective layer 203 determine the position of the doping pocket 207, and the thickness of the second passivation protective layer 205 determines the doping. The size of the miscellaneous pocket 207; the position and size of the main shaft 202 determines the position of the metal gate 210, the thickness of the first passivation protective layer 203 and the second passivation protective layer 205 determines the size of the metal gate 210; The position and size, and the thickness of the first passivation protective layer 203 and the second passivation protective layer 205 determine the position of the source region 206; the position and size of the spindle 202 determines the position and size of the drain region 209. In other words, in the embodiment of the present invention, the source region (source), the drain region (drain), and the metal gate of the tunneling field effect transistor are accurately positioned by the self-aligned process, and the tunnel is realized. The doped pocket is inserted into the field effect transistor, so that the gate width of a smaller size can be realized without being limited by the photolithography process, and the flexible design of the doping pocket can also be realized.

Therefore, the method for fabricating a tunneling field effect transistor having a doped pocket structure provided by the embodiment of the present invention can reduce the difficulty of the photolithography technology by using a self-alignment process, and improve the tunneling of the actually fabricated doped pocket structure. The feasibility of a field effect transistor. In addition, the method for fabricating a tunneling field effect transistor provided by the embodiment of the present invention is compatible with a conventional semiconductor process, and has good feasibility and repeatability, and thus can be applied to an actual manufacturing process of a tunneling field effect transistor.

It should be noted that if the first doping type is N-type and the second doping type is P-type, the type of tunneling field effect transistor fabricated by using the process flow of FIG. 2 to FIG. 10 is pnin; The doping type is P type, and the second doping type is N type, and the type of tunneling field effect transistor fabricated by using the process flow of FIG. 2 to FIG. 10 is npip. That is, two types of tunneling field effect transistors having a doped pocket structure can be prepared by the method provided by the embodiments of the present invention.

As shown in FIG. 11, the embodiment of the present invention further provides a method 300 for simultaneously fabricating a p-n-i-n type and an n-p-i-p type tunneling field effect transistor. The method 300 includes the following steps:

301, a first main axis is formed on the first surface of the first substrate, and a second main axis is formed on the second surface of the second substrate, the first surface is parallel to the second surface, the first main axis and the first main axis The axes of the two main axes are perpendicular to the first surface;

302, covering the first passivation protective layer on the sidewall surfaces of the first main shaft and the second main shaft respectively;

303, performing N-type doping on the first surface that is not covered by the first passivation protective layer and the first main axis to form a first doped region;

304, covering a surface of the first passivation protective layer with a second passivation protective layer;

305, performing P-type doping on a region of the first doped region not covered by the second passivation protective layer to form a first source region, the first doped region being covered by the second passivation protective layer The region is an N-doped first doping pocket, and P-doping is performed on the second surface without the first passivation layer, the second passivation protective layer and the second main axis. Second drain zone;

306, removing the first main axis and the second main axis, and performing P-type doping on the second surface of the second surface to remove the second main axis to form a second doped region;

307, the third passivation protective layer is covered on the surface of the first passivation protective layer away from the second passivation protective layer;

308, performing N-type doping in a region where the second doping region is not covered by the third passivation protective layer, forming a second source region, where the second doping region is covered by the third passivation protective layer a P-doped second doped pocket, the first surface of the first surface is removed to perform N-type doping to form a first drain region;

309, removing the first passivation protective layer, the second passivation protective layer and the third passivation protective layer, and removing the first passivation protective layer, the second passivation protective layer and the third blunt a metal gate is formed on the area of the protective layer,

Wherein, the type of tunneling field effect transistor formed on the first substrate is p-n-i-n, and the type of tunneling field effect transistor formed on the second substrate is n-p-i-p.

As described above, in the method for fabricating a tunneling field effect transistor provided by the embodiment of the present invention, the position and size of the first main axis and the thickness of the first passivation protective layer determine the position of the first doped pocket, and the second passivation The thickness of the protective layer determines the size of the first doped pocket; the position and size of the first major axis, and the thickness of the first, second and third passivation protective layers determine the position and size of the metal gate on the first substrate The position and size of the second spindle determine the position of the second doping pocket, the thickness of the third passivation layer determines the size of the second doping pocket; the position and size of the second spindle, the first and second The thickness of the third passivation protective layer determines the position and size of the metal gate on the second substrate.

In practical applications, the gate width of the smaller size can be realized by controlling the position and size of the first main shaft and the second main shaft, and the thicknesses of the first, second and third passivation protective layers; by controlling the second passivation protection The thickness of the layer is designed to design a doping pocket of a pnin tunneling field effect transistor; the doping pocket of the npip type tunneling field effect transistor is designed by controlling the thickness of the third passivation protective layer.

The method provided by the embodiment of the invention can realize the simultaneous fabrication of tunneling field effect transistors of the ppn type and the npip type, can realize the gate width of a smaller size by overcoming the limitation of the photolithography process, and can also realize the flexible design of the doping pocket. It is compatible with traditional semiconductor processes and has good feasibility and repeatability, so it can be applied to the actual manufacturing process of tunneling field effect transistors.

Optionally, in the above embodiment, step 309 is to form a metal gate on the region where the first passivation protective layer, the second passivation protective layer, and the third passivation protective layer are removed, including:

Etching is performed on a region where the first passivation protective layer, the second passivation protective layer, and the third passivation protective layer are removed;

A metal gate is formed on the area after etching.

Optionally, in step 306 of the foregoing embodiment, before removing the first main axis and the second main axis, the method 300 further includes: covering the region of the first source region on the first surface with an oxide, The second drain region is covered with an oxide on a region of the second surface;

In step 309, before removing the first passivation protective layer, the second passivation protective layer and the third passivation protective layer, the method 300 further includes: covering the oxide on the first drain region on the first surface And covering the oxide on the region of the second source region on the second surface.

Specifically, the material of the first main shaft and the second main shaft is polysilicon.

Specifically, the material of the passivation protective layer is any one of the following materials: silicon nitride, silicon dioxide or silicon oxynitride.

Specifically, the passivation protective layer is formed in an isotropic deposition and etching.

FIG. 12 to FIG. 22 are schematic diagrams showing processes corresponding to a method 300 for simultaneously fabricating a p-n-i-n type and an n-p-i-p type tunneling field effect transistor according to an embodiment of the present invention.

Step 301, as shown in FIG. 12, a first main spindle 601 is formed on the first surface of the first substrate 401, and in the second A second main shaft 602 is formed on the second surface of the substrate 501. The first surface is parallel to the second surface, and the axes of the first main shaft 601 and the second main 602 are perpendicular to the first surface.

As can be seen in conjunction with FIG. 12, the first surface referred to herein may be the upper surface of the substrate 401, and the second surface may be the upper surface of the substrate 501.

The substrate 401 and the substrate 501 may be two substrates defined on a substrate of a Fin structure, and the two may pass through an insulator therebetween (such as the substrate 401 and the substrate 501 shown in FIG. 12). The connection between the two).

It should be understood that the upper surface of the substrate 401 and the substrate 501 is covered with a thin oxide layer.

The material of the first main shaft 601 and the second main shaft 602 may be polysilicon.

Step 302, as shown in FIG. 13, covers the sidewalls of the first main shaft 601 and the second main shaft 602 with a first passivation protective layer 603 (also referred to as a first nitride spacer) made of nitride.

Specifically, the manner of forming the first passivation protective layer 603 is similar to the manner of forming the first passivation protective layer 203 described above, and details are not described herein again.

Step 303, as shown in FIG. 14, the N-type ion doping is performed on the first surface of the first surface that is not covered by the first passivation protective layer 603 and the first main axis 601, or by using a hard mask method. Etching and epitaxy are performed to form an N-type hetero doping, that is, a first doping region 604 is formed.

It should be understood that the first doped region 604 will subsequently evolve into a doped pocket (referred to as a first doped pocket) of the tunneling field effect transistor fabricated on the first substrate 401.

It should also be understood that the energy of the ion doping can determine the doping depth, assuming that the N-type ion doping is used to form the N-type doped first doping region 604, if the N-type doping energy is low energy, then The first doped pocket formed subsequently is a split pocket, and the split pocket can suppress the generation of leakage current; if the energy of the N-type doping is high energy, the subsequently formed first doped pocket is a full pocket.

It should also be understood that the second substrate 501 and portions thereof may be first protected prior to N-type doping of the first substrate 401.

Step 304, as shown in FIG. 15, covers the surface of the first passivation protective layer 603 with a second passivation protective layer 605 (also referred to as a second nitride spacer).

Specifically, the manner of forming the second passivation protective layer 605 is the same as the manner of forming the second passivation protective layer 205 described above, and details are not described herein again.

Step 305, as shown in FIG. 16, P-type doping is performed on a region where the first doping region 604 is not covered by the second passivation protective layer 605, forming a first source region 402, and the first doping region 604 is The region covered by the second passivation protective layer 605 is an N-doped first doping pocket 403, and the second surface is not covered by the first passivation layer 603, the second passivation protective layer 605 and the second spindle 602. P-type doping is performed on the region to form a second drain region 502.

Specifically, the specific mode of P-type doping may be P-type ion implantation or P-type etching and epitaxy.

It should be understood that in this step, the source region of the tunneling field effect transistor to be fabricated on the first substrate 401 and the doping pocket adjacent to the source region and opposite to the source region doping type are formed, and the first A drain region of the tunneling field effect transistor to be fabricated on the second substrate 501.

Step 306, as shown in FIG. 17 and FIG. 18, the first main axis 601 and the second main axis 602 are removed, and P-type doping is performed on the second surface of the second surface to remove the second main axis 602 to form a second doping region 606. .

Specifically, as shown in FIG. 17, an oxide 607 is covered over the first source region 402 and the second drain region 502 to protect the first source region 402 and the second drain region 502. The oxide 607 may be, for example, silicon dioxide, or may be a similar material such as FCVD, SOG, HDP or HARP. After the completion of the capping oxide 607, it can be followed by planarization The process makes the surface of the part flat, for example, using etching and chemical mechanical polishing.

As shown in FIG. 18, after the oxide 607 is overlaid over the first source region 402 and the second drain region 502, the first spindle 601 and the second spindle 602 are removed, and in the region where the second spindle 602 is removed, P+ is utilized. The photomask is doped with P-type ions, or is etched and epitaxially P-doped by a Hard mask method to form a P-doped second doped region 606.

It should be understood that the second doped region 606 may subsequently evolve into a doping pocket (referred to as a second doped pocket) of the tunneling field effect transistor fabricated by the second substrate 501.

It should also be understood that the energy of the ion doping can determine the doping depth, assuming that the P-type ion doping is used to form the second doping region, and if the P-doping energy is low energy, the subsequent second doping is formed. The pocket is a split pocket, and the split pocket can suppress the generation of leakage current; if the energy of the P-type doping is high energy, the subsequently formed second doped pocket is a full pocket.

It should also be understood that in this step, the region where the first spindle 601 is removed may be first protected before the P-type doping of the region where the second spindle 602 is removed.

Step 307, as shown in FIG. 19, the third passivation protective layer 608 is covered on the surface of the first passivation protective layer 603 away from the second passivation protective layer 605.

Specifically, the material of the third passivation protective layer 608 may be the same as the material of the first and second passivation protective layers, and is also a nitride.

Step 308, as shown in FIG. 20, N-type doping is performed in a region where the second doping region 606 is not covered by the third passivation protective layer 608, forming a second source region 503, and the second doping region 606 is third. The region covered by the passivation protective layer 608 is a P-doped second doped pocket 504, and the region of the first surface from which the first major axis 602 is removed is N-type doped to form a first drain region 404.

Specifically, the specific manner of N-type doping may be N-type ion implantation or formation of N-type hetero-doping by etching and epitaxy.

Step 309, as shown in FIG. 21, overlying the second source region 503 and the first drain region 404 to cover the second source region 503 and the first drain region 404. As shown in FIG. 22, the first passivation protective layer 603, the second passivation protective layer 605 and the third passivation protective layer 608 are removed, the gate underlayer is exposed, and the first passivation protective layer 603 and the second are removed. A metal gate is formed on the region of the passivation protective layer 605 and the third passivation protective layer 608. The metal gate formed on the first substrate 401 is 405, and the metal gate formed on the second substrate 501 is 505.

Specifically, the wet etching of hydrofluoric acid or a similar solution may be used before the metal gate is formed, or the dry etching of the CF series may be used to enlarge the gate underlayer, and then the metal gate is formed on the etched region, which may increase The overlap area of the gate and source regions.

It should also be understood that after the fabrication of the metal gates 405 and 505 is completed, the oxide 607 for protecting the source and drain regions can be removed.

So far, a tunneling field effect transistor of the type pnin is fabricated based on the first substrate 401, which includes a substrate 401, a P-doped source region 402, an N-doped doped pocket 403, and an N-doped a drain region 404 and a metal gate 405; a tunneling field effect transistor of type npip is fabricated based on the second substrate 501, including a substrate 501, an N-doped source region 503, and a P-doped doped pocket 504, a P-doped drain region 502 and a metal gate 505.

It can be seen from the process preparation flow of FIG. 12 to FIG. 22 that the position and size of the first main shaft 601 determine the position of the first doping pocket 403, and the thickness of the second passivation protective layer 605 determines the first doping pocket 403. Dimensions; the position and size of the first spindle 601, and the thickness of the first, second, and third passivation protective layers determine the position of the metal gate 405 Position and size; the position and size of the first spindle 601, and the thickness of the first passivation protection layer 603 and the second passivation protection layer 605 determine the position of the first source region 402; the position and size of the first spindle 601 The thickness of the third passivation protection layer 608 determines the location and size of the drain region 209. The position and size of the second spindle 602 determines the position of the second doping pocket 504. The thickness of the third passivation protective layer 608 determines the size of the second doping pocket 504; the position and size of the second spindle 602, first The thickness of the second and third passivation protective layers determines the position and size of the metal gate 505; the position and size of the second spindle 602 and the thickness of the third passivation protective layer 608 determine the position of the second source region 504. The position and size of the second main shaft 602, the thickness of the first passivation protective layer 203 and the second passivation protective layer 205 determine the position and size of the second drain region 502.

Therefore, the method provided by the embodiments of the present invention can simultaneously form a tunneling field effect transistor of a ppn type and an npip type, which can alleviate the difficulty of the lithography technology and improve the feasibility of actually fabricating a tunneling field effect transistor having a doped pocket structure. Sex and efficiency. In addition, the method for fabricating a tunneling field effect transistor provided by the embodiment of the present invention is compatible with a conventional semiconductor process, and has good feasibility and repeatability, and thus can be applied to an actual manufacturing process of a tunneling field effect transistor.

The foregoing is only a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application. It should be covered by the scope of protection of this application. Therefore, the scope of protection of the present application should be determined by the scope of the claims.

Claims (12)

A method of fabricating a tunneling field effect transistor, comprising: Making a spindle on a first surface of the substrate, the axis of the spindle being perpendicular to the first surface; Covering a first passivation protective layer on a sidewall surface of the main shaft; Forming a doped region having a first doping type in a region where the first surface is not covered by the first passivation protective layer and the main axis; Covering a surface of the first passivation protective layer with a second passivation protective layer; Forming a source region having a second doping type in a region where the doped region is not covered by the second passivation protective layer, and a region of the doped region covered by the second passivation protective layer is in close proximity a doping pocket of the source region having the first doping type, the second doping type being opposite to the first doping type; Removing the spindle and forming a drain region having the first doping type on a region where the spindle is removed; Removing the first passivation protective layer and the second passivation protective layer, and fabricating a metal gate on a region where the first passivation protective layer and the second passivation protective layer are removed. The method according to claim 1, wherein the fabricating the metal gate on the region where the first passivation protective layer and the second passivation protective layer are removed comprises: Etching the region where the first passivation protective layer and the second passivation protective layer are removed; The metal gate is fabricated on the region after the etching. The method according to claim 1 or 2, wherein before the removing the spindle, the method further comprises: covering the region of the source region on the first surface with an oxide; Before removing the first passivation protective layer and the second passivation protective layer, the method further comprises: covering the oxide on a region of the drain region on the first surface. The method according to any one of claims 1 to 3, characterized in that the material of the main shaft is polysilicon. The method according to any one of claims 1 to 4, wherein the passivation protective layer is made of any one of the following materials: silicon nitride, silicon dioxide or silicon oxynitride. The method according to any one of claims 1 to 5, wherein the passivation protective layer is formed in an isotropic deposition and etching. A method of fabricating a tunneling field effect transistor, comprising: Forming a first major axis on the first surface of the first substrate, and forming a second major axis on the second surface of the second substrate, the first surface being parallel to the second surface, the first major axis The axis of the second spindle is perpendicular to the first surface; Covering the first passivation protective layer on the sidewall surfaces of the first main axis and the second main shaft, respectively; Forming a first doped region on the first surface that is not covered by the first passivation protective layer and the first main axis; Covering a surface of the first passivation protective layer with a second passivation protective layer; P-type doping is performed on a region where the first doping region is not covered by the second passivation protective layer to form a first source region, and the first doping region is covered by the second passivation protective layer The covered area is an N-doped first doped pocket, and the second surface is not covered by the first passivation layer, the second passivation protective layer and the second main axis P-type doping to form a second drain region; Removing the first main shaft and the second main shaft, and removing the area of the second main shaft on the second surface Performing P-type doping to form a second doped region; Coating a third passivation protective layer on a surface of the first passivation protective layer away from the second passivation protective layer; N-type doping is performed in a region where the second doping region is not covered by the third passivation protective layer, forming a second source region, and the second doping region is covered by the third passivation protective layer The region is a P-doped second doped pocket, and the region of the first surface from which the first major axis is removed is N-type doped to form a first drain region; Removing the first passivation protective layer, the second passivation protective layer and the third passivation protective layer, and removing the first passivation protective layer, the second passivation protective layer and the a metal gate is formed on a region of the third passivation protective layer, Wherein, the type of tunneling field effect transistor formed on the first substrate is p-n-i-n, and the type of tunneling field effect transistor formed on the second substrate is n-p-i-p. The method according to claim 7, wherein the metal gate is formed on a region where the first passivation protective layer, the second passivation protective layer and the third passivation protective layer are removed ,include: Etching on the region where the first passivation protective layer, the second passivation protective layer, and the third passivation protective layer are removed; A metal gate is formed on the region after the etching. The method according to claim 7 or 8, wherein before the removing of the first main axis and the second main axis, the method further comprises: the first source region being located on the first surface The region is covered with an oxide, and the region of the second drain region on the second surface is covered with an oxide; Before the removing the first passivation protective layer, the second passivation protective layer, and the third passivation protective layer, the method further includes: the first drain region is located at the first The region of the surface is covered with an oxide, and the region of the second source region on the second surface is covered with an oxide. The method according to any one of claims 7 to 9, wherein the material of the first main shaft and the second main shaft is polysilicon. The method according to any one of claims 7 to 10, wherein the passivation protective layer is made of any one of the following materials: silicon nitride, silicon dioxide or silicon oxynitride. The method according to any one of claims 7 to 11, wherein the passivation protective layer is formed in an isotropic deposition and etching.

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