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WO2018148997A1 - 一种阵列基板及其制作方法 - Google Patents

一种阵列基板及其制作方法 Download PDF

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Publication number
WO2018148997A1
WO2018148997A1 PCT/CN2017/076308 CN2017076308W WO2018148997A1 WO 2018148997 A1 WO2018148997 A1 WO 2018148997A1 CN 2017076308 W CN2017076308 W CN 2017076308W WO 2018148997 A1 WO2018148997 A1 WO 2018148997A1
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WIPO (PCT)
Prior art keywords
layer
passivation layer
color resist
passivation
array substrate
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PCT/CN2017/076308
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English (en)
French (fr)
Inventor
衣志光
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深圳市华星光电技术有限公司
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Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US16/485,654 priority Critical patent/US10859881B2/en
Priority to JP2019543211A priority patent/JP6829773B2/ja
Priority to EP17896891.3A priority patent/EP3584838A4/en
Priority to KR1020197026136A priority patent/KR102316172B1/ko
Publication of WO2018148997A1 publication Critical patent/WO2018148997A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to an array substrate and a method of fabricating the same.
  • the COA product passivation layer via and the CF via hole were originally developed.
  • a passivation layer via was opened in the CF color resist layer via hole.
  • the COA process flow was to make the color resist layer on the array substrate, and the color resist layer as a whole. Thicker thickness is generally 2.5 ⁇ 3um, and the thickness of the PV dry-etched gate layer, gate insulating layer and source-drain base layer is only about 0.7um. If the color resist layer is not opened, the overall etching time will be Too long, and the color resist layer is physically etched. The etched vias will be substantially vertical, which is not conducive to the ITO electrode layer covering, and there is a risk of breakage. Therefore, the color resist layer is opened and then passivated.
  • the layer via is sleeved in the color resist layer. If the via of the color resist layer overlaps with the via of the passivation layer, the overlapping portion forms a channel through which the gas flows out of the color resist layer. Since the overlap is a local position, the gas evolution should be continued, so After the panel is formed into a box, gas is also precipitated, which forms air bubbles.
  • one method is to make the via of the color resist layer relatively large, so that the problem that the via of the color resist layer overlaps with the via of the passivation layer does not occur, but this improvement countermeasure reduces the aperture ratio.
  • Another method is to open a hole in the color resist layer to allow the gas to precipitate in advance, but the etching rate of the color resist layer and the PV etching rate are largely different, resulting in insufficient etching depth, and the gas release position cannot be reached.
  • An array substrate comprising:
  • a gate layer disposed on the substrate
  • a gate insulating layer disposed on the base substrate and covering the gate layer
  • a source drain layer disposed on the gate insulating layer
  • a first passivation layer covering a portion of the source/drain base layer and the gate insulating layer
  • the source and drain layers are correspondingly provided with passivation layer vias, and the passivation layer vias extend through the second passivation layer, the color resist layer and the first passivation layer and extend to the The surface of the source drain layer is exposed on one side of the via of the passivation layer to allow gas in the color resist layer to escape.
  • a first side of the passivation layer via is in communication with the second passivation layer and the first passivation layer, and a second side of the passivation layer via is opposite to the second
  • the passivation layer, the color resist layer and the first passivation layer are in communication, and a gas in the color resist layer is deposited from a surface of the color resist layer on the second side.
  • the array substrate further includes an ITO electrode layer covering a portion of the second passivation layer, the first side, and a portion of the bottom of the passivation layer via.
  • the surface of the source and drain layers corresponding to the bottom of the passivation layer via is a concave surface, and the bottom of the concave surface is the bottom of the passivation layer via.
  • the bottom of the color resist layer is provided with a plurality of air outlet holes, and the plurality of air outlet holes communicate with each other and communicate with the surface of the color resist layer on the second side.
  • a contact surface of the color resist layer and the second passivation layer is provided with a gas passage, and the gas passage communicates with a surface of the color resist layer on the second side.
  • the surface of the second passivation layer and the first passivation layer on the first side are both inclined surfaces.
  • a cross section of the upper portion of the second side surface has a right angle shape, and a horizontal side of the right angle is located in the color resist layer, which is formed by wet etching.
  • the second passivation layer of the bare portion is etched such that the source and drain layers and the color resist layer corresponding thereto are exposed to form the passivation layer via.
  • the method further comprises:
  • An ITO electrode layer is formed on a bottom surface of the passivation layer via and a side surface covered with the second passivation layer.
  • An array substrate comprising:
  • a gate layer disposed on the substrate
  • a gate insulating layer disposed on the base substrate and covering the gate layer
  • a source drain layer disposed on the gate insulating layer
  • a first passivation layer covering a portion of the source/drain base layer and the gate insulating layer
  • the source and drain layers are respectively provided with passivation layer vias, and the passivation layer vias extend through the second passivation layer, the color resist layer and the first passivation layer and extend to a surface of the source/drain layer, a side of the passivation layer via hole exposing the color resist layer to allow gas in the color resist layer to escape;
  • first side of the passivation layer via is in communication with the second passivation layer and the first passivation layer, and the second side of the passivation layer via is opposite to the second passivation layer
  • the color resist layer and the first passivation layer are in communication, and a gas in the color resist layer is deposited from a surface of the color resist layer on the second side;
  • the array substrate further includes an ITO electrode layer covering a portion of the second passivation layer, the first side surface, and a portion of the bottom of the passivation layer via hole.
  • the surface of the source and drain layers corresponding to the bottom of the passivation layer via is a concave surface, and the bottom of the concave surface is the bottom of the passivation layer via.
  • the bottom of the color resist layer is provided with a plurality of air outlet holes, and the plurality of air outlet holes communicate with each other and communicate with the surface of the color resist layer on the second side.
  • a contact surface of the color resist layer and the second passivation layer is provided with a gas passage, and the gas passage communicates with a surface of the color resist layer on the second side.
  • the surface of the second passivation layer and the first passivation layer on the first side are both inclined surfaces.
  • a cross section of the upper portion of the second side surface has a right angle shape, and a horizontal side of the right angle is located in the color resist layer, which is formed by wet etching.
  • an ITO electrode layer is provided on a bottom surface of the passivation layer via and a side surface covered with the second passivation layer.
  • An array substrate and a method for fabricating the same according to the present invention wherein a passivation layer via hole is formed corresponding to a source/drain layer, and the passivation layer via hole penetrates the second passivation layer, the color resist layer and the first passivation layer.
  • the bottom of the passivation layer via is in contact with the surface of the source and drain layers, the first side of the passivation layer via is in communication with the second passivation layer and the first passivation layer, and the second side of the passivation layer via is
  • the second passivation layer, the color resist layer and the first passivation layer are in communication to form an effective gas deposition path, and the gas in the color resist layer is preliminarily precipitated from the surface of the color resist layer on the second side, thereby reducing the occurrence of the liquid crystal panel. The risk of bubbles.
  • FIG. 1 is a cross-sectional view showing an overall structure of an array substrate according to an embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional view showing an overall structure of an ITO electrode layer of an array substrate according to an embodiment of the invention
  • FIG. 3 is a flow chart showing an implementation procedure of a method for fabricating an array substrate according to an embodiment of the invention
  • FIG. 4 is a schematic diagram of a step of implementing a method for fabricating an array substrate according to an embodiment of the invention, in which a bottom surface of a second via hole and a photoresist layer on one side thereof are removed, and a second passivation layer at a corresponding position is exposed.
  • FIG. 1 is a cross-sectional view showing the overall structure of an array substrate according to an embodiment of the present invention.
  • an array substrate of the present invention includes:
  • the base substrate 1 is preferably a glass substrate.
  • the gate layer 2 is provided on the base substrate 1.
  • the gate insulating layer 3 is provided on the base substrate 1 and covers the gate layer 2.
  • the source and drain layers 4 are provided on the gate insulating layer 3.
  • the first passivation layer 5 covers a portion of the source/drain base layer and the gate insulating layer 3.
  • the color resist layer 6 is disposed on the first passivation layer 5 and covers a portion of the first passivation layer 5.
  • the second passivation layer 7 is disposed on the color resist layer 6 to cover a portion of the color resist layer 6 and the first passivation layer 5.
  • the source/drain layer 4 is provided with a passivation layer via 9 corresponding thereto, and the passivation layer via 9 extends through the second passivation layer 7, the color resist layer 6 and the first blunt
  • the layer 5 is extended to the surface of the source/drain layer 4, and one side of the passivation layer via 9 exposes the color resist layer 6 to allow gas in the color resist layer 6 to escape.
  • the first side of the passivation layer via 9 ie, the left side of the passivation layer via 9 in FIG. 1 is in communication with the second passivation layer 7 and the first passivation layer 5, a second side of the passivation layer via 9 (ie, a right side of the passivation layer via 9 in FIG. 1) and the second passivation layer 7, the color resist layer 6, and the first passivation layer 5, the gas in the color resist layer 6 is deposited from the surface of the color resist layer 6 on the second side.
  • the array substrate further includes an ITO electrode layer 8 covering a portion of the second passivation layer 7, the first side surface, and a portion of the passivation layer via 9 bottom.
  • the surface of the source/drain layer 4 corresponding to the bottom of the passivation layer via 9 is a concave surface, and the bottom of the concave surface is the bottom of the passivation layer via 9.
  • the concave surface is provided to ensure that the first passivation layer 5 is completely etched away, and that the ITO electrode layer 8 can be sufficiently contacted with the source and drain layers 4.
  • the bottom of the color resist layer 6 is provided with a plurality of air outlet holes (not shown), the plurality of air outlet holes communicate with each other, and the color resist layer on the second side surface The surfaces of 6 are connected to each other.
  • a contact surface of the color resist layer 6 and the second passivation layer 7 is provided with a gas passage (not shown), and the gas passage and the color resist layer 6 on the second side surface The surfaces are connected to each other.
  • the surfaces of the second passivation layer 7 and the first passivation layer 5 on the first side are both inclined surfaces.
  • the ITO electrode layer 8 covering the first side is less likely to be broken.
  • the upper portion of the second side surface has a right-angled shape, and the horizontal side of the right angle is located in the color resist layer 6, which is formed by wet etching.
  • the first side bridges the drain and the pixel electrode through the ITO electrode layer 8
  • the portion of the color resist layer 6 and the passivation layer via 9 are not in communication with each other.
  • the second side is to release the gas position in the color resist layer 6, and the color resist layer 6 is required to communicate with the passivation layer via 9. Since the second side design color resist layer 6 and the passivation layer via 9 communicate with each other, the release path is large, and the gas in the color resist layer 6 is completely discharged before the card forming process.
  • the slopes of the first passivation layer 5 and the second passivation layer 7 formed on the first side are relatively flat, the ITO electrode layer 8 deposited thereon does not break, and the slope region of the second side of the color resist layer 6 is not
  • the second passivation layer 7 is covered so that the color resist layer 6 is exposed, so that the gas inside the color resist layer 6 can be quickly precipitated, thereby improving the bubble problem.
  • An array substrate of the present invention is provided with a passivation layer via 9 corresponding to the source/drain layer 4, the passivation layer via 9 penetrating through the second passivation layer 7, the color resist layer 6, and the first passivation layer.
  • the bottom of the passivation layer via 9 is in contact with the surface of the source and drain layer 4
  • the first side of the passivation layer via 9 is in communication with the second passivation layer 7 and the first passivation layer 5
  • the second side of the via 9 communicates with the second passivation layer 7, the color resist layer 6, and the first passivation layer 5 to form an effective gas deposition path, and the gas in the color resist layer 6 is advanced from the second side.
  • the surface of the color resist layer 6 is precipitated, which reduces the risk of bubble generation in the liquid crystal panel.
  • FIG. 3 is a flow chart of implementation steps of a method for fabricating an array substrate according to an embodiment of the invention.
  • the present invention provides a method for fabricating an array substrate according to the first embodiment.
  • the manufacturing method includes the following steps:
  • Step S101 forming the gate layer 2, the gate insulating layer 3, the source/drain layer 4, the first passivation layer 5, and the color sequentially from bottom to top on the base substrate 1. Resistive layer 6.
  • Step S102 forming a color resist via hole on the color resist layer 6, the color resist via hole communicating with the first passivation layer 5 corresponding to the upper side of the source/drain layer 4, that is, the color resist via hole
  • the color resist layer 6 and the first passivation layer 5 extend to the source and drain layers 4.
  • Step S103 forming the second passivation layer 7 on the color resist layer 6 and the color resist via, and the second passivation layer 7 covers the color resist layer 6 and the color resist hole.
  • Step S104 forming a photoresist layer 10 on the second passivation layer 7, and removing the bottom surface of the color resist via and the photoresist layer 10 on one side thereof by exposure development to make corresponding positions The second passivation layer 7 is exposed, wherein the second passivation layer 7 of the bare portion corresponds to the color resist layer 6 vertically below. This step is shown in Figure 4.
  • Step S105 etching the second passivation layer 7 of the bare portion, so that the source/drain layer 4 corresponding thereto and the color resist layer are exposed to form the passivation layer via 9.
  • the method further includes: forming an ITO electrode on a bottom surface of the passivation layer via 9 and a side surface covered with the second passivation layer 7 Layer 8.
  • etching is preferably performed by means of plasma bombardment.
  • a method for fabricating an array substrate according to the present invention comprises: providing a passivation layer via 9 corresponding to the source/drain layer 4, the passivation layer via 9 penetrating through the second passivation layer 7, the color resist layer 6, and the first a passivation layer 5, the bottom of the passivation layer via 9 is in contact with the surface of the source/drain layer 4, and the first side of the passivation layer via 9 is in communication with the second passivation layer 7 and the first passivation layer 5,
  • the second side surface of the passivation layer via 9 communicates with the second passivation layer 7, the color resist layer 6 and the first passivation layer 5 to form an effective gas deposition path, and the gas in the color resist layer 6 is advanced from the second The surface of the color resist layer 6 on the side is deposited, which reduces the risk of bubble generation in the liquid crystal panel.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

一种阵列基板及其制作方法，该阵列基板包括衬底基板（1）、栅极层（2）、栅极绝缘层（3）、源漏极层（4）、第一钝化层（5）、色阻层（6）与第二钝化层（7），其中，源漏极层对应的上方设有钝化层过孔（9），色阻层内的气体从钝化层过孔一侧面上的色阻层的表面析出。实现了在成盒制程前，将色阻层内的气体被全部排出的目的。

Description

一种阵列基板及其制作方法 技术领域
本发明涉及液晶显示领域，特别涉及一种阵列基板及其制作方法。
 背景技术
目前的COA（color filter on array）产品在撞击时容易产生气泡，其原因主要有两个，一个是局部位置CF（彩膜基板）过孔与TFT（薄膜晶体管）过孔重叠，重叠位置PV（钝化层）被干蚀刻掉，导致色阻层中气体在成盒后从重叠位置析出形成空气气泡，改善对策是扩大色阻层过孔大小，使其不与钝化层过孔重叠，这样会降低穿透率。第二个是在震动过程中PV会裂开导致色阻层中气体析出，形成气泡。目前有一个对策是在色阻层上开一个小孔，这样可以提前释放气体，但是色阻层的蚀刻率比PV的时刻率低，这样容易因蚀刻深度不够导致气体无法提前析出。
最初开发的COA产品钝化层过孔与CF过孔，是在CF色阻层过孔内开一个钝化层过孔，COA制程流程是将色阻层做在阵列基板上，色阻层整体厚度较厚一般都是2.5～3um，而PV干蚀刻的栅极层、栅极绝缘层和源漏基层加起来的厚度一共只有0.7um左右，如果色阻层不开孔会导致整体蚀刻时间会太长，且色阻层都是物理性蚀刻，蚀刻出的过孔会是基本垂直的，不利于ITO电极层覆盖，有断裂风险，所以目前都是采用色阻层开孔方式，然后钝化层过孔套在色阻层内。如出现色阻层过孔与钝化层过孔有交叠，交叠部分会形成一个色阻层内气体流出的通道，由于这种交叠是局部位置，气体析出应是持续进行，所以在面板成盒后还有气体析出，即会形成空气气泡。为改善此问题，一个做法是色阻层过孔做的比较大，这样即不会出现色阻层过孔与钝化层过孔交叠问题，但是这个改善对策会降低开口率。还有一种做法，是在色阻层上开孔，让气体提前析出，但因色阻层蚀刻率与PV蚀刻率相差较大，导致蚀刻深度不足，导致无法到达气体释放位置。
 技术问题
本发明的目的在于提供一种阵列基板及显示装置，以实现在成盒制程前，将色阻层内的气体被全部排出的目的。
 技术解决方案
本发明的技术方案如下：
一种阵列基板，其包括：
衬底基板；
栅极层，设于所述衬底基板上；
栅极绝缘层，设于所述衬底基板上，并覆盖所述栅极层；
源漏极层，设于所述栅极绝缘层上；
第一钝化层，其覆盖部分所述源漏基层及所述栅极绝缘层；
色阻层，设于所述第一钝化层上；
第二钝化层，设于所述色阻层上；
其中所述源漏极层对应上方设有钝化层过孔，所述钝化层过孔贯穿所述第二钝化层、所述色阻层与所述第一钝化层并延伸至所述源漏极层的表面，所述钝化层过孔的一侧裸露出所述色阻层以供色阻层内的气体逸出。
优选地，其中，所述钝化层过孔的第一侧面与所述第二钝化层和所述第一钝化层相通，所述钝化层过孔的第二侧面与所述第二钝化层、所述色阻层和所述第一钝化层相通，所述色阻层内的气体从所述第二侧面上的所述色阻层的表面析出。
优选地，其中，所述阵列基板还包括ITO电极层，所述ITO电极层覆盖部分所述第二钝化层、所述第一侧面及部分所述钝化层过孔的底部。
优选地，其中，与所述钝化层过孔的底部对应接触的所述源漏极层的表面为一凹面，所述凹面的底部为所述钝化层过孔的底部。
优选地，其中，所述色阻层底部设有多个出气孔，所述多个出气孔互相连通，并与所述第二侧面上的所述色阻层的表面互相连通。
优选地，其中，所述色阻层与所述第二钝化层的接触面设有气体通道，所述气体通道与所述第二侧面上的所述色阻层的表面互相连通。
优选地，其中，所述第一侧面上的所述第二钝化层与所述第一钝化层的表面均为斜面。
优选地，其中，所述第二侧面上部的截面呈直角形状，且该直角的水平边位于所述色阻层，其通过湿蚀刻形成。
一种如上述任一项所述的阵列基板的制作方法，其包括以下步骤：
在衬底基板上从下到上依次形成所述栅极层、所述栅极绝缘层、所述源漏极层、所述第一钝化层及所述色阻层；
在所述色阻层上形成色阻过孔，所述色阻过孔贯穿所述色阻层和所述第一钝化层以延伸至所述源漏极层；
在所述色阻层及所述色阻过孔上形成所述第二钝化层，且所述第二钝化层覆盖所述色阻层及所述色阻过孔；
在所述第二钝化层上形成光阻层，并通过曝光显影去除与所述色阻过孔的底面及其一侧面相对的所述光阻层，以使对应位置的所述第二钝化层裸露；
对裸露部分的所述第二钝化层进行蚀刻，使与其对应的所述源漏极层和所述色阻层裸露，以形成所述钝化层过孔。
优选地，其中，形成所述钝化层过孔后，还包括：
在所述钝化层过孔的底面及覆盖有所述第二钝化层的一侧面上形成ITO电极层。
一种阵列基板，其包括：
衬底基板；
栅极层，设于所述衬底基板上；
栅极绝缘层，设于所述衬底基板上，并覆盖所述栅极层；
源漏极层，设于所述栅极绝缘层上；
第一钝化层，其覆盖部分所述源漏基层及所述栅极绝缘层；
色阻层，设于所述第一钝化层上；
第二钝化层，设于所述色阻层上；
其中，所述源漏极层对应上方设有钝化层过孔，所述钝化层过孔贯穿所述第二钝化层、所述色阻层与所述第一钝化层并延伸至所述源漏极层的表面，所述钝化层过孔的一侧裸露出所述色阻层以供色阻层内的气体逸出；
其中，所述钝化层过孔的第一侧面与所述第二钝化层和所述第一钝化层相通，所述钝化层过孔的第二侧面与所述第二钝化层、所述色阻层和所述第一钝化层相通，所述色阻层内的气体从所述第二侧面上的所述色阻层的表面析出；
其中，所述阵列基板还包括ITO电极层，所述ITO电极层覆盖部分所述第二钝化层、所述第一侧面及部分所述钝化层过孔的底部。
优选地，其中，与所述钝化层过孔的底部对应接触的所述源漏极层的表面为一凹面，所述凹面的底部为所述钝化层过孔的底部。
优选地，其中，所述色阻层底部设有多个出气孔，所述多个出气孔互相连通，并与所述第二侧面上的所述色阻层的表面互相连通。
优选地，其中，所述色阻层与所述第二钝化层的接触面设有气体通道，所述气体通道与所述第二侧面上的所述色阻层的表面互相连通。
优选地，其中，所述第一侧面上的所述第二钝化层与所述第一钝化层的表面均为斜面。
优选地，其中，所述第二侧面上部的截面呈直角形状，且该直角的水平边位于所述色阻层，其通过湿蚀刻形成。
优选地，其中，在所述钝化层过孔的底面及覆盖有所述第二钝化层的一侧面上设有ITO电极层。
 有益效果
本发明的有益效果：
本发明的一种阵列基板及其制作方法，通过在源漏极层对应上方设置钝化层过孔，该钝化层过孔贯穿第二钝化层、色阻层与第一钝化层，该钝化层过孔的底部与源漏极层的表面接触，钝化层过孔的第一侧面与第二钝化层和第一钝化层相通，钝化层过孔的第二侧面与第二钝化层、色阻层和第一钝化层相通，形成了有效气体析出路径，将色阻层内的气体提前从第二侧面上的色阻层的表面析出，降低了液晶面板发生气泡的风险。
 附图说明
图1为本发明实施例的一种阵列基板的整体结构的剖面示意图；
图2为发明实施例的一种阵列基板的除去ITO电极层的整体结构的剖面示意图；
图3为发明实施例的一种阵列基板的制作方法的实施步骤流程图；
图4为发明实施例的一种阵列基板的制作方法的实施步骤流程图中，去除第二过孔的底面及其一侧面的光阻层，使对应位置的第二钝化层裸露后的示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
实施例一
请参考图1，图1为本实施例的一种阵列基板的整体结构的剖面示意图。从图1可以看到，本发明的一种阵列基板，其包括：
衬底基板1，该衬底基板1优选为玻璃基板。
栅极层2，设于所述衬底基板1上。
栅极绝缘层3，设于所述衬底基板1上，并覆盖所述栅极层2。
源漏极层4，设于所述栅极绝缘层3上。
第一钝化层5，其覆盖部分所述源漏基层及所述栅极绝缘层3。
色阻层6，设于所述第一钝化层5上，并覆盖部分所述第一钝化层5。
第二钝化层7，设于所述色阻层6上，覆盖部分所述色阻层6及所述第一钝化层5。
其中，所述源漏极层4对应上方设有钝化层过孔9，所述钝化层过孔9贯穿所述第二钝化层7、所述色阻层6与所述第一钝化层5并延伸至所述源漏极层4的表面，所述钝化层过孔9的一侧裸露出所述色阻层6以供色阻层6内的气体逸出。
其中，所述钝化层过孔9的第一侧面（即图1中钝化层过孔9的左边侧面）与所述第二钝化层7和所述第一钝化层5相通，所述钝化层过孔9的第二侧面（即图1中钝化层过孔9的右边侧面）与所述第二钝化层7、所述色阻层6和所述第一钝化层5相通，所述色阻层6内的气体从所述第二侧面上的所述色阻层6的表面析出。
在本实施例中，所述阵列基板还包括ITO电极层8，所述ITO电极层8覆盖部分所述第二钝化层7、所述第一侧面及部分所述钝化层过孔9的底部。
在本实施例中，与所述钝化层过孔9的底部对应接触的所述源漏极层4的表面为一凹面，所述凹面的底部为所述钝化层过孔9的底部。设置该凹面是为了保证将所述第一钝化层5完全蚀刻掉，保证ITO电极层8能和源漏极层4充分接触。
在本实施例中，所述色阻层6底部设有多个出气孔（图中未示出），所述多个出气孔互相连通，并与所述第二侧面上的所述色阻层6的表面互相连通。另外，所述色阻层6与所述第二钝化层7的接触面设有气体通道（图中未示出），所述气体通道与所述第二侧面上的所述色阻层6的表面互相连通。以上所述的出气孔和气体通道均为涂布色阻层6时，由于物理化学作用自然形成。这样就使得第一侧面对应的色阻层6内的气体也能够通过第二侧面上的色阻层6的表面析出。
在本实施例中，所述第一侧面上的所述第二钝化层7与所述第一钝化层5的表面均为斜面。这样，覆盖在所述第一侧面上的ITO电极层8就不容易发生断裂。
在本实施例中，所述第二侧面上部的截面呈直角形状，且该直角的水平边位于所述色阻层6，其通过湿蚀刻形成。
在本实施例中，第一侧面因要通过ITO电极层8桥接漏极与像素电极，所以此部分设计色阻层6与钝化层过孔9不相通。第二侧面为释放色阻层6中气体位置，设计上要求色阻层6与钝化层过孔9相通。因为第二侧面设计色阻层6和钝化层过孔9相通，所以释放路径多，在成盒制程前，色阻层6内的气体即会被全部排出。另外，第一侧面形成的第一钝化层5和第二钝化层7的坡度较为平坦，沉积在上面的ITO电极层8就不会断裂，第二侧面的色阻层6的斜坡区域没有第二钝化层7覆盖，使得色阻层6裸露出来，这样色阻层6内部的气体可以快速析出，进而改善气泡问题。
本发明的一种阵列基板，通过在源漏极层4对应上方设置钝化层过孔9，该钝化层过孔9贯穿第二钝化层7、色阻层6与第一钝化层5，该钝化层过孔9的底部与源漏极层4的表面接触，钝化层过孔9的第一侧面与第二钝化层7和第一钝化层5相通，钝化层过孔9的第二侧面与第二钝化层7、色阻层6和第一钝化层5相通，形成了有效气体析出路径，将色阻层6内的气体提前从第二侧面上的色阻层6的表面析出，降低了液晶面板发生气泡的风险。
实施例二
请参考图3，图3为发明实施例的一种阵列基板的制作方法的实施步骤流程图。
本实施提供一种实施例一所述的阵列基板的制作方法，该制作方法包括以下步骤：
步骤S101：在衬底基板1上从下到上依次形成所述栅极层2、所述栅极绝缘层3、所述源漏极层4、所述第一钝化层5及所述色阻层6。
步骤S102：在所述色阻层6上形成色阻过孔，所述色阻过孔与所述源漏极层4上方对应的所述第一钝化层5相通，即色阻过孔贯穿色阻层6和第一钝化层5以延伸至源漏极层4。
步骤S103：在所述色阻层6及所述色阻过孔上形成所述第二钝化层7，且所述第二钝化层7覆盖所述色阻层6及所述色阻过孔。
步骤S104：在所述第二钝化层7上形成光阻层10，并通过曝光显影去除所述色阻过孔的底面及其一侧面上的所述光阻层10，以使对应位置的所述第二钝化层7裸露，其中裸露部分的所述第二钝化层7竖直下方对应有所述色阻层6。此步骤如图4所示。
步骤S105：对裸露部分的所述第二钝化层7进行蚀刻，使与其对应的所述源漏极层4与所述色阻层裸露，以形成所述钝化层过孔9。
在本实施例中，在形成所述钝化层过孔9后，还包括：在所述钝化层过孔9的底面及覆盖有所述第二钝化层7的一侧面上形成ITO电极层8。
在本实施例中，优选采用电浆轰击的方式进行蚀刻。
本发明的一种阵列基板的制作方法，通过在源漏极层4对应上方设置钝化层过孔9，该钝化层过孔9贯穿第二钝化层7、色阻层6与第一钝化层5，该钝化层过孔9的底部与源漏极层4的表面接触，钝化层过孔9的第一侧面与第二钝化层7和第一钝化层5相通，钝化层过孔9的第二侧面与第二钝化层7、色阻层6和第一钝化层5相通，形成了有效气体析出路径，将色阻层6内的气体提前从第二侧面上的色阻层6的表面析出，降低了液晶面板发生气泡的风险。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (17)

  1. 一种阵列基板，其包括：
    衬底基板；
    栅极层，设于所述衬底基板上；
    栅极绝缘层，设于所述衬底基板上，并覆盖所述栅极层；
    源漏极层，设于所述栅极绝缘层上；
    第一钝化层，其覆盖部分所述源漏基层及所述栅极绝缘层；
    色阻层，设于所述第一钝化层上；
    第二钝化层，设于所述色阻层上；
    其中，所述源漏极层对应上方设有钝化层过孔，所述钝化层过孔贯穿所述第二钝化层、所述色阻层与所述第一钝化层并延伸至所述源漏极层的表面，所述钝化层过孔的一侧裸露出所述色阻层以供色阻层内的气体逸出。
  2. 根据权利要求1所述的阵列基板，其中，所述钝化层过孔的第一侧面与所述第二钝化层和所述第一钝化层相通，所述钝化层过孔的第二侧面与所述第二钝化层、所述色阻层和所述第一钝化层相通，所述色阻层内的气体从所述第二侧面上的所述色阻层的表面析出。
  3. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括ITO电极层，所述ITO电极层覆盖部分所述第二钝化层、所述第一侧面及部分所述钝化层过孔的底部。
  4. 根据权利要求1所述的阵列基板，其中，与所述钝化层过孔的底部对应接触的所述源漏极层的表面为一凹面，所述凹面的底部为所述钝化层过孔的底部。
  5. 根据权利要求1所述的阵列基板，其中，所述色阻层底部设有多个出气孔，所述多个出气孔互相连通，并与所述第二侧面上的所述色阻层的表面互相连通。
  6. 根据权利要求1所述的阵列基板，其中，所述色阻层与所述第二钝化层的接触面设有气体通道，所述气体通道与所述第二侧面上的所述色阻层的表面互相连通。
  7. 根据权利要求1所述的阵列基板，其中，所述第一侧面上的所述第二钝化层与所述第一钝化层的表面均为斜面。
  8. 根据权利要求1所述的阵列基板，其中，所述第二侧面上部的截面呈直角形状，且该直角的水平边位于所述色阻层，其通过湿蚀刻形成。
  9. 一种如权利要求1至8任一项所述的阵列基板的制作方法，其包括以下步骤：
    在衬底基板上从下到上依次形成所述栅极层、所述栅极绝缘层、所述源漏极层、所述第一钝化层及所述色阻层；
    在所述色阻层上形成色阻过孔，所述色阻过孔贯穿所述色阻层和所述第一钝化层以延伸至所述源漏极层；
    在所述色阻层及所述色阻过孔上形成所述第二钝化层，且所述第二钝化层覆盖所述色阻层及所述色阻过孔；
    在所述第二钝化层上形成光阻层，并通过曝光显影去除与所述色阻过孔的底面及其一侧面相对的所述光阻层，以使对应位置的所述第二钝化层裸露；
    对裸露部分的所述第二钝化层进行蚀刻，使与其对应的所述源漏极层和所述色阻层裸露，以形成所述钝化层过孔。
  10. 根据权利要求9所述的制作方法，其中，形成所述钝化层过孔后，还包括：
    在所述钝化层过孔的底面及覆盖有所述第二钝化层的一侧面上形成ITO电极层。
  11. 一种阵列基板，其包括：
    衬底基板；
    栅极层，设于所述衬底基板上；
    栅极绝缘层，设于所述衬底基板上，并覆盖所述栅极层；
    源漏极层，设于所述栅极绝缘层上；
    第一钝化层，其覆盖部分所述源漏基层及所述栅极绝缘层；
    色阻层，设于所述第一钝化层上；
    第二钝化层，设于所述色阻层上；
    其中，所述源漏极层对应上方设有钝化层过孔，所述钝化层过孔贯穿所述第二钝化层、所述色阻层与所述第一钝化层并延伸至所述源漏极层的表面，所述钝化层过孔的一侧裸露出所述色阻层以供色阻层内的气体逸出；
    其中，所述钝化层过孔的第一侧面与所述第二钝化层和所述第一钝化层相通，所述钝化层过孔的第二侧面与所述第二钝化层、所述色阻层和所述第一钝化层相通，所述色阻层内的气体从所述第二侧面上的所述色阻层的表面析出；
    其中，所述阵列基板还包括ITO电极层，所述ITO电极层覆盖部分所述第二钝化层、所述第一侧面及部分所述钝化层过孔的底部。
  12. 根据权利要求11所述的阵列基板，其中，与所述钝化层过孔的底部对应接触的所述源漏极层的表面为一凹面，所述凹面的底部为所述钝化层过孔的底部。
  13. 根据权利要求11所述的阵列基板，其中，所述色阻层底部设有多个出气孔，所述多个出气孔互相连通，并与所述第二侧面上的所述色阻层的表面互相连通。
  14. 根据权利要求11所述的阵列基板，其中，所述色阻层与所述第二钝化层的接触面设有气体通道，所述气体通道与所述第二侧面上的所述色阻层的表面互相连通。
  15. 根据权利要求11所述的阵列基板，其中，所述第一侧面上的所述第二钝化层与所述第一钝化层的表面均为斜面。
  16. 根据权利要求11所述的阵列基板，其中，所述第二侧面上部的截面呈直角形状，且该直角的水平边位于所述色阻层，其通过湿蚀刻形成。
  17. 根据权利要求11所述的阵列基板，其中，在所述钝化层过孔的底面及覆盖有所述第二钝化层的一侧面上设有ITO电极层。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107589581B (zh) * 2017-09-01 2020-07-03 深圳市华星光电技术有限公司 一种阵列基板色阻层的制备方法、阵列基板及显示面板
CN108388057B (zh) * 2018-03-16 2020-09-29 深圳市华星光电半导体显示技术有限公司 阵列基板
CN109712994B (zh) * 2019-01-22 2020-08-11 深圳市华星光电半导体显示技术有限公司 阵列基板及其制作方法
US11646320B2 (en) 2020-08-03 2023-05-09 Au Optronics Corporation Pixel array substrate

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7482186B2 (en) * 2006-04-07 2009-01-27 Chunghwa Picture Tubes, Ltd. Method for fabricating active matrix organic light emitting diode display device and structure of such device
JP2011221315A (ja) * 2010-04-12 2011-11-04 Toshiba Mobile Display Co Ltd 液晶表示装置
CN105700258A (zh) * 2016-04-08 2016-06-22 深圳市华星光电技术有限公司 液晶显示面板及其制作方法
CN106324933A (zh) * 2016-10-12 2017-01-11 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及其制备方法及液晶显示面板

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4458563B2 (ja) * 1998-03-31 2010-04-28 三菱電機株式会社 薄膜トランジスタの製造方法およびこれを用いた液晶表示装置の製造方法
JP2000338525A (ja) * 1999-05-31 2000-12-08 Toshiba Corp マトリクスアレイ基板及びその製造方法
JP3637016B2 (ja) * 2001-01-11 2005-04-06 Ｎｅｃ液晶テクノロジー株式会社 アクティブマトリクス型液晶表示装置及びその製造方法
JP4876341B2 (ja) * 2001-07-13 2012-02-15 日本電気株式会社 アクティブマトリクス基板及びその製造方法
KR100905409B1 (ko) * 2002-12-26 2009-07-02 엘지디스플레이 주식회사 액정표시장치 및 그 제조방법
JP4417072B2 (ja) * 2003-03-28 2010-02-17 シャープ株式会社 液晶表示装置用基板及びそれを用いた液晶表示装置
KR101101021B1 (ko) * 2009-10-09 2011-12-29 삼성모바일디스플레이주식회사 액정표시장치 및 그 제조방법
KR101611923B1 (ko) * 2012-02-27 2016-04-14 엘지디스플레이 주식회사 액정 표시 장치 및 이의 제조 방법
KR101987405B1 (ko) * 2013-01-11 2019-09-30 엘지디스플레이 주식회사 액정표시장치의 어레이기판 및 이의 제조 방법
CN104035231B (zh) * 2013-03-07 2017-04-12 群创光电股份有限公司 液晶显示面板及包含其的液晶显示设备
CN103700669A (zh) * 2013-12-19 2014-04-02 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN104460147B (zh) * 2014-11-20 2018-01-09 深圳市华星光电技术有限公司 薄膜晶体管阵列基板、制造方法及显示装置
CN104375344B (zh) * 2014-11-21 2017-09-15 深圳市华星光电技术有限公司 液晶显示面板及其彩膜阵列基板
CN104503127B (zh) * 2014-12-01 2017-10-13 深圳市华星光电技术有限公司 阵列基板及其制作方法
KR102356342B1 (ko) * 2015-06-08 2022-01-27 삼성디스플레이 주식회사 액정 표시 장치 및 그의 제조 방법
US10578784B2 (en) * 2017-09-04 2020-03-03 Shenzhen China Star Optoelectronics Technology Co., Ltd Color-filter on array (COA) display panel, manufacturing method thereof and COA display device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7482186B2 (en) * 2006-04-07 2009-01-27 Chunghwa Picture Tubes, Ltd. Method for fabricating active matrix organic light emitting diode display device and structure of such device
JP2011221315A (ja) * 2010-04-12 2011-11-04 Toshiba Mobile Display Co Ltd 液晶表示装置
CN105700258A (zh) * 2016-04-08 2016-06-22 深圳市华星光电技术有限公司 液晶显示面板及其制作方法
CN106324933A (zh) * 2016-10-12 2017-01-11 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及其制备方法及液晶显示面板

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3584838A4 *

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