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WO2018146554A1 - Procédé et dispositif de détection d'erreur distribuée avec des codes polaires - Google Patents

Procédé et dispositif de détection d'erreur distribuée avec des codes polaires Download PDF

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Publication number
WO2018146554A1
WO2018146554A1 PCT/IB2018/000223 IB2018000223W WO2018146554A1 WO 2018146554 A1 WO2018146554 A1 WO 2018146554A1 IB 2018000223 W IB2018000223 W IB 2018000223W WO 2018146554 A1 WO2018146554 A1 WO 2018146554A1
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WIPO (PCT)
Prior art keywords
bits
bit
code
error detection
communication device
Prior art date
Application number
PCT/IB2018/000223
Other languages
English (en)
Inventor
Yu Chen
Original Assignee
Alcatel Lucent
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Alcatel Lucent filed Critical Alcatel Lucent
Publication of WO2018146554A1 publication Critical patent/WO2018146554A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes

Definitions

  • Embodiments of the present disclosure generally relate to a communication system, and more specifically, to methods and devices for data processing at transmitting and receiving devices in a communication system.
  • Polar code has been proposed for the enhanced mobile broadband (eMBB) control channel.
  • eMBB enhanced mobile broadband
  • mMTC machine type communication
  • polar code has many advantages, such as low complexity and being capable of approximating the capacity. Therefore, for example in a fifth generation (5G) mobile communication system, the polar code will play an important role.
  • a decoding scheme usually used for polar code is a list-based scheme or a scheme based on a cyclic redundancy check (CRC)-aided list. Such a decoding scheme can achieve high performance but may also result in a high false alarm rate (FAR).
  • CRC cyclic redundancy check
  • a method of data processing in a communication system comprises: generating an error detection code for information bits to be encoded with a polar code, the error detection code being distributed in the information bits in a first order: determining, from among the information bits and the error detection code, a set of bits to be redistributed; redistributing a bit in the set of bits such that the error detection code is distributed in the information bits in a second order; and mapping the redistributed information bits and the error detection code to an input of a polar code encoder to be encoded with the polar code.
  • a second aspect of the present disclosure provides a method of data processing in a communication system.
  • the method comprises: performing polar code decoding on received data encoded with a polar code to obtain output bits; obtaining mapping information on an input of a polar code encoder, the mapping information indicating that an error detection code used in the encoding with the polar code is distributed in a predetermined order in information bits; obtaining, based on the predetermined order, the information bits and the error detection code from the output bits; and verifying the information bits with the error detection code.
  • a third aspect of the present disclosure provides a communication device.
  • the communication device comprises: a processor and a memory having instructions stored thereon.
  • the instructions when executed by the processor, cause the communication device to: generate an error detection code for information bits to be encoded with a polar code, the error detection code being distributed in the information bits in a first order; determine, from among the information bits and the error detection code, a set of bits to be redistributed; redistribute a bit in the set of bits such that the error detection code is distributed in the information bits in a second order; and map the redistributed information bits and the error detection code to an input of a polar code encoder to be encoded with the polar code.
  • a fourth aspect of the present disclosure provides a communication device.
  • the communication device comprises: a processor and a memory having instructions stored thereon.
  • the instructions when executed by the processer, cause the communication device to: perform polar code decoding on received data encoded with a polar code to obtain output bits; obtain mapping information on an input of a polar code encoder, the mapping information indicating that an error detection code used in the encoding with the polar code is distributed in a predetermined order in information bits; obtain, based on the predetermined order, the information bits and the error detection code from the output bits; and verify information bits with error detection code.
  • the communication device can provide better error detection capability with the same number of error check bits so as to reduce FAR effectively
  • FIG. 1 is a schematic diagram illustrating an example communication system 100 in which a method in accordance with embodiments of the present disclosure can be implemented;
  • FIG. 2 is a flowchart of a method 200 implemented at a communication device acting as a transmitting device in accordance with embodiments of the present disclosure;
  • FIG. 3 is a flowchart of a method 300 implemented at a communication device acting as a transmitting device in accordance with embodiments of the present disclosure
  • FIG. 4 is a block diagram of an apparatus 400 implemented at a communication device acting as a transmitting device in accordance with embodiments of the present disclosure
  • FIG. 5 is a block diagram of an apparatus 500 implemented at a communication device acting as a receiving device in accordance with embodiments of the present disclosure
  • FIG. 6 is a block diagram of a communication device 600 in accordance with embodiments of the present disclosure.
  • the same or similar reference numerals represent the same or similar element.
  • embodiments of the present invention are not limited to wireless communication systems conforming to wireless communication protocols formulated by 3GPP, but may be applicable to any communication system containing a similar issue, such as WLAN, a wired communication system, or other communication systems to be developed in the future.
  • the terminal device in the present disclosure may be a user equipment (UE), or any terminal having a wired or wireless communication function, including, but not limited to, a mobile phone, a computer, a personal digital assistant, a game machine, a wearable device, an on-vehicle communication device, a Machine Type Communication (MTC) device, a Device-to-Device (D2D) communication device, a sensor and so on.
  • a terminal device can be used interchangeably with a UE, a mobile station, a subscriber station, a mobile terminal, a user terminal, or a wireless device.
  • the network device may be a network node, such as a node B (Node B or NB), a base transceiver station (BTS), a base station (BS), or a base station system (BSS), a relay, remote wireless front (RRF), an access node (AN), an access point (AP), etc.
  • Node B or NB node B
  • BTS base transceiver station
  • BS base station
  • BSS base station system
  • RRF remote wireless front
  • AN access node
  • AP access point
  • FIG. 1A is a diagram illustrating an example wireless communication system 100 in which a method in accordance with embodiments of the present disclosure can be implemented.
  • the wireless communication system 100 may include one or more network devices 101.
  • the network device 101 may be embodied as a base station, such as an evolved node B (eNodeB or eNB).
  • eNodeB evolved node B
  • the network device 101 may be embodied in other manners, such as a node B, a basic transceiver station (BTS), a base station (BS), or a base station sub-system (BSS), a relay and so on.
  • the network device 101 provides a wireless connection to a plurality of terminal devices 111-112 within the coverage thereof.
  • the terminal devices 111 and 112 may communicate with a network device via a wireless transmission channel 131 or 132, and/or may communicate with each other via a wireless transmission channel 133.
  • FIG. IB is a simplified diagram illustrating processing implemented at a transmitting device 120 and a receiving device 130 in communication.
  • the network device 101 or the terminal devices 111 and 112 in FIG. 1 may act as the transmitting device 120 and/or the receiving device 130.
  • a transmitting device performs channel coding (140) on the data to be transmitted to introduce redundancy, thereby resisting distortion probably introduced in a transmission channel (for example, 131, 132, and 133 in FIG. 1A).
  • the channel-coded data may be further channel interleaved (not shown) and/or modulated (150) before being transmitted.
  • a process reverse to that of the transmitting device is performed. That is, the received signal is demodulated (160), de-interleaved (not shown) and decoded (170) to recover the transmitted data.
  • other or different processing may be involved at the transmitting device, and the receiving device may perform a reverse operation accordingly.
  • polar code is used in the channel encoding processing 140 in FIG. IB.
  • the polar code implements polarization of the channel by two steps, namely channel combination and channel splitting.
  • the channel as used herein is an encoding channel, namely a channel involved in the encoding process from an input to an output, rather than the transmission channels 131-133 in FIG. 1A.
  • the channel experienced by each encoding bit may also be referred to as a sub-channel. Different split sub-channels have different channel transfer probabilities. Due to the presence of a channel transfer characteristic, for the polar code, if an error occurs to a certain bit decoded previously, it may affect the decoding of the following bits, thus resulting in error spread.
  • any modulation technique known or to be developed in the future may be used, such as BPSK, QPSK, 64QAM.
  • the embodiments of the present disclosure are not limited to any specific modulating manner. It would be appreciated that, in modulation 160 of the receiving device 130, a de-modulating manner will be varied in accordance to the modulating manner. As those skilled in the art would appreciate, the receiving device may use, alternatively or in addition, processing other than de-modulation, based on different processing used by the transmitting device.
  • the decoding 170 as shown in FIG. IB may use, for example but is not limited to, a list-based decoding method, or a method based on sequence cancellation (SC), or any decoding method known or to be developed in the future.
  • SC sequence cancellation
  • the embodiments of the present disclosure provide methods and devices for improving coding and decoding.
  • CRC will be taken as an example of the error detection code used in polar codes.
  • the error detection code may also include other linear grouping codes, such as a BCH code, a Hamming code, or a Gray code.
  • other types of error detection codes may also be applied, such as a parity check code, an error detection code generated based on a Hash function and so on.
  • the scope of the present disclosure is not limited in this regard.
  • G j (l ⁇ i ⁇ k, k is a natural number) represents a column vector of the 1 th CRC bit C j .
  • C j mod(X£j j ,2), where X represents a row vector in a matrix corresponding to the information bits.
  • X represents a row vector in a matrix corresponding to the information bits.
  • the combined BER of the 1 th CRC bit may be represented as:
  • 6? j represents the sub-channel BER of the 1 th CRC bit corresponding to its generator matrix vector G j
  • ⁇ p( j ) represents the BER of a permutation of several information bits corresponding to the 1 th CRC bit.
  • the purpose of the embodiments of the present disclosure is to minimize the variation of G j .
  • FIGs. 2 and 3 Example methods according to the embodiments of the present disclosure are described with reference to FIGs. 2 and 3. For the ease of discussion, FIGs. 2 and 3 will be depicted with reference to the environment as shown in FIG. 1A.
  • FIG. 2 is a flowchart of a method 200 in accordance with embodiments of the present disclosure.
  • the method 200 may be implemented at the communication device acting as the transmitting device in the communication network 100.
  • the communication device is the terminal device 111 or 112, or the network device 101 as shown in FIG. 1.
  • the method 200 will be described with reference to the network device 101 as shown in FIG. 1. It is to be understood that method 200 may further include additional steps not shown and/or omit some shown steps, and the scope of the present disclosure is not limited in this regard.
  • the network device 101 generates an error detection code for information bits to be encoded with a polar code, the error detection code being distributed in a first order in the information bits.
  • the error detection codes may include linear grouping codes, such as a CRC code, a BCH code, a Hamming code, or a Gray code.
  • the CRC code will be taken as an example of the error detection code in the following depiction.
  • a CRC generator matrix may be used to generate the CRC code, and the first order, for example, may indicate that CRC bits are distributed after the information bits. In some other embodiments, the first order may indicate that CRC bits are distributed before the information bits.
  • the first order may indicate that the CRC bits are distributed in the information bits with the same or different space. In some other embodiments, the first order may indicate that CRC bits are distributed in specific positions so as to be mapped to better sub-channels. In some other embodiments, the first order may indicate that CRC bits are distributed in specific positions so as to be mapped to worse sub-channels.
  • the set of bits to be redistributed may also include both the information bits and the CRC bits.
  • the network device 101 redistributes a bit in the set of bits such that the error detection code is distributed in the information bits in a second order.
  • the second order may reflect an order of the information bits and the CRC code to be encoded being mapped to the sub-channels of the encoder.
  • the network device 101 may obtain configuration information on polar code encoding, and redistribute a bit in the set of bits based on the configuration information.
  • the configuration information may include, but is not limited to, for instance, code rate, a size of an information block and the number of CRC bits in use.
  • the network device 101 may first define a predetermined sequence for the X bits determined at block 220, and rearrange the X bits based on the predetermined sequence for the first time.
  • the predetermined sequence may specify the order of a permutation of the X bits (for example, their respective indices).
  • the predetermined sequence may be applied to each transmission from the network device 101.
  • the network device 101 may then specify an offset for a specific transmission to perform a second round of cyclic permutation to the X bits which have been rearranged for the first time.
  • the offset may be applied in a cyclic manner to the set of bits rearranged for the first time for each transmission, resulting in a plurality of transmission orders depending on the length of the set of bits. Further depiction will be given below with reference to some specific examples.
  • the predetermined sequence defined for the X bits may specify to order the X bits in sequence according to respective indexes of the bits, for example, in an ascending order (namely, from 1 to X) or a descending order (namely, from X to 1).
  • bit reversion can be performed on an index of a bit so as to generate a bit-reverted index for the bit.
  • the X bits can be arranged in sequence according to their respective bit reversed indexes. For example, assuming that the original index of a certain bit is OblOll, its index may become 0b 1101 after the bit reversion.
  • the predetermined sequence defined for the X bits may be a known pseudo-random sequence, such as a gold sequence.
  • the predetermined sequence defined for the X bits may also be some combination of the above sequences.
  • the network device 101 may specify an offset for a specific transmission.
  • the offset may be a predetermined value or a value determined based on history data.
  • the offset may be preconfigured in the system, namely, the offset may be static.
  • the offset may also be specified by signaling.
  • the network device 101 may utilize this offset to perform circular permutation to the X bits rearranged in a predetermined sequence. A specific example will be provided as below.
  • the sequence defined for the 12 bits specifies that the 12 bits are arranged in an ascending order according to their respective indexes. That is, the order of the bits remains unchanged after the first rearrangement.
  • the set of bits after the circular permutation is [b4, b5, b6, b7, b8, cl, c2, c3, c4, bl, b2, b3].
  • the set of bits determined at block 220 may include a first subset and a second subset.
  • the first subset may include the information bits while the second subset may include the CRC bits.
  • Bits in the first subset may be redistributed in a third order while bits in the second subset may be redistributed in a fourth order which is different from the third order.
  • the third and/or fourth order may be determined in a similar manner as that for determining the first and/or second order. Specifically, different predetermined sequences and/or offsets may be assigned for the first and second subsets so as to realize different permutation for different subsets.
  • embodiments of the present disclosure may additionally or alternatively redistribute the information bits and the error detection code to be encoded in any other manner currently known or to be developed in the future, and the scope of the present disclosure is not limited in this regard.
  • the network device 101 maps the redistributed information bits and the error detection code to the input of a polar code encoder for encoding with the polar code.
  • the redistributed information bits and error detection code may be mapped to the sub-channels of the polar code encoder in a conventional manner.
  • the information bits and CRC bits to be encoded may be mapped in the second order to the sub-channels of the encoder sequentially.
  • other predetermined manners may also be used to perform the above mapping. For example, any approach currently known or to be developed in the future may be used to implement the above mapping. The scope of the present disclosure is not limited in this regard.
  • the CRC bits can be distributed in information bits evenly so that the variation of G j in the above equation (2) can be minimized. That is, embodiments of the present disclosure make it possible to reduce FAR without increasing the number of bits of the error detection code and provide better error detection capability.
  • embodiments of the present disclosure allow to make any changes using the existing CRC codecs and/or polar code codecs. Therefore, embodiments of the present disclosure achieve relatively low implementation complexity.
  • part or ail of the blocks 220-240 may be implemented by the specific polar code encoder in the network device 101. In other words, the polar code encoder may complete the process of redistributing the information bits and CRC bits and mapping them to the corresponding sub-channels, thereby reducing the system complexity of the transmitting device.
  • FIG. 3 is a flowchart illustrating a method 300 in accordance with the embodiments of the present disclosure.
  • the method 300 may be implemented at the communication device acting as a receiving device in the communication network 100.
  • the communication device is the terminal device 11 lor 112, or network device 101 as shown in FIG. 1.
  • the method 300 will be described below with reference to the terminal device 111 as shown in FIG. 1. It is to be understood that the method 300 may further include additional acts not shown and/or omit some shown steps, and the scope of present disclosure is not limited in this regard.
  • the terminal device 111 performs polar code decoding on received data encoded with a polar code so as to obtain output bits. It is to be understood that any polar code decoder currently known or to be developed in the future may be used to implement the decoding operation.
  • the terminal device 111 obtains mapping information aboout the input of the polar code encoder.
  • the mapping information may indicate that an error detection code used in the polar code encoding is distributed in a predetermined order in the information bits.
  • the mapping information may include a predetermined sequence, an offset and/or other associated information for redistributing the set of bits to be encoded at the encoder side.
  • the mapping information may be preconfigured in the system (for instance, at the transmitting and receiving devices). That is, the mapping information can be static. Alternatively, the mapping information may also be transmitted between the transmitting device and the receiving device via signaling.
  • the terminal device 111 obtains, based on a predetermined order, the information bits and the error detection code from the output bits. This act is reverse to that as described above with respect to block 230 in FIG. 2, which will not be described in detail herein.
  • block 330 may also be implemented by a specific polar code decoder in the terminal device 111. That is, a polar code decoder may complete the process of polar code decoding and restoring the information bits and the CRC bits from the decoded sequence of bits, thereby reducing the system complexity of the receiving device.
  • the terminal device 111 may verify information bits with the error detection code.
  • block 340 may be completed by an existing CRC decoder. That is, embodiments of the present disclosure do not need to make any changes to the existing CRC decoder.
  • FIG. 4 is a block diagram of an apparatus 400 in accordance with some embodiments of the present disclosure.
  • the apparatus 400 may be implemented at a communication device acting as the transmitting device, for example at the terminal device 111 or 112 or at the network device 101 as shown in FIG. 1.
  • the apparatus 400 may be a software module based system, or may be a hardware component such as a transmitter or the like. Specially, in some embodiments, the apparatus 400 may be considered as an example implementation of the transmitting device itself.
  • the apparatus 400 may include an error detection code generating unit 410 configured to generate an error detection code for information bits to be encoded with a polar code, the error detection code being distributed in the information bits in a first order.
  • the apparatus 400 may further include a mapping unit 420 configured to: determine, from among the information bits and the error detection code, a set of bits to be redistributed; redistribute a bit in the set of bits such that the error detection code is distributed in the information bits in a second order; and map the redistributed information bits and the error detection code to an input of a polar code encoder.
  • the apparatus 400 may further include a polar code encoding unit 430 configured to encode, with the polar code, the information bits together with the error detection code distributed therein.
  • the error detection code is selected from a group consisting of a Cyclic Redundant Check code, a BCH code, a Hamming code, and a Gray code.
  • the mapping unit 420 further includes a first selecting unit configured to select the set of bits such that the set of bits at least include the information bits. [0056] In some embodiments, the mapping unit 420 further includes a second selecting unit configured to select the set of bits such that the set of bits at least include a bit of the error detection code.
  • the mapping unit 420 further includes a first bit distribution unit configured to obtain configuration information on the encoding with the polar code; and redistribute a bit in the set of bits based on the configuration information.
  • the mapping unit 420 further includes a second bit distribution unit configured to order a bit in the set of bits in sequence based on a first index of a bit in the set of bits.
  • the mapping unit 420 further includes a third bit distribution unit configured to perform bit reversion to a first index of a bit in the set of bits so as to generate a second index of the bit; and order the bit based on the second index.
  • the mapping unit 420 further includes a fourth bit distribution unit configured to redistribute a bit in the set of bits based on a pseudorandom sequence.
  • the mapping unit 420 further includes a fifth bit distribution unit configured to determine an offset for redistributing the set of bits; and perform, based on the offset, cyclic permutation to a bit in the set of bits.
  • FIG. 5 is a block diagram of an apparatus 500 according to some embodiments of the present disclosure.
  • the apparatus 500 may be implemented at a communication device acting as a receiving device, for example at the terminal device 111 or 112 or the network device 101 as shown in FIG. 1.
  • the apparatus 500 may be a software module based system, or may be a hardware component such as a transmitter or the like. Specially, in some embodiments, the apparatus 500 may be considered as an example implementation of the receiving device itself.
  • the apparatus 500 may include: a polar code decoding unit 510 configured to perform polar code decoding on received data encoded with a polar code to obtain output bits; an information obtaining unit 520 configured to obtain mapping information on an input of a polar code encoder, the mapping information indicating that an error detection code used in the encoding with the polar code is distributed in a predetermined order in information bits; a reverse mapping unit 530 configured to obtain, based on the predetermined order, the information bits and the error detection code from the output bits; and a verifying unit 540 configured to verify the information bits with the error detection code.
  • a polar code decoding unit 510 configured to perform polar code decoding on received data encoded with a polar code to obtain output bits
  • an information obtaining unit 520 configured to obtain mapping information on an input of a polar code encoder, the mapping information indicating that an error detection code used in the encoding with the polar code is distributed in a predetermined order in information bits
  • a reverse mapping unit 530 configured to obtain
  • the error detection code is selected from a group consisting of a Cyclic Redundant Check code, a BCH code, a Hamming code, and a Gray code.
  • each unit of the apparatus 400 and/or 500 may be a hardware module, or may be a software module.
  • the apparatus 400 and/or 500 may be partially or entirely implemented in software and/or firmware, for example implemented as a computer program product included on a computer readable medium.
  • the apparatus 400 and/or 500 may be partially or entirely implemented based on hardware, for example implemented as an Integrated Circuit (IC), an Application-specific Integrated Circuit (ASIC), a System- on- a-chip systems (SOC), a Field-programmable Gate Array (FPGA), or the like.
  • IC Integrated Circuit
  • ASIC Application-specific Integrated Circuit
  • SOC System- on- a-chip systems
  • FPGA Field-programmable Gate Array
  • FIG. 6 is a block diagram of a communication device 600 suitable for implementing embodiments of the present disclosure.
  • the device 600 may be used to implement the transmitting device or the receiving device in the embodiments of the present disclosure, for example the network device 101 or the terminal device as shown in FIG. 1, such as the terminal device 111 or 112 as shown in FIG. 1.
  • the device 600 includes a processor 610.
  • the processor 610 controls operations and functionality of the device 600.
  • the processor 610 may perform various operations by means of instructions 630 stored in a memory 620 coupled thereto.
  • the memory 620 may be of any appropriate type applicable to a local technical environment, and may be implemented using any appropriate data storage technique, including but not limited to, a semiconductor-based storage device, a magnetic storage device and system, an optical storage device and system. Though FIG. 6 only shows a memory unit, the device 600 may include multiple physically different memory units.
  • the processor 610 may be of any appropriate type applicable to a local technical environment, and may include, but not limited to, one or more of general purpose computers, special purpose computers, microprocessors, digital signal processors (DSPs) and a controller based multi-core processor architecture.
  • the device 600 may further include multiple processors 610.
  • the processor 610 may be coupled to a transceiver 640 which may implement transmitting and receiving of information with aid of one or more antennae 650 and/or other components.
  • the processor 610 and the memory 620 may be operated in cooperation, to implement the methods 200 and/or 300 as described with reference to FIGs. 2-3. Specifically, if the communication device 600 acts as a transmitting device, the communication device 600 may be used to perform the method 200 when the instructions 630 in the memory 620 are executed by the processor 610. If the communication device 600 acts as a receiving device, the communication device 600 may be caused to perform the method 300 when the instructions 630 in the memory 620 are executed by the processor 610. It would be appreciated that all features as described above are all applicable to the device 600, which are omitted herein.
  • various embodiments of the present disclosure may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. Some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, a microprocessor or another computing device. While various aspects of embodiments of the present disclosure are illustrated and described as block diagrams, flowcharts, or using some other pictorial representation, it will be appreciated that the blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.
  • the embodiments of the present disclosure may be described in the context of the machine executable instruction which for example includes program modules executed in the device on a real or virtual processor.
  • program modules include routines, programs, libraries, objects, classes, components, data structures, or the like that perform particular tasks or implement particular abstract data types.
  • the functionality of the program modules may be combined or split between program modules as desired in various embodiments.
  • Machine-executable instructions for program modules may be executed within a local or distributed device. In a distributed device, program modules may be located in both local and remote storage media.
  • Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages.
  • program codes may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by a computer or other programmable data processing devices, cause the functions/operations specified in the flowcharts and/or block diagrams to be implemented.
  • the program code may execute entirely on a machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
  • the machine readable medium may be any tangible medium that may contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
  • the machine readable medium may be a machine readable signal medium or a machine readable storage medium.
  • a machine readable medium may include but not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine readable storage medium would include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

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Abstract

Des modes de réalisation de la présente invention concernent un procédé et un appareil de traitement de données dans un système de communication. Par exemple, un procédé consiste à : générer un code de détection d'erreur pour des bits d'information devant être codés avec un code polaire, le code de détection d'erreur étant distribué dans les bits d'informations dans un premier ordre ; déterminer, parmi les bits d'informations et le code de détection d'erreur, un ensemble de bits devant être redistribué ; redistribuer un bit de l'ensemble de bits de sorte que le code de détection d'erreur soit distribué dans les bits d'informations dans un second ordre ; et mapper les bits d'informations redistribués et le code de détection d'erreur sur une entrée d'un codeur de code polaire devant être codée avec le code polaire. Des modes de réalisation de la présente invention concernent en outre un dispositif de communication apte à implémenter le procédé susmentionné.
PCT/IB2018/000223 2017-02-13 2018-02-09 Procédé et dispositif de détection d'erreur distribuée avec des codes polaires WO2018146554A1 (fr)

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