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WO2018143773A1 - Procédé de transmission d'informations et dispositif de transmission - Google Patents

Procédé de transmission d'informations et dispositif de transmission Download PDF

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WO2018143773A1
WO2018143773A1 PCT/KR2018/001578 KR2018001578W WO2018143773A1 WO 2018143773 A1 WO2018143773 A1 WO 2018143773A1 KR 2018001578 W KR2018001578 W KR 2018001578W WO 2018143773 A1 WO2018143773 A1 WO 2018143773A1
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row
bit
bits
index
channel
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PCT/KR2018/001578
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English (en)
Korean (ko)
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노광석
김봉회
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엘지전자 주식회사
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • the present invention relates to a wireless communication system, and to a method and apparatus for transmitting information.
  • M2M machine-to-machine
  • MTC machine type communication
  • smart phones tablet PCs
  • tablet PCs tablet PCs
  • Multi-antenna technology multi-base station cooperation technology, and the like are developing.
  • eMBB enhanced mobile broadband
  • RAT legacy radio access technology
  • massive machine type communication for connecting a plurality of devices and objects to provide various services anytime and anywhere is one of the major issues to be considered in next-generation communication.
  • next generation radio access technology has been discussed in consideration of eMBB communication, mMTC, ultra-reliable and low latency communication (URLLC), and the like.
  • the method includes encoding input information using a generator matrix G N of size N.
  • the method includes transmitting some of the output bits encoded according to the index sequence.
  • a transmitter for transmitting information in a wireless communication system includes a memory, a radio frequency (RF) unit, and a processor configured to control the RF unit.
  • the processor size N as max of generator matrix G ascending from the row index of the small line row weight, and in ascending order from small row index equal to the row weight, from the memory that stores the row index, based on the following equation: Can be configured to sequentially read N ( ⁇ N max ) row indices to produce an index sequence of N row indices: , Where P max N max , w is the row weight.
  • the processor may be configured to encode input information using a generator matrix G N of size N.
  • the processor may be configured to control the RF unit to transmit some of the output bits encoded according to the index sequence.
  • each aspect of the present invention if the index sequence a 0 , a 1 , a 2 , ...., a N ⁇ 1 , and the number M of bits that can be transmitted is less than N, then row indexes a 0 , a 1 , .. a The remaining bits except for the P encoding bits corresponding to P ⁇ 1 may be transmitted as part of the above.
  • P NM
  • a i is the i-th row index of the rows that make up the index index sequence.
  • the equation represents a starting memory address for each row weight w, wherein generating the index sequence begins with the larger of the row weights of the generator matrix G N , and for each row weight w Starting from the corresponding starting memory address, reading the N row indexes while decrementing the memory address.
  • the generator matrix G N may be a generator matrix of polar code.
  • the input information may be encoded via a polar encoder of the transmitter.
  • the wireless communication signal can be efficiently transmitted / received. Accordingly, the overall throughput of the wireless communication system can be high.
  • delays / delays generated in the communication process between the user equipment and the base station may be reduced.
  • Signals can also be transmitted / received efficiently and at low error rates in wireless communication systems.
  • FIG. 1 illustrates a process of a transport block in an LTE / LTE-A system.
  • FIG. 2 is a block diagram illustrating performing rate matching by separating the systematic and parity portions of an encoded code block.
  • FIG. 4 is a block diagram for a polar code encoder.
  • FIG. 6 illustrates N-th level channel combining for polar code.
  • FIG 9 illustrates a process of generating a bit index sequence according to the present invention.
  • FIG. 10 shows the SNR required to achieve a specific block error ratio (BLER) for polar codes having various information block lengths.
  • BLER block error ratio
  • FIG. 11 illustrates an encoding module of a polar code.
  • FIG. 12 illustrates the row weights and corresponding row indices of the transformation matrix G, and a memory address in accordance with the present invention.
  • Figure 13 illustrates puncturing and information bit allocation in accordance with the present invention.
  • 15 is a block diagram showing the components of the transmitter 10 and the receiver 20 for carrying out the present invention.
  • multiple access systems include code division multiple access (CDMA) systems, frequency division multiple access (FDMA) systems, time division multiple access (TDMA) systems, orthogonal frequency division multiple access (OFDMA) systems, and single carrier frequency (SC-FDMA).
  • CDMA code division multiple access
  • FDMA frequency division multiple access
  • TDMA time division multiple access
  • OFDMA orthogonal frequency division multiple access
  • SC-FDMA single carrier frequency division multiple access
  • MCD division multiple access
  • MCDMA multi-carrier frequency division multiple access
  • CDMA may be implemented in a radio technology such as Universal Terrestrial Radio Access (UTRA) or CDMA2000.
  • TDMA may be implemented in radio technologies such as Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Enhanced Data Rates for GSM Evolution (EDGE) (i.e., GERAN), and the like.
  • GSM Global System for Mobile Communication
  • GPRS General Packet Radio Service
  • EDGE Enhanced Data Rates for GSM Evolution
  • OFDMA may be implemented in wireless technologies such as Institute of Electrical and Electronics Engineers (IEEE) 802.11 (WiFi), IEEE 802.16 (WiMAX), IEEE802-20, evolved-UTRA (E-UTRA), and the like.
  • IEEE Institute of Electrical and Electronics Engineers
  • WiFi WiFi
  • WiMAX WiMAX
  • IEEE802-20 evolved-UTRA
  • UTRA is part of Universal Mobile Telecommunication System (UMTS)
  • 3GPP 3rd Generation Partnership Project
  • LTE Long Term Evolution
  • 3GPP LTE adopts OFDMA in downlink (DL) and SC-FDMA in uplink (UL).
  • LTE-advanced (LTE-A) is an evolution of 3GPP LTE.
  • the present invention will be described on the assumption that the present invention is applied to a 3GPP based communication system, for example, LTE / LTE-A, NR.
  • a 3GPP based communication system for example, LTE / LTE-A, NR.
  • the technical features of the present invention are not limited thereto.
  • the following detailed description is described based on a mobile communication system corresponding to a 3GPP LTE / LTE-A / NR system, except for the matters specific to 3GPP LTE / LTE-A / NR, Applicable to any mobile communication system.
  • the expression “assuming” may mean that the subject transmitting the channel transmits the channel so as to correspond to the "assuming”.
  • the subject receiving the channel may mean that the channel is received or decoded in a form conforming to the "home", provided that the channel is transmitted to conform to the "home”.
  • the UE may be fixed or mobile, and various devices which communicate with a base station (BS) to transmit and receive user data and / or various control information belong to the same.
  • BS Base station
  • UE Terminal Equipment
  • MS Mobile Station
  • MT Mobile Terminal
  • UT User Terminal
  • SS Subscribe Station
  • wireless device PDA (Personal Digital Assistant), wireless modem
  • a BS generally refers to a fixed station communicating with the UE and / or another BS, and communicates with the UE and another BS to exchange various data and control information.
  • the BS may be referred to in other terms such as ABS (Advanced Base Station), Node-B (NB), evolved-NodeB (NB), Base Transceiver System (BTS), Access Point, and Processing Server (PS).
  • ABS Advanced Base Station
  • Node-B Node-B
  • NB evolved-NodeB
  • BTS Base Transceiver System
  • gNB Base Transceiver System
  • PS Processing Server
  • the base station of the UTRAN is called Node-B
  • the base station of the E-UTRAN is called eNB
  • gNB base station of the new radio access technology network
  • the BS is collectively referred to as eNB.
  • a node refers to a fixed point capable of transmitting / receiving a radio signal by communicating with a UE.
  • Various forms of eNBs may be used as nodes regardless of their names.
  • a node may be a BS, an NB, an eNB, a pico-cell eNB (PeNB), a home eNB (HeNB), a relay, a repeater, or the like.
  • the node may not be an eNB.
  • it may be a radio remote head (RRH), a radio remote unit (RRU).
  • RRH, RRU, etc. generally have a power level lower than the power level of the eNB.
  • RRH or RRU, RRH / RRU is generally connected to the eNB by a dedicated line such as an optical cable
  • RRH / RRU and eNB are generally compared to cooperative communication by eNBs connected by a wireless line.
  • cooperative communication can be performed smoothly.
  • At least one antenna is installed at one node.
  • the antenna may mean a physical antenna or may mean an antenna port, a virtual antenna, or an antenna group. Nodes are also called points.
  • a cell refers to a certain geographic area in which one or more nodes provide communication services. Therefore, in the present invention, communication with a specific cell may mean communication with an eNB or a node that provides a communication service to the specific cell.
  • the downlink / uplink signal of a specific cell means a downlink / uplink signal from / to an eNB or a node that provides a communication service to the specific cell.
  • the cell providing uplink / downlink communication service to the UE is particularly called a serving cell.
  • the channel state / quality of a specific cell means a channel state / quality of a channel or communication link formed between an eNB or a node providing a communication service to the specific cell and a UE.
  • a UE may transmit a downlink channel state from a specific node to a CRS (s) in which antenna port (s) of the specific node are transmitted on a Cell-specific Reference Signal (CRS) resource allocated to the specific node; / Or can be measured using the CSI-RS (s) transmitted on the Channel State Information Reference Signal (CSI-RS) resources.
  • CRS Cell-specific Reference Signal
  • the 3GPP-based communication system uses the concept of a cell to manage radio resources.
  • Cells associated with radio resources are distinguished from cells in a geographic area.
  • a "cell” in a geographic area may be understood as coverage in which a node can provide services using a carrier, and a "cell” of radio resources is a bandwidth (frequency) that is a frequency range configured by the carrier. bandwidth, BW).
  • Downlink coverage which is a range in which a node can transmit valid signals
  • uplink coverage which is a range in which a valid signal can be received from a UE, depends on a carrier carrying the signal, so that the coverage of the node is determined by the radio resources used by the node. It is also associated with the coverage of the "cell”.
  • the term "cell” can sometimes be used to mean coverage of a service by a node, sometimes a radio resource, and sometimes a range within which a signal using the radio resource can reach a valid strength.
  • a "cell" associated with a radio resource is defined as a combination of DL resources and UL resources, that is, a combination of a DL component carrier (CC) and a UL CC.
  • the cell may be configured with DL resources alone or with a combination of DL resources and UL resources.
  • the linkage between the carrier frequency of the DL resource (or DL CC) and the carrier frequency of the UL resource (or UL CC) is indicated by system information.
  • SIB2 System Information Block Type 2
  • the carrier frequency means a center frequency of each cell or CC.
  • a cell operating on a primary frequency is referred to as a primary cell (Pcell) or a PCC
  • a cell operating on a secondary frequency (or SCC) is referred to as a secondary cell.
  • cell, Scell) or SCC The carrier corresponding to the Pcell in downlink is called a DL primary CC (DL PCC), and the carrier corresponding to the Pcell in the uplink is called a UL primary CC (DL PCC).
  • Scell refers to a cell that can be configured after RRC (Radio Resource Control) connection establishment is made and can be used for providing additional radio resources.
  • RRC Radio Resource Control
  • the Scell may form a set of serving cells for the UE with the Pcell.
  • the carrier corresponding to the Scell in downlink is called a DL secondary CC (DL SCC)
  • the carrier corresponding to the Scell in the uplink is called a UL secondary CC (UL SCC).
  • DL SCC DL secondary CC
  • UL SCC UL secondary CC
  • the 3GPP-based communication standard provides downlink physical channels corresponding to resource elements carrying information originating from an upper layer and downlink corresponding to resource elements used by the physical layer but not carrying information originating from an upper layer.
  • Physical signals are defined.
  • a physical downlink shared channel (PDSCH), a physical broadcast channel (PBCH), a physical multicast channel (PMCH), a physical control format indicator channel (physical control) format indicator channel (PCFICH), physical downlink control channel (PDCCH) and physical hybrid ARQ indicator channel (PHICH) are defined as downlink physical channels
  • reference signal and synchronization signal Is defined as downlink physical signals.
  • a reference signal (RS) also referred to as a pilot, refers to a signal of a predetermined special waveform known to the eNB and the UE.
  • a cell specific RS, UE- UE-specific RS, positioning RS (PRS), and channel state information RS (CSI-RS) are defined as downlink reference signals.
  • the 3GPP-based communication standard includes uplink physical channels corresponding to resource elements carrying information originating from an upper layer and uplink corresponding to resource elements used by the physical layer but not carrying information originating from an upper layer. It defines physical signals. For example, a physical uplink shared channel (PUSCH), a physical uplink control channel (PUCCH), and a physical random access channel (PRACH) are the uplink physical channels.
  • a demodulation reference signal (DMRS) for uplink control / data signals and a sounding reference signal (SRS) used for uplink channel measurement are defined.
  • Physical Downlink Control CHannel / Physical Control Format Indicator CHannel (PCFICH) / PHICH (Physical Hybrid automatic retransmit request Indicator CHannel) / PDSCH (Physical Downlink Shared CHannel) are respectively DCI (Downlink Control Information) / CFI ( Means a set of time-frequency resources or a set of resource elements that carry downlink format ACK / ACK / NACK (ACKnowlegement / Negative ACK) / downlink data, and also a Physical Uplink Control CHannel (PUCCH) / Physical (PUSCH) Uplink Shared CHannel / PACH (Physical Random Access CHannel) means a set of time-frequency resources or a set of resource elements that carry uplink control information (UCI) / uplink data / random access signals, respectively.
  • DCI Downlink Control Information
  • CFI Means a set of time-frequency resources or a set of resource elements that carry downlink format ACK / ACK
  • the PDCCH / PCFICH / PHICH / PDSCH / PUCCH / PUSCH / PRACH resource is referred to below ..
  • the user equipment transmits the PUCCH / PUSCH / PRACH, respectively.
  • PDCCH / PCFICH / PHICH / PDSCH is used for downlink data / control information on or through PDCCH / PCFICH / PHICH / PDSCH, respectively. It is used in the same sense as sending it.
  • 3GPP LTE / LTE-A standard document for example, 3GPP TS 36.211, 3GPP TS 36.212, 3GPP TS 36.213, 3GPP TS 36.321 and 3GPP TS 36.331 and the like, and 3GPP NR standard documents, such as 3GPP TS 38.xxx.
  • 3GPP TS 38.xxx the principles of encoding and decoding using polar codes and polar codes are described in 'E. Arikan, "Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels," in IEEE Transactions on Information Theory, vol. 55, no. 7, pp. 3051-3073, July 2009).
  • Massive MTC which connects multiple devices and objects to provide various services anytime and anywhere, is also one of the major issues to be considered in next-generation communication.
  • a communication system design considering a service / UE that is sensitive to reliability and latency has been discussed.
  • next generation RAT considering such advanced mobile broadband communication, Massive MTC, and Ultra-Reliable and Low Latency Communication (URLLC) is being discussed.
  • URLLC Ultra-Reliable and Low Latency Communication
  • 3GPP is working on the next generation mobile communication system after EPC.
  • the technology is referred to as a new RAT (new RAT, NR) or 5G RAT.
  • NR communication systems are required to support significantly better performance than existing fourth generation (4G) systems in terms of data rate, capacity, latency, energy consumption and cost.
  • 4G fourth generation
  • NR systems need to make significant advances in the area of bandwidth, spectral, energy, signaling efficiency, and cost per bit.
  • NR needs to utilize efficient waveforms to meet these needs.
  • FIG. 1 illustrates a process of a transport block in an LTE / LTE-A system.
  • information transmitted from the transmitting end is encoded and then transmitted using a forward error correction code.
  • the receiving end demodulates the received signal and then decodes the error correcting code to restore the transmission information. In this decoding process, an error in the received signal caused by the channel is corrected.
  • Data arrives at a coding block in the behavior of up to two transport blocks per TTI per DL / UL cell.
  • the following coding steps may be applied for each transport block of a DL / UL cell:
  • Turbo codes are mainly used in the existing LTE / LTE-A system.
  • the turbo code is composed of a recursive systematic convolution encoder and an interleaver.
  • an interleaver to facilitate parallel decoding, a kind of which is quadratic polynomial permutation (QPP).
  • QPP quadratic polynomial permutation
  • Such a QPP interleaver is known to maintain good performance only for certain data block sizes.
  • the performance of the turbo code is known to be good as the data block size increases.
  • the data block having a predetermined size or more is divided into several small data blocks and encoded. A small divided data block is called a code block.
  • the code blocks generally have the same size, but due to the size limitation of the QPP interleaver, one code block of several code blocks may have a different size. Interleaving is performed to reduce the effects of burst errors that occur during transmission on a wireless channel after an error correction encoding process in units of code blocks having a predetermined interleaver size. And, it is mapped to the actual radio resource and transmitted. Since the amount of radio resources used during the actual transmission is constant, rate matching must be performed on the encoded code block in order to match them. Generally, rate matching consists of puncturing or repetition.
  • the code rate of data to be transmitted through a rate matching process consisting of puncturing and repetition Will be adjusted.
  • a turbo code is used as a channel code in LTE / LTE-A, a process of channel coding and rate matching each code block in a transport channel processing process as shown in FIG. 1 is illustrated in FIG. 2.
  • FIG. 2 is a block diagram illustrating performing rate matching by separating the systematic and parity portions of an encoded code block.
  • the mother code rate of the LTE / LTE turbo encoder is 1/3.
  • the rate matching module comprises three so-called sub-block interleavers for the three output streams of the turbo encoder and a bit selection and pruning (realized) by a circular buffer. pruning).
  • the sub-block interleaver is based on a classic row-column interleaver with 32 rows and a length-32 intra-column permutation.
  • the bits of each of the three streams are written in a matrix of 32 columns, row-by-row (the number of rows depends on the stream size). Dummy bits are padded in front of each stream to completely fill the matrix. After column permutation bits are read from the matrix in column-by-column.
  • the circular buffer is the most important part of the rate matching module, which enables puncturing and repetition of mother code.
  • interleaved systematic bits are written to the circular buffer in sequence, with the first bit of the interleaved systematic bit streams at the beginning of the circular buffer.
  • Interleaved and interlaced parity bit streams are sequentially written to the circular buffer, putting the first bit of the stream after the last bit of the interleaved systematic bit stream.
  • Coded bits are read sequentially from any start point specified by redundancy version (RV) points in the circular buffer (depending on the code rate). If the end of the circular buffer is reached and more coded bits are needed for transmission (e.g., for code rates less than one third), the transmitter wraps around and continues from the beginning of the circular buffer. continue).
  • RV redundancy version
  • HARQ which stands for hybrid ARQ, is an error correction mechanism based on retransmission of packets detected as being in error.
  • the transmitted packet arrives after some propagation delay at the receiving device.
  • the receiver produces an ACK in the case of an error-free transmission and produces a NACK when an error is detected.
  • the ACK / NACK is produced after some processing time and sent to the transmitter, and reaches the transmitter after a propagation delay. In the case of NACK, after some processing delay at the transmitter, the desired packet will be sent again.
  • the bits read from the circular buffer and sent in each retransmission are different and depend on the location of the RV. There are four RVs (0, 1, 2, 3) that define the location of the starting point at which bits are read from the circular buffer. Referring to FIG. 3, as the number of retransmissions progresses, the RV increases, so fewer systematic bits and more parity bits are read from the circular buffer for retransmission.
  • NR currently offers better speed and coverage than 4G, operates in high frequency bands, speeds up to 1 Gb / s for dozens of connections, or speeds up to tens of Mb / s for tens of thousands of connections. It is required to do In order to meet the requirements of the NR system, the introduction of an advanced coding scheme is being discussed. Since data communication occurs in an inverted channel environment, channel coding plays an important role in achieving higher data rates for fast, error-free communication.
  • the selected channel code should have excellent block error ratio (BLER) performance over a certain range of block lengths and code rates.
  • BLER is defined as the ratio of the number of erroneous receiving blocks to the total number of blocks sent.
  • eMBB Massive IoT
  • URLLC Ultra-high reliability and low latency, such as industrial automation, driverless cars, remote surgery, and smart grids.
  • Polar code is a code that provides a new framework to solve the problems of existing channel codes and was invented by Arikan of Bikent University (see E. Arikan, "Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels, "in IEEE Transactions on Information Theory, vol. 55, no. 7, pp. 3051-3073, July 2009).
  • Polar codes are mathematically proven, first capacity-achieving codes with low encoding and decoding complexity. Polar code outperforms turbo code at large block lengths without any error flow.
  • channel coding using a polar code is called polar coding.
  • Polar codes are known as achieve number codes in a given binary discrete memoryless channel. This can only be done when the block size is large enough. That is, a polar code is a code that can achieve channel capacity if the code size N is infinitely large. Polar codes are less complex to encode and decode and can be successfully decoded. Polar code is a type of linear block error correcting code, and a number of recursive concatenations are the basic building blocks for polar code and the basis for code construction. A physical transformation of the channel occurs that transforms the physical channels into virtual channels, which is based on a recursive multiple concatenation. When multiple channels are multiplied and accumulated, most of the channels get better or worse, and the idea behind the polar code is to use good channels. For example, sending data at rate 1 on good channels and rate 0 on bad channels. In other words, through channel polarization, channels enter a polarized state from a normal state.
  • FIG. 4 is a block diagram for a polar code encoder.
  • W 2 denotes an entire equivalent channel obtained by combining two binary discrete memory channels (B-DMC) and W.
  • B-DMC binary discrete memory channels
  • u 1 and u 2 are binary-input source bits
  • y 1 and y 2 are output coded bits.
  • Channel combining is a process of parallel concatenating B-DMC channels.
  • Channel W 2 may achieve symmetric capacity I (W), which is the highest rate.
  • Symmetric capacity is an important parameter in the B-DMC W, which is used for the measurement of rate, and is the highest rate at which reliable communication can occur across the channel W.
  • B-DMC may be defined as follows.
  • channel polarization is the process of creating a second set of N channels ⁇ W N (i) : 1 ⁇ i ⁇ N ⁇ using N independent copies of a given B-DMC W, where the channel polarization effect is N
  • N all symmetric capacity terms ⁇ I (W N (i) ) ⁇ tend to be zero or one except for the vanishing fraction of the indices i.
  • the concept behind channel polarization in polar codes is that N copies (i.e., N transmissions) of a channel (eg, additive white Gaussian noise channel) with symmetric capacity of I (W). S) to extreme channels of close capacity of one or zero.
  • Channel polarization consists of two phases: the channel combining phase and the channel splitting phase.
  • FIG. 5 illustrates the concept of channel combining and channel splitting for channel polarization.
  • Bits passing through the in-channel cannot transmit information, so it is better to transmit frozen bits, which are meaningless bits.
  • N 2 n and n is an integer greater than or equal to 0.
  • n 1 means the first level of regression where two independent copies of W 1 combine together.
  • Combining the two copies yields channel W 2 : X 2 ⁇ Y 2 .
  • the transitional probability of this new channel W 2 can be expressed by the following equation.
  • channel W 2 Once the channel W 2 is obtained, a single copy of channel W 4 can be obtained by combining two copies of W 2 .
  • This regression can be represented by W 4 : X 4 ⁇ Y 4 with the next transition probability.
  • G N is a generator matrix of size N.
  • G 2 corresponds to the base matrix F shown in FIG. 4 (b).
  • G 4 may be represented by the following matrix.
  • x N 1 u N 1 G N.
  • x N 1 ⁇ x 1 , ..., x N ⁇
  • u N 1 ⁇ u 1 , ..., u N ⁇ .
  • each B-DMC may be expressed in a recursive form. That is, G N may be expressed by the following equation.
  • R N first expands to Basic-2. The bit-reversing interleaver may not be included in the transmitting end. The relationship of equation (6) is shown in FIG.
  • FIG. 6 illustrates N-th level channel combining for polar code.
  • Channel splitting may be expressed as a channel transition probability as shown in the following equation.
  • channels ⁇ W N (i) ⁇ are polarized in the following sense.
  • indices of I (W N (i) ) ⁇ (1- ⁇ , 1] as N goes to infinity through a power of 2
  • the fraction of i ⁇ ⁇ 1, ..., N ⁇ goes to I (W)
  • the fraction of I (W N (i) ) ⁇ [0, ⁇ ) goes to 1-I (W). Therefore, if N ⁇ ⁇ , the channels are completely noisy or are freely polarized in noise, and these channels are exactly known at the transmitting end. Thus, it is possible to fix bad channels and to send the unsolidified bits on the good channels.
  • An input of a polar encoder is divided into a bit channel to which information data is mapped and a bit channel not to it.
  • input bit channels may be divided into a noiseless channel and a noise channel as the codeword of the polar code becomes infinity. Therefore, by allocating information to a noiseless bit channel, channel capacity can be obtained.
  • the reliability of the input bit channel is calculated and the data bits are allocated in that order.
  • a bit channel to which data bits are allocated is referred to as a good bit channel.
  • a good bit channel is an input bit channel to which data bits are mapped.
  • the bit channel to which data is not mapped is called a frozen bit channel, and encoding is performed by inputting a known value (eg, 0) to the frozen bit channel. Any value known to the transmitter and receiver can be mapped to the frozen bit channel.
  • a codeword bit (ie, output bit) location corresponding to an input bit location that is not assigned to an information bit may be punctured.
  • the decoding method of the polar code is a successive cancellation (SC) decoding method.
  • SC decoding is a method of obtaining a channel transition probability and calculating a likelihood ratio (LLR) for an input bit.
  • the channel transition probability may be calculated in a recursive manner by using a characteristic in which the channel combining and channel splitting processes are recursive.
  • the LLR value can also be calculated in a recursive fashion.
  • u 1 ) for the input bit u i can be obtained as follows.
  • u 1 i is divided into an odd index and an even index, It can be expressed as u 1, o i , u 1, e i .
  • the channel transition probability may be expressed as the following equations.
  • the polar decoder retrieves the information and generates an estimate u ⁇ N 1 of u N 1 with values known to the polar code (eg, received bits, frozen bits, etc.).
  • LLR is defined as follows.
  • LLR can be calculated recursively as follows.
  • LLR L (1) 1 (y i ) W (y i
  • L (1) 1 (y i ) is the soft information observed from the channel.
  • d min (C) min i ⁇ I 2 wt (i) .
  • SC List (SCL) decoding is an extension of the basic SC decoder.
  • the L decoding paths are considered simultaneously in each stage of decoding.
  • L is an integer.
  • the list-L decoding algorithm is an algorithm that simultaneously tracks L paths in the decoding process.
  • FIG. 7 illustrates the evolution of decoding paths in the List-L decoding process.
  • the number of bits to be determined is n and not all bits are frozen.
  • CRC aided SCL decoding is SCL decoding using CRC, which improves the performance of the polar code.
  • CRC assisted SCL decoding aims to detect an error-free path while checking a cyclic redundancy check (CRC) code for each path at a receiver.
  • the SCL decoder outputs candidate sequences to the CRC detector which feeds back the check result to aid in codeword determination.
  • CRC cyclic redundancy check
  • SCL decoding or CRC assisted SCL decoding is more complex than SC algorithm, but has the advantage of superior decoding performance.
  • List-X decoding algorithm for polar codes, see 'I. Tal and A. Vardy, "List decoding of polar codes," in Proc. IEEE Int. Symp. Inf. Theory, pp. 1-5, Jul. 2011 '.
  • Polar code has the disadvantage that the code design is independent of the channel, so that there is no flexibility in the mobile fading channels, and since it is a relatively recently introduced code, it is not yet mature and is only limitedly applied.
  • the polar coding proposed up to now is not defined in many applications.
  • the present invention is to propose a polar coding method suitable for a wireless communication system.
  • the present invention provides a method for polar coding in which data is sent at a rate of 1 in channels having a channel capacity of 1 or almost 1 and data at a rate of 0 in channels having a channel capacity of 0 or almost 0. Suggest.
  • C (W i ) is the capacity of channel W i , which corresponds to the reliability of the channels that the input bits of the polar code will experience. If the channel capacities corresponding to the input bit positions of the polar code are as shown in FIG. 8, the reliability of the input bit positions can be ranked as shown in FIG. 8. In this case, in order to transmit data at the code rate 1/2, the transmitter transmits the four bits constituting the data to four input bit positions having a high channel capacity among eight input bit positions of the polar code. assigned to the input bit position of the 8 U 1 ⁇ U 8 of U 4, U 6, the input bit position indicated by U 7 and U 4), and the remaining input bit positions are frozen.
  • the generator matrix G 8 corresponding to the polar code of FIG. 8 is as follows. The generator matrix G 8 may be obtained based on Equation 6.
  • the input bit positions labeled U 1 to U 8 in FIG. 8 correspond one-to-one to the rows from the lowest row to the highest row of G 8 .
  • an input bit corresponding to U 8 affects all output coded bits.
  • the input bit corresponding to U 1 only affects Y 1 of the output coded bits.
  • Equation 12 when the binary-input source bits U 1 to U 8 and G 8 are multiplied, a row that causes the corresponding input bit to appear in all the output bits is represented by all elements of the rows of G 8 . Lowest row [1, 1, 1, 1, 1, 1, 1].
  • a row that causes the corresponding binary-input source bit to appear in only one output bit is a row where one element of the rows of G 8 is 1, that is, the row weight is 1 [1, 0, 0, 0 , 0, 0, 0, 0].
  • a row having a row weight of 2 reflects the input bits corresponding to the rows in the two output bits. Referring to FIG. 8) and (12, U 1 ⁇ U 8 corresponds one-to-one to the rows of the G 8, the input position of U 1 ⁇ U 8, that is, to distinguish between the input position to the rows of the G 8 Bit indexes may be given.
  • bit indices are sequentially assigned from N to N-1, starting from the highest row having the smallest row weight, for the N input bits to G N.
  • the input position of U 1 that is, to be a bit index 0 given to the first row of the G 8
  • the input position of the U 8 that is, the bit index 7 in the last row of G 8 Is given.
  • the bit indices may be allocated differently. For example, starting from the lowest row having the largest row weight, bit indexes 0 to N-1 may be allocated.
  • bit index sequence of the present invention is obtained by subtracting the corresponding element value from N-1. Same as converted to value.
  • bit index 0 is allocated from an input position corresponding to the lowest row having the largest row weight
  • the bit index sequence of Example 1 may be converted from the highest index to the lowest index as follows.
  • bit indices are allocated from 0 to N-1, but it is also possible to start with a number other than zero. That is, in the present invention, the bit indices may be able to distinguish the input positions of the polar code, and the input positions to which the information bits are assigned and the frozen bits are allocated to the transmitter and the receiver using the same or corresponding bit index sequences. You can interpret them the same way.
  • the present invention proposes a sequence generation method for a reliability-based bit index in order to be able to allocate information bits to input positions having high reliability at an input terminal of a polar code.
  • Density evolution generates a bit order based on the signal to noise ratio (SNR) of the channel.
  • SNR signal to noise ratio
  • density evolution has a disadvantage that the optimal bit order may be different according to the SNR and the calculation is complicated.
  • Huawei has proposed a method for generating bit index sequences using density evolution (see R1-1611254, "Details of the Polar code design," Huawei, November, 2016).
  • R1-1611254 "Details of the Polar code design," Huawei, November, 2016.
  • reliability calculation and alignment should be performed for every 2 n size of mother code.
  • the method of suggesting a bit index sequence proposed by Qualcomm uses a sequence of different mother code sizes based on one mother code size. Generate using only compare logic. Specifically, Qualcomm's method extends a sequence for a small mother code size to generate a sequence for a large mother code size. However, Qualcomm's proposed method suffers from performance degradation, as will be discussed later (see FIG. 7).
  • the present invention proposes a method for extending the mother code based on the bit reliability of the smallest mother code.
  • the present invention is to propose a method for generating a bit reliability order having high performance while reducing the reliability calculation.
  • W- W1
  • W + W2.
  • descendants of W- are denoted W--, W- +, and descendants of W + are denoted W +-, W ++.
  • bit reliability sequence i.e., bit reliability sequence sequence
  • the generated sequence for each length of power of 2 is stored.
  • W is a binary erasure channel with an erasure probability 'p', and since the information can be transmitted without error in the erasure channel by an unerasured amount, the erasure probability is p It is assumed that the capacity of the in binary erasure channel is 1-p. Here, the size of p may be any value and may vary depending on the mother code size. The channel capacity of the erasure channel is well known.
  • the erasure probability corresponding to the bit index i of the m-th step is p i (0 ⁇ i ⁇ 2 m ⁇ 1).
  • p - i and p + i are sorted in ascending order and stored in memory to produce a bit reliability sequence (ie, a bit index sequence).
  • the stored bit index sequence is nested for variable coded block sizes having variable rates and powers of two.
  • a bit index sequence for a larger code block size includes a bit index sequence for a smaller code block size.
  • the bit index sequence for the smaller code rate includes the bit index sequence for the larger code rate.
  • FIG. 9 illustrates a process of generating a bit index sequence according to the present invention.
  • the bit indexes are arranged in the order of the lowest reliability to the highest reliability, but the bit index sequences are generated in the order of the highest reliability to the lowest reliability.
  • bit reliability calculation When generating a bit reliability sequence based on the erasure probability according to the present invention, one logic, i.e., p (1-p) is added to or subtracted from the previous erasure probability in each step, thus simplifying the bit reliability calculation. There is an advantage that it can.
  • n long reliability that is, the bit index sequence
  • Nested structures may require less than 8K bits of storage.
  • CAP means capacity.
  • the mother code size is fixed to 128 in FIG.
  • the sequence according to the invention has better performance than the sequence of Qualcom, in particular the block.
  • the required SNR of the sequence according to the present invention is about 0.5 dB lower than the required SNR of the sequence by Qualcomm. Therefore, according to the present invention, the performance of the transmitter and the receiver in a wireless communication system can be improved.
  • bit index sequences generated according to the present invention are as follows.
  • the bit index sequence is represented by assuming that bit indexes 0 to N-1 are applied to the input bit positions of the polar code and the lowest bit index starts from the row having the smallest row weight.
  • the bit index may be given from 1 to N, and the lowest bit index may be started from the row having the largest row weight.
  • the sorted order of the bit indexes is more important in the bit index sequence than the bit indexes themselves assigned to the bit positions.
  • the bit index sequence obtained by sorting from the index of the high reliability bit (position) to the index of the low reliability bit (position) according to the present invention is as follows. : ⁇ 127, 126, 125, 120, 123, 119, 118, 106, 124, 117, 115, 103, 114, 101, 99, 83, 122, 113, 112, 100, 111, 97, 95, 79, 109, 94, 91, 74, 88, 70, 66, 50, 121, 110, 108, 93, 107, 90, 89, 72, 104, 87, 84, 67, 80, 63, 58, 41, 96, 81, 76, 59, 71, 54, 52, 35, 65, 49, 45, 29, 42, 25, 22, 11, 116, 105, 102, 85, 98, 82, 78, 62, 92, 75, 73,
  • the highest reliability bit position is a bit position whose bit index is 127, which is the first element of the bit index sequence, and the lowest reliable bit position is the last element of the bit index sequence. It can be said that the bit position of the bit index is 0. Since the information bit (s) is preferably assigned to the bit position (s) with the highest confidence, for example, 4-bit information can be assigned to the input bits with bit indices of 127, 126, 125, 120. have.
  • the bit index sequence obtained by sorting from the index of the high reliability bit (position) to the index of the low reliability bit (position) according to the present invention is as follows. : ⁇ 127, 126, 125, 121, 124, 120, 119, 110, 123, 117, 116, 107, 114, 104, 101, 86, 122, 115, 112, 102, 111, 98, 95, 78, 106, 92, 90, 72, 87, 66, 63, 42, 118, 109, 108, 94, 105, 91, 88, 67, 99, 83, 82, 60, 79, 57, 54, 29, 96, 80, 76, 53, 74, 52, 50, 26, 70, 49, 47, 25, 44, 23, 22, 7, 113, 103, 100, 85, 97, 81, 77, 55, 93, 75, 73, 51, 69,
  • the highest reliability bit position is a bit position whose bit index is 127, which is the first element of the bit index sequence, and the lowest reliable bit position is the last element of the bit index sequence. It can be said that the bit position of the bit index is 0. Since the information bit (s) is preferably assigned to the bit position (s) with the highest confidence, for example, 4-bit information can be assigned to the input bits with bit indices of 127, 126, 125, 121. have.
  • the bit index sequence obtained by sorting from the index of the high reliability bit (position) to the index of the low reliability bit (position) according to the present invention is as follows. : (255, 254, 253, 248, 252, 247, 246, 234, 251, 245, 244, 232, 243, 231, 227, 210, 250, 241, 240, 229, 239, 225, 223, 204, 236, 220, 216, 196, 213, 190, 185, 155, 249, 238, 237, 222, 233, 217, 214, 193, 228, 211, 207, 182, 201, 176, 170, 136, 221, 202, 197, 171, 192, 165, 161, 123, 186, 156, 149, 112, 146, 107, 104, 64, 242, 230, 226, 209, 224, 206, 200, 175, 218, 198, 194,
  • the highest reliability bit position is a bit position whose bit index is 255, which is the first element of the bit index sequence, and the highest reliable bit position is the last element of the bit index sequence. It can be said that the bit position of the bit index is 0. Since the information bit (s) is preferably assigned to the bit position (s) with the highest confidence, for example, 4-bit information can be assigned a bit index of 255, 254, 253, 248.
  • bit index sequence that supports a small mother code size may be generated from a large mother code size.
  • a method of generating a bit index that supports a small mother code size based on a large mother code size according to the present invention will be described.
  • a bit index sequence may be generated through the following process.
  • max_N be the maximum length of a sequence to be created.
  • the present invention first generates a sequence for max_N.
  • the sequence for max_N may be generated by the method described above using the erasure probability p, or by using the method of density evolution as in " R1-1700832, " Design of Polar codes for control channel, " Qualcomm, January, 2017. have.
  • the sequence may consist of indices representing an order, and may also consist of values representing an ordered reliability order.
  • the sequence may be a sequence of bit indices in which bit positions are sorted in ascending or descending order of reliability.
  • a new sequence of size N1 may be generated based on the sequence for max_N. For example, a sequence of size N1 may be generated by selecting only elements smaller than N1 (elements from 0 to N1-1) among elements of the sequence for max_N. At this time, the order of the elements forming the sequence of size N1 may be maintained to be the same as the order of the corresponding elements in the sequence for max_N.
  • sequence-1 a sequence generated by maintaining the order of the elements in the sequence for the mother code of size max_N is referred to as sequence-1.
  • the least memory-consuming way to create a bit index sequence is to store the sequence for max_N in memory, and load it from the sequence for max_N whenever necessary, without storing the sequence for N1 when N1 ⁇ max_N. .
  • values corresponding to max_N clocks should be read regardless of the size of N1 every encoding or decoding. Therefore, there is a disadvantage in that the time required for encoding and decoding increases.
  • the method that requires the most memory for the bit index sequence (s) is to store the sequence in memory by mother code size.
  • This method can have the best performance in terms of encoding or decoding delay since storing the sequence in the memory for each mother code size does not require calculation for generating the sequence whenever it is necessary to support a specific mother code size. .
  • the bit index sequence may be stored in a table in memory.
  • the transmitter does not separately transmit information on the sequence used for channel coding, and the receiver may know the sequence based on the mother code size.
  • the receiving end may know the mother code size, for example, from a modulation and coding scheme (MCS) table. For example, if the transmitting end informs the receiving end of the MCS index, the receiving end may know the mother code size corresponding to the MCS index from the MCS table.
  • the transmitter may perform an instruction on the mother code size for generating a sequence to the receiver. For example, when the transmitting end transmits an indicator set to '1' to the receiving end, the receiving end may perform the generation of the necessary mother code size from the sequence for max_N or the sequence that is the basis of sequence generation.
  • the sequence for the required mother code size can be read from the memory.
  • some of several sequences may be selected and used for one mother code size, and the transmitter may decide which of the sequences to use. Can be instructed to the receiving end.
  • the present invention proposes a method of determining an input bit position based on a bit index sequence and a punctured bit.
  • Equation 12 The generator matrix, that is, the transform matrix G of FIG. 11 is represented by Equation 12.
  • transmission bits If the number of bits that can be actually transmitted (hereinafter, referred to as transmission bits) is smaller than the number of output coded bits, puncturing is performed for rate matching. If puncturing is performed, input data may not be transmitted due to puncturing the output coded bits. For example, referring to FIG. 11 (or FIG. 8), if Y1 is punctured, U1 is not included in the coded bits transmitted. If U1 is an information bit, U1 is included only in Y1, so that the information bit should be replaced with a known bit. This is called shortening. In other words, shortening is a rate matching scheme that inserts a known bit into an input bit position coupled to an output bit position.
  • the input position (s) for the input data is preferably determined based on the puncturing bits.
  • the row weight of the transformation matrix G can be expressed in descending order by reflecting the extremization property of the polar code, and when the row weight of the transformation matrix G corresponding to FIG. 7, 6, 5, 3, 4, 2, 1, 0 ⁇ .
  • 0, 1, 2, 3, 4, 5, 6, and 7 are row indices sequentially assigned from the first row to the last row of G.
  • the row weight can be known from the number of nodes U i branches in the encoding module. For example, in FIG.
  • the weight of the last row corresponding to the row index 7 corresponds to 8
  • the row indexes 6, 5, and 3 It can be seen that the rows each have a row weight of 4, the rows corresponding to row indexes 4, 2, and 1 have a row weight of 2 and the row weight of the first row corresponding to row index 0 is 1, respectively.
  • the size 8 order can be configured by selecting them.
  • the number of input bits connected to each punctured bit is always '1'. For example, if the row weight is punctured in descending order, the Y8 corresponding to the row index 7 having the largest row weight is punctured first. Since Y8 is connected only to U8, the number of input bits connected to the punctured bits is one. According to the puncturing pattern based on the row weight, Y7 corresponding to the row index 6 is then punctured, and since U8 is a value not transmitted by the puncturing of Y7, only the input bit connected to Y7 is U7 1.
  • Y6 is punctured after Y8 and Y7, and U8 and U7 are values not transmitted by the puncturing of Y8 and Y7, so that only one input bit connected to Y6 is U6.
  • FIG. 12 illustrates the row weights and corresponding row indices of the transformation matrix G, and a memory address in accordance with the present invention.
  • FIG. 12 (c) illustrates memory addresses in accordance with the present invention.
  • the row indexes are stored in the memory in the order of the row index of the smallest to the row index of the largest of the row weights, and the row indexes of the smallest to the largest indexes.
  • FIG. 12 (c) when the relationship between the 32 row indexes and the corresponding memory addresses is displayed as follows.
  • the weight order for a particular mother code is a nested structure, which can be constructed into entries in a larger mother code size.
  • the row index table for the maximum mother code size may be constructed from or based on US provisional application 62 / 350,167 (see FIG. 12 (a)).
  • the puncturing pattern and the freezing (ie shortening) pattern can be stored in a single memory, and read addresses from the memory can use Pascal's triangle.
  • the number of indices with weight w for mother code size N is as follows.
  • P max is the maximum length of the puncturing pattern stored in the memory.
  • P max may be equal to the maximum mother code size N max .
  • the maximum length P max of the puncturing pattern the starting read address from the stored memory is as follows.
  • the processor may read the bit indices for the puncturing pattern having the size 8 in only eight clocks. For example, referring to FIG. 12 (c), the processor of the present invention provides a puncturing pattern for mother code having size 32 ⁇ 31, 30, 29, 27, 23, 15, 28, 26, 25, 22, 21.
  • Puncturing patterns of size 8 from 19, 14, 13, 11, 7, 24, 20, 18, 17, 12, 10, 9, 6, 5, 3, 16, 8, 4, 2, 1, 0 ⁇ ⁇ 7, 6, 5, 3, 4, 2, 1, 0 ⁇ can be loaded into only eight clocks.
  • the processor retrieves bit indices for mother code of size 16 from memory according to Equation 14, it starts reading from address 26 at weight 16, starts at address 19 at weight 8, and at weight 4 Start reading from address 11, and start reading from address 4 if weight 2 and start reading from address 1 if weight 1. Accordingly, a puncturing pattern ⁇ 15, 14, 13, 11, 7, 12, 10, 9, 6, 5, 3, 8, 4, 2, 1, 0 ⁇ having a size 16 is generated.
  • the present invention stores the row indexes in memory from the row index of the smallest row weight of the transformation matrix G having N max to the index of the largest row weight, and from the row index of the smallest row index to the largest row index if the row weight is the same.
  • N bit indexes smaller than N max are read from the memory to generate a puncturing bit index sequence for the mother code having a size N, that is, a puncturing pattern.
  • Figure 13 illustrates puncturing and information bit allocation in accordance with the present invention.
  • F represents a frozen bit
  • D represents an information bit
  • 0 represents a skipping bit.
  • An information bit may change to a frozen bit according to an index or a position of a punctured bit among coded bits.
  • Input bits that are changed to frozen bits by puncturing the coded bits are called skipping bits or shortening bits, and the corresponding input positions are called skipping positions or shortening positions.
  • the information bit positions may be reallocated in the order of high reliability within the frozen bit set.
  • the skipping position may vary depending on the puncturing pattern or puncturing length, code rate, and the like.
  • the present invention proposes a method of displaying a skipping pattern indicating a skipping position according to each situation.
  • the skipping pattern appears in the same order as the puncturing order. For example, when the output bits are punctured in the order of Y8, Y7, Y6, and Y4, the input bits are skipped in the order of U8, U7, U6, and U4.
  • the puncturing pattern represented by the bit index is ⁇ 7, 6, 5, 3 ⁇
  • the skipping pattern is ⁇ 7, 6, 5, 3 ⁇ . Regardless of the position of the frozen bit, the bit index that should be frozen in the skipping pattern is indicated in the order of the puncturing pattern.
  • the output bits from the encoder are sequentially stored in the circular buffer starting from output bit index zero.
  • the LTE / LTE-A system punctures the bits stored behind the circular buffer.
  • an interleaver may be used in the polar code to maintain the form of puncturing from the bits stored after the circular buffer for the polar code. For example, length-16 puncturing pattern ⁇ 15, 14, 13, 11, 7, 12, 10, 9, 6, 5, 3, 8, 4, 2, 1, 0 ⁇ according to weight is used as the interleaver.
  • the order of the bit indexes stored in the circular buffer is ⁇ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 ⁇ , not ⁇ 0, 1, 2, 4, 8, 3, 5, 6, 9, 10, 12, 7, 11, 13, 14, 15 ⁇ , so that in the circular buffer ⁇ 0, 1, 2, 4, 8, 3, 5 , 6, 9, 10, 12, 7, 11, 13, 14, 15 ⁇ may be transmitted.
  • 15 is a block diagram showing the components of the transmitter 10 and the receiver 20 for carrying out the present invention.
  • the transmitter 10 and the receiver 20 are radio frequency (RF) units 13 and 23 capable of transmitting or receiving radio signals carrying information and / or data, signals, messages, and the like, and in a wireless communication system.
  • the device is operatively connected to components such as the memory 12 and 22, the RF unit 13 and 23, and the memory 12 and 22, which store various types of information related to communication, and controls the components.
  • a processor (11, 21) configured to control the memory (12, 22) and / or the RF unit (13, 23), respectively, to perform at least one of the embodiments of the invention described above.
  • the memories 12 and 22 may store a program for processing and controlling the processors 11 and 21, and may temporarily store input / output information.
  • the memories 12 and 22 may be utilized as buffers.
  • the processors 11 and 21 typically control the overall operation of the various modules in the transmitter or receiver. In particular, the processors 11 and 21 may perform various control functions for carrying out the present invention.
  • the processors 11 and 21 may also be called controllers, microcontrollers, microprocessors, microcomputers, or the like.
  • the processors 11 and 21 may be implemented by hardware or firmware, software, or a combination thereof.
  • application specific integrated circuits ASICs
  • DSPs digital signal processors
  • DSPDs digital signal processing devices
  • PLDs programmable logic devices
  • FPGAs field programmable gate arrays
  • the firmware or software when implementing the present invention using firmware or software, may be configured to include a module, a procedure, or a function for performing the functions or operations of the present invention, and configured to perform the present invention.
  • the firmware or software may be provided in the processors 11 and 21 or stored in the memory 12 and 22 to be driven by the processors 11 and 21.
  • the processor 11 of the transmission apparatus 10 is predetermined from the processor 11 or a scheduler connected to the processor 11 and has a predetermined encoding and modulation on a signal and / or data to be transmitted to the outside. After performing the transmission to the RF unit 13. For example, the processor 11 converts the data sequence to be transmitted into K layers through demultiplexing, channel encoding, scrambling, and modulation.
  • the coded data string is also called a codeword and is equivalent to a transport block, which is a data block provided by the MAC layer.
  • One transport block (TB) is encoded into one codeword, and each codeword is transmitted to a receiving device in the form of one or more layers.
  • the RF unit 13 may include an oscillator for frequency upconversion.
  • the RF unit 13 may include N t transmit antennas, where N t is a positive integer of 1 or more.
  • the signal processing of the receiver 20 is the reverse of the signal processing of the transmitter 10.
  • the RF unit 23 of the receiving device 20 receives a radio signal transmitted by the transmitting device 10.
  • the RF unit 23 may include N r receive antennas, and the RF unit 23 frequency down-converts each of the signals received through the receive antennas to restore the baseband signal. .
  • the RF unit 23 may include an oscillator for frequency downconversion.
  • the processor 21 may decode and demodulate a radio signal received through a reception antenna to restore data originally transmitted by the transmission apparatus 10.
  • the RF units 13, 23 have one or more antennas.
  • the antenna transmits a signal processed by the RF units 13 and 23 to the outside under the control of the processors 11 and 21, or receives a radio signal from the outside to receive the RF unit 13. , 23).
  • Antennas are also called antenna ports.
  • Each antenna may correspond to one physical antenna or may be configured by a combination of more than one physical antenna elements.
  • the signal transmitted from each antenna can no longer be decomposed by the receiver 20.
  • a reference signal (RS) transmitted in correspondence with the corresponding antenna defines the antenna as viewed from the perspective of the receiver 20, and whether the channel is a single radio channel from one physical antenna or includes the antenna.
  • RS reference signal
  • the receiver 20 enables channel estimation for the antenna. That is, the antenna is defined such that a channel carrying a symbol on the antenna can be derived from the channel through which another symbol on the same antenna is delivered.
  • the antenna In the case of an RF unit supporting a multi-input multi-output (MIMO) function for transmitting and receiving data using a plurality of antennas, two or more antennas may be connected.
  • MIMO multi-input multi-output
  • the transmitter 10 may be configured to include a polar encoder according to the present invention
  • the receiver 20 may be configured to include a polar decoder according to the present invention.
  • processor 11 of transmitter 10 may be configured to perform polar encoding according to the present invention
  • processor 21 of receiver 20 is configured to perform polar decoding according to the present invention.
  • the processor 11 of the present invention may generate an input bit index sequence in accordance with the present invention.
  • the memory 12 of the present invention may store an input bit index sequence in accordance with the present invention.
  • the processor 11 may allocate information bits to input bit positions of a polar encoder according to the input bit index sequence, and encode the information bits through the polar encoder.
  • the processor 11 may control the RF unit 13 to transmit the coded bits.
  • the processor 11 of the present invention may generate a puncturing pattern according to the present invention.
  • the memory 12 of the present invention may store puncturing patterns, i.e., row indices, in accordance with the present invention.
  • the processor 11 may generate the puncturing pattern for the small mother code from the puncturing pattern for the large mother code according to the present invention.
  • the processor 11 may generate a puncturing pattern for the small mother code by reading some of the indexes of the puncturing pattern stored for the large mother code from the memory. If the number of bits that can be transmitted, that is, the number of transmitted bits is less than the coded bits, based on the puncturing pattern for the corresponding mother code, ie for the corresponding mother code size, the processor 11 coded Some of the bits may be punctured.
  • the processor 11 may control the RF unit 13 to transmit only unpunctured coded bits.
  • Embodiments of the present invention may be used in a base station or user equipment or other equipment in a wireless communication system.

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Abstract

Des indices de lignes d'une matrice génératrice Gmax de taille Nmax sont stockés dans la mémoire d'un dispositif de transmission dans un système de communication sans fil, par ordre croissant à partir d'un indice de ligne d'une ligne de celle-ci présentant le plus petit poids de ligne et par ordre croissant à partir d'un plus petit indice de ligne lorsque les poids de lignes sont les mêmes. Le dispositif de transmission lit séquentiellement, à partir de la mémoire, N (<Nmax) indices de lignes selon une formule mathématique prédéterminée, et génère une suite d'indices constituée des N indices de lignes. Le dispositif de transmission peut coder des informations d'entrée en utilisant une matrice génératrice GN de taille N et émettre une partie de bits de sortie codés selon la suite d'indices.
PCT/KR2018/001578 2017-02-06 2018-02-06 Procédé de transmission d'informations et dispositif de transmission WO2018143773A1 (fr)

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"Discussion on Polar Codes Design", RL-1700867, 3GPP TSG RAN WG1 NR AD-HOC MEETING, 10 January 2017 (2017-01-10), Spokane, USA, XP051203170 *
ERICSSON: "Consideration of Implementation Aspects of Polar Codes", RL-1611318, 3GPP TSG RAN WG1 MEETING #87, 6 November 2016 (2016-11-06), Reno, USA, XP051190686 *
HUAWEI ET AL.: "Details of the Polar Code Design", RL-1611254, 3GPP TSG RAN WG1 MEETING #87, 3 November 2016 (2016-11-03), Reno, USA, XP051189033 *
SAMSUNG: "Discussion on Polar Code Design", RL-1700978, 3GPP TSG RAN WG1 AD-HOC, 10 January 2017 (2017-01-10), Spokane, Washington, XP051203270 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112087237A (zh) * 2020-09-15 2020-12-15 Oppo广东移动通信有限公司 数据处理方法、芯片及终端
WO2022088876A1 (fr) * 2020-10-26 2022-05-05 中兴通讯股份有限公司 Procédé et appareil de traitement de données de communication, dispositif, et support de stockage
EP4489316A1 (fr) * 2023-07-07 2025-01-08 Nokia Technologies Oy Séquences imbriquées pour les codes polaires
WO2025012757A1 (fr) * 2023-07-07 2025-01-16 Nokia Technologies Oy Séquences imbriquées pour codes polaires

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