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WO2018003113A1 - Dispositif de réception - Google Patents

Dispositif de réception Download PDF

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Publication number
WO2018003113A1
WO2018003113A1 PCT/JP2016/069622 JP2016069622W WO2018003113A1 WO 2018003113 A1 WO2018003113 A1 WO 2018003113A1 JP 2016069622 W JP2016069622 W JP 2016069622W WO 2018003113 A1 WO2018003113 A1 WO 2018003113A1
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WO
WIPO (PCT)
Prior art keywords
signal
output
converter
output signal
signals
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PCT/JP2016/069622
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English (en)
Japanese (ja)
Inventor
裕翔 榊
圭佑 中村
田島　賢一
檜枝　護重
Original Assignee
三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2016/069622 priority Critical patent/WO2018003113A1/fr
Publication of WO2018003113A1 publication Critical patent/WO2018003113A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J1/00—Frequency-division multiplex systems
    • H04J1/02—Details

Definitions

  • the present invention relates to a receiving apparatus that performs signal processing by converting a plurality of received analog signals having different frequencies into digital signals.
  • the direct RF method is different from the well-known techniques of heterodyne method and direct conversion method, and does not frequency-convert the received analog signal, but directly inputs it to the AD converter to convert the analog signal into a digital signal. It is a method.
  • undersampling is a method of operating an AD converter below the Nyquist frequency to sample an analog signal and convert it into a digital signal.
  • Aliasing occurs from the Nyquist theorem, and a digital signal can be obtained by using the aliasing.
  • the direct RF undersampling system is a system combining these two, and the direct RF undersampling receiver indicates a receiver having the above system.
  • analog signals can be converted simultaneously into digital signals with a single AD converter using undersampling.
  • the frequency of the sampling signal is selected so that signals output from the AD converter do not overlap each other.
  • a wide vacant frequency region occurs between the signals output from the AD converter after undersampling. In such a case, the frequency of the sampling signal increases and the power consumption of the AD converter increases.
  • the AD converter can be operated at a frequency lower than that of the method of selecting the frequency of the sampling signal so that the bands of the signals after undersampling do not overlap each other.
  • the power consumption of the AD converter can be reduced.
  • the receiver described in Patent Document 1 has a problem that the signals cannot be separated when three or more analog signals are received.
  • the present invention has been made to solve such a problem, and an object of the present invention is to provide a receiving apparatus capable of separating signals even when three or more analog signals are received.
  • a receiving apparatus includes a first AD converter and a second AD converter that sample three analog signals having different frequencies, and a low-pass filter that passes the output of the first AD converter in a low-pass manner.
  • a high pass filter that passes the output of the first AD converter in a high pass
  • a first decimation processor that makes the output signal of the low pass filter and the high pass filter a half frequency
  • a second Three analog signals having different frequencies by performing an operation using the output signal of the first thinning processor, the output signal of the second thinning processor, and the output signal of the second AD converter.
  • the sampling frequency of the second AD converter is 1 ⁇ 2 of the sampling frequency of the first AD converter, and the first AD Supply to the converter
  • the pulling signal and the sampling signal of the second AD converter have a phase difference of 90 °, and the sampling frequencies of the first AD converter and the second AD converter are overlapped with the frequency bands of the three analog signals.
  • the frequency is set so that it does not become.
  • the sampling frequency of the second AD converter is set to 1 ⁇ 2 of the sampling frequency of the first AD converter, and the sampling signal supplied to the first AD converter and the second AD converter A signal obtained by processing the output of the first AD converter with the low-pass filter and the first decimation processor and the output of the first AD converter with a 90 ° phase difference from the sampling signal of the AD converter.
  • the three signals are separated and output using the signal processed by the high-pass filter and the second thinning processor and the signal output from the second AD converter. Thereby, even when three analog signals are received, the signals can be separated.
  • FIG. FIG. 1 is a configuration diagram of a receiver to which a receiving apparatus according to this embodiment is applied.
  • the receiver shown in FIG. 1 includes an antenna 1, an analog circuit unit 2, and a signal processing unit 3.
  • the analog circuit unit 2 includes an amplifier 21, a filter 22, and a sampling circuit 23.
  • the antenna 1 is an antenna that receives a plurality of analog signals having different frequencies.
  • the analog circuit unit 2 is a circuit that processes an analog signal received by the antenna 1.
  • the signal processing unit 3 is a processing unit that performs signal processing using the output signal of the analog circuit unit 2.
  • the amplifier 21 in the analog circuit unit 2 is an amplifier that amplifies an analog signal received by the antenna 1 with a predetermined amplification factor.
  • the filter 22 is a filter that suppresses unnecessary analog signals.
  • the sampling circuit 23 is a circuit that performs processing for converting an analog signal into a digital signal, and corresponds to the receiving apparatus of the present embodiment.
  • FIG. 2 is a configuration diagram showing details of the sampling circuit 23.
  • the sampling circuit 23 includes an oscillator 101, a first power divider 102, a two-frequency divider 103, a phase shifter 104, a second power divider 105, a first AD converter 106, a low frequency band, Pass filter (hereinafter referred to as LPF) 107, first decimation processor 108, first delay unit 109, high-pass filter (hereinafter referred to as HPF) 110, second decimation processor 111, second delay unit 112, a second AD converter 113, a third delay unit 114, and a signal separation unit 115.
  • LPF Pass filter
  • HPF high-pass filter
  • the oscillator 101 is an oscillator that excites a reference signal of a sampling signal input to the first AD converter 106 and the second AD converter 113.
  • a crystal oscillator is used.
  • Oscillator 101 is connected to a first power splitter 102, it oscillates at a frequency 2f 0, and outputs an oscillation signal to the power divider 102.
  • the first power distributor 102 is a circuit that receives the signal output from the oscillator 101 and distributes the power of the signal into two. For example, a discrete power distributor is used.
  • the first power divider 102 is connected to the oscillator 101, the two-frequency divider 103, and the phase shifter 104.
  • the first power divider 102 distributes the power of the signal output from the oscillator 101 to two, and the two-frequency divider 103 and the phase shifter 104. To each output.
  • the phase shifter 104 is a circuit that delays the phase of the signal output from the first power distributor 102 by 90 ° and outputs the delayed signal. For example, a discrete phase shifter is used.
  • the phase shifter 104 is connected to the first power divider 102 and the first AD converter 106, delays the phase of the signal output by the first power divider 102 by 90 °, and the first AD converter 106. Output to.
  • the frequency divider 103 is a circuit that halves the frequency of the signal output from the first power distributor 102.
  • the two-frequency divider 103 is connected to the first power divider 102 and the second AD converter 113, halves the frequency of the signal output from the first power divider 102, and the second AD converter 113.
  • the second power distributor 105 is a circuit that distributes the power of the signal output from the filter 22 into two.
  • a discrete power distributor is used.
  • the second power distributor 105 is connected to the filter 22, the first AD converter 106, and the second AD converter 113, and distributes the power of the signal output from the filter 22 into two, and the first AD converter 106 and the second AD converter 113, respectively.
  • the first AD converter 106 is a circuit that uses the signal output from the phase shifter 104 as a sampling signal, converts the signal output from the second power distributor 105 into a digital signal using the sampling signal, and outputs the digital signal. is there.
  • an IC AD converter is used.
  • the first AD converter 106 is connected to the phase shifter 104, the second power distributor 105, the LPF 107, and the HPF 110, converts the signal output from the second power distributor 105 into a digital signal, and the LPF 107 and the HPF 110. To each output.
  • the LPF 107 is a circuit that passes a frequency band below a specific frequency in the digital signal output from the first AD converter 106 and attenuates the frequency band above the specific frequency. For example, it is configured with an FPGA logic circuit.
  • the LPF 107 is connected to the first AD converter 106 and the first decimation processor 108, and passes a signal having a low frequency among the signals output from the first AD converter 106, and the first decimation processor To 108.
  • the first decimation processor 108 is a circuit that decimates the signal output from the LPF 107.
  • the first decimation processor 108 is connected to the LPF 107 and the first delay unit 109, decimates the signal output from the LPF 107, and outputs it to the first delay unit 109.
  • the first delay unit 109 is a circuit that delays the signal output from the first decimation processor 108 and outputs the delayed signal. For example, it is configured with an FPGA logic circuit.
  • the first delay unit 109 is connected to the first decimation processor 108 and the signal separation unit 115, delays the signal output from the first decimation processor 108 in time, and outputs the delayed signal to the signal separation unit 115. .
  • the HPF 110 is a circuit that passes a frequency band of a specific frequency or higher and attenuates a frequency band of a specific frequency or lower in the digital signal output from the first AD converter 106. For example, it is configured with an FPGA logic circuit.
  • the HPF 110 is connected to the first AD converter 106 and the second decimation processor 111, and passes a signal having a high frequency among the signals output from the first AD converter 106, and the second decimation processor To 111.
  • the second decimation processor 111 is a circuit that decimates the signal output from the HPF 110. For example, it is configured with an FPGA logic circuit.
  • the second decimation processor 111 is connected to the HPF 110 and the second delay unit 112, decimates the signal output from the HPF 110, and outputs the signal to the second delay unit 112.
  • the second delay unit 112 is a circuit that delays the signal output from the second decimation processor 111 and outputs the delayed signal. For example, it is configured with an FPGA logic circuit.
  • the second delay unit 112 is connected to the second decimation processor 111 and the signal separation unit 115, delays the signal output from the second decimation processor 111 in time, and outputs the delayed signal to the signal separation unit 115.
  • the second AD converter 113 uses the signal output from the frequency divider 103 as a sampling signal, converts the signal output from the second power distributor 105 into a digital signal using the sampling signal, and outputs the digital signal It is. For example, an IC AD converter is used.
  • the second AD converter 113 is connected to the frequency divider 103, the second power distributor 105, and the third delay device 114, and the signal output from the frequency divider 103 is used as a sampling signal. Is used to convert the signal output from the second power distributor 105 into a digital signal and output it to the third delay unit 114.
  • the third delay unit 114 is a circuit that delays the signal output from the second AD converter 113 and outputs the delayed signal. For example, it is configured with an FPGA logic circuit.
  • the third delay unit 114 is connected to the second AD converter 113 and the signal separation unit 115, delays the signal output from the second AD converter 113 in time, and outputs the delayed signal to the signal separation unit 115.
  • FIG. 3 is a configuration diagram of the signal separation unit 115.
  • the signal separation unit 115 includes a phase shifter 201, an adder 202, and a separator 203.
  • the phase shifter 201 is a circuit that delays the phase of the signal output from the first delay unit 109 by 90 ° and outputs the delayed signal. For example, it is configured with an FPGA logic circuit.
  • the phase shifter 201 is connected to the first delay unit 109, the adder 202, and the signal processing unit 3, delays the phase of the signal output from the first delay unit 109 by 90 °, and adds the adder 202 and the signal processing unit 3. Output to.
  • the adder 202 is a circuit that adds the signals output from the third delay device 114 and the phase shifter 201.
  • the adder 202 adds the signals output from the third delay unit 114 and the phase shifter 201 and outputs the result to the separator 203.
  • the separator 203 is a circuit that separates the signals output from the second delay unit 112 and the adder 202.
  • it is configured with an FPGA logic circuit.
  • the separator 203 separates the signal using the signals output from the second delay unit 112 and the adder 202 and outputs the separated signal to the signal processing unit 3.
  • FIG. 4 is a configuration diagram illustrating an example of the separator 203.
  • the separator 203 includes a phase shifter 301, a subtracter 302, and an adder 303.
  • the phase shifter 301 is a circuit that delays the phase of the signal output from the second delay unit 112 by 90 ° and outputs the delayed signal.
  • the subtractor 302 is a circuit that subtracts the output signal of the phase shifter 301 and the signal output from the adder 202 to obtain the output 1 of the separator 203.
  • the adder 303 is a circuit that adds the output signal of the phase shifter 301 and the signal output from the adder 202 to output 2 of the separator 203.
  • FIG. 5 shows the phase of the signal.
  • 5B shows a signal delayed by 90 ° with respect to the phase of the signal shown in FIG. 5A
  • FIG. 5C shows a signal delayed by 180 °
  • FIG. 5D shows a signal delayed by 270 °.
  • the second power distributor 105 distributes the power of the signal output from the filter 22 into two, and outputs the signal to the first AD converter 106 and the second AD converter 113.
  • An example of a signal input to the second power distributor 105 is shown in FIG.
  • the signals input to the second power distributor 105 are three signals having different frequencies from those of the signal 1, the signal 2, and the signal 3. Further, the signal 1, the signal 2, and the signal 3 exist between 0 to 1 / 2f 0 , 1 / 2f 0 to f 0 , and f 0 to 3 / 2f 0 , respectively. That is, the sampling frequency of the first AD converter 106 and the second AD converter 113 is set to a frequency that does not overlap with the bands of the signal 1, the signal 2, and the signal 3.
  • the Oscillator 101 outputs a signal of the frequency 2f 0.
  • the first power distributor 102 divides the power of the signal output from the oscillator 101 into two, and outputs the signal to the two-frequency divider 103 and the phase shifter 104.
  • the phase shifter 104 delays the phase of the signal output from the oscillator 101 by 90 °, and outputs the signal to the first AD converter 106.
  • the first AD converter 106 operates with the signal having the frequency 2f 0 output from the phase shifter 104, samples the signal 1 and the signal 2 among the output signals of the second power distributor 105, and outputs the signal 3. Undersampling is performed, and signals are output to the LPF 107 and the HPF 110.
  • An output signal of the first AD converter 106 is shown in FIG. Among the output signals of the first AD converter 106, the phases of the signals 1 and 2 are delayed by 90 ° compared to FIG. 6, and the phase of the signal 3 is delayed by 270 °.
  • the LPF 107 passes a signal in the range of 0 to 1 / 2f 0 among the signals output from the first AD converter 106 and outputs the signal to the first decimation processor 108.
  • the output signal of the LPF 107 is shown in FIG.
  • the first decimation processor 108 decimates the output signal of the LPF 107 with a decimation factor of 2, and outputs a signal to the first delay unit 109.
  • the output signal of the LPF 107 is a digital signal having a time period of 1 / (2f 0 ).
  • the first decimation processor 108 operating with the decimation factor 2 extracts and outputs one of the two digital signals from the digital signal output from the LPF 107.
  • the output signal of the first decimation processor 108 is a digital signal with a time period of 1 / f 0 .
  • the HPF 110 passes the signal in the range of 1 / 2f 0 to f 0 among the signals output from the first AD converter 106 and outputs the signal to the first thinning processor 108.
  • the output signal of the HPF 110 is shown in FIG.
  • the second decimation processor 111 decimates the output signal of the HPF 110 with a decimation factor of 2, and outputs a signal to the second delay unit 112.
  • the output signal of the HPF 110 is a digital signal having a time period of 1 / (2f 0 ).
  • the second decimation processor 111 operating with the decimation factor 2 extracts and outputs one of the two digital signals from the digital signal output from the HPF 110.
  • the output signal of the second decimation processor 111 is a digital signal with a time period of 1 / f 0 .
  • a signal existing between 1 / 2f 0 and f 0 is frequency-converted by the second decimation processor 111 from 0 to 1 / 2f 0 .
  • the output signal of the second thinning processor 111 is shown in FIG.
  • the frequency divider 103 divides the frequency 2f 0 signal output from the first power divider 102 by 2 and outputs the signal to the second AD converter 113.
  • the second AD converter 113 operates with the signal of the frequency f 0 output from the frequency divider 103, samples the signal 1 out of the output signal of the second power divider 105, and outputs the signal 2 and the signal 3. Is undersampled and a signal is output to the third delay unit 114.
  • An output signal of the second AD converter 113 is shown in FIG.
  • the phase of the output signal of the second AD converter 113 is the same for all signals compared to FIG.
  • the signals input from the first delay unit 109, the second delay unit 112, and the third delay unit 114 to the signal separation unit 115 do not coincide with each other in time. Don't be. Therefore, the delay amounts of the first delay unit 109, the second delay unit 112, and the third delay unit 114 are determined so that the signals input to the signal separation unit 115 coincide with each other in time. Therefore, the delay amounts of the first delay device 109, the second delay device 112, and the third delay device 114 are not the same.
  • the signals output from the first delay unit 109, the second delay unit 112, and the third delay unit 114 to the signal separation unit 115 are the same as those in FIGS. 8, 10, and 11, respectively.
  • the phase shifter 201 delays the phase of the output signal of the first delay unit 109 by 90 °, and outputs a signal to the adder 202 and the signal processing unit 3.
  • the output signal of the phase shifter 201 is shown in FIG.
  • the phase of the signal 1 is delayed by 180 ° compared to FIG.
  • the adder 202 adds the output signals of the third delay unit 114 and the phase shifter 201 and outputs a signal to the separator 203.
  • the signal 1 that is the output signal of the phase shifter 201 is 180 degrees out of phase with the signal 1 that is the output signal of the third delay device 114.
  • the separator 203 separates signals using the output signals of the second delay unit 112 and the adder 202 shown in FIGS. 10 and 13, respectively, and outputs a signal to the signal processing unit 3. Signal separation is performed using other well known techniques including Weber architecture or Hartley architecture.
  • a signal 2 is output from the output 1 of the separator 203 shown in FIG. 4 and a signal 3 is output from the output 2.
  • the output 1 and output 2 signals of the separator 203 are shown in FIGS. 14 and 15, respectively.
  • three signals having different frequencies can be separated and output to the signal processing unit 3.
  • the signal 2 and the signal 3 are 180 degrees out of phase with respect to the signal 1, but this is because the signal processing unit 3 rotates the phase of the signal 1 by 180 degrees. It can be demodulated. Further, the direction of the signal 2 in FIG. 14 is left and right inverted as compared with FIG. 6, but this can also be restored by the signal processing unit 3 and demodulated.
  • phase shifter 201 may be a 270 ° phase shifter. In that case, the same effect can be obtained by changing the adder 202 to a subtracter.
  • the signal 2 is output from the output 1 of the separator 203 and the signal 3 is output from the output 2, but the output 1 is separated so that the signal 3 is output and the signal 2 is output from the output 2.
  • the vessel 203 may be configured. That is, the signal output by replacing the subtracter 302 and the adder 303 shown in FIG. 4 is reversed.
  • the first AD converter and the second AD converter that sample three analog signals having different frequencies, and the output of the first AD converter.
  • the low-pass filter that passes the low-pass signal, the high-pass filter that passes the output of the first AD converter high-pass, and the output signals of the low-pass filter and the high-pass filter are 1 ⁇ 2 the frequency. Calculation is performed using the first thinning processor and the second thinning processor, the output signal of the first thinning processor, the output signal of the second thinning processor, and the output signal of the second AD converter.
  • a signal separation unit that separates and outputs three signals corresponding to three analog signals having different frequencies
  • the sampling frequency of the second AD converter is set to 1 / of the sampling frequency of the first AD converter. 2 and the second
  • the sampling signal supplied to the AD converter and the sampling signal of the second AD converter have a phase difference of 90 °, and the sampling frequencies of the first AD converter and the second AD converter are set to three Since the frequency is set so as not to overlap with the frequency band of the analog signal, the signal can be separated even when three analog signals are received.
  • the signal separation unit includes a phase shifter that shifts the output of the first decimation processor by 90 °, an output signal of the phase shifter, and the second AD converter. And an adder that adds the output signals of the second decimation processor and an output signal of the adder, and outputs two separated signals, the output of the phase shifter Since the signal and the two separated signals of the separator are output as three signals, the signals can be separated even when three analog signals are received.
  • the signal separation unit includes a phase shifter that shifts the output of the first decimation processor by 270 °, the output signal of the phase shifter, and the second AD conversion.
  • a subtractor for subtracting the output signal of the counter, and a separator for inputting the output signal of the second decimation processor and the output signal of the subtractor and outputting two separated signals Since the output signal and the two separated signals of the separator are output as three signals, the signals can be separated even when three analog signals are received.
  • the first delay device that delays the output of the first decimation processor, the second delay device that delays the output of the second decimation processor, A third delay unit that delays the output of the second AD converter, and outputs the delay amounts of the first delay unit, the second delay unit, and the third delay unit from the first decimation processor The signal output from the second delay unit and the signal output from the second AD converter are input to the signal separation unit at the same timing.
  • the signals to be processed are the same in time, and there is no need to match the timing in the signal separation unit.
  • Embodiment 2 FIG. In the first embodiment, the configuration in which three analog signals having different frequencies input to the second power distributor 105 are separated has been described. In the second embodiment, a configuration in which four analog signals having different frequencies input to the second power distributor 105 are separated will be described.
  • FIG. 16 is a configuration diagram of the sampling circuit 23a of the second embodiment.
  • FIG. 17 is a configuration diagram of the signal separation unit 115a shown in FIG.
  • the configuration of the receiver to which the receiving apparatus of the second embodiment is applied is the same as that of the first embodiment shown in FIG.
  • the first LPF 116 is provided between the second power distributor 105 and the second AD converter 113.
  • the first LPF 116 is a circuit that passes a frequency band equal to or lower than a specific frequency and reflects a frequency band equal to or higher than a specific frequency among signals output from the second power distributor 105.
  • it is mounted using a chip inductor, a chip capacitor, or the like.
  • the first LPF 116 is connected to the second power divider 105 and the second AD converter 113, and passes a frequency band equal to or lower than a specific frequency among the signals output from the second power divider 105, Output to the second AD converter 113. Since the configuration other than the signal separation unit 115a in the sampling circuit 23a is the same as that of the first embodiment shown in FIG. 2, the same reference numerals are given to the corresponding portions, and the description thereof is omitted. In the second embodiment, the LPF 107 is described as the second LPF 107 in order to distinguish it from the first LPF 116.
  • the adder 202 of the first embodiment is deleted, and a second adder 401, a first subtracter 402, a second subtractor 403, a first An adder 404 and a third subtracter 405 are provided.
  • the second adder 401 is a circuit that adds the signal output from the phase shifter 201 and the signal output from the third subtractor 405. For example, it is configured with an FPGA logic circuit.
  • the second adder 401 is connected to the phase shifter 201, the third subtracter 405, and the signal processing unit 3, and adds the signal output from the phase shifter 201 and the signal output from the third subtractor 405. Output to the signal processing unit 3.
  • the first subtractor 402 is a circuit that subtracts the signal output from the third delay unit 114 and the signal output from the separator 203.
  • the first subtractor 402 is connected to the third delay unit 114, the separator 203, the first adder 404 and the signal processing unit 3, and the signal output from the third delay unit 114 and the separator 203 output The obtained signals are subtracted and output to the first adder 404 and the signal processing unit 3.
  • the second subtractor 403 is a circuit that subtracts the signal output from the third delay unit 114 and the signal output from the separator 203.
  • the second subtractor 403 is connected to the third delay unit 114, the separator 203, the first adder 404, and the signal processing unit 3, and the signal output from the third delay unit 114 and the separator 203 output The obtained signals are subtracted and output to the first adder 404 and the signal processing unit 3.
  • the first adder 404 is a circuit that adds the signal output from the first subtractor 402 and the signal output from the second subtractor 403. For example, it is configured with an FPGA logic circuit.
  • the first adder 404 is connected to the first subtractor 402, the second subtractor 403, and the third subtracter 405, and the signal output from the first subtractor 402 and the second subtractor 403 are connected to each other.
  • the output signals are added and output to the third subtractor 405.
  • the third subtracter 405 is a circuit that subtracts the signal output from the third delay unit 114 and the signal output from the first adder 404.
  • the third subtractor 405 is connected to the third delay unit 114, the first adder 404, the second adder 401, and the signal processing unit 3, and the third delay unit 114 and the first adder 404 are connected. Is subtracted and output to the second adder 401 and the signal processing unit 3.
  • the second power distributor 105 distributes the power of the signal output from the filter 22 into two, and outputs the signal to the first AD converter 106 and the first LPF 116.
  • An example of a signal input to the second power distributor 105 is shown in FIG.
  • Signals input to the second power distributor 105 are four signals having frequencies different from those of the signal 1, the signal 2, the signal 3, and the signal 4.
  • signal 1, signal 2, signal 3, and signal 4 exist between 0 to 1 / 2f 0 , 1 / 2f 0 to f 0 , f 0 to 3 / 2f 0 , and 3 / 2f 0 to 2f 0 , respectively. To do.
  • the first AD converter 106 operates on the signal of the frequency 2f 0 output from the phase shifter 104, samples the signal 1 and the signal 2 among the output signals of the second power divider 105, The signal 4 is undersampled, and a signal is output to the second LPF 107 and the HPF 110.
  • An output signal of the first AD converter 106 is shown in FIG. Among the output signals of the first AD converter 106, the phases of the signals 1 and 2 are delayed by 90 ° compared to FIG. 18, and the phases of the signals 3 and 4 are delayed by 270 °.
  • the second LPF 107 passes a signal in the range of 0 to 1 / 2f 0 among the signals output from the first AD converter 106 and outputs the signal to the first decimation processor 108.
  • the output signal of the second LPF 107 is shown in FIG.
  • the first thinning processor 108 performs the same operation as in the first embodiment.
  • the HPF 110 performs the same operation as in the first embodiment.
  • the output signal of the HPF 110 is shown in FIG.
  • the second thinning processor 111 performs the same operation as in the first embodiment.
  • the output signal of the second thinning processor 111 is shown in FIG.
  • the first LPF 116 passes a signal in the range of 0 to 3 / 2f 0 among the signals output from the second power distributor 105 and outputs the signal to the second AD converter 113.
  • the output signal of the first LPF 116 is shown in FIG.
  • the second AD converter 113 operates with the signal of the frequency f 0 output from the frequency divider 103, samples signal 1 out of the output signal of the second power divider 105, and outputs signal 2 and signal 3. Is undersampled and a signal is output to the third delay unit 114.
  • the output signal of the second AD converter 113 is shown in FIG.
  • the phase of the output signal of the second AD converter 113 is the same for all signals compared to FIG.
  • the first delay device 109, the second delay device 112, and the third delay device 114 operate in the same manner as in the first embodiment.
  • the phase shifter 201 delays the phase of the output signal of the first delay unit 109 by 90 ° and outputs a signal to the second adder 401.
  • the output signal of the phase shifter 201 is shown in FIG.
  • the phase of signal 1 is 180 ° behind that of FIG. 18, and signal 4 is in phase.
  • the separator 203 performs signal separation using the output signals of the second delay unit 112 and the third delay unit 114 shown in FIGS. 22 and 24, respectively, and performs the first subtractor 402 and the second subtractor 402.
  • a signal is output to the subtracter 403.
  • Signal separation is performed using other well-known techniques, including Weber architecture or Hartley architecture.
  • the signal 1 and the signal 2 are output from the output 1 of the separator 203 shown in FIG. 17, and the signal 1 and the signal 3 are output from the output 2.
  • the output 1 and output 2 signals of the separator 203 are shown in FIGS. 26 and 27, respectively.
  • the first subtractor 402 subtracts the output signal of the third delay unit 114 shown in FIGS. 24 and 26 and the separated signal of the output 1 in the separator 203, and uses the output signal as a signal processing unit. 3 and the first adder 404.
  • the output signal of the first subtractor 402 is shown in FIG.
  • the second subtracter 403 performs subtraction between the output signal of the third delay unit 114 shown in FIGS. 24 and 27 and the output 2 separation signal in the separator 203, and outputs the output to the signal processing unit 3. And a signal is output to the first adder 404.
  • the output signal of the second subtractor 403 is shown in FIG.
  • the first adder 404 adds the output signal of the first subtractor 402 and the output signal of the second subtractor 403 shown in FIGS. 28 and 29, respectively, and sends the signal to the third subtracter 405. Output.
  • the output signal of the first adder 404 is shown in FIG.
  • the third subtracter 405 subtracts the output signal of the third delay unit 114 and the output signal of the first adder 404 shown in FIGS. 24 and 30, respectively, and outputs the output signal to the signal processing unit 3. Output to.
  • the output signal of the third subtractor 405 is shown in FIG.
  • the second adder 401 adds the output signal of the phase shifter 201 and the output signal of the third subtractor 405 shown in FIGS. 25 and 31 respectively, and outputs the output signal to the signal processing unit 3. .
  • the output signal of the second adder 401 is shown in FIG.
  • phase shifter 201 may be a 270 ° phase shifter. In that case, the same effect can be obtained by changing the second adder 401 to a subtracter.
  • the first LPF 116 may be changed to a notch filter for removing one specific signal.
  • the notch filter when used, the band of the signal 4 is blocked.
  • the first AD converter that samples four analog signals having different frequencies and the first low-pass signal that allows the four analog signals to pass through the low-frequency signal.
  • the sampling frequency of the second AD converter is set to 1 ⁇ 2 of the sampling frequency of the first AD converter.
  • the sampling signal of the converter is set to a phase difference of 90 °, and the sampling frequencies of the first AD converter and the second AD converter are set to frequencies that do not overlap with the frequency bands of the four analog signals. Therefore, even when four analog signals are received, the signals can be separated.
  • the signal separation unit includes a phase shifter that shifts the output of the first decimation processor by 90 °, the output signal of the second decimation processor, and the second signal.
  • a separator that inputs the output signal of the AD converter 113 and outputs the first and second separated signals, and a first that subtracts the first separated signal and the output signal of the second AD converter.
  • a subtracter, a second subtractor for subtracting the second separated signal and the output signal of the second AD converter, and the output signal of the first subtracter and the output signal of the second subtractor are added.
  • the first adder, the third subtracter for subtracting the output signal of the first adder and the output signal of the second AD converter, the output signal of the phase shifter and the third subtractor A second adder for adding the output signal, an output signal of the second adder, an output signal of the first subtractor, an output signal of the second subtractor, 3 of the output signal of the subtractor, since the output as four signal, it is possible to separate the signals even in the case of receiving the four analog signals.
  • Embodiment 3 FIG. In the third embodiment, a configuration in which an analog signal received by the antenna 1 is frequency-converted and then output to the sampling circuit 23 will be described.
  • FIG. 33 is a configuration diagram of a receiver to which the receiving apparatus of the third embodiment is applied.
  • the receiver includes an antenna 1, an analog circuit unit 2, and a signal processing unit 3, and the analog circuit unit 2 includes an amplifier 21, a filter 22, a sampling circuit 23, and a frequency converter 24.
  • the third embodiment is different from the first embodiment in that a frequency converter 24 is provided between the filter 22 and the sampling circuit 23.
  • the frequency converter 24 is a circuit that converts the frequency of the analog signal output from the filter 22 to a low frequency.
  • it is composed of a mixer, a filter, and an IC PLL.
  • the frequency converter 24 converts the analog signal output from the filter 22 into a low frequency and outputs the signal to the sampling circuit 23.
  • the configuration of the sampling circuit 23 is the same as that of the first embodiment shown in FIG. 2 except that the signal input to the second power distributor 105 is the output signal of the frequency converter 24. This is different from the first form.
  • the receiving frequency is generally 1 GHz to 2 GHz.
  • the frequency converter 24 lowers it in advance from several MHz to several tens of MHz, and then the signal is input to the sampling circuit 23. As a result, the cost of the AD converter can be reduced.
  • the frequency converter 24 is provided for the configuration of the first embodiment, but may be applied to the configuration of the second embodiment.
  • the three analog signals having different frequencies are used as input signals, and the frequency converter is provided that converts the frequency of the input signal to a low frequency to be an output signal, Since the first AD converter and the second AD converter sample the output signal of the frequency converter, the frequency of the target signal can be lowered, so that the cost of the receiving apparatus can be reduced. Can be achieved.
  • the receiving apparatus relates to a configuration for performing signal processing by converting a plurality of analog signals having different frequencies into digital signals, and is suitable for use in a multi-channel receiver.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

Dans la présente invention, la phase d'un signal d'échantillonnage d'un premier convertisseur analogique-numérique (106) est décalée de 90°. Un second convertisseur analogique-numérique (113) fonctionne à la moitié de la fréquence d'échantillonnage. La sortie du premier second convertisseur analogique-numérique (106) traverse un filtre passe-bas (107) et un premier processeur d'amincissement (108) et traverse un filtre passe-haut (110) et un second processeur d'amincissement (111) et est entrée dans une unité de séparation de signaux (115). La sortie du second convertisseur analogique-numérique (113) est entrée dans l'unité de séparation de signaux (115). Sur la base de ces signaux entrés, l'unité de séparation de signaux (115) sépare et délivre des signaux correspondant à trois signaux analogiques ayant des fréquences différentes.
PCT/JP2016/069622 2016-07-01 2016-07-01 Dispositif de réception WO2018003113A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002354056A (ja) * 2001-05-25 2002-12-06 Toyota Central Res & Dev Lab Inc 受信装置
JP2004096177A (ja) * 2002-08-29 2004-03-25 Mitsubishi Heavy Ind Ltd 復調器，並びにこれを用いた受信機，車載器，及び路側装置
JP2011526132A (ja) * 2008-06-27 2011-09-29 エントロピック・コミュニケーションズ・インコーポレイテッド 直接直交サンプリング装置および方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002354056A (ja) * 2001-05-25 2002-12-06 Toyota Central Res & Dev Lab Inc 受信装置
JP2004096177A (ja) * 2002-08-29 2004-03-25 Mitsubishi Heavy Ind Ltd 復調器，並びにこれを用いた受信機，車載器，及び路側装置
JP2011526132A (ja) * 2008-06-27 2011-09-29 エントロピック・コミュニケーションズ・インコーポレイテッド 直接直交サンプリング装置および方法

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