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WO2018068847A1 - Convertisseur numérique-temps hautement linéaire destiné à une boucle à verrouillage de phase entièrement numérique à faible bruit - Google Patents

Convertisseur numérique-temps hautement linéaire destiné à une boucle à verrouillage de phase entièrement numérique à faible bruit Download PDF

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Publication number
WO2018068847A1
WO2018068847A1 PCT/EP2016/074481 EP2016074481W WO2018068847A1 WO 2018068847 A1 WO2018068847 A1 WO 2018068847A1 EP 2016074481 W EP2016074481 W EP 2016074481W WO 2018068847 A1 WO2018068847 A1 WO 2018068847A1
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WIPO (PCT)
Prior art keywords
capacitor
array
capacitors
phase
voltage
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Ceased
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PCT/EP2016/074481
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English (en)
Inventor
Pasquale Lamanna
Danilo CARDISCIANI
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to CN201680090024.8A priority Critical patent/CN109863697B/zh
Priority to PCT/EP2016/074481 priority patent/WO2018068847A1/fr
Publication of WO2018068847A1 publication Critical patent/WO2018068847A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/80—Simultaneous conversion using weighted impedances
    • H03M1/802—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices
    • H03M1/804—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices with charge redistribution
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H03K2005/00071—Variable delay controlled by a digital setting by adding capacitance as a load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/82—Digital/analogue converters with intermediate conversion to time interval
    • H03M1/822—Digital/analogue converters with intermediate conversion to time interval using pulse width modulation

Definitions

  • the invention relates to the field of a digital phase locked loop, and more particularly to a linear digital-to-time converter intended for a low noise all-digital phase locked loop.
  • DTCs digital-to-time converters
  • ADPLL fractional-N all digital phase locked loops
  • BPD binary phase detector
  • the linearity specification in terms of integral-non-linearity (INL) is rather hard to meet in an ADPLL for radio applications because the output spur level of the ADPLL depends on the INL.
  • the noise specification is very tight as the DTC noise is added to the reference noise and contributes to the output phase noise of the ADPLL.
  • a DTC also commonly referred as a delay line, is an electronic circuit that receives at its input a clock signal and a digital control word and generates at its output a delayed copy of its input clock signal.
  • the basic element of a DTC is a variable delay element. If a delay tuning is linear, a high-linearity DTC can be realized and only two points are sufficient for calibration.
  • Most existing DTCs as found in "A 2.9-to-4.0 GHz fractional-N digital PLL with bang-bang phase detector and 560 fsrms integrated jitter at 4.5 mW power", IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2745-2758 (December 2011), by D. Tasca, M. Zanuso, G. Marzin, S. Levantino, C. Samori and A. L. Lacaita, are implemented using a coarse/fine architecture. Although that simplifies the construction, the coarse/fine architectures are inherently prone to linearity issues and a non-monotonic behavior, particularly at the transition between the fine and coarse control, and complex calibrations are often required to align the fine and coarse components.
  • delay lines as found for example in "A wideband 3.6 GHz digital ⁇ fractional-N PLL with phase interpolation divider and digital spur cancellation", IEEE J. Solid-State Circuits, vol. 46, no. 3, pp. 627- 638 (March 2011), by M. Zanuso, S. Levantino, C. Samori and A. L. Lacaita, are implemented using delay stages comprising digital inverters, wherein the desired delay is selected by a multiplexer at the output.
  • the standard issues met with those delay lines are the bad matching between the inverters, the high current consumption and the added noise.
  • the varia ble delay can be generated by: - switched capacitors, as depicted in Fig. 1 and found in "A 5.3GHz digital-to-time-converter-based fractional-N a ll-digital PLL", IEEE International Solid-State Circuits Conference (ISSCC), pp.54-56, 20-24 February 2011, by N. Pavlovic and J. Bergervoet;
  • a Capacitor Array Digital to Analog Converter having 2 m -l capacitors for an input code with a resolution of m bits, is connected in parallel with a capacitor CI (Fig. 5a) or in parallel with a capacitor C2 (Fig. 5b).
  • the voltage value is not linear versus the digital input code in none of those two configurations.
  • the switch Tl is turned off and the CI and Cx capacitors are connected to a capacitor C2, which has a zero initial charge, by means of a switch T2.
  • Vc(x) VDD * (4)
  • a sharing phase the switch Tl is turned off and the capacitor CI is connected to the C2 and Cx capacitors, which have a zero initial charge, by mea ns of a switch T2.
  • Vc x VDD * (5)
  • n 2 m -l equal capacitors.
  • x capacitors with a total value of X*C L SB are connected, while the remaining n-x capacitors with a total value of (n-x)*C L s B are always left unconnected to the other ca pacitors (CI, C2) by remaining connected to a floating node.
  • the invention relates to an apparatus for generating an analog output voltage from a digital input signal x.
  • the apparatus comprises a first capacitor connected to a first node; a second capacitor (C2) connected to a second node (N2); a nd a capacitor array of n elementary capacitors from a capacitor array digital-to-analog converter.
  • the n elementary capacitors can be connected in parallel to the first capacitor (CI) and the second capacitor (C2).
  • a charging phase a first array of x elementary capacitors of the capacitor array are connected in parallel to the first capacitor (CI) and a second array of n-x elementary capacitors of the capacitor array are connected in parallel to the second capacitor (C2), wherein x is the digital input signal.
  • a charge sharing phase the n elementary capacitors of the capacitor array are connected in parallel to the first capacitor (CI) and the second capacitor (C2).
  • the first array of x elementary capacitors is connected to a first terminal and the second array of n-x capacitors is connected to a second terminal.
  • the apparatus further comprises a plurality of switching elements adapted to operate according to a switching sequence, wherein the switching sequence comprises:
  • the apparatus can generate an analog output voltage that varies linearly according to a digital input code x corresponding to an x-bit digital input.
  • the first array of x capacitors connected in parallel with the first capacitor is charged to a first reference voltage level during the second phase, and the second array of n-x capacitors connected in parallel with the second capacitor is charged to a second reference voltage level.
  • the second reference voltage may be, for instance, ground.
  • the reference voltage levels can have any values such that the apparatus can be used in both the analog domain and the digital domain.
  • the first reference voltage can be a supply voltage, for example VDD
  • the second reference voltage can be a ground voltage.
  • the first reference voltage can be a ground voltage
  • the second reference voltage can be a supply voltage, for example VDD.
  • the plurality of switching elements comprises a first switching element connected between the first reference voltage and the first node, a second switching element connected between the first node and the second node, a third switching element connected between the first node and the first terminal, a fourth switching element connected between the second reference voltage and the second node and a fifth switching element connected between the second node and the second terminal.
  • the first, second and third phases can be controllable through the first to fifth switching elements.
  • the third and fifth switching elements are in a conductive state and the second and fourth switching elements are in a non-conductive state during the first phase, whereas the first, third, fourth and fifth switching elements are in a conductive state and the second switching element is in a non-conductive state during the second phase and the second, third and fifth switching elements are in a conductive state and the first and fourth switching elements are in a non- conductive state during the third phase.
  • the state of the switching elements during the switching sequence can be clearly identified.
  • the first switching element during the first phase can be either in a non- conductive state or in a conductive state.
  • the conductive state of the first switching element during the first phase advantageously allows the first array of x capacitors and the first capacitor to be more quickly charged during the second phase.
  • the plurality of switching elements can comprise respective transistors operating in the switching mode.
  • the apparatus can be made of only capacitors and transistors.
  • the apparatus has a simple and compact design and a low-noise and energy-efficient configuration.
  • the above object is also solved in accordance with a second aspect.
  • the invention relates to an apparatus for adjustably generating a time delay during a charging phase, the apparatus comprising the apparatus according to the first aspect or any of the implementation thereof, a constant current source adapted to charge, during a fourth phase following the third phase, the second capacitor starting from an initial voltage value corresponding to the analog output voltage in order to generate a voltage ramp having a constant slope, and a comparator adapted to input the voltage across the second capacitor and generate the time delay corresponding to the charging time taken by the voltage across the second capacitor to reach a threshold voltage of the comparator starting from the initial voltage value.
  • the charge is linear and a voltage ramp with a constant slope and starting from an initial voltage value varying linearly according to a digital input code x can be generated, which allows the time delay to be adjustable according to the digital input code x.
  • the apparatus exhibits a simple and compact design while having a low-noise and energy-efficient configuration.
  • the initial voltage value is set according to x corresponding to the x-bit digital input in order to be lower than the threshold voltage of the comparator.
  • an output edge can be generated at the output of the comparator as soon as the voltage ramp crosses upwards the threshold value of the comparator.
  • the step of charging the second capacitor comprises disconnecting the second capacitor from the first capacitor, the first array of x capacitors and the second array of n-x capacitors, and connecting the second capacitor to the constant current source through a sixth switching element.
  • the current charging phase can be controllable through the sixth switching element and the current of the constant current source can entirely flow through the second capacitor.
  • the invention relates to an apparatus for adjustably generating a time delay during a current discharging phase, the apparatus comprising the apparatus according to the first aspect or any of the implementations thereof, a constant current source adapted to discharge, during a fourth phase following the third phase, the second capacitor starting from an initial voltage value corresponding to the analog output voltage in order to generate a voltage ramp having a constant slope, and a comparator adapted to input the voltage across the second capacitor and generate the time delay corresponding to the discharging time taken by the voltage across the second capacitor to reach a threshold voltage of the comparator starting from the initial voltage value.
  • the current discharge can be linear and a voltage ramp with a constant slope and starting from an initial voltage value varying linearly according to a digital input code x can be generated, which allows the time delay to be adjustable according to the digital input code x.
  • the apparatus exhibits a simple and compact design while having a low-noise and energy-efficient configuration.
  • the initial voltage value is set according to x corresponding to the x-bit digital input in order to be higher than the threshold voltage of the comparator.
  • an output edge can be generated at the output of the comparator as soon as the voltage ramp crosses downwards the threshold value of the comparator.
  • the step of current discharging the second capacitor comprises disconnecting the second capacitor from the first capacitor, the first array of x capacitors and the second array of n-x capacitors, and connecting the second capacitor to the constant current source through a sixth switching element.
  • the current discharging phase can be controllable through the sixth switching element and the current of the constant current source can entirely flow through the second capacitor.
  • the sixth switching element is in a non-conductive state during the first, second and third phases and in a conductive state during the fourth phase, and the second, fourth and fifth switching elements are in a non-conductive state during the fourth phase.
  • the sixth switching element comprises a transistor operating in the switching mode.
  • the apparatus can have a simple and compact design and a low-noise and energy-efficient configuration.
  • the comparator is a CMOS inverter or an analog comparator.
  • the comparator can have a simple and compact design.
  • the invention relates to a linear digital-to-time converter comprising the apparatus according to the second or third aspect.
  • the invention relates to a digital phase locked loop comprising the apparatus according to the second, third or fourth aspect.
  • the invention relates to a method for generating an analog output voltage from a digital input signal x, by controlling an apparatus including a first capacitor connected to a first node, a second capacitor connected to a second node and a capacitor array of n elementary capacitors from a capacitor array digital-to-analog converter, CDAC, the n elementary capacitors being connectable in parallel to the first capacitor and the second capacitor.
  • the method comprises: in a charging phase connecting a first array of x elementary capacitors of the capacitor array in parallel to the first capacitor and connecting a second array of n-x elementary capacitors of the capacitor array in parallel to the second capacitor, x is the digital input signal.
  • a charge sharing phase connecting the n elementary capacitors of the capacitor array in parallel to the first capacitor and the second capacitor.
  • the first array of x elementary capacitors is connected to a first terminal and the second array of n-x elementary capacitors is connected to a second terminal, and wherein the apparatus further includes a plurality of switching elements adapted to operate according to a switching sequence.
  • the method further comprises:
  • the invention relates to a method for adjustably generating a time delay during a charging phase, the method comprising applying the steps of the method according to the sixth aspect, charging, during a fourth phase following the third phase, the second capacitor starting from an initial voltage value corresponding to the analog output voltage in order to generate a voltage ramp having a constant slope, and inputting the voltage across the second capacitor and generating the time delay corresponding to the current charging time taken by the second capacitor to reach a threshold voltage of the comparator starting from the initial voltage value, the initial voltage value being set according to x corresponding to the x-bit digital input in order to be lower than the threshold voltage of the comparator.
  • the step of current charging comprises disconnecting the second capacitor from the first capacitor, the first array of x capacitors and the second array of n-x capacitors, and connecting, after the step of
  • the invention relates to a method for adjustably generating a time delay during a current discharging phase, the method comprising applying the steps of the method according to the sixth aspect, current discharging, during a fourth phase following the third phase, the second capacitor starting from an initial voltage value corresponding to the analog output voltage in order to generate a voltage ramp having a constant slope, and inputting the voltage across the second capacitor and generating the time delay corresponding to the current discharging time taken by the second capacitor to reach a threshold voltage of the comparator starting from the initial voltage value, the initial voltage value being set according to x corresponding to the x-bit digital input in order to be higher than the threshold voltage of the comparator.
  • the step of current discharging comprises disconnecting the second capacitor from the first capacitor, the first array of x capacitors and the second array of n-x capacitors, and connecting, after the step of disconnecting, the second capacitor to a constant current source through a sixth switching element.
  • the invention relates to a computer program comprising a program code for performing the method according to any one of the sixth, seventh and eighth aspects and/or any one of their respective implementation forms when executed on a computer.
  • the method can be performed in an automatic and repeatable manner.
  • the computer program can be performed by any one of the above apparatuses.
  • the apparatuses can be programmably arranged to perform the computer program.
  • Embodiments of the invention can be implemented in hardware, software or in any combination thereof.
  • Fig. 1 shows a conventional delay line circuit, the variable delay of which is generated by switched capacitors, and the corresponding variable slope voltage ramp starting from an initial voltage value equal to zero
  • Fig. 2 shows a conventional delay line circuit, the variable delay of which is generated by switched current sources, and the corresponding variable slope voltage ramp starting from an initial voltage value equal to zero;
  • Fig. 3 shows a conventional delay line circuit, the variable delay of which is generated by a combination of switched capacitors, and switched current sources and the corresponding variable slope voltage ramp starting from an initial voltage value equal to zero;
  • Fig. 4 shows the non-linear behavior of a threshold comparator receiving a variable slope ramp
  • Fig. 5 shows a conventional voltage generator circuit comprising a capacitor array digital-to- analog converter (CDAC) connected at an input of the voltage generator circuit as shown in Fig. 5a and at an output of the voltage generator circuit as shown in Fig. 5b;
  • Fig. 6 shows the generation of a constant slope voltage ramp by the charge of a capacitor through a constant current source and a threshold comparison through a comparator;
  • CDAC capacitor array digital-to- analog converter
  • Fig. 7a shows a voltage generator circuit according to a first embodiment of the invention
  • Fig. 7b shows a detail of a voltage generator circuit according to an embodiment of the
  • Fig. 8 shows a voltage generator circuit according to a second embodiment of the invention
  • Fig. 9 shows a digital-to-time converter circuit according to a third embodiment of the
  • Fig. 10 shows a digital-to-time converter circuit according to a fourth embodiment of the
  • the present invention is based on the observation that, conventional solutions based on CDAC capacitor array still do not allow to generate a voltage, which is linear in the digital input code.
  • the present invention as described below provides an apparatus that is able to generate an initial voltage value on a capacitor that is linear with an input digital code. Using a conventional CDAC this would not be possible as the input-output relation is not linear as shown in equation 4 and 5 in the background section.
  • the new CDAC described below, implemented together with a constant slope technique allows to generate a very linear delay.
  • the constant-slope method in which the ramp keeps a constant slope, is used.
  • an apparatus for generating an analog output voltage, or voltage generator circuit generates a voltage ramp, by using a constant current source charging a capacitor starting from an initial value (Vc) that is set according to a digital code x.
  • the voltage generator circuit generates a voltage, which is constant in time and varies linearly with input code x.
  • the input code x is a digital control word representing a number.
  • the constant current source generates a constant slope voltage ramp on a capacitor from the initial value Vc set by the voltage generator as will be described in detail below.
  • the initial value Vc is linear versus the digital code x.
  • the voltage generator circuit may be used, for instance, in a DTC which exploits the generated voltage to set the initial voltage value (linearly dependent from an input digital code) in a capacitor, constant current source and a comparator with a threshold voltage (Vth).
  • a current (I) is used to charge a capacitor as shown in Fig. 6, where the slope (S) satisfies the following equation:
  • the delay function contains two distinct actions, namely a ramp generation and a threshold comparison.
  • the ramp generation produces a ramp with a controlled slope
  • the threshold comparison defines a decision threshold (Vth) and produces an output edge as soon as said threshold has been reached.
  • the biggest technica l challenge of the constant ramp technique is to generate the initial value (Vc) according to a digital input code x, namely Vc(x), in a very linear way.
  • the voltage ramp can start from an initial value Vc(x) different from zero.
  • the corresponding delay time td(x) satisfies the following equation:
  • a capacitor array such as for instance a digital-to-analog converter (CDAC)
  • CDAC digital-to-analog converter
  • a capacitor C is charged with a charge Q (m bits) that is linear with the digital input code x.
  • the voltage generator circuit is configured to generate an analog output voltage (Vc) from a digital input signal x.
  • the digital input signal may be a digital control word input to a DTC device comprising the voltage generator circuit.
  • the voltage generator circuit comprises a first capacitor CI connected to a first node N l.
  • the first node N l may be in turn connecta ble through a switch to a reference voltage source V re f,i-
  • a first array of x elementary capacitors of the capacitor array are connected in parallel to the first capacitor CI and the complementary n-x elementary capacitors (forming a second array) are connected in parallel to the second capacitor C2.
  • the remaining n-x elementary capacitors in the capacitor array are connected to a second reference voltage, for instance to ground.
  • n elementary capacitors of the capacitor array are connected in parallel to the first capacitor (CI) and the second capacitor (C2).
  • Such a configuration allows to generate a constant voltage, which has a linear dependence from the digital input signal. In other words, the generated constant voltage and the digital input signal are linearly dependent.
  • the above described voltage generator circuit in com bination with a constant current source a nd a threshold comparator implements a DTC based on the constant slope ramp technique.
  • Such architecture based only on capacitors and switches will be very low power and very low noise because no active devices are used and complex architectures, like current steering DACs (high power, high noise and high area occupation) are avoided.
  • the linearity performance is very good as the constant slope ramp technique is used.
  • the current process technology allows a very good matching for the elements of the Capacitive DAC array. Therefore, manufacturing of the above described architecture is easy and cost effective.
  • Fig. 7a shows a voltage generator circuit 100 according to an embodiment of the invention.
  • the voltage generator circuit comprises a ca pacitor array of n capacitors (each one having a capacitance value equal to CLSB) from a capacitor a rray, such as a digital-to-analog converter (CDAC), a first capacitor (CI), a second capacitor (C2) and a plurality of switching elements (T1-T5).
  • the capacitor array and the first and second capacitors are connected to a main circuit line including a first and a second node N l and N2 and among themselves by the switching elements.
  • the first capacitor (CI) is connected to a first node (Nl), while the second capacitor (C2) is connected to a second node (N2).
  • the plurality of switching elements comprises a first, second, third, fourth and fifth switching element (Tl, T2, T3, T4, T5) and is adapted to operate according to a switching sequence comprising a first, second, third and fou rth phase.
  • the splitting of the elementary capacitors in the capacitor array may vary and is set based on the input digital signal. This splitting is schematically represented in figure 7a by the switch T2. A detailed illustration of a possible internal structure of the capacitor array is shown in figure 7b.
  • each elementary capacitor Ci (where Ci is a generic elementary capacitor with the index i in the range [1; 2 m -l]) can be connected to the node Nl by the switch T3i or to the node N2 by the switch T5i. Only one a mong T3i and T5i can be on at the same time.
  • Figure 7b shows the case where x capacitors are connected to node Nl and n-x are connected to node N2.
  • the notation f indicates that the corresponding switch is off.
  • capacitor array and in particular the first and second arrays of elementary capacitors in any of the embodiments of the present invention may be implemented in the same way.
  • the first array of x capacitors (Cx) is connected in parallel with the first capacitor (CI) by turning on the third switching element (T3) connected between the first node (N l) and the first terminal (El), and the second array of n-x capacitors (Cn-x) is connected in parallel with the second capacitor (C2) by turning on the fifth switching element (T5) connected between the second node (N2) and the second terminal (E2).
  • the second switching element (T2) connected between the first node (Nl) and the second node (N2) and the fourth switching element (T4) connected between a second reference voltage (Vref2) and the second node (N2) remain turned off, i.e., in a non-conductive state.
  • the first switching element (Tl) can remain either turned off (i.e., in a non-conductive state) or turned on (i.e., in a conductive state).
  • the first switching element (Tl) being connected between a first reference voltage (Vrefl) and the first node (El), the conductive state of the first switching element (Tl) during the first phase allows the first array of x capacitors (Cx) and the first ca pacitor (CI) to be more quickly charged during the second phase.
  • a first group of capacitors formed of the first array of x capacitors (Cx) connected in parallel with the first capacitor (CI) and a second group of capacitors formed of the second array of n-x capacitors (Cn-x) connected in parallel with the second capacitor (C2) are separately charged by turning off the second switching element (T2) and turning on the first, third, fourth and fifth switching elements (Tl, T3, T4, T5).
  • Vref2 could be any value between 0 and VDD but different from Vrefl.
  • the step of charging is interrupted and the first and second groups of capacitors are connected in parallel with each other as to obtain the analog output voltage (Vc) across the second capacitor (C2).
  • Fig. 8 showing a voltage generator circuit 200 according to a second embodiment of the invention corresponding to another embodiment of the voltage generator circuit 100, wherein the first reference voltage (Vrefl) is connected to a power supply (VDD), the second reference voltage (Vref2) is connected to a ground terminal (GND) and all the capacitors (CI, C2, Cx, Cn-x) are connected to the ground terminal (GND).
  • the first and second reference voltages can have other analog voltage levels such that the voltage generator circuit 100 can operate in either an analog domain or a digital domain, and some or all of the capacitors (CI, C2, Cx, Cn-x) can be connected to a voltage terminal other than the ground terminal (GND).
  • the first reference voltage (Vrefl) can be connected to the ground terminal (GND)
  • the second reference voltage (Vref2) can be connected to the power supply (VDD) and the whole capacitors (CI, C2, Cx, Cn-x) can stay connected to the ground terminal (GND).
  • VDD power supply
  • x capacitors (Cx) from the CDAC are connected in parallel with the first capacitor (CI) by means of the third switching element (T3) as to form the first group of capacitors and n-x capacitors (Cn-x) from the CDAC are connected in parallel with the second capacitor (C2) by means of the fifth switching element (T5) as to form the second group of capacitors.
  • the first and fourth switching elements (Tl, T4) are turned off and the first and second groups of capacitors are connected to each other by means of the second switching element (T2).
  • the charge Q is shared on all the capacitors (CI, C2, Cx, Cn-x) such that the following equation is obtained:
  • Vc VDD * (CI + x * C LSB ) (6)
  • Vc analog output voltage
  • Fig. 9 shows a digital-to-time converter (DTC) circuit 300 according to a third embodiment of the invention.
  • the DTC circuit 300 comprises the voltage generator circuit 100 according to the first embodiment of the invention, a constant current source (CCS), a comparator and a sixth switching element (T6).
  • CCS constant current source
  • T6 sixth switching element
  • the second capacitor (C2) is disconnected from the first group of capacitors (CI, Cx) and the n-x capacitors (Cn-x) by turning off the second and fifth switching elements (T2, T5).
  • the constant current source (CCS) linearly charges with a constant current (I), by means of the sixth switching element (T6), the second capacitor (C2) starting from an initial voltage value corresponding to the analog output voltage (Vc) across the second capacitor (C2) obtained during the third phase.
  • the initial voltage value Vc(x) is set according to the digital input code x in order to be lower than the threshold voltage of the comparator. Thereby, a voltage ramp having a positive constant slope and starting from the initial voltage value is generated.
  • the voltage across the second capacitor (C2) is provided to an input of the comparator, e.g., a CMOS inverter or an analog comparator, such that a time delay (td) is generated as follows:
  • td (8) where td corresponds to the charging time taken by the voltage across the second capacitor to reach a threshold voltage (Vth) of the comparator starting from the initial voltage value (Vc).
  • Vth threshold voltage
  • the time delay (td) is dependent on the initial voltage value (Vc) and therefore on x corresponding to the digital input code x.
  • An output edge can then be generated at an output of the comparator as soon as the voltage ramp crosses upwards the threshold value of the comparator.
  • Fig. 10 shows a digital-to-time converter (DTC) circuit 400 according to a fourth embodiment of the invention.
  • the fourth embodiment differs from the third embodiment in that the constant current source (CCS) is configured to linearly discharge, by means of the sixth switching element (T6), the second capacitor (C2) starting from an initial voltage value corresponding to the analog output voltage (Vc) across the second capacitor (C2) obtained during the third phase.
  • the initial voltage value Vc(x) is set according to the digital input code x in order to be higher than the threshold voltage of the comparator. Thereby, a voltage ramp having a negative constant slope and starting from the initial voltage value is generated.
  • the voltage across the second capacitor (C2) is provided to an input of the comparator, e.g., a CMOS inverter or an analog comparator, such that a time delay (td) is generated as follows:
  • td (9) where td corresponds to the charging time taken by the voltage across the second capacitor to reach a threshold voltage (Vth) of the comparator starting from the initial voltage value (Vc).
  • Vth threshold voltage
  • the time delay (td) is dependent on the initial voltage value (Vc) and therefore on x corresponding to the digital input code x.
  • An output edge can then be generated at an output of the comparator as soon as the voltage ramp crosses downwards the threshold value of the comparator.
  • first, second, third, fourth, fifth and sixth switching elements may be respective transistors operating in the switching mode.
  • any one of the preceding embodiments of the present invention can be combined in cascade in order to increase a resolution and/or an output delay range.
  • One of the main application fields of the DTC can be related to the fractional frequency generation in digital phase locked loops (DPLLs) and all digital phase locked loops (ADPLLs).
  • the DTC can then be used to generate a delayed copy of a reference clock and controlled with a saw tooth ramp of digital codes in order to generate a delay linearly increasing or decreasing with the time.
  • the phase shift generated by the DTC creates a fractional frequency at the input of a phase detector of the ADPLL.
  • the DTC can also be put on the feed back path to create a linear phase shift on a feed back input of the phase detector.
  • the present invention relates to an apparatus and method for generating an analog output voltage (Vc) perfectly linear according to the d igital input code associated with a capacitor array digital-to-analog converter (CDAC).
  • a capacitor array digital-to-analog converter CDAC
  • an array of n capacitors, each of which has a capacitance value equal to CLSB is split into a first array of x capacitors (Cx) and a second array of n-x capacitors (Cn-x).
  • the x a nd n-x capacitors (Cx, Cn-x) are respectively connected in parallel with a first and second capacitor (CI, C2) as to form a respective first and second group of capacitors (Cl+Cx, C2+Cn-x).
  • the first and second groups of capacitors (Cl+Cx, C2+Cn-x) are separately charged .
  • the charged capacitors (CI, C2, Cx, Cn-x) are connected to each other as to obtain the analog output voltage (Vc) across the second capacitor (C2), which varies linearly according to a d igital input code x corresponding to an x-bit digital input.
  • the second capacitor (C2) is disconnected apart from the other capacitors (CI, Cx, Cn-x) and charged or discharged by a constant current source (CCS).
  • CCS constant current source
  • a computer program may be stored/distributed on a suitable medium, such as an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems.
  • a suitable medium such as an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

La présente invention concerne un appareil et un procédé permettant de générer une tension de sortie analogique parfaitement linéaire selon le code d'entrée numérique associé à un CNA de réseau de condensateurs. Un réseau de n condensateurs est divisé en un premier et un second réseau de condensateurs x et n-x respectifs. Dans une première phase, les condensateurs x et n-x sont respectivement connectés en parallèle à des premier et second condensateurs pour former un premier et un second groupes de condensateurs respectifs. Dans une deuxième phase, les premier et second groupes sont chargés séparément. Dans une troisième phase, les condensateurs chargés sont connectés l'un à l'autre pour obtenir la tension de sortie analogique parcourant le second condensateur, qui varie linéairement selon un code d'entrée numérique x correspondant à une entrée numérique de x-bit. Dans une quatrième phase, le second condensateur est déconnecté des autres condensateurs et chargé ou déchargé par une source de courant constant.
PCT/EP2016/074481 2016-10-12 2016-10-12 Convertisseur numérique-temps hautement linéaire destiné à une boucle à verrouillage de phase entièrement numérique à faible bruit Ceased WO2018068847A1 (fr)

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PCT/EP2016/074481 WO2018068847A1 (fr) 2016-10-12 2016-10-12 Convertisseur numérique-temps hautement linéaire destiné à une boucle à verrouillage de phase entièrement numérique à faible bruit

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WO2022119722A3 (fr) * 2020-12-03 2023-01-12 Qualcomm Incorporated Convertisseur numérique-temps économique en énergie et en surface à stabilité améliorée
TWI797839B (zh) * 2020-12-03 2023-04-01 美商高通公司 帶有改進穩定性的功率及面積有效數位時延轉換器以及其操作方法
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CN116530014A (zh) * 2020-12-10 2023-08-01 高通股份有限公司 具有平衡拓扑和负反馈的故障恢复触发器
CN118677450A (zh) * 2024-08-22 2024-09-20 成都电科星拓科技有限公司 基于调序的dtc校正方法和adpll

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