WO2017221519A1 - Nitride semiconductor element, nitride semiconductor substrate, method for manufacturing nitride semiconductor element, and method for manufacturing nitride semiconductor substrate - Google Patents

Abstract

According to one embodiment of the present disclosure, a nitride semiconductor element is provided with: a nitride semiconductor substrate having a main surface that is tilted in the a-axis direction at θ° or more (20°≤θ≤90°) from the c plane; and a superlattice layer formed by having the main surface as a crystal growing surface. The superlattice layer is configured by alternately laminating Al_x1In_y1Ga_z1N layers (0≤x1≤1, 0≤y1≤1, 0≤z1≤1, x1+y1+z1=1) and Al_x2In_y2Ga_z2N layers (0≤x2≤1, 0≤y2≤1, 0≤z2≤1, x2+y2+z2=1). The composition ratio of the Al_x1In_y1Ga_z1N layers and the Al_x2In_y2Ga_z2N layers satisfy formula of x1≠x2 and/or y1≠y2.

Description

Nitride semiconductor element, nitride semiconductor substrate, method for manufacturing nitride semiconductor element, and method for manufacturing nitride semiconductor substrate

The present disclosure relates to a nitride semiconductor device, a nitride semiconductor substrate, a method for manufacturing a nitride semiconductor device, and a method for manufacturing a nitride semiconductor substrate.

In recent years, blue-green light-emitting diodes and laser diodes using nitride semiconductors have been actively developed as light source applications. Among these, semipolar or nonpolar nitride semiconductors are effective materials as means for increasing the emission wavelength because the influence of the piezoelectric field can be reduced (see, for example, Patent Document 1).

JP 2011-003661 A

However, when crystal growth is performed on a nitride semiconductor substrate having a semipolar plane or nonpolar plane inclined by 20 ° or more in the a-axis direction from the c-plane as a main plane of crystal growth, misfit dislocations of the substrate are the starting points. Pits occurred, causing current leakage and non-light emission due to the pits. Accordingly, it is possible to provide a nitride semiconductor device, a nitride semiconductor substrate, a method for manufacturing a nitride semiconductor device, and a method for manufacturing a nitride semiconductor substrate capable of suppressing the occurrence of current leakage and non-luminescence due to pits. Is desirable.

A first nitride semiconductor device according to an embodiment of the present disclosure includes a nitride semiconductor substrate having a main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane, and the main surface And a superlattice layer formed as a crystal growth surface. The superlattice layers are Al _x1 In _{y1 Gaz1} N layer (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ z1 ≦ 1, x1 + y1 + z1 = 1) and Al _x2 In _{y2 Gaz2} N layer (0 ≦ x2 ≦). 1, 0 ≦ y2 ≦ 1, 0 ≦ z2 ≦ 1, x2 + y2 + z2 = 1) are alternately stacked. The composition ratio of the Al _x1 In _y1 Ga _z1 N layer and the Al _x2 In _y2 Ga _z2 N layer satisfies at least one of the expressions x1 ≠ x2 and y1 ≠ y2.

A nitride semiconductor substrate according to an embodiment of the present disclosure includes a nitride semiconductor substrate having a principal surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane, and the principal surface is crystallized. And a superlattice layer formed as a growth surface. The superlattice layers are Al _x1 In _{y1 Gaz1} N layer (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ z1 ≦ 1, x1 + y1 + z1 = 1) and Al _x2 In _{y2 Gaz2} N layer (0 ≦ x2 ≦). 1, 0 ≦ y2 ≦ 1, 0 ≦ z2 ≦ 1, x2 + y2 + z2 = 1) are alternately stacked. The composition ratio of the Al _x1 In _y1 Ga _z1 N layer and the Al _x2 In _y2 Ga _z2 N layer satisfies at least one of the expressions x1 ≠ x2 and y1 ≠ y2.

In the first nitride semiconductor device and nitride semiconductor substrate according to an embodiment of the present disclosure, a nitride semiconductor having a main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane The superlattice layer is formed on the main surface of the substrate. Thereby, generation | occurrence | production of a pit can be suppressed.

A first nitride semiconductor substrate manufacturing method according to an embodiment of the present disclosure includes a nitride semiconductor substrate having a principal surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane. On the other hand, the method includes a step of forming a superlattice layer using the main surface as a crystal growth surface. The superlattice layers are Al _x1 In _{y1 Gaz1} N layer (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ z1 ≦ 1, x1 + y1 + z1 = 1) and Al _x2 In _{y2 Gaz2} N layer (0 ≦ x2 ≦). 1, 0 ≦ y2 ≦ 1, 0 ≦ z2 ≦ 1, x2 + y2 + z2 = 1) are alternately stacked. The composition ratio of the Al _x1 In _y1 Ga _z1 N layer and the Al _x2 In _y2 Ga _z2 N layer satisfies at least one of the expressions x1 ≠ x2 and y1 ≠ y2.

In the first method for manufacturing a nitride semiconductor substrate according to an embodiment of the present disclosure, a nitride semiconductor substrate having a principal surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane The superlattice layer is formed on the main surface. Thereby, generation | occurrence | production of the pit which starts from the misfit dislocation of a board | substrate can be suppressed.

A second nitride semiconductor device according to an embodiment of the present disclosure includes a nitride semiconductor layer having a main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane, and the main And a junction structure layer formed with the surface as a crystal growth surface. The junction structure layer includes a lower cladding layer, an active layer, and an upper cladding layer in this order from the nitride semiconductor layer side.

In the second nitride semiconductor device according to the embodiment of the present disclosure, the main surface of the nitride semiconductor layer having a main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane. On the other hand, the junction structure layer is formed. Thereby, generation | occurrence | production of a pit can be suppressed.

A method for manufacturing a first nitride semiconductor device according to an embodiment of the present disclosure includes the following four steps.
(A1) A superlattice layer is formed on a nitride semiconductor substrate having a principal surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane with the principal surface as a crystal growth surface. (A2) forming a bulk layer using the surface of the superlattice layer as a crystal growth surface (A3) forming a junction structure layer using the surface of the bulk layer as a crystal growth surface (A4) nitride semiconductor substrate and super Step of removing lattice layer Here, the superlattice layer is composed of Al _x1 In _{y1 Gaz1} N layer (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ z1 ≦ 1, x1 + y1 + z1 = 1) and Al _x2 In _y2 Ga _z2 N layers (0 ≦ x2 ≦ 1, 0 ≦ y2 ≦ 1, 0 ≦ z2 ≦ 1, x2 + y2 + z2 = 1) are alternately stacked. The composition ratio of the Al _x1 In _{y1 Gaz1} N layer and the Al _x2 In _{y2 Gaz2} N layer satisfies at least one of the expressions x1 ≠ x2 and y1 ≠ y2. Furthermore, the junction structure layer includes a lower cladding layer, an active layer, and an upper cladding layer in this order from the nitride semiconductor substrate side.

In the first method for manufacturing a nitride semiconductor device according to an embodiment of the present disclosure, a nitride semiconductor layer having a main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane is provided. The superlattice layer is formed on the main surface, and the junction structure layer is formed on the superlattice layer via a bulk layer. Thereby, generation | occurrence | production of the pit which starts from the misfit dislocation of a board | substrate can be suppressed.

A second method for manufacturing a nitride semiconductor device according to an embodiment of the present disclosure is provided on a nitride semiconductor substrate having a main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane. On the other hand, the method includes a step of forming a junction structure layer using the main surface as a crystal growth surface. Here, the junction structure layer includes a lower cladding layer, an active layer, and an upper cladding layer in this order from the nitride semiconductor substrate side.

In the second method for manufacturing a nitride semiconductor device according to an embodiment of the present disclosure, a nitride semiconductor substrate having a main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane is provided. The junction structure layer is formed on the main surface. Thereby, generation | occurrence | production of the pit which starts from the misfit dislocation of a board | substrate can be suppressed.

According to the first nitride semiconductor device, the nitride semiconductor substrate, and the first nitride semiconductor substrate manufacturing method according to an embodiment of the present disclosure, θ ° or more (20 ° ≦ 20 ° in the a-axis direction from the c-plane. (θ ≦ 90 °) Since the superlattice layer is formed on the main surface of the nitride semiconductor substrate having the inclined main surface, current leakage and non-light emission caused by pits can be suppressed. Can do. In addition, the effect of this indication is not necessarily limited to the effect described here, Any effect described in this specification may be sufficient.

According to the second nitride semiconductor device according to an embodiment of the present disclosure, the main component of the nitride semiconductor layer having a main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane. Since the bonding structure layer is formed on the surface, it is possible to suppress the occurrence of current leakage and non-luminescence due to the pits. In addition, the effect of this indication is not necessarily limited to the effect described here, Any effect described in this specification may be sufficient.

According to the first method for manufacturing a nitride semiconductor device according to an embodiment of the present disclosure, a nitride semiconductor having a main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane. The superlattice layer is formed on the main surface of the layer, and the junction structure layer is formed on the superlattice layer via a bulk layer. Occurrence can be suppressed. In addition, the effect of this indication is not necessarily limited to the effect described here, Any effect described in this specification may be sufficient.

According to the second method for manufacturing a nitride semiconductor device according to an embodiment of the present disclosure, a nitride semiconductor having a principal surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane Since the junction structure layer is formed on the main surface of the substrate, it is possible to suppress the occurrence of current leakage and non-luminescence due to pits. In addition, the effect of this indication is not necessarily limited to the effect described here, Any effect described in this specification may be sufficient.

It is a figure showing the example of a section composition of the semiconductor light emitting element concerning a 1st embodiment of this indication. It is a figure showing the cross-sectional structural example of the superlattice layer of FIG. It is a figure showing an example of the manufacture process of the semiconductor light-emitting device of FIG. It is a figure showing an example of the manufacture process following Drawing 3A. It is a figure showing the example of a section composition of the semiconductor light emitting element concerning a 2nd embodiment of this indication. It is a figure showing the cross-sectional structural example of the semiconductor substrate which concerns on 3rd Embodiment of this indication. It is a figure showing an example of the manufacturing process of the semiconductor substrate of FIG. It is a figure showing an example of the manufacture process following Drawing 6A. It is a figure showing the cross-sectional structural example of the semiconductor light-emitting device which concerns on a modification. It is a figure showing the cross-sectional structural example of the semiconductor light-emitting device which concerns on a modification. It is a figure showing the cross-sectional structural example of the semiconductor substrate of FIG. It is a figure showing an example of the manufacturing process of the semiconductor light-emitting device of FIG. It is a figure showing an example of the manufacturing process of the semiconductor light-emitting device of FIG.

Hereinafter, modes for carrying out the present disclosure will be described in detail with reference to the drawings. The following description is one specific example of the present disclosure, and the present disclosure is not limited to the following aspects. In addition, the present disclosure is not limited to the arrangement, dimensions, dimensional ratio, and the like of each component illustrated in each drawing. The description will be given in the following order.

1. First Embodiment (Semiconductor Light Emitting Element)
2. Second embodiment (semiconductor light emitting device)
3. Modified example of the third embodiment (semiconductor substrate)

<1. First Embodiment>
[Constitution]
A configuration of the semiconductor light emitting element 1 according to the first embodiment of the present disclosure will be described. FIG. 1 illustrates a cross-sectional configuration example of a semiconductor light emitting element 1 according to the present embodiment.

The semiconductor light emitting device 1 can be suitably applied as a blue to green light source. The semiconductor light emitting element 1 includes, for example, a substrate 10, a superlattice layer 20, and a junction structure layer 30. The superlattice layer 20 is formed using the main surface of the substrate 10 as a crystal growth surface. The junction structure layer 30 is formed by using the surface of the superlattice layer 20 as a crystal growth surface. The superlattice layer 20 and the junction structure layer 30 are formed by an epitaxial crystal growth method such as MOCVD (Metal Organic Chemical Vapor Deposition).

The substrate 10 is a nitride semiconductor substrate and is made of, for example, n-type GaN. The nitride semiconductor substrate used for the substrate 10 has a main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane. The crystal plane of the main surface is, for example, the (11-20) plane, the (11-22) plane, or the (11-24) plane. The substrate 10 is doped with an n-type impurity such as silicon (Si). In the present specification, the “main surface of the substrate 10” refers to a crystal plane inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane.

The junction structure layer 30 has, for example, a double hetero junction structure. The double heterojunction structure refers to a structure in which a heterogeneous semiconductor (an active layer 34 described later) with a narrow band gap is sandwiched between pn semiconductors (a lower cladding layer 32 and an upper cladding layer 36 described later) of the same material. Yes. The junction structure layer 30 includes, for example, a base layer 31, a lower cladding layer 32, a lower guide layer 33, an active layer 34, an upper guide layer 35, an upper cladding layer 36, and a contact layer 37. The junction structure layer 30 includes a base layer 31, a lower clad layer 32, a lower guide layer 33, an active layer 34, an upper guide layer 35, an upper clad layer 36, and a contact layer 37 in this order from the superlattice layer 20 side. Has been.

The underlayer 31 is made of n-type GaN, for example. The lower cladding layer 32 is made of, for example, n-type AlGaN. The lower guide layer 33 is made of, for example, n-type InGaN. The underlayer 31, the lower cladding layer 32, and the lower guide layer 33 are doped with an n-type impurity such as silicon (Si). The active layer 34 has, for example, a multiple quantum well (MQW) structure in which well layers made of InGaN and barrier layers made of AlGaN are alternately and repeatedly stacked. The active layer 34 may be composed of a single layer. The upper guide layer 35 is made of, for example, undoped InGaN. The upper cladding layer 36 is made of, for example, p-type AlGaN. The contact layer 37 is made of, for example, p-type GaN. The upper cladding layer 36 and the contact layer 37 are doped with a p-type impurity such as magnesium (Mg).

The semiconductor light emitting device 1 may further include a lower electrode that is in contact with the substrate 10 or the lower cladding layer 32 and is electrically connected to the lower cladding layer 32. The semiconductor light emitting device 1 may further include an upper electrode that is in contact with the contact layer 37 and is electrically connected to the upper cladding layer 36. The bonding structure layer 30 may have a layer other than the above. In the bonding structure layer 30, the lower guide layer 33 and the upper guide layer 35 may be omitted, and the base layer 31 may be omitted. Further, a stripe-shaped ridge portion or a columnar mesa portion may be provided for the bonding structure layer 30.

Next, the superlattice layer 20 will be described. FIG. 2 illustrates a cross-sectional configuration example of the superlattice layer 20. As described above, the superlattice layer 20 is formed by using the main surface of the substrate 10 as a crystal growth surface. Therefore, no layer such as an underlayer is provided between the main surface of the substrate 10 and the superlattice layer 20. For example, as shown in FIG. 2, the superlattice layer 20 includes an Al _x1 In _{y1 Gaz1} N layer 20A (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ z1 ≦ 1, x1 + y1 + z1 = 1) and Al. _x2 In _y2 Ga _z2 N layers 20B (0 ≦ x2 ≦ 1, 0 ≦ y2 ≦ 1, 0 ≦ z2 ≦ 1, x2 + y2 + z2 = 1) are alternately stacked. The composition ratio of the Al _x1 In _{y1 Gaz1} N layer 20A and the Al _x2 In _{y2 Gaz2} N layer 20B satisfies at least one of the expressions x1 ≠ x2 and y1 ≠ y2.

The degree of lattice mismatch between the Al _x1 In _y1 Ga _z1 N layer 20A and the Al _x2 In _y2 Ga _z2 N layer 20B is 0.00048 or more. For example, the Al _x1 In _y1 Ga _z1 N layer 20A is composed of Al _0.08 Ga _0.02 N with a thickness of 2.0 nm, and the Al _x2 In _y2 Ga _z2 N layer 20B is composed of GaN with a thickness of 2.0 nm. As a result, the degree of lattice mismatch within the above-described range can be realized.

In order to obtain the lattice mismatch within the above-described range, the film thicknesses of the Al _x1 In _y1 Ga _z1 N layer 20A and the Al _x2 In _y2 Ga _z2 N layer 20B are 1 nm or more and 10 nm or less, respectively. It is preferable. In order to obtain the lattice mismatch degree within the above-described range, the number of stacked layers in the superlattice layer 20 is preferably 10 pairs or more, and more preferably 100 pairs or more.

[Production method]
Next, a method for manufacturing the semiconductor light emitting device 1 according to this embodiment will be described. FIG. 3A shows an example of the manufacturing process of the semiconductor light emitting device 1. FIG. 3B shows an example of the manufacturing process following FIG. 3A.

In order to manufacture the semiconductor light emitting device 1, nitride semiconductors are collectively formed on a substrate 10 made of, for example, GaN by an epitaxial crystal growth method such as an MOCVD method. At this time, for example, trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn), ammonia (NH ₃ ) or the like is used as a compound semiconductor material, and monosilane (SiH) is used as a source material for donor impurities. ₄ ) and the acceptor impurity material is, for example, biscyclopentadienylmagnesium (Cp ₂
Mg) is used.

First, for example, as shown in FIG. 3A, a substrate 10 having a main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane is prepared. Next, for example, as illustrated in FIG. 3B, the superlattice layer 20 is formed on the substrate 10 with the main surface of the substrate 10 as a crystal growth surface. Next, the junction structure layer 30 is formed using the surface of the superlattice layer 20 as a crystal growth surface. Thereafter, an upper electrode and a lower electrode are formed as necessary. In this way, the semiconductor light emitting element 1 is manufactured.

[Operation]
In the semiconductor light emitting device 1 having such a configuration, when a predetermined voltage is applied between the upper electrode and the lower electrode, a current is injected into the active layer 34, thereby emitting light by recombination of electrons and holes. Arise. For example, when a stripe-shaped ridge portion is formed with respect to the junction structure layer 30 and a resonator mirror (multilayer film) is provided on both end faces in the extending direction of the ridge portion, the occurrence occurs in the active layer 34. The light is reflected by the pair of resonator mirrors, and laser oscillation occurs at a predetermined oscillation wavelength λ. Then, the laser beam having the oscillation wavelength λ is emitted to the outside from the end surface having a relatively low reflectance. Further, for example, when a columnar mesa portion is formed with respect to the bonding structure layer 30 and the lower cladding layer 32 and the upper cladding layer 36 are composed of DBR, the light generated in the active layer 34 Reflected by the layer 32 and the upper cladding layer 36, laser oscillation occurs at a predetermined oscillation wavelength λ. Then, laser light having an oscillation wavelength λ is emitted from the upper surface of the bonding structure layer 30 to the outside. Further, for example, when the junction structure layer 30 does not have a resonator structure and spontaneous emission light is output, light having an emission wavelength λ generated in the active layer 34 is externally transmitted from the upper surface of the junction structure layer 30. Is emitted.

[effect]
Next, the effect of the semiconductor light emitting device 1 according to the present embodiment will be described.

In recent years, blue-green light-emitting diodes and laser diodes using nitride semiconductors have been actively developed as light source applications. Among these, semipolar or nonpolar nitride semiconductors are effective materials as means for increasing the emission wavelength because the influence of the piezoelectric field can be reduced. However, when crystal growth is performed on a nitride semiconductor substrate having a semipolar plane or nonpolar plane inclined by 20 ° or more in the a-axis direction from the c-plane as a main plane of crystal growth, misfit dislocations of the substrate are the starting points. Pits occurred, causing current leakage and non-light emission due to the pits.

On the other hand, in the present embodiment, superlattice layer 20 is formed on the main surface of substrate 10 having the main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from c-plane. Yes. As a result, strain stress is generated by the Al _x1 In _y1 Ga _z1 N layer 20A and the Al _x2 In _y2 Ga _z2 N layer 20B. This strain stress causes misfit dislocations of the substrate to the superlattice layer 20 as a starting point. It is possible to suppress the occurrence of pits. As a result, it is possible to suppress the generation of pits even in the bonding structure layer 30 formed on the superlattice layer 20. Therefore, it is possible to suppress the occurrence of current leakage and non-light emission due to the pits.

In this embodiment, the lattice mismatch between the Al _x1 In _y1 Ga _z1 N layer 20A and the Al _x2 In _y2 Ga _z2 N layer 20B has a 0.00048 or more. Thus, in the manufacturing process, when the superlattice layer 20 is formed on the main surface of the substrate 10, the generation of pits in the superlattice layer 20 due to the strain stress generated in the superlattice layer 20 is effectively suppressed. can do. As a result, it is possible to suppress the generation of pits even in the bonding structure layer 30 formed on the superlattice layer 20. Therefore, it is possible to suppress the occurrence of current leakage and non-light emission due to the pits. When the degree of lattice mismatch between the Al _x1 In _y1 Ga _z1 N layer 20A and the Al _x2 In _y2 Ga _z2 N layer 20B is less than 0.00048, the strain stress generated in the superlattice layer 20 is small. Since it is difficult to suppress generation of pit starting points between the main surface of the substrate 10 and the superlattice layer 20, pits may be formed while the superlattice layer 20 is grown. High nature.

By the way, when the junction structure layer 30 is formed with the (11-20) plane, the (11-22) plane, or the (11-24) plane as the crystal growth plane, the m plane (1-100) is used as the cleavage plane. There are advantages such as being able to. However, when the bonding structure layer 30 is formed directly on the (11-20) plane, the (11-22) plane, or the (11-24) plane of the substrate 10, pits are likely to be generated in the bonding structure layer 30. . On the other hand, in the present embodiment, when the superlattice layer 20 is formed on the (11-20) plane, the (11-22) plane, or the (11-24) plane of the substrate 10 and then the junction structure layer 30 is formed. Therefore, the occurrence of pits in the bonding structure layer 30 can be suppressed. As a result, for example, a light-emitting element having an m-plane (1-100) as a cleavage plane can be put into practical use.

In the present embodiment, the junction structure layer 30 including the lower cladding layer 32, the active layer 34, and the upper cladding layer 36 in this order is formed on the main surface of the substrate 10 via the superlattice layer 20. Yes. As a result, for example, a light-emitting element having an m-plane (1-100) as a cleavage plane can be put into practical use.

<2. Second Embodiment>
[Constitution]
Next, the configuration of the semiconductor light emitting element 2 according to the second embodiment of the present disclosure will be described. FIG. 4 illustrates a cross-sectional configuration example of the semiconductor light emitting element 2 according to the present embodiment.

The semiconductor light emitting element 2 can be suitably applied as a blue to green light source. The semiconductor light emitting element 2 includes, for example, a substrate 10, a superlattice layer 20, and a junction structure layer 40. The superlattice layer 20 is formed using the main surface of the substrate 10 as a crystal growth surface. The junction structure layer 40 is formed using the surface of the superlattice layer 20 as a crystal growth surface. The superlattice layer 20 and the junction structure layer 40 are formed by an epitaxial crystal growth method such as an MOCVD method, for example.

The junction structure layer 40 has, for example, one heterojunction structure in a double heterojunction. The bonding structure layer 40 has a configuration in which the base layer 31 and the lower cladding layer 32 are omitted from the bonding structure layer 30 of the above embodiment. The superlattice layer 20 also serves as the lower cladding layer 32 of the above embodiment. Accordingly, the superlattice layer 20 and the junction structure layer 40 constitute a double heterojunction. In the present embodiment, the superlattice layer 20 is formed by a method similar to the method described in the first embodiment.

[effect]
Next, the effect of the semiconductor light emitting element 2 according to the present embodiment will be described.

In the present embodiment, as in the above-described embodiment, the superlattice layer with respect to the main surface of the substrate 10 having the main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane. 20 is formed. As a result, strain stress is generated by the Al _x1 In _y1 Ga _z1 N layer 20A and the Al _x2 In _y2 Ga _z2 N layer 20B. This strain stress causes misfit dislocations of the substrate to the superlattice layer 20 as a starting point. It is possible to suppress the occurrence of pits. As a result, the generation of pits can be suppressed even in the bonding structure layer 40 formed on the superlattice layer 20. Therefore, it is possible to suppress the occurrence of current leakage and non-light emission due to the pits.

In the present embodiment, the lattice mismatch degree between the Al _x1 In _y1 Ga _z1 N layer 20A and the Al _x2 In _y2 Ga _z2 N layer 20B is 0.00048 or more, as in the above embodiment. Thus, in the manufacturing process, when the superlattice layer 20 is formed on the main surface of the substrate 10, the generation of pits in the superlattice layer 20 due to the strain stress generated in the superlattice layer 20 is effectively suppressed. can do. As a result, the generation of pits can be suppressed even in the bonding structure layer 40 formed on the superlattice layer 20. Therefore, it is possible to suppress the occurrence of current leakage and non-light emission due to the pits.

By the way, when the junction structure layer 30 of the above embodiment is formed using the (11-20) plane, the (11-22) plane, or the (11-24) plane as the crystal growth plane, the m plane ( 1-100) can be used. However, when the junction structure layer 30 is formed directly on the (11-20) plane, the (11-22) plane, or the (11-24) plane, pits are easily generated in the junction structure layer 30. On the other hand, in the present embodiment, the superlattice layer 20 is formed on the (11-20) plane, the (11-22) plane, or the (11-24) plane, the junction structure layer 40 is formed, and the superlattice layer is formed. When the layer 20 is also used as the lower clad layer 32 of the above embodiment, it is possible to suppress the generation of pits in the superlattice layer 20 and the junction structure layer 40. As a result, for example, a light-emitting element having an m-plane (1-100) as a cleavage plane can be put into practical use.

<3. Third Embodiment>
[Constitution]
Next, the configuration of the semiconductor substrate 3 according to the third embodiment of the present disclosure will be described. FIG. 5 illustrates a cross-sectional configuration example of the semiconductor substrate 3 according to the present embodiment.

The semiconductor substrate 3 can be suitably applied as a substrate (so-called seed substrate) for crystal growth of the bonding structure layer 30 or the like that can function as a blue to green light source. The semiconductor substrate 3 includes, for example, a base material 38, a superlattice layer 20, and a bulk layer 39. The superlattice layer 20 is formed by using the main surface of the substrate 38 as a crystal growth surface. The bulk layer 39 is formed using the surface of the superlattice layer 20 as a crystal growth surface.

The base material 38 is a nitride semiconductor wafer and is made of, for example, n-type GaN. The nitride semiconductor wafer used for the base material 38 has a main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane. The crystal plane of the main surface is, for example, the (11-20) plane, the (11-22) plane, or the (11-24) plane. The base material 38 is doped with an n-type impurity such as silicon (Si). In the present specification, the “main surface of the substrate 38” refers to a crystal plane inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane.

The bulk layer 39 is a nitride semiconductor layer and is made of, for example, n-type GaN. The bulk layer 39 has a thickness of, for example, millimeter order. The bulk layer 39 has a main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane, like the base material 38. The bulk layer 39 is formed by an epitaxial crystal growth method such as MOCVD method or HVPE (HydrideydVapor Phase Epitaxy) method. The bulk layer 39 is doped with an n-type impurity such as silicon (Si).

[Production method]
Next, a method for manufacturing the semiconductor substrate 3 according to the present embodiment will be described. FIG. 6A shows an example of the manufacturing process of the semiconductor substrate 3. FIG. 6B shows an example of the manufacturing process following FIG. 6A.

In order to manufacture the semiconductor substrate 3, nitride semiconductors are collectively formed on the base material 38 made of, for example, GaN by an epitaxial crystal growth method such as MOCVD method or HVPE method. At this time, for example, trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn), ammonia (NH ₃ ), or the like is used as a compound semiconductor material, and monosilane (SiH) is used as a source material for donor impurities. ₄ ) and as the acceptor impurity material, for example, biscyclopentadienylmagnesium (Cp ₂ Mg) is used.

First, for example, as shown in FIG. 6A, a base material 38 having a main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane is prepared. Next, for example, as illustrated in FIG. 6B, the superlattice layer 20 is formed on the substrate 38 with the main surface of the substrate 38 as a crystal growth surface. Next, the bulk layer 39 is formed using the surface of the superlattice layer 20 as a crystal growth surface. In this way, the semiconductor substrate 3 is manufactured.

[effect]
Next, the effect of the semiconductor substrate 3 according to the present embodiment will be described.

In the present embodiment, the superlattice layer 20 is formed on the main surface of the base material 38 having a main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane. . As a result, strain stress is generated by the Al _x1 In _y1 Ga _z1 N layer 20A and the Al _x2 In _y2 Ga _z2 N layer 20B. This strain stress causes misfit dislocations of the substrate to the superlattice layer 20 as a starting point. It is possible to suppress the occurrence of pits. As a result, generation of pits can be suppressed also for the bulk layer 39 formed on the superlattice layer 20. Therefore, for example, as shown in FIG. 7, when the junction structure layer 30 is formed on the semiconductor substrate 3 (bulk layer 39), current leakage or non-light emission caused by pits occurs in the junction structure layer 30. Can be suppressed. Here, the junction structure layer 30 is formed by using the main surface of the bulk layer 39 (a crystal plane inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane) as a crystal growth surface. is there.

In the present embodiment, as in the first embodiment, the degree of lattice mismatch between the Al _x1 In _y1 Ga _z1 N layer 20A and the Al _x2 In _y2 Ga _z2 N layer 20B is 0.00048 or more. Yes. Thereby, when the superlattice layer 20 is formed on the main surface of the base material 38 in the manufacturing process, it is possible to effectively generate pits in the superlattice layer 20 due to the strain stress generated in the superlattice layer 20. Can be suppressed. As a result, generation of pits can be suppressed also for the bulk layer 39 formed on the superlattice layer 20. Therefore, for example, as shown in FIG. 7, when the junction structure layer 30 is formed on the semiconductor substrate 3 (bulk layer 39), current leakage or non-light emission caused by pits occurs in the junction structure layer 30. Can be suppressed.

By the way, when the junction structure layer 30 of the above embodiment is formed using the (11-20) plane, the (11-22) plane, or the (11-24) plane as the crystal growth plane, the m plane ( 1-100) can be used. However, when the bonding structure layer 30 is formed directly on the (11-20) surface, the (11-22) surface, or the (11-24) surface of the substrate 38, pits are generated in the bonding structure layer 30. Cheap. On the other hand, for example, as shown in FIG. 7, when the bonding structure layer 30 is formed on the semiconductor substrate 3 (bulk layer 39), the generation of pits in the bonding structure layer 30 can be suppressed. As a result, for example, a light-emitting element having an m-plane (1-100) as a cleavage plane can be put into practical use.

Incidentally, in the semiconductor light emitting device 1 shown in FIG. 7, instead of the semiconductor substrate 3, for example, as shown in FIGS. 8 and 9, a semiconductor substrate 4 made of a bulk layer 39 may be used. The semiconductor substrate 4 is composed of, for example, a bulk layer 39 left by removing the base material 38 and the superlattice layer 20 from the semiconductor substrate 3.

The semiconductor light-emitting device 1 shown in FIG. 8 includes a semiconductor substrate 4 composed of a bulk layer 39 and a crystal tilted by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane. And a bonding structure layer 30 formed with the crystal plane as a crystal growth plane. The junction structure layer 30 includes a lower clad layer 32, a lower guide layer 33, an active layer 34, an upper guide layer 35, an upper clad layer 36, and a contact layer 37 in this order from the semiconductor substrate 4 side. 7, for example, as shown in FIG. 10, after forming the bonding structure layer 30 on the semiconductor substrate 3, the bottom surface of the semiconductor substrate 3 is polished so that the base material 38 and the superstructure It is formed by removing the lattice layer 20. 7, for example, as shown in FIG. 11, the bonding structure layer 30 is formed on the semiconductor substrate 4 with the main surface of the semiconductor substrate 4 as the crystal growth surface. It may be formed. Even when the bonding structure layer 30 is formed by any method, in the bonding structure layer 30, it is possible to suppress the occurrence of current leakage and non-light emission due to the pits as in the above embodiment.

Although the present disclosure has been described with reference to a plurality of embodiments, the present disclosure is not limited to the above-described embodiments, and various modifications can be made. In addition, the effect described in this specification is an illustration to the last. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than those described in this specification.

For example, this indication can take the following composition.
(1)
a nitride semiconductor substrate having a principal surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane;
A superlattice layer formed using the main surface as a crystal growth surface,
The superlattice layer includes an Al _x1 In _y1 Ga _z1 N layer (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ z1 ≦ 1, x1 + y1 + z1 = 1) and an Al _x2 In _y2 Ga _z2 N layer (0 ≦ x2). ≦ 1, 0 ≦ y2 ≦ 1, 0 ≦ z2 ≦ 1, x2 + y2 + z2 = 1) are alternately stacked,
A nitride semiconductor device in which a composition ratio of the Al _x1 In _{y1 Gaz1} N layer and the Al _x2 In _{y2 Gaz2} N layer satisfies at least one of x1 ≠ x2 and y1 ≠ y2.
(2)
The degree of lattice mismatch between the Al _x1 In _y1 Ga _z1 N layer and the Al _x2 In _y2 Ga _z2 N layer is 0.00048 or more.
(3)
The nitride semiconductor device according to (1) or (2), wherein the main surface is a (11-20) plane, a (11-22) plane, or a (11-24) plane.
(4)
A bonding structure layer formed using the surface of the superlattice layer as a crystal growth surface;
The nitride semiconductor device according to any one of (1) to (3), wherein the junction structure layer includes a lower cladding layer, an active layer, and an upper cladding layer in this order from the superlattice layer side. .
(5)
A bonding structure layer formed using the surface of the superlattice layer as a crystal growth surface;
The junction structure layer includes an active layer and an upper clad layer in this order from the superlattice layer side,
The superlattice layer also serves as a lower cladding layer. The nitride semiconductor device according to any one of (1) to (3).
(6)
a nitride semiconductor substrate having a principal surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane;
A superlattice layer formed using the main surface as a crystal growth surface,
The superlattice layer includes an Al _x1 In _y1 Ga _z1 N layer (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ z1 ≦ 1, x1 + y1 + z1 = 1) and an Al _x2 In _y2 Ga _z2 N layer (0 ≦ x2). ≦ 1, 0 ≦ y2 ≦ 1, 0 ≦ z2 ≦ 1, x2 + y2 + z2 = 1) are alternately stacked,
A nitride semiconductor substrate in which a composition ratio of the Al _x1 In _{y1 Gaz1} N layer and the Al _x2 In _{y2 Gaz2} N layer satisfies at least one of x1 ≠ x2 and y1 ≠ y2.
(7)
forming a superlattice layer with respect to a nitride semiconductor substrate having a main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane with the main surface as a crystal growth surface; Including
The superlattice layer includes an Al _x1 In _y1 Ga _z1 N layer (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ z1 ≦ 1, x1 + y1 + z1 = 1) and an Al _x2 In _y2 Ga _z2 N layer (0 ≦ x2). ≦ 1, 0 ≦ y2 ≦ 1, 0 ≦ z2 ≦ 1, x2 + y2 + z2 = 1) are alternately stacked,
A method for manufacturing a nitride semiconductor substrate, wherein a composition ratio of the Al _x1 In _{y1 Gaz1} N layer and the Al _x2 In _{y2 Gaz2} N layer satisfies at least one of x1 ≠ x2 and y1 ≠ y2.
(8)
a nitride semiconductor layer having a principal surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane;
A junction structure layer formed using the main surface as a crystal growth surface,
The junction structure layer includes a lower clad layer, an active layer, and an upper clad layer in this order from the nitride semiconductor layer side.
(9)
forming a superlattice layer on a nitride semiconductor substrate having a principal surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane with the principal surface as a crystal growth surface; ,
Forming a bulk layer using the surface of the superlattice layer as a crystal growth surface;
Forming a junction structure layer using the surface of the bulk layer as a crystal growth surface;
Removing the nitride semiconductor substrate and the superlattice layer,
The superlattice layer includes an Al _x1 In _y1 Ga _z1 N layer (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ z1 ≦ 1, x1 + y1 + z1 = 1) and an Al _x2 In _y2 Ga _z2 N layer (0 ≦ x2). ≦ 1, 0 ≦ y2 ≦ 1, 0 ≦ z2 ≦ 1, x2 + y2 + z2 = 1) are alternately stacked,
The composition ratio of the Al _x1 In _{y1 Gaz1} N layer and the Al _x2 In _{y2 Gaz2} N layer satisfies at least one of the expressions x1 ≠ x2 and y1 ≠ y2.
The junction structure layer includes a lower cladding layer, an active layer, and an upper cladding layer in this order from the nitride semiconductor substrate side. A method for manufacturing a nitride semiconductor device.
(10)
forming a junction structure layer with respect to a nitride semiconductor substrate having a main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane with the main surface as a crystal growth surface. ,
The junction structure layer includes a lower clad layer, an active layer, and an upper clad layer in this order from the nitride semiconductor substrate side. A method for manufacturing a nitride semiconductor device.

This application claims priority on the basis of Japanese Patent Application No. 2016-121525 filed on June 20, 2016 at the Japan Patent Office. The entire contents of this application are incorporated herein by reference. This is incorporated into the application.

Those skilled in the art will envision various modifications, combinations, subcombinations, and changes, depending on design requirements and other factors, which are within the scope of the appended claims and their equivalents. It is understood that

Claims (10)

a nitride semiconductor substrate having a principal surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane;
A superlattice layer formed using the main surface as a crystal growth surface,
The superlattice layer includes an Al _x1 In _y1 Ga _z1 N layer (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ z1 ≦ 1, x1 + y1 + z1 = 1) and an Al _x2 In _y2 Ga _z2 N layer (0 ≦ x2). ≦ 1, 0 ≦ y2 ≦ 1, 0 ≦ z2 ≦ 1, x2 + y2 + z2 = 1) are alternately stacked,
A nitride semiconductor device in which a composition ratio of the Al _x1 In _{y1 Gaz1} N layer and the Al _x2 In _{y2 Gaz2} N layer satisfies at least one of x1 ≠ x2 and y1 ≠ y2. The nitride semiconductor device according to claim 1, wherein a lattice mismatch degree between the Al _x1 In _y1 Ga _z1 N layer and the Al _x2 In _y2 Ga _z2 N layer is 0.00048 or more. The nitride semiconductor device according to claim 1, wherein the main surface is a (11-20) plane, a (11-22) plane, or a (11-24) plane. A bonding structure layer formed using the surface of the superlattice layer as a crystal growth surface;
The nitride semiconductor device according to claim 1, wherein the junction structure layer includes a lower cladding layer, an active layer, and an upper cladding layer in this order from the superlattice layer side. A bonding structure layer formed using the surface of the superlattice layer as a crystal growth surface;
The junction structure layer includes an active layer and an upper clad layer in this order from the superlattice layer side,
The nitride semiconductor device according to claim 1, wherein the superlattice layer also serves as a lower cladding layer. a nitride semiconductor substrate having a principal surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane;
A superlattice layer formed using the main surface as a crystal growth surface,
The superlattice layer includes an Al _x1 In _y1 Ga _z1 N layer (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ z1 ≦ 1, x1 + y1 + z1 = 1) and an Al _x2 In _y2 Ga _z2 N layer (0 ≦ x2). ≦ 1, 0 ≦ y2 ≦ 1, 0 ≦ z2 ≦ 1, x2 + y2 + z2 = 1) are alternately stacked,
A nitride semiconductor substrate in which a composition ratio of the Al _x1 In _{y1 Gaz1} N layer and the Al _x2 In _{y2 Gaz2} N layer satisfies at least one of x1 ≠ x2 and y1 ≠ y2. forming a superlattice layer with respect to a nitride semiconductor substrate having a main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane with the main surface as a crystal growth surface; Including
The superlattice layer includes an Al _x1 In _y1 Ga _z1 N layer (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ z1 ≦ 1, x1 + y1 + z1 = 1) and an Al _x2 In _y2 Ga _z2 N layer (0 ≦ x2). ≦ 1, 0 ≦ y2 ≦ 1, 0 ≦ z2 ≦ 1, x2 + y2 + z2 = 1) are alternately stacked,
A method for manufacturing a nitride semiconductor substrate, wherein a composition ratio of the Al _x1 In _{y1 Gaz1} N layer and the Al _x2 In _{y2 Gaz2} N layer satisfies at least one of x1 ≠ x2 and y1 ≠ y2. a nitride semiconductor layer having a principal surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane;
A junction structure layer formed using the main surface as a crystal growth surface,
The junction structure layer includes a lower clad layer, an active layer, and an upper clad layer in this order from the nitride semiconductor layer side. forming a superlattice layer on a nitride semiconductor substrate having a principal surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane with the principal surface as a crystal growth surface; ,
Forming a bulk layer using the surface of the superlattice layer as a crystal growth surface;
Forming a junction structure layer using the surface of the bulk layer as a crystal growth surface;
Removing the nitride semiconductor substrate and the superlattice layer,
The superlattice layer includes an Al _x1 In _y1 Ga _z1 N layer (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ z1 ≦ 1, x1 + y1 + z1 = 1) and an Al _x2 In _y2 Ga _z2 N layer (0 ≦ x2). ≦ 1, 0 ≦ y2 ≦ 1, 0 ≦ z2 ≦ 1, x2 + y2 + z2 = 1) are alternately stacked,
The composition ratio of the Al _x1 In _{y1 Gaz1} N layer and the Al _x2 In _{y2 Gaz2} N layer satisfies at least one of the expressions x1 ≠ x2 and y1 ≠ y2.
The junction structure layer includes a lower cladding layer, an active layer, and an upper cladding layer in this order from the nitride semiconductor substrate side. A method for manufacturing a nitride semiconductor device. forming a junction structure layer with respect to a nitride semiconductor substrate having a main surface inclined by θ ° or more (20 ° ≦ θ ≦ 90 °) in the a-axis direction from the c-plane with the main surface as a crystal growth surface. ,
The junction structure layer includes a lower clad layer, an active layer, and an upper clad layer in this order from the nitride semiconductor substrate side. A method for manufacturing a nitride semiconductor device.

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