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WO2017213329A1 - Procédé de décodage de code de correction d'erreurs sur la base d'un canal d'effacement binaire présentant un ratio de probabilité, et dispositif associé - Google Patents

Procédé de décodage de code de correction d'erreurs sur la base d'un canal d'effacement binaire présentant un ratio de probabilité, et dispositif associé Download PDF

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Publication number
WO2017213329A1
WO2017213329A1 PCT/KR2017/002439 KR2017002439W WO2017213329A1 WO 2017213329 A1 WO2017213329 A1 WO 2017213329A1 KR 2017002439 W KR2017002439 W KR 2017002439W WO 2017213329 A1 WO2017213329 A1 WO 2017213329A1
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symbol
code
crc
codewords
parity
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PCT/KR2017/002439
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English (en)
Korean (ko)
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노광석
김동규
변일무
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엘지전자 주식회사
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems

Definitions

  • the present invention relates to an error correction code decoding method in a wireless communication system, and more particularly, to an error correction code decoding method based on a binary erasure channel (BEC) having a likelihood ratio.
  • BEC binary erasure channel
  • Wireless access systems are widely deployed to provide various kinds of communication services such as voice and data.
  • a wireless access system is a multiple access system capable of supporting communication with multiple users by sharing available system resources (bandwidth, transmission power, etc.).
  • multiple access systems include code division multiple access (CDMA) systems, frequency division multiple access (FDMA) systems, time division multiple access (TDMA) systems, orthogonal frequency division multiple access (OFDMA) systems, and single carrier frequency (SC-FDMA). division multiple access) system.
  • CDMA code division multiple access
  • FDMA frequency division multiple access
  • TDMA time division multiple access
  • OFDMA orthogonal frequency division multiple access
  • SC-FDMA single carrier frequency division multiple access
  • channel codes are essentially used in broadcast systems.
  • a transmitter may perform encoding on an input symbol by using an encoder and transmit an encoded symbol.
  • the receiving end may restore the input symbol by receiving the encoded symbol and performing decoding on the received symbol.
  • the size of the input symbol and the size of the encoded symbol may be defined differently according to the communication system.
  • LTE Long Term Evolution
  • 3GPP 3rd Generation Partnership Project
  • an input symbol has a maximum size of 6144 bits and a coded symbol size 18432 (6144 * 3) bits.
  • Turbo coding in an LTE communication system may be referred to by 3GPP Technical Specification 36.212.
  • the LTE turbo code has a slight improvement in performance even if the signal to noise ratio (SNR) increases due to the structure of the code.
  • SNR signal to noise ratio
  • it may be considered to use a code having a lower error rate, but in this case, there is a problem that the complexity increases.
  • Another object of the present invention is to provide an error correction method with low error rate and complexity.
  • Another object of the present invention is to provide an apparatus supporting these methods.
  • a data decoding method of a terminal of a wireless communication system of the present invention for solving the above problems includes the steps of: receiving data from a transmitting end; Decoding a transport block comprising a plurality of codewords and parity for the plurality of codewords from the received data based on a first code on a physical layer; Determining whether each of the symbols is error based on a Log-Likelihood Ratio (LLR) value for each of the symbols in the transport block; Performing a transport block cyclic redundancy check (CRC) on the transport block; Erasing at least one symbol determined as an error when the transport block CRC fails; And recovering, on the upper layer, the erase marked at least one symbol based on a second code and the parity, wherein the parity is exclusive of bits in the same position of the plurality of codewords.
  • XOR may be composed of a series of bits generated by the operation.
  • a terminal for transmitting and receiving signals; And a processor configured to control the transceiver, the processor receiving data from a transmitting end, the plurality of codewords and the plurality of codes from the received data based on a first code on a physical layer.
  • LLR Log-Likelihood Ratio
  • parity can be used to recover error rate bits.
  • FIG. 1 illustrates an encoding process according to an example.
  • FIG. 2 illustrates an encoding process of a transport block according to an example.
  • FIG 3 illustrates a Recursive Systematic Convolutional (RSC) encoder according to an example.
  • FIG 5 shows an example of a trellis according to an RSC encoder.
  • FIG. 6 shows an example of a trellis structure.
  • FIG. 7 illustrates a structured parity check matrix, according to one example.
  • FIG. 8 illustrates a model matrix according to an example.
  • 9 is a diagram for explaining transformation of a matrix according to the number of shifts.
  • FIG. 10 is a flowchart illustrating an LDPC code decoding method according to an example.
  • FIG. 11 illustrates a bipartite graph, according to one example.
  • FIG. 13A illustrates processing of error data in accordance with the UDP protocol.
  • 13B illustrates processing of error data according to the UDP-lite protocol.
  • 15 illustrates encoding using single parity, according to an example.
  • 16 illustrates decoding using single parity according to an example.
  • 17 is a flowchart of a decoding method according to an embodiment of the present invention.
  • FIG. 18 is a configuration diagram of a base station and a terminal according to an embodiment of the present invention.
  • CDMA code division multiple access
  • FDMA frequency division multiple access
  • TDMA time division multiple access
  • OFDMA orthogonal frequency division multiple access
  • SC-FDMA single carrier frequency division multiple access
  • CDMA may be implemented with a radio technology such as Universal Terrestrial Radio Access (UTRA) or CDMA2000.
  • TDMA may be implemented with wireless technologies such as Global System for Mobile communications (GSM) / General Packet Radio Service (GPRS) / Enhanced Data Rates for GSM Evolution (EDGE).
  • GSM Global System for Mobile communications
  • GPRS General Packet Radio Service
  • EDGE Enhanced Data Rates for GSM Evolution
  • OFDMA may be implemented in a wireless technology such as IEEE 802.11 (Wi-Fi), IEEE 802.16 (WiMAX), IEEE 802-20, Evolved UTRA (E-UTRA), or the like.
  • UTRA is part of the Universal Mobile Telecommunications System (UMTS).
  • 3rd Generation Partnership Project (3GPP) long term evolution (LTE) employs OFDMA in downlink and SC-FDMA in uplink as part of Evolved UMTS (E-UMTS) using E-UTRA.
  • LTE-A Advanced is an evolution of 3GPP LTE.
  • FIG. 1 illustrates an encoding process according to an example.
  • the encoding process of FIG. 1 may be applied to many channel codes including a turbo code used in an LTE communication system.
  • a turbo code used in an LTE communication system.
  • the encoding process will be described based on terms according to standard documents of the LTE communication system.
  • the transmitting end may generate a transport block (TB) (S101).
  • the transmitting end adds a CRC bit for the transport block to the transport block (S102).
  • the transmitter may generate a code block from the transport block to which the CRC bit is added (S103).
  • the transmitting end may segment the transport block into code blocks based on the input size of the encoder.
  • the transmitter may add a CRC bit to each divided code block (S104). In this case, for example, the size of the code block and the code block CRC bits may consist of 6144 bits.
  • the transmitter may perform encoding and modulation (S105) on each block composed of a code block and CRC bits. For example, as described above, turbo coding may be applied.
  • the decoding process may be performed in the reverse order of the encoding process of FIG. 1.
  • the receiver may decode each code block by using a decoder corresponding to each encoder, and finally configure one transport block to check whether the CRC passes through the transport block.
  • the size of the input symbol may be different from the size of a transport block (TB) from the Media Access Control (MAC) layer. If the size of the transport block is larger than the maximum input symbol size of the turbo code, the transport block may be divided into a plurality of code blocks (CBs). According to the standard of the LTE communication system, the size of the code block may be the same as subtracting the Cyclic Redundancy Check (CRC) bit from 6144 bits.
  • An input symbol of a turbo code may be defined as data comprising a code block and a CRC or data including a transport block (eg, a transport block is less than 6144 bits) and a CRC. The CRC bit is a very small value (e.g.
  • a code block may refer to a code block itself or a CRC bit corresponding to a code block
  • a transport block refers to a transport block itself or a CRC bit corresponding to a transport block. can do.
  • FIG. 2 illustrates an encoding process of a transport block according to an example.
  • FIG. 2 illustrates an encoding process of the transport block 201 corresponding to the encoding process described above with reference to FIG. 1.
  • a transport block CRC 202 is added to the transport block 201.
  • the transport block CRC 202 may be used for identification of the transport block 201 in the decoding process.
  • the transport block 201 and transport block CRC 202 are then divided into three code blocks 203.
  • the code block 203 is divided into three code blocks, but the transport block 201 may be divided into a plurality of code blocks based on an input size of the encoder 205.
  • Code block CRC 204 is added to each code block 203.
  • the code block CRC 204 may be used for identification of the code block 203 at the receiving end.
  • Code block 203 and code block CRC 204 may be encoded via encoder 205 and modulator 206.
  • FIG 3 illustrates a Recursive Systematic Convolutional (RSC) encoder according to an example.
  • the RSC encoder 300 of FIG. 3 may be used for turbo coding.
  • m denotes input data
  • C1 denotes a systematic bit string
  • C2 denotes a coded bit string.
  • the RSC encoder 300 has a 1/2 code rate.
  • RSC encoder 300 may be configured by feeding back the encoded output to the input of a nonrecursive-non-systematic convoluational encoder.
  • the encoder 300 includes two delayers 301 and 302.
  • the values D of the delayers 301 and 302 may be determined according to a coding scheme.
  • Delays 301 and 302 may be configured as memory or shift registers.
  • the coding scheme of the LTE turbo encoder 400 is a parallel concatenation with two eight-state element encoders 410 and 420 and one turbo code internal interleaver 430.
  • Parallel Concatenated Convolutional Code (PCCC) is a parallel concatenation with two eight-state element encoders 410 and 420 and one turbo code internal interleaver 430.
  • Parallel Concatenated Convolutional Code (PCCC) is a parallel concatenation with two eight-state element encoders 410 and 420 and one turbo code internal interleaver 430.
  • PCCC Parallel Concatenated Convolutional Code
  • the turbo encoder 400 is composed of a first constituent encoder 410, a second element encoder 420, and a turbo code internal interleaver 430.
  • the first element encoder 410 and the second element encoder 420 are eight-state element encoders.
  • Each of the first element encoder 410 and the second element encoder 420 has a structure similar to that of the RSC encoder of FIG. 3.
  • the first element encoder 410 and the second element encoder 420 each include three delayers 411, 412, 413, 421, 422, and 423.
  • D is a value determined according to a coding scheme.
  • c k is the input to the turbo encoder 400.
  • the outputs from the first element encoder 410 and the second element encoder 420 are denoted as z k and z ' k , respectively.
  • the value output from the turbo code internal interleaver 430 is denoted by c ' k .
  • the delays 411, 412, 413, 421, 42, and 423 may delay the input value by one clock.
  • the delays 411, 412, 413, 421, 42, 423 may be configured to delay the input value for more than one clock according to the internal setting.
  • the delays 411, 412, 413, 421, 42, and 423 may be configured as shift registers, and may be configured to delay the input bits by a predetermined clock and then output the input bits to the next delays 411, 412, 413, 421, 42, 423. .
  • the turbo code internal interleaver 430 may reduce the effects of burst errors that may occur when transmitting signals over a wireless channel.
  • the turbo code internal interleaver 430 may be a Quadratic Polynomial Permutation (QPP) interleaver.
  • QPP Quadratic Polynomial Permutation
  • Turbo codes are high performance forward error correction (FEC) codes and are used in LTE communication systems.
  • a data block coded by turbo code may consist of three subblocks.
  • One subblock may correspond to m-bit payload data.
  • Another subblock may consist of n / 2 bits of parity bits for the payload, calculated using a recursive systematic convolution (RSC) code.
  • the remaining sub-blocks may be composed of n / 2 bits of parity bits for permutation of payload data, calculated using an RSC code.
  • the above-described permutation may be performed by an interleaver.
  • two subblocks of parity bits different from each other with the payload may be configured as one block. For example, if m is equal to n / 2, one block has a code rate of 1/3.
  • a process of reaching the input bit z k by the input c k may be divided into two paths.
  • the two paths are a first path connected without input feedback from the input to the output and a second path fed back from the input to the input.
  • c k is input, input via a delay unit 411, a rough input c k, and the retarder (411, 412, and 413), c k is applied to the output stage.
  • the relationship between the input end and the output end of the first path may be expressed by a polynomial.
  • the polynomial for the first path is called a forward generator polynomial and may be expressed as g1 of the following equation.
  • a rough input c k is fed back to the input end.
  • the polynomial for the second path is called a recursive generator polynomial and can be expressed as g0 in the following equation.
  • Equations 1 and 2 "+” means exclusive OR (XOR), and 1 means that the input goes through 0 delays.
  • D n means that the input goes through n delays.
  • FIG 5 shows an example of a trellis according to an RSC encoder.
  • FIG. 5 shows the configuration of the trellis of the RSC encoder shown in FIG.
  • S i represents a state of the i th input data.
  • each circle represents each node.
  • the line between each node means a branch.
  • the solid line refers to the branch for input value 1
  • the dotted line refers to the branch for input value 0.
  • the value on the branch is expressed as m / C1C2 (input value / systematic bit, coded bit). It may also have a state that is exponentially proportional to the number of memories of the encoder. For example, if the encoder includes a memory, 2 a states can be included in the trellis.
  • Trellis is a state machine that shows the possible state transitions of an encoder between two states.
  • a convolutional encoder such as an RSC encoder, may perform encoding according to a trellis diagram. Codewords encoded by the RSC encoder may be decoded according to an algorithm based on the trellis structure. For example, Viterbi or BCJR (Bahl, Cocke, Jelinek and Raviv) algorithms can be used.
  • FIG. 6 shows an example of a trellis structure.
  • n represents the length of a codeword.
  • trellis can be terminated by adding additional bits after the input sequence.
  • a sequence consisting of a sequence of zeros is called a tail bit. The tail bit terminates the trellis so that nodes in one state of the trellis have a value of zero.
  • the length of a codeword may be determined in consideration of the length k of input data and the length t of tail bits.
  • the length n of the codeword may have a value of (k + t) / R.
  • the length t of the tail bits can be determined as the length by which all delays (eg, memories) of the encoder can be reset.
  • the RSC encoder of FIG. 3 may use a total of 2 bits of tail bits.
  • the turbo encoder of the LTE communication as shown in FIG. 4 may use 3 bits of tail bits.
  • the tail bit has a relatively short length compared to the length of the input data.
  • code rate loss due to the tail bits may occur when the length of the codeword is limited.
  • trellis termination using tail bits is widely used. This is because the computational complexity is low and the error correction performance is excellent.
  • a puncturing code is a method of puncturing some of codewords.
  • some codewords are not transmitted because some of the codewords are punctured.
  • puncturing codes may be used to reduce code rate loss due to the addition of tail bits.
  • the receiving end may decode by using the trellis corresponding to the sum of the length k of the input data and the length t of the tail bit. That is, the receiver may perform decoding on the assumption that it has received a non-punctured codeword. In this case, the receiving end may assume that there is no input value for the branch from the node corresponding to the punctured bit (ie, the bit not transmitted at the transmitting end). That is, input data is assumed to be 0 or 1 with equal probability for branches of the node.
  • the CRC for the code block is added to the code block.
  • the CRC may be determined as the remainder derived after dividing the data to be transmitted using a preset check value as a divisor.
  • the CRC can generally be added at the end of the transmission data.
  • the receiving end may compare the remainder obtained by dividing the received data by a predetermined check value with the CRC or determine whether the remainder obtained by dividing the received data by the check value for the entire received data including the CRC is 0.
  • the size of the transport block is 6144 bits
  • the size of the CRC may be configured up to 24 bits. Therefore, the remaining bits except the CRC bit are determined as the size of the code block.
  • the receiving end may perform decoding in units of code blocks. Thereafter, the receiving end may configure the transport block from the code block, and determine success of decoding by checking the CRC for the transport block.
  • codeblock CRC is used for early decoding termination. For example, when a CRC check for one code block fails, the receiving end may transmit a negative acknowledgment (NACK) to the transmitting end without decoding the remaining code blocks.
  • NACK negative acknowledgment
  • the transmitting end may retransmit at least part of the transmission data. For example, the transmitting end may retransmit a transport block or one or more code blocks. For example, when retransmitting the entire transport block, excessive radio resources may be consumed for retransmission. Also, for example, when a NACK occurs due to a code block CRC failure at the receiver, the receiver may transmit information (eg, an index of a code block) of the code block at which the CRC failure occurs to the transmitter. In addition, the transmitting end may increase the radio resource efficiency by transmitting only the code block in which the CRC failure occurs using the information of the code block. However, when the number of code blocks is increased, the amount of data for feeding back the information of the code blocks (for example, the index of the code blocks) is increased.
  • the receiving end may inform the transmitting end of whether data reception was successful by using an ACK / NACK signal.
  • ACK / NACK for data received in the i-th subframe is transmitted in the i + 4th subframe.
  • retransmission may be performed in the i + 8th subframe. This takes into account the time for processing the transport block and the time for ACK / NACK generation. This is because the channel code processing for the processing of the transport block takes a lot of time.
  • the ACK / NACK and retransmission subframes are based on the processing of the transport block and the time for uplink ACK / NACK generation and uplink subframe allocation (for example, TDD uplink / downlink configuration). This can be determined.
  • ACK / NACK bundling and multiplexing may be used.
  • the turbo code has no further error rate improvement over a certain SNR.
  • a low-density parity-check (LDPC) code has been proposed.
  • the LDPC code is a linear block code, which is used in IEEE 802.11n, 802.11ac and Digital Video Broadcasting (DVB).
  • the LDPC code may be composed of a generation matrix and a parity check matrix.
  • data may be encoded through a product operation on message bits and a generation matrix.
  • a parity check matrix may be used instead of a generation matrix. For example, encoding of data may be performed using a parity check matrix.
  • the linear block code may be generated based on the generation matrix G or the parity check matrix H.
  • the linear block code is coded so that for every codeword c, Hc t has a value of zero.
  • the LDPC code may also be performed by checking whether the product of the parity check matrix H and the codeword c becomes '0' like other linear block codes. For example, the decoding of the LDPC code may be performed by determining whether the product (ie, Hc t ) of the transpose matrix and the parity check matrix of the codeword c is 0.
  • the parity check matrix is defined in a non-systematic form, and a uniform weight is applied to the rows and columns of the parity check matrix. The weight may mean the number of 1s included in a row or column.
  • the density of nonzero elements on the parity check matrix H of the LDPC code is low.
  • the LDPC code has a low decoding complexity and performance close to Shannon's theoretical limit. Due to the high error correction performance and low decoding complexity of the LDPC code, the LDPC code has characteristics suitable for high speed wireless communication.
  • the parity check matrix H may be used to generate the LDPC code.
  • the H matrix contains many zeros and one less.
  • the size of the H matrix may be 10 5 bits or more, and a lot of memory may be consumed to represent the H matrix.
  • the elements of the H matrix may be represented as sub-blocks of constant size, as shown in FIG. In FIG. 7, each element of the matrix H represents one subblock.
  • the size of the memory for representing the H matrix can be reduced by marking the subblocks with one integer index.
  • Each subblock may be, for example, a constant size permutation matrix.
  • FIG. 8 illustrates a model matrix according to an example.
  • the model matrix used for LDPC code encoding / decoding is shown in FIG. 8.
  • the model matrix may mean a parity check matrix composed of at least one subblock described below.
  • a sub block may be referred to as a shift number in the following description.
  • the model matrix may be extended to a parity check matrix based on the method described below. Therefore, encoding and decoding based on a specific model matrix means encoding and decoding based on a parity check matrix generated from an extension of the corresponding model matrix.
  • an index '-1' represents a zero matrix of a predetermined size.
  • the index '0' represents an identity matrix of a predetermined size.
  • Positive integer indices except '-1' and '0' represent the number of shifts.
  • the sub block represented by the index of '1' may mean a matrix shifted once in a specific direction from the unit matrix.
  • 9 is a diagram for explaining transformation of a matrix according to the number of shifts.
  • FIG. 9 illustrates a case in which the size of the sub block has four rows and four columns.
  • the subblock is shifted three times to the right from the unit matrix.
  • the parity check matrix of the code of the structured LDPC may indicate a sub block using an integer index of '3'.
  • encoding of the LDPC code may be performed by generating a generation matrix G from the parity check matrix H and encoding the information bits using the generation matrix.
  • Gaussian reduction is performed on the parity check matrix H to form a matrix of the form [P T : I].
  • the matrix P is a matrix in which the number of rows is k and the number of columns is nk
  • I is an identity matrix of size k.
  • the generation matrix G has the form [I: P T ].
  • the encoded information bits may be represented by a matrix x of one row k columns.
  • codeword c is xG
  • xG has the form [x: xP].
  • x represents an information part (or a systematic part)
  • xP represents a parity part.
  • the H matrix into a special structure without using Gaussian elimination, it is also possible to code information bits directly from the H matrix without inducing the matrix G. From the structures of the H matrix and the G matrix described above, the product of the transpose matrix of the matrix G and the matrix H has a value of zero. Using this feature and the relationship between the information bits and codewords described above, a codeword can be obtained by adding a parity bit after the information bits.
  • FIG. 10 is a flowchart illustrating an LDPC code decoding method according to an example.
  • codeword c is represented by codeword c 'which includes noise at the receiving end.
  • the receiver performs demultiplexing and demodulation on the received signal (S1000) and initializes decoding parameters (S1005).
  • the receiver updates check nodes and variable nodes (S1010 and S1015) and performs syndrome checks (S1020). That is, by checking whether c'H T is 0, the decoding procedure may be terminated.
  • the first k bits in c ' may be determined as information bits x. If c'H T is not 0, the information bit x may be recovered by finding c 'where c'H T satisfies 0 based on a decoding technique such as a sum-product algorithm.
  • FIG. 11 illustrates a bipartite graph, according to one example.
  • nodes on the left represent variable nodes
  • nodes on the right represent check nodes.
  • a binary graph is shown around the variable node v 0 and the check node c 1 for illustrative purposes.
  • the connecting line of the binary graph of FIG. 11 may be referred to as an edge.
  • the binary graph of FIG. 11 can be generated from Hc t .
  • the edge from variable node v 0 corresponds to one column of parity check matrix H and the edge from check node c 1 corresponds to one row of matrix H.
  • the product of the parity check matrix H and the transpose matrix of the codeword matrix c must have a value of '0'. Therefore, the value of variable nodes connected to one check node should be zero. Therefore, in FIG. 11, the exclusive OR (XOR) of the values of the variable nodes (v 0 , v 1 , v 4 , v 6 , v 9 , v 11 ) connected to the check node c 1 is' It must be 0 '.
  • Syndrome check means to check whether the value of the variable nodes connected to each check node is exclusive OR.
  • Turbo code can provide error correction performance that is close to Shannon's theoretical limit while having a relatively simple structure. However, if the signal exceeds a specific signal-to-noise ratio (SNR), further improvement of the decoding performance is insignificant. That is, the turbo code tends to generate an error-floor above a certain SNR.
  • SNR signal-to-noise ratio
  • two methods can be considered. For example, it may be considered to use code that does not generate an error-floor compared to current turbo code. Also, for example, concatenate code may be used by adding overhead to the current turbo code.
  • a concatenation code For example, as an example of a concatenation code, a Repeat-Accumulate (RA) code may be used. 12 is an example of an RA code encoder.
  • a concatenation code, such as an RA code is a simple form of processing between two encoders (e.g., Repetition Code 1201 and Accumulator 1203) and encoders (e.g., Permutation 1202) may be implemented.
  • the RA code encoder may repeat the data a predetermined number of times and replace the repeated data by the substitution matrix.
  • the substitution may be performed by the interleaver.
  • the accumulator may perform encoding by accumulating information in the data.
  • the RA code has similar performance as the turbo code but with significantly lower complexity.
  • the overall performance may be improved as the number of concatenated codes increases, and as each individual performance of the concatenated codes is excellent.
  • the RA code may be applied to the current turbo code.
  • a turbo code with a code rate higher than that of the currently set LTE communication system is used, and a complex and high performance code (for example, Reed-) is used instead of the RA code.
  • Solomon code may apply.
  • FIG. 13A shows processing of error data according to the UDP protocol
  • FIG. 13B shows processing of error data according to the UDP-lite protocol.
  • UDP-Lite Lightweight User Datagram Protocol
  • the payload is discarded.
  • the payload is transferred to an upper layer of the physical layer using a partial checksum, with some symbols in the payload being in error.
  • UDP-Lite may be suitable for such a multimedia data transmission system.
  • 3GPP's MBMS Multimedia Broadcast Multicast Services
  • MBMS Multimedia Broadcast Multicast Services
  • A-FEC application layer-forward error correction
  • Raptor Raptor code.
  • the raptor code is a fraction code with linear time encoding and decoding.
  • the raptor code encodes a message consisting of k symbols into a potentially limitless sequence of encoding symbols. The probability that an encoded message can be recovered is closer to 1 as more than k symbols are received.
  • the raptor cord can be formed by the concatenation of two kinds of cords.
  • a fixed rate erase code is applied as "pre-code” or "outer code".
  • the outer code may be formed by concatenation of multiple codes.
  • the high density parity check code of 3GPP may be derived from a binary gray sequence concatenated with a simple regular low density parity check code.
  • the outer code may be derived from the concatenation of the low density parity check code and the Hamming code.
  • the inner code may have the form of a LT (Luby Transform) code.
  • Each encoding symbol can be generated by performing an Exclusive-OR (XOR) operation on a pseudo-randomly selected set from the output of the outer code.
  • XOR Exclusive-OR
  • Raptor code can be decrypted by two approaches.
  • the inner code is first decoded using a trust propagation algorithm. Decoding succeeds if enough symbols are recovered so that the outer code can recover the remaining symbols.
  • the relationship of symbols defined by both inner and outer code is considered.
  • an edge between the packet 1410 to be recovered and the packet 1420 received from the transport layer is shown.
  • the number of edges of each received packet 1420 may be referred to as a degree.
  • decoding starts from a received packet of degree 1. The decoding process is repeated until all packets are restored or there are no nodes of order 1.
  • Protocols using CRC including conventional UDP protocols, etc., discard the entire packet if the packet fails a checksum due to some error symbol in the packet. Therefore, especially in the physical layer, using a checksum may be inefficient when the error symbol in the packet is small.
  • data in a communication system may have a smaller payload size than multimedia data.
  • a CRC bit may be inserted in units of one transport block.
  • the size of information discarded due to a CRC error is at least one transport block. Therefore, the application of the error correction code in the upper layer may be valid only when the payload in the upper layer is divided into a large number of transport blocks. For example, if the payload size consists of 1024 transport blocks, even if some transport blocks are discarded, an error correction code at the higher layer may be applied. However, for example, if the payload size consists of two transport blocks, the application of the error correction code at the higher layer would be meaningless because one half of the payload data is deleted when one transport block is discarded. Can be.
  • the error correction code may be valid when there are more than the appropriate number of symbols.
  • meaningful results can be obtained when the input size is about 1000 bits (up to 6144 bits) or more.
  • the error correction code in the physical layer is processed in units of bits, one symbol may be regarded as composed of one bit. Therefore, when the payload is composed of many transport blocks in order to increase the efficiency of the error correction code in the upper layer, the error correction in the lower layer (for example, the physical layer) because the size of each transport block is smaller. The efficiency of the code can be reduced.
  • One transport block may be divided into a plurality of code blocks. For example, it may be assumed that the error probability of each code block is relatively low. For example, in the case of the Ultra Reliable and Low Latency Communication (URLLC) scenario, the current LTE system's scheme of retransmitting the entire transport block due to CRC error may be inefficient. Therefore, in an environment where the error probability of the code block is sufficiently low, it may be more efficient to correct the error at the receiving end by adding a small overhead. For example, error correction may be attempted by adding parity.
  • a decoding scheme is proposed after transport block CRC processing, i.e., for the erase channel for the outer code. Decoding complexity may be reduced by performing error correction after the transport block CRC processing.
  • 15 illustrates encoding using single parity, according to an example.
  • the transport block TB is divided into m code blocks CB1, CB2,... CBm. Where m is one or more natural numbers.
  • the length of each code block may be K.
  • codewords CW1, CW2, ... CWm are generated.
  • zero-bit padding may be added so that each codeword CW1, CW2,... CWm has a length N.
  • CW1 may be added with 2 bits of zero-bit padding.
  • Zero-bit padding is performed so that all codewords have the same length N.
  • N may be set as the length of the codeword having the largest length or may be a predetermined length.
  • a single parity For all codewords CW1, CW2,... CWm having the same length N, a single parity can be generated. For example, one bit of parity may be generated by XORing bits of the same position of each codeword. For example, the first bit of parity may be generated by performing an XOR (ie, bit-wise XOR) operation on the first bits of all codewords CW1, CW2,... CWm.
  • XOR ie, bit-wise XOR
  • zero-bit padding may be performed for each codeword.
  • the length of the parity N may be determined by the transmitting end to the receiving end, or may be determined based on the codeword received by the receiving end.
  • 16 illustrates decoding using single parity according to an example.
  • the parity described above with reference to FIG. 15 may be transmitted to the receiving end together with the codewords.
  • the receiving end may attempt to correct the errored codeword based on parity. For example, as shown in FIG. 16, each bit of CW2 may be recovered by performing an XOR operation on the codewords other than CW2 and each bit of parity.
  • parity may be generated through an XOR operation on some codewords.
  • a first parity is generated through an XOR operation on all codewords
  • a second parity is generated through an XOR operation on odd codewords
  • a third parity is generated through an XOR operation on even codewords. May be generated.
  • Codewords for generating a plurality of parity may be selected according to a selection preset rule.
  • the transmitting end may inform the receiving end of information about the selected codewords.
  • the receiving end may perform zero-bit padding on the codewords so that the length of the codeword is N.
  • the codeword may be preset between the transmitter and the receiver having a length N, or the transmitter may inform the receiver, or the receiver may determine based on the length of the received codewords.
  • N may be the length of the longest codeword of the codewords.
  • likelihood ratio may be used.
  • LLR Log Likelihood Ratio
  • b represents a modulated bit value at the transmitter
  • z represents a received bit.
  • the additive white Gaussian noise (AWGN) channel has a probability density function as shown in the following equation.
  • Equation 1 can be simplified by using the Euclidean distance of the received bit and the modulated bit.
  • the channel code decoding error in the physical layer may be determined based on the LLR as shown in Equation (1). For example, when the transmitting end transmits a bit corresponding to '+1', the receiving end may determine whether the receiving bit is an error according to the following equation.
  • P (E) means the error probability, and as a result, the probability that the following equation holds.
  • an error due to a physical layer channel code may be recognized using Equation 6.
  • the transport block may be delivered to a higher layer along with a bit position recognized as an error using the above equation.
  • the CRC may identify an error in the transport block, but the CRC may not identify the exact bit in which the error occurred.
  • a threshold a value below the threshold may be considered an error. For example, when the threshold is set to ⁇ (where ⁇ is a zero or more real number), the determination of the error may be performed through the following equation.
  • the error probability for the input value can be determined as in Equation 7. For example, when the value of Equation 7 is less than ⁇ , it may mean that the distance between '+1' and '-1' with respect to the value of the input signal does not have a large difference. Therefore, this may mean that the error probability is higher than that of ⁇ or more.
  • Equation 7 is summarized using Equation 4, where Equation 7 is the difference between the Euclidean distance between the input signal and the average value of +1 and the Euclidean distance between the input signal and the average value of -1. It can be seen that the case is less than the threshold value.
  • SNR signal-to-noise ratio
  • 17 is a flowchart of a decoding method according to an embodiment.
  • the receiving end may decode data received from the transmitting end in the order of FIG. 17.
  • the receiving end may decode the transport block on the physical layer based on the first code (S1701).
  • the receiving end marks (S1702) a bit having an LLR value below a threshold value among the decoded transport blocks.
  • the LLR value may be calculated based on at least one of Equations 3 to 7 described above. Bits with LLR values below a predetermined threshold are likely to be errors. Thus, bits with LLR values below a predetermined threshold are marked for decoding in the upper layer.
  • the CRC may be performed only for the header. If the CRC check is successful, the data is decoded based on the second code on the upper layer (S1704).
  • the marked bit is erased and information about the position of the erased bit is transmitted to the upper layer (S1705).
  • the cleared bit is treated as an "unknown" value rather than a value of zero or one.
  • Data is decoded (S1706) based on the information on the position of the erased bit on the upper layer and the second code. For example, a codeword in which a code block CRC fails may be classified as a codeword to be restored.
  • the above-described parity can be used for data recovery with LLR-based bit erasure.
  • the code block when a code block is recovered using a CRC and parity for a code block, the code block can be restored only when an error existing in the transport block is equal to or less than the number of parity.
  • bit erasure based on LLR when bit erasure based on LLR is performed, restoration may be performed even when an error exceeding the number of parity exists.
  • erasure marking is performed on bits that are less than or equal to a threshold value based on Equation 7 described above.
  • the CRC for the code block fails as described above, the corresponding codeword is classified as a codeword for recovery.
  • the success or failure of the restoration is determined by the number and position of the erase-marked bits in the codewords for the restoration. For example, n (n is one or more natural numbers) parity may be provided to the receiving end. Recovery can be successful if the number of erase marked bits present in one bit position in the codewords is n or less.
  • code block CRC for three codewords may fail, and one parity may be provided.
  • the first bit of the first codeword may be erased
  • the third bit of the second codeword may be erased
  • the fifth bit of the third codeword may be erased.
  • all bits erased using parity can be recovered.
  • the erased bits may be recovered using the Massage Passing restoration as described above.
  • the erased bits may be recovered using, for example, Maximum Likelihood Restoration.
  • CRC successful bits may be used preferentially. Thereafter, of the bits of the CRC failed codeword, bits that are not erased marked may be used for recovery.
  • whether the restoration is successful may be confirmed through a CRC check. If the restoration is successful, the receiving end may transmit an acknowledgment (ACK) to the transmitting end.
  • ACK acknowledgment
  • NACK Negative Acknowledgment
  • ACK / NACK is generated based on whether the restoration is successful, but ACK / NACK may be generated based on different criteria described later.
  • a CRC generated in a bit-wise manner may be used.
  • a CRC for the first bits of each codeword, a CRC for the second bits, and the like may be delivered to the receiving end. Therefore, if such a CRC is present, the receiving end can check the CRC immediately after decoding / recovering for each bit. If the CRC for each bit fails, the receiving end may stop further decoding / recovery, generate a NACK, and send the NACK to the transmitting end.
  • the receiving end may stop decoding and transmit a NACK to the transmitting end.
  • the ACK / NACK is checked by checking the CRC for the corresponding codeword. May be generated.
  • ACK / NACK may be generated by checking only the CRC for the transport block instead of the CRC for each codeword, or both the codeword and the CRC for the transport block.
  • early termination may be considered to reduce the decoding complexity. If early termination is determined, the receiving end may terminate decoding and transmit a NACK. Early termination can lead to parity or early retransmission of data.
  • an early termination may be determined based on the number of CRC failed code blocks. For example, an early termination may be determined when the number of CRC failed code blocks exceeds the number of parity. In addition, when the LLR value is used as described above, if the number of erase-marked bits or the number of CRC failed code blocks exceeds the number of parity, an early termination may be determined.
  • the receiving end may determine an early termination.
  • the receiving end may request the new end parity. For example, the receiving end may attempt to decode all transport blocks without premature termination. The receiving end may determine the number of parities required for recovery based on the CRC and / or erasure marking, and may feed back the determined number of parity to the transmitting end.
  • FIG. 18 is a diagram for schematically describing a configuration of devices to which the embodiments of the present invention described with reference to FIGS. 1 to 17 may be applied.
  • the base station apparatus 10 may include a receiving module 11, a transmitting module 12, a processor 13, a memory 14, and a plurality of antennas 15. .
  • the transmission module 12 may transmit various signals, data, and information to an external device (eg, a terminal).
  • the reception module 11 may receive various signals, data, and information from an external device (eg, a terminal).
  • the receiving module 11 and the transmitting module 12 may be referred to as transceivers.
  • the processor 13 may control the overall operation of the base station apparatus 10.
  • the plurality of antennas 15 may be configured according to, for example, a two-dimensional antenna arrangement.
  • the processor 13 of the base station apparatus 10 may be configured to receive channel state information according to examples proposed by the present invention.
  • the processor 13 of the base station apparatus 10 performs a function of processing information received by the base station apparatus 10, information to be transmitted to the outside, and the like. And may be replaced by a component such as a buffer (not shown).
  • the terminal device 20 may include a receiving module 21, a transmitting module 22, a processor 23, a memory 24, and a plurality of antennas 25.
  • the plurality of antennas 25 refers to a terminal device that supports MIMO transmission and reception.
  • the transmission module 22 may transmit various signals, data, and information to an external device (eg, a base station).
  • the reception module 21 may receive various signals, data, and information from an external device (eg, a base station).
  • the receiving module 21 and the transmitting module 22 may be referred to as transceivers.
  • the processor 23 may control operations of the entire terminal device 20.
  • the processor 23 of the terminal device 20 may be configured to transmit channel state information according to examples proposed by the present invention.
  • the processor 23 of the terminal device 20 performs a function of processing the information received by the terminal device 20, information to be transmitted to the outside, etc., and the memory 24 stores the calculated information and the like for a predetermined time. And may be replaced by a component such as a buffer (not shown).
  • terminal device 10 may be implemented so that the above-described matters described in various embodiments of the present invention can be applied independently or two or more embodiments are applied at the same time, overlapping description will be described for clarity Omit.
  • a downlink transmission entity or an uplink reception entity is mainly described using a base station
  • a downlink reception entity or uplink transmission entity is mainly described using a terminal as an example.
  • the scope of the present invention is not limited thereto.
  • the description of the base station is a cell, an antenna port, an antenna port group, an RRH, a transmission point, a reception point, an access point, a repeater, or the like as a downlink transmission entity to a terminal or an uplink reception entity from a terminal.
  • the repeater becomes a downlink transmission entity to the terminal or an uplink reception entity from the terminal, or when the repeater becomes an uplink transmission entity to the base station or a downlink reception entity from the base station,
  • the principles of the present invention described through various embodiments may be equally applied.
  • Embodiments of the present invention described above may be implemented through various means.
  • embodiments of the present invention may be implemented by hardware, firmware, software, or a combination thereof.
  • a method according to embodiments of the present invention may include one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), and Programmable Logic Devices (PLDs). It may be implemented by field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, and the like.
  • ASICs Application Specific Integrated Circuits
  • DSPs Digital Signal Processors
  • DSPDs Digital Signal Processing Devices
  • PLDs Programmable Logic Devices
  • FPGAs field programmable gate arrays
  • processors controllers, microcontrollers, microprocessors, and the like.
  • the method according to the embodiments of the present invention may be implemented in the form of a module, a procedure, or a function that performs the functions or operations described above.
  • the software code may be stored in a memory unit and driven by a processor.
  • the memory unit may be located inside or outside the processor, and may exchange data with the processor by various known means.
  • each component or feature is to be considered optional unless stated otherwise.
  • Each component or feature may be embodied in a form that is not combined with other components or features. It is also possible to combine some of the components and / or features to form an embodiment of the invention.
  • the order of the operations described in the embodiments of the present invention may be changed. Some components or features of one embodiment may be included in another embodiment or may be replaced with corresponding components or features of another embodiment. It is obvious that the claims may be combined to form an embodiment by combining claims that do not have an explicit citation relationship in the claims or as new claims by post-application correction.
  • Embodiments of the present invention can be applied to various wireless access systems and broadcast communication systems.
  • various radio access systems include 3rd Generation Partnership Project (3GPP), 3GPP2 and / or IEEE 802.xx (Institute of Electrical and Electronic Engineers 802) systems.
  • Embodiments of the present invention can be applied not only to the various radio access systems, but also to all technical fields to which the various radio access systems are applied.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

L'invention concerne un procédé de décodage d'un code de correction d'erreurs sur la base d'un ratio de probabilité et de la parité. Un procédé de décodage de données selon un mode de réalisation de la présente invention peut être configuré pour : déterminer, sur la base d'un ratio de probabilité (LLR), un symbole d'erreur par rapport à un bloc de transport décodé sur la base d'un premier code ; et, si un CRC par rapport au bloc de transport échoue, à récupérer le symbole d'erreur sur la base de la parité.
PCT/KR2017/002439 2016-06-10 2017-03-07 Procédé de décodage de code de correction d'erreurs sur la base d'un canal d'effacement binaire présentant un ratio de probabilité, et dispositif associé WO2017213329A1 (fr)

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