WO2017113358A1

WO2017113358A1 - Universal interface of programmable logic block array edge and chip

Info

Publication number: WO2017113358A1
Application number: PCT/CN2015/100261
Authority: WO
Inventors: 刘成利
Original assignee: 京微雅格（北京）科技有限公司
Priority date: 2015-12-31
Filing date: 2015-12-31
Publication date: 2017-07-06
Also published as: CN107430672B; CN107430672A

Abstract

Provided are a universal interface of a programmable logic block (PLB) array edge and a chip. A multiplexer is disposed at an input terminal of a feedback line of a PLB array edge. One branch of an output terminal of the feedback line is used to directly output an output, and another branch of the output terminal of the feedback line is used to input an input to an input terminal of the multiplexer. By disposing a multiplexer at an input terminal of a feedback line of a PLB array edge, an interface between the PLB array edge and a dedicated module can provide more connecting lines than connecting lines provided by an Xbar module, and a PLB and the dedicated module can be connected without needing an Xbar module, thereby eliminating an Xbar module and saving an area occupied by the Xbar module in a chip. Moreover, delay and power consumption of the chip are reduced. In addition, a dedicated module is not restricted to be placed on the left and right sides of a PLB array, and can be placed at any location around the PLB array.

Description

Universal interface and chip for programmable logic block array edge

Technical field

The invention relates to the field of integrated circuit design technology in the field of microelectronics, in particular to a universal interface and chip of a programmable logic block array edge.

Background technique

Field Programmable Gate Array (FPGA) is a logic device with rich hardware resources, powerful parallel processing capability and flexible reconfigurability. These features make FPGAs more and more widely used in many fields such as data processing, communication, and network.

FIG. 1 is a schematic diagram of a connection between a general interface and a dedicated interface of a prior art programmable logic block array edge. As shown in FIG. 1, a programmable logic block (PLB) includes a basic logic unit LE (Logic Element) and a connection resource Xbar of a logic unit; each LE includes four logical slices LP (Logic Parcel); an IP module. It is a dedicated module in the FPGA chip. When the PLB array edge common interface is connected to the IP module, it needs to be connected to the IP module through an Xbar module; and the Xbar module has only 24 input (Input) and 56 output (Output) lines.

As the function of the FPGA chip increases, more and more interfaces between the required PLB array and the IP module are connected, and the number of input and output lines of the xbar connected to the PLB array cannot meet the requirements. Moreover, in the current interface connection mode, the Xbar module must be connected to the IP module, which occupies more chip area; the delay is also increased; the power consumption of the chip is also increased.

At present, there is no interface method between the general interface and the IP module capable of solving the edge of the PLB array.

Summary of the invention

The purpose of the present invention is to provide a general-purpose interface and chip for the edge of a programmable logic block array according to the defects of the prior art; the interface does not need to be connected to the IP module through the Xbar module, and the Xbar module is omitted, thereby saving the chip. Area; the universal interface through the edge of the PLB array is directly connected to the interface of the dedicated module, reducing the delay and reducing the power consumption of the chip.

A first aspect of the present invention provides a general interface of a programmable logic block array edge, a multiplexer is disposed at a feedback line input end of the programmable logic block array edge; and a branch of the output end of the feedback line is directly output Its other branch is input to one input of the multiplexer.

Preferably, the multiplexer is a 2-to-1 multiplexer.

Preferably, the universal interface of the edge of the programmable logic block array is connected to a dedicated module, which includes a central processing unit CPU module, a hard logic Logic hard core module, a universal serial bus USB module, and a double rate synchronous dynamic random. Memory DDR module, serial high speed input and output SERDES module and input and output IO module.

Preferably, the general interface of the edge of the programmable logic block array is located on the upper and lower sides of the edge of the programmable logic block array.

Preferably, the general purpose interface of the programmable logic block array edge is located on the left and right sides of the edge of the programmable logic block array.

Preferably, the feedback line of the edge of the programmable logic block array includes an embedded memory EMB, a digital signal processor DSP, a local memory LRAM, and a feedback line of the programmable logic block.

A second aspect of the present invention provides an FPGA chip comprising a general purpose interface of a programmable logic block array edge as described above.

By providing a multiplexer at the input end of the PLB array edge feedback line, the common interface of the PLB array edge can provide more connections, and the PLB array and the dedicated module no longer need to be connected through the Xbar module, saving The Xbar module saves the chip area; it also reduces latency and chip power consumption.

DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention, Those skilled in the art can also obtain other drawings based on these drawings without paying any creative work.

1 is a schematic diagram of a connection between a general interface and a dedicated interface of a prior art programmable logic block array edge;

2 is a schematic diagram of a feedback line of a programmable logic block array edge in a prior art chip;

3 is a schematic diagram of feedback lines on the left and right edges of the programmable logic block array of the prior art;

4 is a schematic diagram of a feedback line of the upper and lower edges of the programmable logic block array of the prior art;

5 is a schematic diagram of a feedback line on the left and right edges of a programmable logic block array according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a feedback line on the upper and lower edges of a programmable logic block array according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. It is a partial embodiment of the invention, and not all of the embodiments.

The following is a description of an embodiment of the present invention with reference to FIG. 2. FIG. 2 is a schematic diagram of a feedback line of a programmable logic block array edge in a prior art chip. As shown in FIG. 2, taking the PLB in the upper left corner of the figure as an example, on the left side and above, there are TIE lines, and the TIE is divided into O lines, T lines, M lines, and Q lines. There are 8 sets of O lines across 8 adjacent PLBs; 4 sets of T lines across 4 adjacent PLBs; 4 sets of M lines across 4 adjacent PLBs; Q lines across 12 adjacent PLBs have 1 group.

Now describe the TIE line. The TIE line is also called the interconnect line. In the FPGA chip, when the PLB is placed with any adjacent module, the TIE line in the PLB will be connected to the port line of the adjacent module. . Therefore, in the PLB array, each PLB is connected to a module such as an adjacent PLB or EMB through a TIE line.

The TIE line is in the PLB array. The xbar winding resource in the PLB spans a plurality of adjacent PLBs and is then fed back into the PLB of the edge of the PLB array to form a feedback line. The xbar winding resources mentioned here span and run through the interior of multiple PLBs.

The feedback line is now described. At the edge of the PLB array, there are ports for output to the outside of the PLB array, ports for input to the PLB array; and the output port is connected to its own input port, which is called a feedback line. The function of the feedback line is to make the entire PLB array form a complete whole. Any TIE line has the same drive, the same load, and the same winding capability.

When the general interface of the edge of the PLB array is connected to the IP module interface, the feedback effect of the TIE line disappears; when the IP module is not used, the TIE line constitutes the feedback line.

It should be noted that, FIG. 2 is a schematic diagram of a cross-PLB, and only a part of the feedback line is given as an illustration. The feedback line at the edge of the PLB array is connected to the dedicated module via the Xbar module. Moreover, in the prior art, the edge of the PLB array can only be connected to the dedicated module through the Xbar module on the left and right sides, thereby limiting the shape of the chip.

Dedicated modules, ie IP modules, include: central processing unit CPU module, hard logic Logic hard core module, universal serial bus USB module, double rate synchronous dynamic random access memory DDR module, serial high speed input and output SERDES module and input and output IO Modules are not listed here.

An explanation is given to the IP of the FPGA chip. The IP (Intellectual Property) kernel module is a pre-designed or even verified integrated circuit, device or component with certain certain functions. It comes in several different forms. The IP core module has different levels of behavior, structure, and physical design, corresponding to the "soft IP core" that mainly describes the functional behavior, and the "solid IP" that describes the structure. The "firm IP core" and the "hard IP core" based on physical description and process verification are three levels. This is equivalent to the design techniques of blanks, semi-finished products and finished products of integrated circuits (devices or components).

The common interface of the edge of the PLB array in the prior art will be described by taking FIG. 3 as an example. FIG. 3 is a schematic diagram of the feedback lines of the left and right edges of the programmable logic block array of the prior art. The figure shows the number of interfaces on the left and right sides of the programmable logic block. The O line has 8 lines per group, the T line has 4 lines in each group, the M line has 4 lines in each group, and the Q line has 12 lines in each group. In the figure, the PLB array and the IP module must be connected by the winding resource Xbar module; the Xbar takes the right side as an example, only 56 output Outputs, and 24 input inputs can be used by the IP module.

It should be noted that the PLB array is omitted in the figure, and only one PLB of the PLB array is used as a schematic diagram.

Obviously, when the left and right sides of the PLB in the chip need to be connected to the IP module, the Xbar module cannot provide enough winding resources when the demand for the connection is greater than the connection provided by one Xbar module.

4 is a schematic diagram of a feedback line on the upper and lower edges of the programmable logic block array of the prior art. As shown in FIG. 4, the upper and lower sides of the PLB array in the chip are the same as those on the left and right sides of the chip, and are not described herein again.

In the embodiment of the present invention, a general interface of the edge of the programmable logic block array is provided with a multiplexer at the input end of the feedback line of the edge of the programmable logic block array; a branch of the output end of the feedback line is directly outputted, Its other branch is input to one input of the multiplexer.

Specifically, FIG. 5 is used as an example for description. FIG. 5 is a schematic diagram of the feedback lines on the left and right edges of the programmable logic block array according to an embodiment of the present invention. As shown in FIG. 5, the multiplexer is a 2-to-1 multiplexer.

In the figure, the output of the feedback line is directly output by one branch, and the other branch is input to the multiplexer mux of 2 to 1. At the input, the other input of the mux provides a connection to the IP module.

It should be noted that the function of the feedback line still exists, which is output from the output end of the feedback line and input from the input end of the feedback line. When the mux is not added, these TIE lines have only feedback function; after adding the mux, these TIE lines have selectivity. That is, the TIE line can be selected as the feedback line, the input port can be selected to connect the line of the IP module, or the line directly connected to the output port; the output port can be directly connected to the line of the IP module, or can be connected via the mux to the input port. To achieve the feedback line function. Compared with the prior art, the feedback line provides a way for the output to be directly connected to the IP module, and after adding a mux to the input end of the feedback line, the input from the external IP module is increased.

In the embodiment of the present invention, the feedback line is disconnected, and then a mux is added to the input end of the feedback line, and the feedback line can be used to use the xbar in the PLB within 12 columns of the edge of the PLB array. Therefore, embodiments of the present invention can provide more lines to be connected to the IP module.

A 2-to-1 mux is given in the embodiment of the present invention, but the invention is limited thereto. The multiplexer can be N-selected and N is an integer greater than one.

Obviously, a multiplexer is added to the feedback line of the PLB array. The interface between the PLB array and the IP module does not need to pass through the winding resource Xbar module, but is directly connected. And the number of external interfaces of each side of each PLB in the PLB array is 8 lines of O lines, 8 lines of each group; 4 groups of T lines, 4 lines of each group; 4 groups of M lines, 4 pieces of each group; Q Line 1 group, 12 in each group; that is, the line on each side of the PLB is 108.

That is to say, each PLB in the PLB array has 108 TIE lines on each side, that is, 108 ports on each side; PLBs inside the PLB array can be docked with each other, forming on the edge of the PLB array. The feedback line.

As shown, the input and output of the feedback line are corresponding. That is, each side of each PLB can provide 108 input and output lines. Obviously, the number of connections that can be provided is much larger than the number of lines that the wire resource Xbar module can provide. The PLB array is omitted in the figure, and only one PLB of the PLB array is used as a schematic diagram.

It should be noted that in the prior art, the feedback line of the PLB array always exists, but is limited to the 56 input inputs and 24 output outputs that can be provided by the Xbar module, and these lines cannot be connected to the IP module.

When the interface is located on the upper and lower sides of the programmable logic block, it will be described with reference to FIG. 6. FIG. 6 is a schematic diagram of a feedback line on the upper and lower edges of a programmable logic block array according to an embodiment of the present invention.

The feedback lines on the upper and lower sides of the chip are the same as those on the left and right sides, and will not be described here.

By providing a multiplexer at the input end of the edge feedback line of the PLB array, the universal interface of the edge of the PLB array can provide more connections, and the PLB and the dedicated module no longer need to be connected by Xbar, saving Xbar. The module saves the area of the chip; it also reduces the latency and power consumption of the chip. And the dedicated module is no longer placed on the left and right sides of the edge of the programmable logic block array, and can be placed anywhere around the programmable logic block array, so the FPGA chip can make more shapes.

A person skilled in the art should further appreciate that the elements and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both, in order to clearly illustrate hardware and software. Interchangeability, the composition and steps of the various examples have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods for implementing the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present invention.

The steps of a method or algorithm described in connection with the embodiments disclosed herein can be implemented in hardware, a software module executed by a processor, or a combination of both. The software module can be placed in random access memory (RAM), memory, read only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or technical field. Any other form of storage medium known.

The specific embodiments of the present invention have been described in detail with reference to the preferred embodiments of the present invention. All modifications, equivalent substitutions, improvements, etc., made within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims

A general-purpose interface for an edge of a programmable logic block array, characterized in that a multiplexer is provided at a feedback line input end of the edge of the programmable logic block array; a branch of the output end of the feedback line is directly outputted, Another branch is input to one input of the multiplexer.
The interface of claim 1 wherein said multiplexer is a 2-to-1 multiplexer.
The interface of claim 1 wherein the general purpose interface of the programmable logic block array edge is coupled to a dedicated module, the dedicated module comprising a central processing unit CPU module, a hard logical Logic hard core module, a universal serial Bus USB module, double rate synchronous dynamic random access memory DDR module, serial high speed input and output SERDES module and input and output IO module.
The interface of claim 1 wherein the general purpose interface of the edge of the programmable logic block array is located on the upper and lower sides of the edge of the programmable logic block array.
The interface of claim 1 wherein the common interface of the edges of the programmable logic block array is located on the left and right sides of the edge of the programmable logic block array.
The interface of claim 1 wherein the feedback line of the programmable logic block array edge comprises an embedded memory EMB, a digital signal processor DSP, a local memory LRAM, and a feedback line of the programmable logic block.
An FPGA chip characterized by comprising a universal interface of programmable logic block array edges as claimed in any of claims 1-6.