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WO2017166109A1 - Amplificateur à faible bruit - Google Patents

Amplificateur à faible bruit Download PDF

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Publication number
WO2017166109A1
WO2017166109A1 PCT/CN2016/077832 CN2016077832W WO2017166109A1 WO 2017166109 A1 WO2017166109 A1 WO 2017166109A1 CN 2016077832 W CN2016077832 W CN 2016077832W WO 2017166109 A1 WO2017166109 A1 WO 2017166109A1
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WO
WIPO (PCT)
Prior art keywords
transistor
coupled
gate
output node
noise
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Application number
PCT/CN2016/077832
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English (en)
Chinese (zh)
Inventor
张科峰
刘览琦
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武汉芯泰科技有限公司
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Publication date
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Priority to PCT/CN2016/077832 priority Critical patent/WO2017166109A1/fr
Publication of WO2017166109A1 publication Critical patent/WO2017166109A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements

Definitions

  • the present invention relates to the field of wireless communication transceiver technologies, and in particular, to a low noise amplifier.
  • the processed first-stage amplifier (low-noise amplifier, English abbreviated LNA) needs to have characteristics such as wideband, high gain, high linearity, low noise, and impedance matching.
  • the LNA is required to output a differential signal.
  • the LNA is the first stage in which the chip is connected to the antenna, which acts to amplify the antenna signal.
  • the useful signal in the communication band is amplified by the low noise amplifier, and the noise generated by the wireless spatial channel is suppressed by the gain of the amplifier, and the added noise of the amplifier itself is very small, so that the useful signal is amplified without affecting Its quality.
  • the various types of interference from the wireless spatial channel will produce signal intermodulation, which will be suppressed by the good linear performance of the amplifier.
  • the LNAs currently on the market are mainly divided into two categories: one is the differential input differential output type LNA.
  • this structure When this structure is matched with the antenna, it needs to connect a single-ended to differential transformer, which is improved in disguise. Cost; the other is a single-ended input, differential output LNA, this LNA needs no external transformer, and the noise-cancellation structure can eliminate the noise of one transistor at the input (the main source of noise), but this structure There is often a problem that the output impedance differential end is unbalanced.
  • the LNAs currently on the market are mainly divided into the following two categories: one is the use of off-chip inductors for impedance matching, but this scheme adds off-chip passive components, and often makes the LNA work in a narrow band.
  • the other is to use the source input impedance characteristics of the transistor to form a common gate tube matching.
  • This matching can achieve good results in the frequency band of several GHz, but due to the crystal
  • the transconductance requirements of the body tube are strict, which greatly limits the gain performance of the LNA.
  • the technical problem to be solved by the present invention is to provide a low noise amplifier for the compromise between the characteristics of impedance matching, low noise, high linearity, impedance balance, and high gain of the LNA in the background art.
  • the technical solution adopted by the present invention to solve the technical problem thereof is to construct a low noise amplifier, including:
  • a matching amplifier stage circuit comprising: an input node, a first transistor, a second transistor, a first output node, and a second output node; a source of the first transistor coupled to the input node, a drain coupled to the An output node to convert a noise current at the input node to a first noise voltage of the first output node; a gate of the second transistor coupled to a source stage of the first transistor, a drain thereof Coupled to the second output node to convert a noise current at the input node to a second noise voltage of the second output node; summing the second noise voltage with the first noise voltage to Eliminating the noise of the first transistor;
  • a gain boosting stage circuit comprising: a first pair of transistors and a second pair of transistors coupled to the first pair of transistors; the first pair of transistors being coupled to the first output node and the second output node, respectively
  • the current polarity of the first pair of transistors and the second pair of transistors is determined to suppress noise of the second transistor.
  • the first pair of transistors includes:
  • a third transistor having a gate coupled to the first output node
  • a fourth transistor having a gate coupled to the second output node.
  • the second pair of transistors includes:
  • a fifth transistor having a gate coupled to a gate of the third transistor, a second derivative of a transconductance of the fifth transistor being opposite to a second derivative of a transconductance of the third transistor;
  • a sixth transistor having a gate coupled to a gate of the fourth transistor, a second derivative of a transconductance of the sixth transistor being opposite a second derivative of a transconductance of the fourth transistor.
  • the gain boosting stage circuit further includes a first capacitor and a second capacitor; the first capacitor is coupled to a gate of the third transistor and a gate of the fifth transistor Extreme The second capacitor is coupled between a gate of the fourth transistor and a gate of the sixth transistor.
  • the gain boosting stage circuit further includes a first resistor and a second resistor; the first resistor is coupled to a drain of the third transistor, and the second resistor is coupled to The drain of the fourth transistor.
  • the first transistor is a common gate transistor and the second transistor is a common source transistor.
  • the matched amplification stage circuit further includes:
  • a common gate resistor coupled to a drain of the first transistor
  • the matched amplifier stage circuit further includes an input capacitor coupled between the source stage of the first transistor and the gate of the second transistor.
  • the matched amplifier stage circuit further includes an off-chip inductor coupled to the source stage of the first transistor.
  • the low noise amplifier disclosed above has the following beneficial effects: by adopting a noise canceling structure in the matching amplifier stage of the preceding stage, the broadband impedance matching is realized while ensuring the minimization of the first stage noise, thereby improving the noise of the overall LNA. Performance; in the gain-enhancing stage of the latter stage, a multi-transistor multiplexing structure is adopted. Since it is a symmetrical structure, the output impedance of the differential terminal is balanced. This structure eliminates the nonlinearity caused by gain boost while increasing the overall gain. At the same time, since the weak inversion transistor is in the latter stage of the LNA, the noise introduced is negligible. On the whole, such a technical solution effectively improves the noise performance and gain performance of the LNA circuit without deteriorating its linear performance.
  • FIG. 1 is a functional block diagram of a low noise amplifier provided by the present invention
  • FIG. 2 is a schematic structural diagram of a low noise amplifier provided by the present invention.
  • FIG. 3 is a schematic diagram of the principle of eliminating the second derivative of the transconductance provided by the present invention.
  • FIG. 1 is a functional block diagram of a low noise amplifier provided by the present invention.
  • the low noise amplifier comprises two stages, a matching amplification stage and a gain improvement stage.
  • the matching amplifier stage adopts the common gate input matching and noise cancellation structure, which realizes broadband matching of LNA, single-ended to differential conversion and extremely low noise performance.
  • the gain boosting stage provides a positive gain, which improves the overall LNA gain, and solves the problem that the matching amplifier stage has low gain due to common-gate matching.
  • the gain boost stage two NMOS transistors operating in the weak inversion region are used, and their increased third-order nonlinear current polarity is opposite to that of the amplifier transistor of the stage, thereby canceling each other, thereby eliminating the non- Linearity issues, so this stage provides both gain and excellent linear performance.
  • FIG. 2 is a schematic structural diagram of a low noise amplifier 100 according to the present invention.
  • the low noise amplifier 100 includes a matching amplifier stage circuit 1 and a gain boost stage circuit 2.
  • the matching amplifier circuit 1 First, the matching amplifier circuit 1
  • the matching amplifier stage circuit 1 includes an input node 10, a first transistor 11, a second transistor 12, a first output node 13, and a second output node 14; a source stage of the first transistor 11 is coupled to the input node 10 (ie An antenna impedance) having a drain coupled to the first output node 13 to convert a noise current at the input node 10 to a first noise voltage of the first output node 13; A gate coupled to a source stage of the first transistor 11 and a drain coupled to the second output node 14 to convert a noise current at the input node 10 to a second of the second output node 14 a noise voltage; forming a differential signal with the first noise voltage by the second noise voltage to cancel noise of the first transistor 11; specifically, the first transistor 11 is a common gate transistor (M1), the second The transistor 12 is a common source transistor (M2).
  • the matched amplifier stage circuit 1 further includes an input capacitor 17, an off-chip inductor 18, a common gate resistor 15 (R CG ), and a common source resistor 16 (R CS ).
  • a common gate resistor 15 is coupled to the drain of the first transistor 11; a common source resistor 16 is coupled to the drain of the second transistor 12.
  • the input capacitor 17 is coupled between a source stage of the first transistor 11 and a gate of the second transistor 12.
  • the off-chip inductor 18 is coupled to a source stage of the first transistor 11.
  • the parameters in the matching amplifier stage circuit 1 are as follows:
  • g m,CS input transconductance of the common source transistor M2;
  • V n,in the equivalent of the noise voltage generated by M1 at its source
  • V n, CG the equivalent noise voltage of M1 at the output (drain);
  • V n,CS the equivalent noise voltage of M2 at the output (drain);
  • a v, CG M1 amplification gain of the signal
  • a v, CS M2 amplification gain of the signal.
  • the matching amplifier stage is formed by combining a common gate input transistor M1 and a common source input transistor M2.
  • the input impedance of the common-gate input transistor can be regarded as the reciprocal of its transconductance, that is, 1/g m, CG , and the apparent antenna impedance is R S , so that only the two are equal, impedance matching can be achieved over a relatively wide frequency range. , which is
  • the principle of converting a single-ended signal to a differential signal is as follows: First, for a signal input from the antenna impedance R S to the source of M1, the signal is considered to be a small signal current i in , and the small signal current will pass through M1. The load of M1 flows through R CG . According to Kirchhoff's current law, the input small signal current is calculated as:
  • the low noise principle is to use the common source transistor M2 to amplify the noise Vn at the source end of the M1 to generate noise having the same phase and the same amplitude as the M1 drain terminal, that is, the R CG , so that the noise can cancel each other out in the output differential signal.
  • M1 is a transistor in the first stage, it amplifies the signal, so this part of the noise is eliminated, which will greatly benefit the low noise design of the LNA. This process needs to meet some conditions.
  • the noise current generated by M1 flows from R CG to R S at the antenna end. This noise current will generate noise voltage at the source and drain of M1, respectively.
  • V n,in 1/2 ⁇ i n ⁇ R s ;
  • V n, CG -1/2 ⁇ i n ⁇ R CG .
  • V n,in is amplified via the gate of M2. According to equation (3), this noise voltage is amplified as:
  • Equations (2), (3), and (4) can be converted into:
  • the noise voltage generated by M1 is in phase and amplitude is one. Since the differential signal is subtracted from the signal at both ends, in differential signal transmission, this noise is cancelled out during the subtraction due to the phase amplitude, and the noise of M1 is completely eliminated. It is worth noting that since M1 and M2 are the amplifying transistors in the first stage, their noise has the greatest influence on the LNA. Eliminating the noise of M1 will greatly optimize the noise performance of the LNA.
  • the noise of M2 cannot be eliminated by this structure, but since the work of impedance matching is mainly done by M1, the size of M2 does not necessarily need to maintain a specific transconductance, so it is possible to increase the size of M2 ( That is, the transconductance is increased to suppress the noise of M2.
  • the load resistance R CS of M2 which causes the output impedance imbalance of the matching amplifier stage, which is solved by the second stage gain boost stage.
  • the gain boost stage circuit 2 includes a first pair of transistors 21 and a second pair of transistors 22 coupled to the first pair of transistors 21; the first pair of transistors 21 are coupled to the first output node 13 and the second, respectively
  • the output node 14 suppresses the noise of the second transistor 12 by setting the current polarity of the first pair of transistors 21 and the second pair of transistors 22.
  • the first pair of transistors 21 includes a third transistor 211 (M3) and a fourth transistor 212 (M4).
  • a gate of the third transistor 211 is coupled to the first output node 13; a gate of the fourth transistor 212 is coupled to the second output node 14.
  • the second pair of transistors 22 includes a fifth transistor 221 (M5) and a sixth transistor 222 (M6).
  • a gate of the fifth transistor 221 is coupled to a gate of the third transistor 211, a second derivative of the transconductance of the fifth transistor 221 is opposite to a second derivative of the transconductance of the third transistor 211;
  • the gate of the six transistor 222 is coupled to the gate of the fourth transistor 212, and the second derivative of the transconductance of the sixth transistor 222 is opposite to the second derivative of the transconductance of the fourth transistor 212.
  • the gain boosting stage circuit 2 further includes a first resistor 25 (Rout), a second resistor 26 (Rout), a first capacitor 23 and a second capacitor 24; the first capacitor 23 is coupled to the third transistor 211 Between the gate and the gate of the fifth transistor 221, the second capacitor 24 is coupled between the gate of the fourth transistor 212 and the gate of the sixth transistor 222.
  • the first resistor 25 is coupled to a drain of the third transistor 211, and the second resistor 26 is coupled to a drain of the fourth transistor 212.
  • the parameters in the gain boost stage circuit 2 are as follows:
  • g m ′′ the second derivative of the transconductance of the transistor.
  • IIP 3 Input Third Intercept Point inputs the third-order intercept point to characterize the linear performance of the circuit. The bigger the better.
  • M2 in Fig. 2 can change the size boost transconductance to suppress noise, its gain is still limited by M1 because it has to be kept the same size as M1. M1 needs to meet the impedance matching
  • the technique seeks an increase in gain at the gain boost stage and solves the problem of unbalanced output impedance of the matched amplifier stage.
  • the present invention introduces a multi-transistor multiplexing technique (MGTR) in the gain boosting stage, and uses an additional weak inversion transistor to eliminate the nonlinear current of the amplifying transistor.
  • MGTR multi-transistor multiplexing technique
  • M3 and M4 are amplifying transistors operating in the saturation region, while M5 and M6 are additional transistors operating in the weak inversion region (weak signal amplification).
  • the calculation of the third-order intercept point IIP 3 is:
  • M5 operate in the weak inversion region by introducing and M6 , a positive g m ", and the transistors M3 and M4 amplifying negative g m" cancel each other, eliminating third-order nonlinearity, such that the formula (6) radical in the denominator close to zero, greatly improved
  • the indicator level of IIP 3 is shown in Figure 3.
  • the input voltage is scanned for M3 to M6, and the second derivative transconductance g m "" at different input voltages is measured.
  • the figure shows the g m of the amplifying transistors M3 and M4 operating in the saturation region. "It is a negative value, and transistors M5 and M6 operating in the weak inversion region generate a positive value of g m ".
  • the combined equivalent g m " is close to 0 in the small signal range. (The curve in the figure near the middle portion), whereby, according to equation (6), the structure can increase the maximum IIP 3 value.
  • This structure also solves the problem of gain design. Since M3 and M4 work in the saturation region, the signal amplification is performed, and the gain of the signal is:
  • This gain can effectively compensate for the gain limitation of the previous matching amplifier stage due to the common-gate matching structure.
  • the technical solution creatively combines the noise canceling structure and the multi-transistor multiplexing structure. Potential. Because in the radio frequency wireless communication module, there is such a law: 1. The more the module in the former stage, the greater the influence of noise on the overall communication link, and the less the degree of influence on the linear performance of the link; In the latter stage, the linearity performance has greater influence on the overall communication link, and the impact on the noise performance of the link is smaller. 3. The gain improvement leads to the optimization of noise performance and the deterioration of linear performance.
  • the noise canceling structure is adopted, and the broadband impedance matching is realized while minimizing the noise of the first stage, thereby improving the noise performance of the overall LNA; in the gain boosting stage of the latter stage, A multi-transistor multiplexing structure, since it is a symmetrical structure, the output impedance of the differential terminal is balanced. This structure eliminates the nonlinearity caused by gain boost while increasing the overall gain. At the same time, since the weak inversion transistor is in the latter stage of the LNA, the noise introduced is negligible. On the whole, such a technical solution effectively improves the noise performance and gain performance of the LNA circuit without deteriorating its linear performance.
  • the technical solution solves the design challenges of impedance matching, impedance balance, noise performance, gain performance, and linear performance of the LNA circuit.
  • the prior art proposed in the background art employs a low gain design or a compensating design as in the first scheme when improving the linear performance of the LNA.
  • the technical solution introduces two PMOS transistors operating in the weak inversion region in the first stage, the noise generated by them will have a huge impact on the LNA.
  • the prior art proposed in the background art employs a noise canceling technique when improving the noise performance of the LNA.
  • This technique can achieve broadband matching at the same time, but its negative effect is that the gain design is pinched by the antenna impedance, which makes it difficult for the LNA to achieve higher gain, and in order to achieve output differential impedance balance, a buffer stage must be introduced. If you add a gain at the buffer level, it will have a large amount of nonlinear effects because the stage is at the back stage. If a structure with no gain or negative gain is used at the buffer level, it does not help to increase the inherently low circuit gain.
  • the scheme adopts a similar structure of the prior art sound canceling technology to ensure that the first stage having the greatest influence on noise can have the minimum noise and achieve broadband matching.
  • the second stage of the LNA a multi-transistor multiplexing structure is introduced, and output impedance balance, high gain, high linearity, etc. are achieved, and the noise of the introduced transistor is negligible due to the noise level in the second stage. .
  • the one or more operations may constitute computer readable instructions stored on one or more computer readable media, which are executed by an electronic device The line time will cause the computing device to perform the operation.
  • the order in which some or all of the operations are described should not be construed as implying that the operations must be sequential. Those skilled in the art will appreciate alternative rankings that have the benefit of this specification. Moreover, it should be understood that not all operations must be present in every embodiment provided herein.
  • the word "preferred” as used herein is intended to serve as an example, instance, or illustration. Any aspect or design described herein as “preferred” need not be construed as being more advantageous than other aspects or designs. Instead, the use of the word “preferred” is intended to present a concept in a specific manner.
  • the term “or” as used in this application is intended to mean an “or” or “an” That is, unless otherwise specified or clear from the context, "X employs A or B” means naturally including any one of the permutations. That is, if X uses A; X uses B; or X uses both A and B, then "X uses A or B" is satisfied in any of the foregoing examples.
  • Each functional unit in the embodiment of the present invention may be integrated into one processing module, or each unit may exist physically separately, or two or more units may be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or in the form of software functional modules.
  • the integrated modules, if implemented in the form of software functional modules and sold or used as stand-alone products, may also be stored in a computer readable storage medium.
  • the above mentioned storage medium may be a read only memory, a magnetic disk or an optical disk or the like.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
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Abstract

L'invention porte sur un amplificateur à faible bruit (LNA) qui comprend un circuit d'étage d'amplification d'adaptation (1) et un circuit d'étage d'amélioration de gain (2). Le circuit d'étage d'amplification d'adaptation comprend un premier transistor (11), un second transistor (12), un premier nœud de sortie (13) et un second nœud de sortie (14) ; une électrode de source du premier transistor (11) est couplée à une impédance d'antenne (10) et une électrode déversoir du premier transistor est couplée au premier nœud de sortie (13) ; une électrode de grille du second transistor (12) est couplée à l'électrode de source du premier transistor (11) et une électrode déversoir du second transistor est couplée au second nœud de sortie (14). Le circuit d'étage d'amélioration de gain comprend une première paire de transistors (21) et une seconde paire de transistors (22) couplés à la première paire de transistors (21) ; les transistors de la première paire (21) sont couplés respectivement au premier nœud de sortie (13) et au second nœud de sortie (14). L'amplificateur à faible bruit offre des effets bénéfiques en ce qui concerne l'obtention d'une adaptation d'impédance à large bande tout en garantissant la réduction à un minimum du bruit de premier étage, ce qui permet d'améliorer l'efficacité de bruit globale du LNA, d'obtenir l'équilibre des impédances de sortie d'une extrémité différentielle et d'éliminer la non-linéarité apportée par l'amélioration de gain.
PCT/CN2016/077832 2016-03-30 2016-03-30 Amplificateur à faible bruit WO2017166109A1 (fr)

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Cited By (9)

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CN110896300A (zh) * 2018-09-12 2020-03-20 武汉芯泰科技有限公司 一种宽带低噪声放大器
CN111371412A (zh) * 2020-03-16 2020-07-03 华东师范大学 一种工作于66～83GHz的CMOS毫米波宽带低噪声放大器
CN111987998A (zh) * 2020-08-19 2020-11-24 成都瑞迪威科技有限公司 一种噪声抵消低噪声放大器
CN112803899A (zh) * 2020-12-28 2021-05-14 东南大学 一种采用噪声抵消的无片内电感单转双的低噪声放大器
CN112968674A (zh) * 2021-01-28 2021-06-15 电子科技大学 一种低噪声放大器的双路噪声抵消电路
CN113904635A (zh) * 2021-10-12 2022-01-07 中国电子科技集团公司第二十四研究所 一种高三阶交调点的场效应晶体管射频放大器
CN114221624A (zh) * 2021-11-11 2022-03-22 华南理工大学 一种低噪声放大器及芯片
CN116346045A (zh) * 2023-03-21 2023-06-27 中山大学 基于噪声抵消与体偏置技术的超宽带低噪声放大器
CN119070755A (zh) * 2024-11-01 2024-12-03 成都瑞迪威科技有限公司 一种基于噪声相消结构的cmos超宽带低噪声放大器

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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110896300A (zh) * 2018-09-12 2020-03-20 武汉芯泰科技有限公司 一种宽带低噪声放大器
CN111371412B (zh) * 2020-03-16 2023-07-25 华东师范大学 一种工作于66～83GHz的CMOS毫米波宽带低噪声放大器
CN111371412A (zh) * 2020-03-16 2020-07-03 华东师范大学 一种工作于66～83GHz的CMOS毫米波宽带低噪声放大器
CN111987998A (zh) * 2020-08-19 2020-11-24 成都瑞迪威科技有限公司 一种噪声抵消低噪声放大器
CN111987998B (zh) * 2020-08-19 2024-02-02 成都瑞迪威科技有限公司 一种噪声抵消低噪声放大器
CN112803899A (zh) * 2020-12-28 2021-05-14 东南大学 一种采用噪声抵消的无片内电感单转双的低噪声放大器
CN112803899B (zh) * 2020-12-28 2023-10-03 东南大学 一种采用噪声抵消的无片内电感单转双的低噪声放大器
CN112968674A (zh) * 2021-01-28 2021-06-15 电子科技大学 一种低噪声放大器的双路噪声抵消电路
CN113904635B (zh) * 2021-10-12 2023-08-11 中国电子科技集团公司第二十四研究所 一种高三阶交调点的场效应晶体管射频放大器
CN113904635A (zh) * 2021-10-12 2022-01-07 中国电子科技集团公司第二十四研究所 一种高三阶交调点的场效应晶体管射频放大器
CN114221624A (zh) * 2021-11-11 2022-03-22 华南理工大学 一种低噪声放大器及芯片
CN114221624B (zh) * 2021-11-11 2024-03-26 华南理工大学 一种低噪声放大器及芯片
CN116346045A (zh) * 2023-03-21 2023-06-27 中山大学 基于噪声抵消与体偏置技术的超宽带低噪声放大器
CN119070755A (zh) * 2024-11-01 2024-12-03 成都瑞迪威科技有限公司 一种基于噪声相消结构的cmos超宽带低噪声放大器

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