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WO2017039583A1 - Utilisation d'un matériau sacrificiel pour compenser la variation de l'épaisseur dans des substrats microélectroniques - Google Patents

Utilisation d'un matériau sacrificiel pour compenser la variation de l'épaisseur dans des substrats microélectroniques Download PDF

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Publication number
WO2017039583A1
WO2017039583A1 PCT/US2015/047440 US2015047440W WO2017039583A1 WO 2017039583 A1 WO2017039583 A1 WO 2017039583A1 US 2015047440 W US2015047440 W US 2015047440W WO 2017039583 A1 WO2017039583 A1 WO 2017039583A1
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WO
WIPO (PCT)
Prior art keywords
sacrificial material
microelectronic substrate
microelectronic
back surface
forming
Prior art date
Application number
PCT/US2015/047440
Other languages
English (en)
Inventor
Chi-Mon CHEN
Yi Li
Tao Wu
Zheng Zhou
Islam A. Salama
Yueli LIU
Amruthavalli P. Alur
Nikhil Sharma
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2015/047440 priority Critical patent/WO2017039583A1/fr
Publication of WO2017039583A1 publication Critical patent/WO2017039583A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
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Definitions

  • Example 24 the subject matter of Example 19 can optionally include attaching an additional microelectronic device to the microelectronic substrate front surface.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

Cette invention concerne un boîtier microélectronique éventuellement fabriqué par la formation d'un substrat microélectronique présentant une surface avant et une surface arrière, le transfert de la variation de l'épaisseur dans le substrat micro-électronique vers la surface arrière du substrat microélectronique par la fixation de la surface avant du substrat microélectronique à un premier dispositif de fixation, la formation d'un matériau sacrificiel sur la surface arrière du substrat microélectronique présentant une première surface opposée à la surface arrière de substrat microélectronique, l'extraction du substrat microélectronique à partir du premier substrat, la fixation de la première surface du matériau sacrificiel à un second dispositif de fixation, et la fixation d'au moins un dispositif microélectronique à la surface avant du substrat microélectronique. Selon un autre mode de réalisation, une couche de anti-adhésive peut être disposée entre la surface arrière du substrat microélectronique et le matériau sacrificiel.
PCT/US2015/047440 2015-08-28 2015-08-28 Utilisation d'un matériau sacrificiel pour compenser la variation de l'épaisseur dans des substrats microélectroniques WO2017039583A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2015/047440 WO2017039583A1 (fr) 2015-08-28 2015-08-28 Utilisation d'un matériau sacrificiel pour compenser la variation de l'épaisseur dans des substrats microélectroniques

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2015/047440 WO2017039583A1 (fr) 2015-08-28 2015-08-28 Utilisation d'un matériau sacrificiel pour compenser la variation de l'épaisseur dans des substrats microélectroniques

Publications (1)

Publication Number Publication Date
WO2017039583A1 true WO2017039583A1 (fr) 2017-03-09

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080237810A1 (en) * 2007-03-29 2008-10-02 Gopalakrishnan Subramanian Controlling substrate surface properties via colloidal coatings
US20110037156A1 (en) * 2009-08-13 2011-02-17 Qualcomm Incorporated Variable Feature Interface That Induces A Balanced Stress To Prevent Thin Die Warpage
US20130099374A1 (en) * 2011-10-19 2013-04-25 SK Hynix Inc. Package of electronic device including connecting bump, system including the same and method for fabricating the same
US20140138823A1 (en) * 2012-11-21 2014-05-22 Nvidia Corporation Variable-size solder bump structures for integrated circuit packaging
US20140167255A1 (en) * 2012-12-17 2014-06-19 Princo Middle East Fze Package structure and package method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080237810A1 (en) * 2007-03-29 2008-10-02 Gopalakrishnan Subramanian Controlling substrate surface properties via colloidal coatings
US20110037156A1 (en) * 2009-08-13 2011-02-17 Qualcomm Incorporated Variable Feature Interface That Induces A Balanced Stress To Prevent Thin Die Warpage
US20130099374A1 (en) * 2011-10-19 2013-04-25 SK Hynix Inc. Package of electronic device including connecting bump, system including the same and method for fabricating the same
US20140138823A1 (en) * 2012-11-21 2014-05-22 Nvidia Corporation Variable-size solder bump structures for integrated circuit packaging
US20140167255A1 (en) * 2012-12-17 2014-06-19 Princo Middle East Fze Package structure and package method

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