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WO2017067842A1 - Système de commande pour communiquer avec des dispositifs connectés à un bus, et procédé de communication - Google Patents

Système de commande pour communiquer avec des dispositifs connectés à un bus, et procédé de communication Download PDF

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Publication number
WO2017067842A1
WO2017067842A1 PCT/EP2016/074587 EP2016074587W WO2017067842A1 WO 2017067842 A1 WO2017067842 A1 WO 2017067842A1 EP 2016074587 W EP2016074587 W EP 2016074587W WO 2017067842 A1 WO2017067842 A1 WO 2017067842A1
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WO
WIPO (PCT)
Prior art keywords
bus
sensor
type
luminaire
line
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Application number
PCT/EP2016/074587
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English (en)
Inventor
Jan Joost 'T HART
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Philips Lighting Holding B.V.
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Filing date
Publication date
Application filed by Philips Lighting Holding B.V. filed Critical Philips Lighting Holding B.V.
Publication of WO2017067842A1 publication Critical patent/WO2017067842A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/64—Hybrid switching systems
    • H04L12/6418—Hybrid transport

Definitions

  • This invention relates generally to the field of communications with devices over a bus, and more specifically to a controller that allows devices of different types to connect to the same bus.
  • a lighting system comprises a set of luminaires connected together over a network, for example a DALI network.
  • a lighting system comprises a set of luminaires connected together over a network, for example a DALI network.
  • additional (non-lighting) functionality at the luminaire such as movement detection (using a PIR sensor), remote control sensing (using an IR detector), temperature sensing etc. The luminaries then become part of an overall building lighting automation system.
  • the external connection typically comprises a bus, which provides a data communication channel and also provides the power supply for the locally connected device.
  • communications standard is used for the external connection port, all devices to connect to the port must also conform to that proprietary standard. Some communications standards command a price premium over others so it would be desirable to be able to use a lower level bus standard for simpler devices at a lower price, as well as the higher level bus standard for the more complicated devices.
  • I 2 C Inter-Integrated Circuit
  • I 2 C Inter-Integrated Circuit
  • I 2 C Intra Luminaire Bus
  • a device connects to each of the two communications wires on the bus, which are a serial data line (SDA) for the communication of data, and a serial clock line (SCL) for the control and synchronization of the communication of data between the devices.
  • SDA serial data line
  • SCL serial clock line
  • an I 2 C compliant device needs a microcontroller able to implement various functions.
  • the output of an I 2 C compliant device is configured as an open-collector/open-drain, and one or more pull-up resistors maintain a soft logic high value on the bus while the bus is in a quiescent state.
  • the device pulls the bus to a logic low value, via the open-collector/open-drain device that is placed in a conductive state to ground potential.
  • a device that is connected to an I 2 C bus is identifiable by an address, and can operate as either a transmitter or a receiver, or both.
  • Data transfers are effected using a master-slave communications protocol.
  • a master is a device that initiates a data transfer and generates the clock signals to permit the transfer; any device that is addressed is considered a slave for this transfer.
  • the data transfer can be initiated by a master to either transmit data to the slave (a write command), or to request data from the slave (a read command).
  • an output device such as an EEPROM memory for non-volatile storage is typically not able to initiate a data transfer, and therefore would be configured to only operate as a slave device.
  • a sensor on the other hand, may be configured to operate as either a master or a slave, as the situation demands.
  • both the SDA and SCL bus lines are in the logic-high state.
  • a master initiates a data transfer by asserting a transition to a logic-low state on the SDA line while the SCL line is high; this is termed a START condition. Thereafter, the master toggles the SCL line to control the synchronization of the data transfer; data value changes occur on the SDA line when the SCL clock is low, and the state of the SDA line is considered valid only when the SCL clock is high.
  • the data transfer for example comprises an address transmitted by the host (i.e. the device initiating the communication), nominally seven bits, followed by a read/write- not indicator. After transmitting the address and the direction of data transfer, the host releases the SDA line, allowing it to rise to a logic-high level. If a slave device recognizes its address, the slave device transmits an acknowledge signal (ACK) by pulling the SDA line low. The absence of a low signal when the host releases the SDA line, therefore, indicates a non- acknowledgement (NAK). If the address is acknowledged, via a low at SDA, the transmitting device transmits the data.
  • ACK acknowledge signal
  • NAK non- acknowledgement
  • the slave device is the transmitting device; if the direction is a "write” relative to the host, then the master device is the transmitting device.
  • the transmitting device releases control of the SDA line, and the receiving device acknowledges the receipt of the data by asserting a logic-low value on the SDA line. If the data is acknowledged, the transmitter sends additional data.
  • the master can subsequently reassert a START signal, and repeat the process above, or, can assert a STOP signal to terminate this data- transfer session.
  • This STOP signal is a low-to-high transition on the SDA line while the SCL clock is high. Thereafter, any device may assume control of the bus as a master by asserting a high-to-low transition on the SDA line, as above.
  • Examples in accordance with an aspect of the invention provide a controller for communicating with a device over a bus, the controller supporting a first, synchronized, communications protocol over the bus, wherein the bus lines comprise at least a data line for transferring data and a clock line for communicating timing information,
  • controller is adapted to: analyze a signal on the clock line;
  • the type of signal present on a clock line of the bus is used to determine the type of device with which communication is to be made.
  • One type is a device which operates using a clock signal, i.e. has a synchronized communications protocol, and the other type is a device which holds the clock line e.g. at ground and thus does not make use of a clock signal for communication.
  • the controller may therefore be adapted to detect a DC ground level on the clock line for a predetermined period as an indication that the device is of the second type. This period is a length of time which is not expected for devices of the first type.
  • the controller may be adapted to detect a transition on the clock line as an indication that the device is of the first type.
  • the first type of device is for example I 2 C compliant device and the protocol used for communication with a device of the first type is the I 2 C protocol.
  • the system enables the I 2 C communication standard to be used without modification.
  • the clock signal may be held at a logical 0 by an I 2 C compliant device when clock stretching occurs; hence, detecting a DC ground level on the clock line is equivalent to identifying an infinitely stretched clock signal. This may arise in an error situation even with a device of the first type connected, but this invention makes use of an assumption that a device of the second type is in fact connected, in which the clock line is deliberately held at ground.
  • the protocol used for communication with a device of the second type is for example a general purpose input/output protocol. This enables connection of a lower cost simple general purpose sensor device to the I 2 C bus.
  • the bus lines preferably further comprise a ground line and a power supply line.
  • Examples in accordance with another aspect of the invention provide a luminaire, comprising:
  • an external port to which an external device can be connected over a bus; and a control system as defined above, for communicating with the external device over the bus.
  • This aspect provides the control system in a luminaire, so that different types of external device can be connected to the luminaire.
  • the luminaire may further comprise the external device connected to the external bus port, wherein the external device comprises:
  • a temperature, humidity or light sensor a temperature, humidity or light sensor
  • different type of sensor may be connected to the luminaire, typically for extending the functionality of the lighting system, for example to provide automated control features in response to ambient conditions such as temperature, ambient light level, and presence or absence of occupants in the area which is illuminated.
  • the external device for example connects the clock line of the bus to ground.
  • This type of external device is of the second type, and does not need a clock signal to communicate.
  • the external device may comprise a power terminal connected to a power line of the bus, a ground terminal connected to a ground line of the bus and a data terminal connected to the data line of the bus, and wherein the ground terminal is also connected to the clock line of the bus.
  • Examples in accordance with another aspect of the invention provide a method for communicating with a device connected to a bus using a controller, wherein the bus lines comprise at least a data line for transferring data and a clock line for communicating timing information, the controller supporting a first, synchronized, communications protocol over the bus, the method comprising:
  • the device determines if the device is of a first type which is compliant with the first communications protocol or of a different second type; and communicating with the device using a communication protocol which depends on the type of device detected.
  • This method involves using a clock line as a mechanism for sensing a type of device connected to a communications bus.
  • the method may comprise: detecting a DC ground level on the clock line for a predetermined period as an indication that the device is of the second type; or
  • the first type of device is for example an I 2 C compliant device and the protocol used for communication with a device of the first type is the I 2 C protocol, and the protocol used for communication with a device of the second type is a general purpose input output protocol.
  • a power terminal of the device may be connected to a power line of the bus
  • a ground terminal of the device may be connected to a ground line of the bus
  • a data terminal of the device may be connected to the data line of the bus
  • the clock line of the bus may be coupled to the ground line.
  • the invention may be implemented in software at the main control system, e.g. the luminaire controller.
  • Fig. 1 is used to explain the I 2 C communication protocol briefly;
  • Fig. 2 is used to explain clock stretching in the I 2 C protocol;
  • Fig. 3 shows a luminaire with a connected device of a first type, and also shows a device of the second type;
  • Fig. 4 shows a first communications method
  • Fig. 5 shows a second communications method
  • Fig. 6 shows a computer which may be used to implement the required processing.
  • the invention provides a control system for communicating with a device over a bus, the control system supporting a first communications protocol over the bus which uses clocked communications.
  • the system has connection terminals for connection to lines of the bus, wherein the bus lines comprise at least a data line for transferring data and a clock line for communicating timing information.
  • a signal on the clock line is analyzed, and from the signal on the clock line, it is determined if the device is of a first type which is compliant with the first communications protocol or of a different second type. Communication with the device then using a communication protocol which depends on the type of device detected.
  • the type of signal present on a clock line of the bus is used to determine the type of device with which communication is to be made.
  • One type is a device which operates using a clock signal and the other type is a device which holds the clock line e.g. at ground and thus does not make use of a clock signal for communication.
  • the device which uses the first communications protocol is typically a more expensive type of device.
  • the system can communicate with other general purpose types of device based on analysis of the clock signal.
  • the invention will be described for a system which uses the I 2 C protocol as the first communications protocol. It is not sufficient simply to detect the presence of a regular clock as evidence of an I 2 C compliant device, because a non-regular clock may arise even for I 2 C compliant devices. In particular, the I 2 C protocol supports clock stretching.
  • the invention is based on on detection of a ground level as the clock signal. This could be caused by an infinitely long clock stretch on the I 2 C bus. However, it would require an I 2 C device in an error state to bring the bus into this condition.
  • the invention instead assumes that the error condition is not at hand. Even if this assumption happens to be wrong, the sensor function will simply not work (or be considered absent), which can then be discovered and reported on the network.
  • the I 2 C protocol will be explained further as well as the clock stretching function.
  • bus For operating a slave over the I 2 C, bus only six simple operating codes are required for transmitting or receiving bits of information. These operating codes are: the start bit; a slave address; a read/write bit which defines whether the slave is a transmitter or receiver; an acknowledge bit; message bits divided into 8-bit segments; and the stop bit.
  • the bus is not busy.
  • the start condition (discussed above) is needed from a master; and to release the lines, a stop condition (discussed above) is required.
  • the start condition is defined as a HIGH-to-LOW transition of the data line while the clock line is in a HIGH state.
  • the stop condition is defined as a LOW-to-HIGH transition of the data line while the clock line is in a HIGH state.
  • the master always generates the start and stop conditions. After the start condition, the bus is in the busy state. The bus becomes free after the stop condition. After a start condition one data bit is transferred during each clock pulse. The data must be stable during the HIGH-period of the clock. The data line can only change when the clock line is at a LOW level. Normally, each data transfer is implemented with 8 data bits and 1
  • the master generates the acknowledge clock pulse.
  • the transmitter releases the data line (SDA-HIGH) during the acknowledge clock pulse. If there was no error detected, the receiver will pull down the SDA line during the HIGH period of the acknowledge clock pulse.
  • a slave receiver If a slave receiver is not able to acknowledge, the slave will keep the SDA line HIGH and the master can then generate a STOP condition to abort the transfer. If a master receiver keeps the SDA line HIGH during the acknowledge clock pulse, the master signals the end of data transmission and the slave transmitter releases the data line to allow the master to generate a STOP-condition.
  • FIG. 1 shows a timing diagram for an I 2 C communication. Data transfer is initiated with a START bit 10 which is represented by SDA being pulled low while SCL stays high.
  • step 1 the SDA line sets the first data bit level while keeping SCL low.
  • the data is received when the SCL line rises in step 12 for the first bit.
  • the next bits are set and received in sequence (e.g. steps 13,14 and finally 15.16). Each time, the SDA line transitions while SCL is low, and the data is read while SCL is high.
  • Step 17 represents an acknowledgement ACK.
  • a STOP bit 18 is represented by the SDA line being pulled high while the SCL line is high.
  • the I 2 C bus protocol allows slower devices to stretch the clock at the bit level until they finish their transaction. Therefore, the slower device screens the clock signal SCL and if this signal is low it pulls down the clock signal SCL to stretch the clock pulse until the data is stable on the data lines.
  • a slave will perform bit level clock stretching if the clock speed as applied by the master is too high for the slave to cope with. Typically, the slave would need to apply this sort of clock stretching at every bit.
  • a clock stretch may also be implemented at the byte level. For example this may be needed if a byte has been successfully received but additional time is needed before the slave device is ready to receive the next byte. An example is shown after the
  • FIG 2 shows the clock stretching at the bit level, whereby the low phase of The stretch 20 is accomplished by the slave device, and the master detects this clock stretching so that the original clock sequence can be resumed once the clock (which was released by the master device at the start of the period 20) has gone high.
  • Figure 3 shows a luminaire 30 which comprises a control system for communicating with an external device 31 over a bus 32.
  • the luminaire has connection terminals 33 for connection to lines of the bus 32, wherein the bus lines comprise at least a data line SDA for transferring data, a clock line SCL for communicating timing information, a power line Vcc, for example 5V DC, and a ground line GND.
  • the connection terminals 33 for example together form an RJ-1 1 connector.
  • the luminaire 30 is in preferred examples for implementing the I 2 C bus protocol, but as explained above it may implement other clocked communications protocols.
  • the luminaire 30 comprises a light source 34, such as an LED array, a light source driver circuit 36 such as an LED driver, and a controller 38.
  • a light source 34 such as an LED array
  • a light source driver circuit 36 such as an LED driver
  • the controller 38 enables the luminaire to communicate with other luminaires over a bus 39 so that the luminaire is part of a control system network.
  • the network allows luminaires to communicate and it allows remote upgrading of the luminaire control software, resident in the controller 38.
  • the controller 38 gives the luminaire intelligence. For example the the luminaire can, based on environmental conditions, autonomously change its light output.
  • the controller needs input from a sensing device, and this is the role of the external device 31.
  • a sensing device Depending on the system floor plan, only a subset of the luminaires may actually need a sensor function.
  • the other luminaires can function based on information that is coming to them from the network bus 39. If a sensing function is needed in a particular luminaire, the RJ-1 1 connector 33 is used to connect a sensing device during installation of the system.
  • the external device 31 for example comprises a so-called ILB (Intra
  • An ILB device has a local microcontroller and communicates using a protocol stack that uses a master-transmitter / slave-receiver I 2 C protocol in its transport layer.
  • a known luminaire has a standardized RJ-1 1 bus in the form of the I 2 C data and clock lines plus ground and sensor power supply.
  • the ILB protocol stack allows multiple (sensing) functions such as occupancy detection, temperature/light level/humidity measurement, infra-red remote control command reception. These make it a powerful and flexible system, but also a complex and expensive system.
  • the microcontroller and ILB mechanism is actually not needed and thus too expensive.
  • controller software update is acceptable, as this can be implemented even for already installed system.
  • hot plugin capability because in this particular application, the full network configuration is established at installation. If system configuration changes are needed, it is acceptable to require a system reboot.
  • the controller 38 implements the I 2 C (ILB) system for communication over the bus 32 as well as the network protocols for communicating over the bus 39.
  • the controller 38 is adapted to analyze a signal on the clock line SCL resulting from the connection of the external device 31 to the bus.
  • the controller can determine if the device is of a first type (which is an I 2 C compliant type in the preferred example) or of a different second type.
  • the communication with the device may then be selected to use a communication protocol which depends on the type of device detected.
  • the device 31 is shown an as I 2 C compliant device, and it has an I 2 C processor 40.
  • I 2 C compliant device For communication with an I 2 C compliant device, the standard protocol is used for the communication, without needing any modification.
  • the device 31 has input pins
  • the device 31 has a power terminal connected to the power line Vcc of the bus, a ground terminal connected to the ground line GND of the bus, a data terminal connected to the data line SDA of the bus and a clock terminal connected to the clock line SCL of the bus.
  • Figure 3 also shows an external device 41 of the second type.
  • the device 41 of the second type is a simple sensor which does not support the first protocol. Instead, it may for example simply provide sensor data to an output pin "Data".
  • An example is an infrared receiver (e.g. remote control receiver).
  • the data line SDA needs to be configured by the control system 30 as a general purpose input/output pin.
  • the device 41 has a power input pin which connects to the Vcc line of the bus 32, a ground pin which connects to the GND line of the bus 32 and a data output pin. This data output pin connects to the SDA data line. The device 41 does not need to receive an external clock signal.
  • the device 41 couples the ground line GND to the clock line SCL.
  • This may be an internal connection within the device as shown, but it may instead be made by an external connector, for example which provides a four-to-three coupling between four pins of the bus 32 and three output pins of the device 41.
  • a DC ground level is provided on the clock line SCL by the device 41.
  • a DC ground level may be interpreted by the controller 38 as infinite clock stretching, as will be understood from Figure 2, and this is interpreted as indicating that the device is not I 2 C compliant.
  • the data is received as if coming from an on-board sensor.
  • the controller software is updated to provide a local decoder for the output of the external device, using the SDA pin as as general purpose input output pin (GPIO). This means data can be received in an asynchronous and non-clocked manner.
  • GPIO general purpose input output pin
  • a monitor is implemented for monitoring the state of the SCL pin.
  • the monitoring takes place during a predetermined time period, for example 50ms. This time period is sufficient to exclude any expected amount of clock stretching of an I 2 C compliant device.
  • the controller detects a DC ground level on the clock line for a predetermined period as an indication that the device is of the second type; or it detects a transition on the clock line as an indication that the device is of the first type. The default is that the device is of the second type.
  • Figure 4 shows the method of determining the type of device from which communications are received over the bus. This example is for a method that is carried out at reboot of the controller.
  • step 44 the controller 38 is configured to receive data from both the clock and data lines, in the general purpose mode.
  • step 45 the signal on the clock line is analyzed. This takes place for a maximum time period T such as 50ms.
  • the time period T it is determined if there have been any transitions in the signal on the clock line, in step 46. Thus, it is determined if the clock line is a DC level or if there is information present. As soon as a transition is detected to a clock high, the monitoring can be terminated, so that the full duration is not needed in the case of a device of the first type. Thus, the time period T is a maximum time period.
  • a communicating device is of a first type in which clocked communication is employed (e.g. an I 2 C compliant device) or of a different second type (e.g. a simple sensor providing an output on the data line).
  • step 47 it is determined in step 47 that the device is of the second type and communication then takes place in step 48 using a general purpose communications protocol (which was already set in step 44). This is communication over a single wire system which is not explicitly clocked.
  • step 49 If a transition did arise (in which case the monitoring was terminated earlier than after time T), it is determined in step 49 that the device is of the first type and communication takes place in step 50 using the first protocol. This is communication over a two wire clocked system.
  • the devices which operate according to the first protocol i.e. the I 2 C devices, for example comprise sensors or other devices with some configurability over the two wire communication system, or devices which combine multiple functions.
  • the devices which can operate according to the second protocol i.e. a general purpose communication protocol, are those that require only single wire communication and for example do not need dynamic configurability.
  • protocol information may be encoded on the SCL line, of which a permanent LOW-state is only one of the many possible options, to allow detection of what alternate sensor type is connected from those that are available.
  • the detection routine (of Figure 4) to take place only at a reboot, which is carried out after a change in the system configuration. For example, in the case of a luminaire, there are not frequent dynamic reconfigurations.
  • the controller knows a few things. It may have a sensor connected. If so, it needs to take a decision how to service this sensor, but also it must be able to service this sensor within a certain time. This maximum time is the time period T. The longer the period T, the longer it may take for the system to be up and running but also the less chance of a clock stretch of an I 2 C device being misinterpreted.
  • a periodic test may be carried out for systems which are reconfigured in a more dynamic way.
  • a modified version of the routine of Figure 4 may be kept running indefinitely, as it then allows the controller to enter any mode at any time, corresponding to the state of the clock line.
  • FIG. 5 shows this alternative monitoring method.
  • step 44a the controller is set to the GPIO mode if the clock line SCL is at GND, otherwise the I 2 C protocol is set. Note that the latter also occurs without a sensor connected.
  • step 45a monitoring is carried out in step 45a to detect if SCL goes high. When it does, then an I 2 C device is detected in step 49a and the controller is set to the I 2 C mode.
  • step 45b monitoring is carried out in step 45b to detect if SCL remains at DC ground for the time period T. When it does, then a GPIO device is detected in step 49b and the controller is set to the GPIO mode.
  • the time period T may be longer than for Figure 4, for example 1 second or multiple seconds.
  • step 45 a When a GPIO device is detected the method passes to step 45 a (to listen out for an I 2 C device) and when an I 2 C device is detected the method passes to step 45b (to listen out for a GPIO device).
  • This method can thus run continuously.
  • the response time of the loop part is not critical, as it takes at least a second or so to replace the sensor, and every replacement has an intermediate or prolonged I 2 C state from the moment the old sensor is unplugged.
  • the alterations to a standard I 2 C controller may be implemented as software running on a computer, which is the already existing controller 38 of the system.
  • Figure 5 illustrates an example of a computer 60 for implementing the controller 38 described above.
  • the computer 60 may include one or more processors 61, memory 62, and one or more I/O devices 63 that are communicatively coupled via a local interface (not shown).
  • the local interface can be, for example but not limited to, one or more buses or other wired or wireless connections, as is known in the art.
  • the local interface may have additional elements, such as controllers, buffers (caches), drivers, repeaters, and receivers, to enable communications. Further, the local interface may include address, control, and/or data connections to enable appropriate communications among the aforementioned components.
  • the processor 61 is a hardware device for executing software that can be stored in the memory 62.
  • the processor 61 can be virtually any custom made or
  • processors such as a central processing unit (CPU), a digital signal processor (DSP), or an auxiliary processor among several processors associated with the computer 60, and the processor 61 may be a semiconductor based microprocessor (in the form of a microchip) or a microprocessor.
  • CPU central processing unit
  • DSP digital signal processor
  • auxiliary processor among several processors associated with the computer 60
  • the processor 61 may be a semiconductor based microprocessor (in the form of a microchip) or a microprocessor.
  • the memory 62 can include any one or combination of volatile memory elements (e.g., random access memory (RAM), such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.) and non-volatile memory elements (e.g., ROM, erasable programmable read only memory (EPROM), electronically erasable programmable read only memory (EEPROM), programmable read only memory (PROM), tape, compact disc read only memory (CD-ROM), disk, diskette, cartridge, cassette or the like, etc.).
  • RAM random access memory
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • non-volatile memory elements e.g., ROM, erasable programmable read only memory (EPROM), electronically erasable programmable read only memory (EEPROM), programmable read only memory (PROM), tape, compact disc read only memory (CD-ROM), disk, diskette, cartridge, cassette or the like, etc.
  • the memory 62 may incorporate electronic, magnetic, optical, and/or other types
  • the software in the memory 62 may include one or more separate programs, each of which comprises an ordered listing of executable instructions for implementing logical functions.
  • the software in the memory 62 includes a suitable operating system (O/S) 64, compiler 65, source code 66, and one or more applications 67 in accordance with exemplary embodiments.
  • O/S operating system
  • compiler 65 compiler 65
  • source code 66 source code 66
  • applications 67 application 67 in accordance with exemplary embodiments.
  • the application 67 comprises numerous functional components such as computational units, logic, functional units, processes, operations, virtual entities, and/or modules.
  • the operating system 64 controls the execution of computer programs, and provides scheduling, input-output control, file and data management, memory management, and communication control and related services.
  • Application 67 may be a source program, executable program (object code), script, or any other entity comprising a set of instructions to be performed.
  • a source program then the program is usually translated via a compiler (such as the compiler 65), assembler, interpreter, or the like, which may or may not be included within the memory 62, so as to operate properly in connection with the operating system 64.
  • the application 67 can be written as an object oriented programming language, which has classes of data and methods, or a procedure programming language, which has routines, subroutines, and/or functions, for example but not limited to, C, C++, C#, Pascal, BASIC, API calls, HTML, XHTML, XML, ASP scripts, JavaScript, FORTRAN, COBOL, Perl, Java, ADA, .NET, and the like.
  • the I/O devices 63 may include input devices such as, for example but not limited to, a mouse, keyboard, scanner, microphone, camera, etc. Furthermore, the I/O devices 67 may also include output devices, for example but not limited to a printer, display, etc. Finally, the I/O devices 63 may further include devices that communicate both inputs and outputs, for instance but not limited to, a NIC or modulator/demodulator (for accessing remote devices, other files, devices, systems, or a network), a radio frequency (RF) or other transceiver, a telephonic interface, a bridge, a router, etc. The I/O devices 63 also include components for communicating over various networks, such as the Internet or intranet.
  • a NIC or modulator/demodulator for accessing remote devices, other files, devices, systems, or a network
  • RF radio frequency
  • the I/O devices 63 also include components for communicating over various networks, such as the Internet or intranet.
  • the processor 61 When the computer 60 is in operation, the processor 61 is configured to execute software stored within the memory 62, to communicate data to and from the memory 62, and to generally control operations of the computer 60 pursuant to the software.
  • the application 67 and the operating system 64 are read, in whole or in part, by the processor 610, perhaps buffered within the processor 61, and then executed.
  • a computer readable medium may be an electronic, magnetic, optical, or other physical device or means that can contain or store a computer program for use by or in connection with a computer related system or method.
  • the invention is not limited to luminaires, but may be applied to other networks of devices, where the devices have an external port for connection of local sensors.
  • the invention may be applied to any control system in which sensing or external triggering plays a role.
  • Home automation, factory automation and transport automation, are examples.

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  • Selective Calling Equipment (AREA)

Abstract

L'invention concerne un système de commande qui est destiné à communiquer avec un dispositif sur un bus, le système de commande prenant en charge un premier protocole de communication sur le bus. Le système a des terminaux de connexion pour une connexion à des lignes du bus, les lignes de bus comprenant au moins une ligne de données pour transférer des données et une ligne d'horloge pour communiquer des informations de temporisation. Un signal sur la ligne d'horloge est analysé et, à partir du signal sur la ligne d'horloge, il est déterminé si le dispositif est d'un premier type qui est conforme au premier protocole de communication ou d'un second type différent. Une communication avec le dispositif utilisant ensuite un protocole de communication qui dépend du type de dispositif détecté. Dans ce système, le type de signal présent sur une ligne d'horloge du bus est utilisé pour déterminer le type de dispositif avec lequel une communication doit être réalisée. Un type est un dispositif qui fonctionne à l'aide d'un signal d'horloge et l'autre type est un dispositif qui maintient la ligne d'horloge par exemple au sol et n'utilise donc pas de signal d'horloge pour une communication.
PCT/EP2016/074587 2015-10-19 2016-10-13 Système de commande pour communiquer avec des dispositifs connectés à un bus, et procédé de communication WO2017067842A1 (fr)

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EP15190356.4 2015-10-19

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109977704A (zh) * 2019-02-26 2019-07-05 武汉光迅科技股份有限公司 一种i2c总线访问权限的确定方法、装置及存储介质
CN111917752A (zh) * 2020-07-24 2020-11-10 南昌欧菲光电技术有限公司 通讯接口转换装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2309395A1 (fr) * 2008-07-31 2011-04-13 Actions Semiconductor Co., Ltd. Procédé de réalisation d'un multiplexage par partage du temps de broches et système sur puce
US20120110218A1 (en) * 2010-11-01 2012-05-03 Analog Devices, Inc. Auto-Detection and Mode Switching for Digital Interface
US20140189177A1 (en) * 2013-01-03 2014-07-03 International Business Machines Corporation High speed overlay of idle i2c bus bandwidth
WO2015128172A1 (fr) * 2014-02-28 2015-09-03 Koninklijke Philips N.V. Affectation d'adresse de bus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2309395A1 (fr) * 2008-07-31 2011-04-13 Actions Semiconductor Co., Ltd. Procédé de réalisation d'un multiplexage par partage du temps de broches et système sur puce
US20120110218A1 (en) * 2010-11-01 2012-05-03 Analog Devices, Inc. Auto-Detection and Mode Switching for Digital Interface
US20140189177A1 (en) * 2013-01-03 2014-07-03 International Business Machines Corporation High speed overlay of idle i2c bus bandwidth
WO2015128172A1 (fr) * 2014-02-28 2015-09-03 Koninklijke Philips N.V. Affectation d'adresse de bus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109977704A (zh) * 2019-02-26 2019-07-05 武汉光迅科技股份有限公司 一种i2c总线访问权限的确定方法、装置及存储介质
CN109977704B (zh) * 2019-02-26 2023-02-14 武汉光迅科技股份有限公司 一种i2c总线访问权限的确定方法、装置及存储介质
CN111917752A (zh) * 2020-07-24 2020-11-10 南昌欧菲光电技术有限公司 通讯接口转换装置

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