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WO2016111798A1 - Matériaux d'empilement de grille pour applications dans le domaine des semi-conducteurs pour améliorer la surimpression lithographique - Google Patents

Matériaux d'empilement de grille pour applications dans le domaine des semi-conducteurs pour améliorer la surimpression lithographique Download PDF

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Publication number
WO2016111798A1
WO2016111798A1 PCT/US2015/064684 US2015064684W WO2016111798A1 WO 2016111798 A1 WO2016111798 A1 WO 2016111798A1 US 2015064684 W US2015064684 W US 2015064684W WO 2016111798 A1 WO2016111798 A1 WO 2016111798A1
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WIPO (PCT)
Prior art keywords
substrate
processing chamber
film layer
plasma
gas
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PCT/US2015/064684
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English (en)
Inventor
Michael Wenyoung Tsiang
Praket P. Jha
Xinhai Han
Nagarajan Rajagopalan
Bok Hoen Kim
Tsutomu Kiyohara
Subbalakshmi SREEKALA
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Applied Materials, Inc.
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Application filed by Applied Materials, Inc. filed Critical Applied Materials, Inc.
Priority to KR1020177018925A priority Critical patent/KR102579241B1/ko
Priority to JP2017536255A priority patent/JP2018508980A/ja
Publication of WO2016111798A1 publication Critical patent/WO2016111798A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates

Definitions

  • Embodiments of the disclosure generally relate to methods for forming a dielectric layer with minimum contribution to lithographic overlay errors, more specifically, methods for forming a dielectric layer with minimum contribution to lithographic overlay errors used in gate stack materials for semiconductor applications.
  • devices on semiconductor substrates are manufactured by a sequence of lithographic processing steps in which the devices are formed from a plurality of overlying layers, each having an individual pattern.
  • lithographic processing steps Generally, a set of 15 to 100 masks is used to construct a chip and can be used repeatedly.
  • a measurement of alignment marks may be obtained by a metrology tool which is then used by a lithography tool to align the subsequent layers during exposure and again after a lithography process to recheck a performance of the alignment.
  • overlay errors or pattern registration errors between layers are inevitable, and error budgets are calculated by IC designers for which the manufacturing must meet.
  • Overlay errors of the device structure may originate from different error sources, such as overlay errors from previous exposure tool/metrology tool, substrate warpage, current exposure tool/metrology tool limitation, a matching error between the overlay errors of the previous exposure tool/metrology tool and of the current exposure tool/metrology tool, or substrate film layer deformation caused by film stress and the like.
  • error sources such as overlay errors from previous exposure tool/metrology tool, substrate warpage, current exposure tool/metrology tool limitation, a matching error between the overlay errors of the previous exposure tool/metrology tool and of the current exposure tool/metrology tool, or substrate film layer deformation caused by film stress and the like.
  • Figure 1 depicts an overlay error map 100 of a semiconductor substrate measured after a sequence of lithographic exposure processes.
  • some patterns shown in an enlarged portion 102 of the substrate are shifted or displaced, e.g., in-plane displacement (IPD), from their designed location.
  • IPD in-plane displacement
  • displacement or misalignment of the patterns creates overlay errors that may be detriment to device performance.
  • overlay errors or in-plane displacement (IPD) undesirably occurs, the size, dimension or structures of dies formed on the substrate may be irregularly deformed or distorted, thus increasing likelihood of misalignment between the film layers stacked thereon that may adversely increase the probability of misalignment in the subsequent lithographic exposure process.
  • a method for forming a film layer on a substrate includes supplying a deposition gas mixture including a silicon containing gas and a reacting gas onto a substrate disposed on a substrate support in a processing chamber, forming a plasma in the presence of the depositing gas mixture in the processing chamber, applying current to a plasma profile modulator disposed in the processing chamber while supplying the depositing gas mixture into the processing chamber, and rotating the substrate while depositing a film layer on the substrate.
  • a method for forming a film layer on a substrate includes controlling a plasma generated from a gas mixture in a processing chamber by applying current to a plasma profile modulator disposed in the processing chamber, and forming a film layer on a substrate with the controlled plasma, wherein the film layer has a local bow range less than 50 ⁇ .
  • a film structure includes a film stack includes a first film layer and a second film layer disposed on the first layer, wherein the first film layer and the second film layer are alternatively and repeatedly formed in the film stack with a total thickness between about 600 nm and about 4000 nm, wherein the film stack has a local bow range less than 200 ⁇ .
  • Figures 1 depicts an overlay error map of a semiconductor substrate measured after a sequence of lithographic processes
  • Figure 2 depicts a deposition apparatus that may be utilized to form film layers overlay errors on a semiconductor substrate
  • Figure 3 depicts a flow diagram of a method of manufacturing a film layer with a desired range of stress on a semiconductor substrate;
  • Figures 4A-4B depict cross-sectional views of a film layer with a desired range of stress deposited on a semiconductor substrate in accordance with the manufacturing method of Figure 3;
  • Figure 5A-5B depict cross-sectional views of a film structure formed on a substrate utilizing the method depicted in Figure 3;
  • Figure 6 depicts an overlay error map with film layers formed utilizing the manufacturing method of Figure 3.
  • Embodiments of the disclosure describe an apparatus and a method for depositing a film layer that may have minimum contribution to overlay error after a sequence of deposition and lithographic exposure processes.
  • the deposition method may form a film layer with minimum stress variation or in-plane displacement across the film layer surface so as to provide consistent film stress in each film layer as formed on the substrate. By doing so, the overlay error may be minimized and/or eliminated when integrating all film layers to form semiconductor devices so that alignment precision is increased for the next lithographic exposure process.
  • the deposition method may utilize an apparatus with a plasma profile modulator to provide an uniform plasma generated during deposition as well as rotating the substrate while depositing.
  • FIG. 2 is a schematic side view of a processing chamber 200 that may be used to practice processes described herein.
  • the processing chamber 200 features a chamber body 202, a substrate support 204 disposed inside the chamber body 202, and a lid assembly 206 coupled to the chamber body 202 and enclosing the substrate support 204 in a processing volume 220.
  • a substrate 402 is provided to the processing volume 220 through an opening 226, which may be conventionally sealed for processing using a door.
  • the substrate support 204 may be rotatable, as indicated by the arrow 245, along an axis 247, where a shaft 244 of the substrate support 204 is located. Alternatively, the substrate support 204 may be lifted up to rotate as necessary during a deposition process.
  • a plasma profile modulator 21 1 may be disposed in the processing chamber 200 to control plasma distribution across the substrate 402 disposed on the substrate support 204.
  • the plasma profile modulator 21 1 includes a first electrode 208 that may be disposed adjacent to the chamber body 202 and separate the chamber body 202 from other components of the lid assembly 206.
  • the electrode 208 may be part of the lid assembly 206, or may be a separate side wall electrode.
  • the electrode 208 may be an annular, or ring-like member, and may be a ring electrode.
  • the electrode 208 may be a continuous loop around a circumference of the processing chamber 200 surrounding the processing volume 220, or may be discontinuous at selected locations if desired.
  • the electrode 208 may also be a perforated electrode, such as a perforated ring or a mesh electrode.
  • the electrode 208 may also be a plate electrode, for example a secondary gas distributor.
  • An isolator 210 which may be a dielectric material such as a ceramic or metal oxide, for example aluminum oxide and/or aluminum nitride, contacts the electrode 208 and separates the electrode 208 electrically and thermally from a gas distributor 212 and from the chamber body 202.
  • the gas distributor 212 features openings 218 for admitting process gases into the processing volume 220.
  • the gas distributor 212 may be coupled to a source of electric power (power source) 242, such as an RF generator, RF power source, DC power, pulsed DC power, and pulsed RF power may also be used.
  • the electric power source 242 is an RF power source.
  • the gas distributor 212 may be a conductive gas distributor or a non- conductive gas distributor.
  • the gas distributor 212 may also be made of conductive and non-conductive components.
  • a body of the gas distributor 212 may be conductive while a face plate of the gas distributor 212 is non-conductive.
  • the gas distributor 212 may be powered, such as by the power source 242 as shown in Figure 2, or the gas distributor 212 may be coupled to ground.
  • the electrode 208 may be coupled to a tuning circuit 228 that controls a ground pathway of the processing chamber 200.
  • the tuning circuit 228 comprises an electronic sensor 230 and an electronic controller 234.
  • the electronic controller 234 may be or include a variable capacitor or other circuit element(s).
  • the tuning circuit 228 may be or include one or more inductors 232.
  • the tuning circuit 228 may be any circuit that enables variable or controllable impedance under the plasma conditions present in the processing volume 220 during processing.
  • the tuning circuit 228 features a first circuit leg and a second circuit leg coupled in parallel between ground and the electronic sensor 230.
  • the first circuit leg includes a first inductor 232A.
  • the second circuit leg includes a second inductor 232B coupled in series with the electronic controller 234.
  • the second inductor 232B disposed between the electronic controller 234 and the node connecting both the first and second circuit legs to the electronic sensor 230.
  • the electronic sensor 230 may be a voltage or current sensor, and may be coupled to the electronic controller 234 to afford a degree of closed-loop control of plasma conditions inside the processing volume 220.
  • a second electrode 222 may be coupled to the substrate support 204.
  • the second electrode 222 may be embedded within the substrate support 204 or coupled to a surface of the substrate support 204.
  • the second electrode 222 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed arrangement of conductive elements.
  • the second electrode 222 may be a tuning electrode, and may be coupled to a second tuning circuit 236 by a conduit 246, for example a cable having a selected resistance, such as 50 ohms ( ⁇ ), disposed in the shaft 244 of the substrate support 204.
  • the second tuning circuit 236 may have a second electronic sensor 238 and a second electronic controller 240, which may be a second variable capacitor.
  • the second electronic sensor 238 may be a voltage or current sensor, and may be coupled to the second electronic controller 240 to provide further control over plasma conditions in the processing volume 220.
  • a third electrode 224 which may be a bias electrode and/or an electrostatic chucking electrode, may be coupled to the substrate support 204.
  • the third electrode may be coupled to a second source of electric power (second power source) 250 through a filter 248, which may be an impedance matching circuit.
  • the second source of electric power 250 may be DC power, pulsed DC power, RF bias power, pulsed RF source or bias power, or a combination thereof.
  • the second source of electric power 250 is a RF bias power.
  • the lid assembly 206 and substrate support 204 of Figure 2 may be used with any processing chamber for plasma or thermal processing.
  • a plasma processing chamber with which the lid assembly 206 and substrate support 204 may be beneficially used is the PRODUCER ® or PRECISION ® platform and chambers available from Applied Materials, Inc., located in Santa Clara, California. Chambers from other manufacturers may also be used with the components described above.
  • the processing chamber 200 affords real-time control of plasma conditions in the processing volume 220.
  • the substrate 402 is disposed on the substrate support 204, and process gases are flowed through the lid assembly 206 using an inlet 214 according to any desired flow plan. Gases exit the processing chamber 200 through an outlet 252. Electric power is coupled to the gas distributor 212 to establish a plasma in the processing volume 220.
  • the substrate may be subjected to an electrical bias using the third electrode 224, if desired.
  • a potential difference is established between the plasma and the first electrode 208.
  • a potential difference is also established between the plasma and the second electrode 222.
  • the electronic controllers 234, 240 may then be used to adjust the flow properties of the ground paths represented by the two tuning circuits 228 and 236.
  • a set point may be delivered to the first tuning circuit 228 and the second tuning circuit 236 to provide independent control of deposition rate and of plasma density uniformity from center to edge.
  • the electronic controllers are both variable capacitors
  • the electronic sensors may adjust the variable capacitors to maximize deposition rate and minimize thickness non-uniformity independently.
  • Each of the tuning circuits 228, 236 has a variable impedance that may be adjusted using the respective electronic controllers 234, 240.
  • the electronic controllers 234, 240 are variable capacitors
  • the capacitance range of each of the variable capacitors, and the inductances of the inductors 232A, 232B are chosen to provide an impedance range, depending on the frequency and voltage characteristics of the plasma, that has a minimum in the capacitance range of each variable capacitor.
  • impedance of the circuit 228 is high, resulting in a plasma shape that has a minimum aerial (lateral) coverage over the substrate support.
  • the capacitance of the electronic controller 234 approaches a value that minimizes the impedance of the circuit 228, the aerial coverage of the plasma grows to a maximum, effectively covering the entire working area of the substrate support 204.
  • the capacitance of the electronic controller 234 deviates from the minimum impedance setting, the plasma shape shrinks from the chamber walls and aerial coverage of the substrate support declines.
  • the electronic controller 240 has a similar effect, increasing and decreasing aerial coverage of the plasma over the substrate support as the capacitance of the electronic controller 240 is changed.
  • the electronic sensors 230, 238 may be used to tune the respective circuits 228, 236 in a closed loop.
  • a set point for current or voltage, depending on the type of sensor used, may be installed in each sensor, and the sensor may be provided with control software that determines an adjustment to each respective electronic controller 234, 240 to minimize deviation from the set point. In this way, a plasma shape can be selected and dynamically controlled during processing.
  • electronic controllers 234, 240 that are variable capacitors
  • any electronic component with adjustable characteristic may be used to provide tuning circuits 228 and 236 with adjustable impedance.
  • Figure 3 illustrates a method 300 for forming a film layer, such as a dielectric layer, on a substrate, which may be later utilized to form a gate structure for semiconductor devices.
  • the film layer may be utilized to form gate structures for three dimensional (3D) NAND semiconductor applications.
  • stair-like oxide-nitride pairs of structures are often utilized to high aspect ratio gate stack NAND cells so as to increase circuit density.
  • Figures 4A-4B illustrate schematic cross-sectional views of the substrate 402 having at least a first film layer 406 disposed on a surface 404 of the first film layer 406.
  • the first film layer 406 may be a dielectric layer, such as a silicon oxide containing layer, a silicon nitride containing layer, a silicon carbide containing layer, and the like.
  • the deposition process may be performed directly on the substrate 402.
  • the method 300 begins at operation 302 with a substrate, such as the substrate 402 depicted in Figure 4A, disposed into the processing chamber, such as the processing chamber 200 depicted in Figure 2, or other suitable processing chamber.
  • the substrate 402 shown in Figure 4A includes the first film layer 406 formed on the substrate 402.
  • the substrate 402 may have a substantially planar surface, an uneven surface, or a substantially planar surface having a structure formed thereon.
  • the substrate 402 may be a material such as crystalline silicon (e.g., Si ⁇ 1 00> or Si ⁇ 1 1 1 >), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or non-patterned wafers silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire.
  • SOI silicon on insulator
  • the substrate 402 may have various dimensions, such as 200 mm or 300 mm diameter wafers, as well as, rectangular or square panels.
  • the substrate 402 may include a buried dielectric layer disposed on a silicon crystalline substrate.
  • the substrate 402 may be a crystalline silicon substrate.
  • the first film layer 406 is may be a silicon oxide containing layer, a silicon nitride containing layer, a silicon containing layer, such as amorphous silicon, polycrystalline silicon or any suitable crystalline silicon layers.
  • the first film layer 406 is a silicon oxide containing layer, such as a silicon oxide layer.
  • a deposition gas mixture is provided into the processing chamber.
  • the deposition gas mixture may include a silicon containing gas and a reacting gas.
  • Suitable examples of the silicon containing gas include, but not limited to, silane (SiH 4 ), di-silane(S i2 H 6 ), silicon tetrafluoride (SiF 4 ), silicon tetrachloride(SiC
  • the reacting gas may be an oxygen containing gas, for forming a silicon oxide containing layer, a nitrogen containing gas, for forming a silicon nitride containing layer, or a carbon containing gas, for forming a silicon carbide containing layer.
  • Suitable examples of the oxygen containing gas include 0 2 , N 2 0, N0 2 , 0 3 , H 2 0 and the like.
  • Suitable examples of the nitrogen containing gas include N 2 , N 2 0, N0 2 , NH 3 , N 2 H 2 and the like.
  • Suitable examples of the carbon containing gas include C0 2 , CO, CH 4 , CF 4 , other suitable carbon based polymer gases and the like.
  • the silicon containing gas is silane (SiH 4 ) and the reacting gas is a nitrogen containing gas, such as N 2 , N 2 0 or NH 3 , to form a second film layer 408, such as a silicon nitride containing layer, depicted in Figure 4B, which will be described in greater detail below.
  • the gas ratio of the silicon containing gas, such as SiH 4 gas, and reacting gas, such as nitrogen containing gas (N 2 , N 2 0 or NH 3 gas) is maintained to control reaction behavior of the gas mixture, thereby allowing a desired proportion of the nitrogen elements in the formed silicon film.
  • the SiH 4 gas may be supplied at a flow rate between about 40 seem and about 200 seem and the N 2 , N 2 0 or NH 3 gas may be supplied at a flow rate at between about 500 seem and about 9000 seem.
  • the gas mixture of SiH 4 gas and N 2 , N 2 0 or NH 3 gas may be supplied at a ratio of SiH 4 to N 2 or NH 3 gas of between about 1 : 1 and about 1 : 150, such as between about 1 : 1 and about 1 : 120, for example, about 1 : 100.
  • one or more inert gases may be included in the deposition gas mixture provided to the processing chamber 200.
  • the inert gas may include, but not limited to, noble gas, such as Ar, He, and Xe, or N 2 and the like.
  • the inert gas may be supplied to the processing chamber 200 at a flow ratio of inert gas to SiH 4 gas of between about 1 : 1 and about 1 : 150.
  • a pressure of the process gas mixture in the deposition processing chamber is regulated between about 10 mTorr to about 15 Torr, and the substrate temperature is maintained between about 200 degrees Celsius and about 700 degrees Celsius.
  • an RF source power may be generated by the power source 242 (depicted in Figure 2) and coupled to the gas mixture to assist dissociating the deposition gas mixture into reactive species in a plasma.
  • the RF source and/or bias power energizes the deposition gas mixture within the processing volume 220 such that the plasma may be sustained.
  • the power source 242 may be operated to provide RF power at a frequency between 0.3 MHz and about 14MHz, such as about 13.56 MHz.
  • the power source 242 may generate RF power at about 10 Watts to about 5000 Watts, such as about 500 Watts.
  • the RF bias power provided by the second power source 250 (depicted in Figure 2) may also be utilized during the deposition process to assist dissociating the deposition gas mixture forming the plasma.
  • the power source 242 may be operated to provide RF power at a frequency between 0.3 MHz and about 14MHz, such as about 13.56 MHz.
  • the RF bias power may be supplied at between about 10 Watts and about 100 Watts at a frequency of 300 kHz.
  • the RF bias power may be pulsed with a duty cycle between about 10 to about 95 percent at a RF frequency between about 500 Hz and about 10 kHz.
  • current/voltage may be supplied to the plasma profile modulator 21 1 to assist controlling profile and distribution of the plasma across the substrate 402.
  • the side wall tuning electrode current target ⁇ e.g., supplied to the electrode 208) is set to between about 0.5 A and about 40 A, such as about 6A
  • substrate support tuning electrode current target e.g., supplied to the second electrode 222 is set to between about 0.5 A and about 40 A, such as about 6 A, to assist controlling the plasma as generated in the processing volume 220.
  • the substrate support 204 may be rotated to assist exposing the plasma across the substrate surface in a more uniform manner.
  • the substrate support 204 may be rotated continuously or periodically during deposition of the second film layer 408 on the substrate 402.
  • the substrate support 204 may rotate about the axis 247 between about 1 ° and about 360°, such as between about 30° and about 270°, for example, between about 90° and about 180°.
  • the substrate support 204 may be rotated about between 0 rpm and about 100 rpm until a desired thickness of the second film layer 408 is formed on the substrate 402, as shown in Figure 4B.
  • the deposition process may then be terminated.
  • the second film layer 408 may have a thickness between about 10 nm and about 60 nm, such as about 30 nm.
  • the silicon nitride containing layer may have a stress range between about -200 Mpa and about +1200 Mpa with a stress uniformity less than 50 %.
  • the second film layer 408 have may a ratio of N element to Si element substantially between about 0.8 : 1 and about 2 : 1 .
  • the second film layer 408 may have a local bow range less than 50 ⁇ .
  • the deposition processes for forming the first film layer 406 and the second film layer 408 may be performed repeatedly to form a film stack 502, which may be later patterned to form stair-like structures 504 for 3D NAND semiconductor devices, as depicted in a cross sectional view of the stair-like structures 504 illustrated in Figure 5A.
  • the film stack 502 typically includes alternating layers of first film layer 406 and the second film layer 408 (shown as 406a, 408a, 406b, 408b, , 406n, 408n).
  • the film stack 502 may have a total thickness between about
  • the film stack 502 may include a total of about 5 to 90 pairs of first film layer 406 and the second film layer 408.
  • a photoresist layer may be used to sequentially trim to different dimensions while serving as an etch mask formed on the stairlike structure 504 to complete gate structures for the 3D NAND semiconductor devices.
  • the deposition method 300 of Figure 3 may be continuously performed to form the film stack 502 with alternating first film layers 406 and second film layers 408.
  • the deposition method 300 of Figure 3 may be performed by switching different deposition gas mixture at operation 304 to form the film layers 406, 408 with different compositions without removing the substrate 402 from the processing chamber 200 (e.g., without breaking vacuum).
  • the film stack 502 may be formed by first supplying a first deposition gas mixture (regulated at operation 304) with a first set of process parameters (regulated at operation 306, 308) to form the first film layer 406, such as a silicon oxide layer.
  • the first deposition gas mixture may include at least a silicon containing gas and an oxygen containing gas.
  • the deposition process may be looped back to operation 304 to switch the first deposition gas mixture to a second deposition gas mixture (regulated at operation 304) with a second set of process parameters (regulated at operation 306, 308) to form a first layer 408a of the second film layer 408, such as a silicon nitride layer.
  • the second deposition gas mixture may include at least a silicon containing gas and a nitrogen containing gas. Switch between the first and the second deposition gas mixtures may optionally have a pump/purge process to pump/purge the residual gases or deposit byproducts from the processing chamber prior to forming a next film layer on the substrate 402.
  • a uniform film layer with a uniform stress profile may be obtained so that the substrate warpage, substrate bent, or in-plane displacement may be eliminated/or minimized so as to provide film layers with desired stress uniformity and film properties for the subsequent lithographic process with minimum likelihood of overlay error occurrence.
  • the film residual stress may undesirably result in substrate bow, warpage or substrate curvature. In such cases, misalignment between the features present on the film layer pattern formed by the lithographic exposure process may become significant, resulting in an overlay error that may result in feature deformation or structure collapse.
  • the plasma profile modulator 21 1 may assist controlling plasma distribution at local position on the substrate surface along with the assistance from rotation of the substrate support during the deposition process, so that localized residual stress in discrete regions of the film layers may be eliminated or reduced so as to locally change the in- plane displacement (or strain, pattern shift, or substrate curvature) in the film layer. By doing so, substantially linear and uniform film properties across the substrate surface may be obtained. The straightened and uniform features allow for reduced overlay errors in the subsequent lithographic exposure process, enhancing alignment precision during the lithographic exposure process.
  • the whole film stack 502 may have stress range between about -100 Mpa and about +100 Mpa with a stress uniformity less than 50 %. Alternatively, whole film stack 502 may have a local bow range less than 200 ⁇ .
  • the substrate support 204 may commence rotating when the substrate 402 is positioned on the substrate support (at operation 302), or even prior to the substrate 402 positioning onto the substrate support 204 in preparation for performing the deposition process. Similarly, the substrate support 204 may commence rotating after a deposition process in preparation for the next deposition process to be performed in the processing chamber. It is noted that rotation of the substrate support 204 may be in any arrangements, such as during the deposition process (operation 308), in between deposition processes (prior to operation 302 or after operation 310), prior to performing a deposition process (prior to operation 302), or after a first deposition process (after operation 310) is performed but prior to performing a second deposition process as needed.
  • Figure 6 depict an in-plane displacement map generated after the multiple film stack 502 with alternating first and second film layers (406a, 408a,
  • the metrology tool may be utilized to scan the semiconductor substrate and determine the overlay error map or substrate distortion may be a metrology tool available from KLA-Tencor ® of California. Prior to exposure, one may measure in-plane distortion using a metrology tool such as the KLA Wafer Sight or the Ultratec Superfast 3G. After lithography, one may use a conventional overlay tool to measure actual layer to layer pattern overlay and registration. It is noted that other suitable metrology tools from other manufacturers may also be utilized to perform the scan and measurement process.
  • the in-plane displacement or stress deviation of the substrate is significantly reduced, particularly as compared to that of Figure 1 .
  • the reduction in in-plane displacement or stress deviation of the substrate enhances the alignment precision in the lithographic exposure process, which reduces overlay errors and improves device performance.
  • the materials utilized to form the film layers may be a dielectric material selected from a group consisting of silicon nitride (Si 3 N 4 ), silicon nitride hydride (Si x N y :H), amorphous carbon, silicon carbide, silicon oxide, silicon oxynitride, a composite film of silicon oxide, silicon nitride, silicon carbide or amorphous carbon, an aluminum oxide layer, a tantalum oxide layer, a titanium oxide layer, spin-cast organic polymers, or other suitable material.
  • film layer may be any suitable polymer organic material, including SOG, polyimide or any suitable materials.
  • embodiments of the disclosure provide a deposition process that utilizes a plasma profile modulator along with substrate support rotation during the deposition process so as to provide a film layer with uniform film properties across the substrate surface with minimum in-plane displacement after a sequence of lithographic exposure processes.
  • Utilization of the plasma profile modulator along with substrate support rotation may improve uniformity of film stress/strain distribution in the film layer disposed on the semiconductor substrate. By forming film layers with uniform film properties with minimum stress deviation, the overlay error may be eliminated so as to increase alignment precision for the next lithographic exposure process.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Memories (AREA)
  • Plasma Technology (AREA)
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Abstract

Selon des modes de réalisation, l'invention concerne des procédés et un système de fabrication de couches de film avec un minimum d'erreurs de surimpression lithographique sur un substrat semi-conducteur. Dans un mode de réalisation, un procédé de formation d'une couche de film sur un substrat consiste à amener un mélange gazeux de dépôt comprenant un gaz contenant du silicium et un gaz de réaction sur un substrat disposé sur un support de substrat dans une chambre de traitement, à former un plasma en présence du mélange gazeux de dépôt dans la chambre de traitement, à appliquer un courant à un modulateur de profil de plasma disposé dans la chambre de traitement tout en introduisant le mélange gazeux de dépôt dans la chambre de traitement, et à faire tourner le substrat tout en déposant une couche de film sur le substrat.
PCT/US2015/064684 2015-01-09 2015-12-09 Matériaux d'empilement de grille pour applications dans le domaine des semi-conducteurs pour améliorer la surimpression lithographique WO2016111798A1 (fr)

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JP2017536255A JP2018508980A (ja) 2015-01-09 2015-12-09 リソグラフィオーバーレイ改善のための半導体アプリケーション用ゲートスタック材料

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KR102579241B1 (ko) 2023-09-14
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