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WO2016035587A1 - Dispositif de traitement de signaux, procédé de commande, élément d'imagerie et dispositif électronique - Google Patents

Dispositif de traitement de signaux, procédé de commande, élément d'imagerie et dispositif électronique Download PDF

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Publication number
WO2016035587A1
WO2016035587A1 PCT/JP2015/073653 JP2015073653W WO2016035587A1 WO 2016035587 A1 WO2016035587 A1 WO 2016035587A1 JP 2015073653 W JP2015073653 W JP 2015073653W WO 2016035587 A1 WO2016035587 A1 WO 2016035587A1
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WIPO (PCT)
Prior art keywords
unit
signal
reference signal
comparison
capacitor
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PCT/JP2015/073653
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English (en)
Japanese (ja)
Inventor
克彦 半澤
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ソニー株式会社
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Publication of WO2016035587A1 publication Critical patent/WO2016035587A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/56—Input signal compared with linear ramp
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors

Definitions

  • the present technology relates to a signal processing device, a control method, an image sensor, and an electronic device, and more particularly, to a signal processing device, a control method, an image sensor, and an electronic device that can suppress an increase in cost.
  • a two-step single slope A / D conversion (also referred to as a two-step SS-ADC) has been proposed as a technique for speeding up high-resolution AD conversion (see, for example, Non-Patent Document 1).
  • the 2-step SS-ADC first performs A / D conversion of the upper bit, and performs A / D conversion of the lower bit based on the result.
  • the ramp wave serving as a reference signal is input directly to the comparator or is input to the comparator via a fixed capacitor. For this reason, the input range of the comparator must be matched to the output voltage specification of the D / A converter that generates the reference signal, and the comparator and the D / A converter cannot be designed independently of each other. Therefore, the difficulty of these designs is increased, and there is a risk that the development and manufacturing costs increase.
  • This technology has been proposed in view of such a situation, and an object thereof is to facilitate the design of a comparator and a D / A converter and to suppress an increase in cost.
  • One aspect of the present technology compares signal levels between a charge storage unit that stores charges and a variable capacitance, an input signal, and a reference signal that is input via the charge storage unit, and outputs a comparison result.
  • a comparison unit wherein the comparison unit compares the signal levels a plurality of times, and the charge storage unit is a signal processing device that sets the capacitance according to an output of the comparison unit.
  • the charge storage unit includes a plurality of capacitors that store the charge, and a switch that controls connection between the reference signal line, which is a signal line for transmitting the reference signal, and the capacitor according to the output of the comparison unit. Can be provided.
  • the switch can reduce the capacitance between the reference signal line and the comparison unit by disconnecting a part of the capacitor from the reference signal line when the output of the comparison unit is inverted.
  • the switch can disconnect a capacitor having a capacity corresponding to the resolution of the signal level comparison by the comparison unit from the reference signal line.
  • the switch can disconnect a part of the capacitor from the reference signal line at a timing according to the inversion timing of the output of the comparator.
  • the switch can disconnect a part of the capacitor from the reference signal line at the count timing immediately after the inversion of the output of the comparator.
  • the switch can disconnect a part of the capacitor from the reference signal line at the count timing immediately before the inversion of the output of the comparison unit in the next comparison of the comparison unit.
  • the reference signal is a ramp wave
  • the switch reduces the capacitance between the reference signal line and the comparison unit by separating a part of the capacitor from the reference signal line, and the reference signal The inclination of the waveform can be reduced.
  • the signal level of the reference signal can be set to an initial value corresponding to the width of the signal level of the reference signal every time the signal level is compared.
  • the reference signal can be configured such that the direction of the ramp wave waveform is reversed each time the signal level is compared.
  • the charge storage unit may further include a holding capacitor that holds a signal level of the reference signal, and the capacitor separated from the reference signal line by the switch is connected to the holding capacitor. it can.
  • the charge storage unit further includes an inter-capacitor switch that controls connection between the capacitors, the holding capacitor is connected to any one of the plurality of capacitors, and the inter-capacitor switch is The capacitors can be connected such that the capacitor disconnected from the reference signal line is connected to the holding capacitor.
  • the holding capacitor may be provided for each of the plurality of capacitors.
  • the control unit may further include a control unit that controls the capacitance between the reference signal line and the comparison unit by controlling the switch of the charge storage unit according to the output of the comparison unit.
  • a counting unit that counts until the output of the comparison unit is inverted can be further provided.
  • the input signal may be a signal read from a unit pixel.
  • the input signal may be a signal read from a unit pixel to be processed in a predetermined unit pixel group corresponding to the comparison unit of a pixel region in which the unit pixels are arranged in a matrix.
  • One aspect of the present technology is also configured to compare a signal level between a reference signal and an input signal that are input via a charge storage unit that stores charges and has a variable capacitance, and the charge storage unit according to the comparison result.
  • This is a signal processing method for setting the capacity of.
  • Another aspect of the present technology is a pixel array in which a plurality of unit pixels are arranged in a matrix, a charge storage unit that stores charges and a variable capacity, and an input signal that is read from the unit pixels of the pixel array.
  • a comparison unit that compares a signal level with a reference signal input through the charge storage unit and outputs a comparison result, and the comparison unit performs the signal level comparison a plurality of times, and the charge storage unit
  • the unit is an image sensor that sets the capacitance according to the output of the comparison unit.
  • Still another aspect of the present technology includes an imaging unit that images a subject and an image processing unit that performs image processing on image data obtained by imaging by the imaging unit, and the imaging unit includes a plurality of unit pixels in a matrix.
  • a pixel array arranged in a shape, a charge storage unit that stores charges, a variable capacitance, an input signal read from the unit pixel of the pixel array, and a reference signal input via the charge storage unit
  • a comparison unit that compares the signal level and outputs a comparison result, the comparison unit performs the signal level comparison a plurality of times, and the charge storage unit determines the capacitance according to the output of the comparison unit.
  • the electronic device to be set.
  • a signal level is compared between an input signal and a reference signal that is input via a charge storage unit that stores charge and has a variable capacity, and the capacity of the charge storage unit is determined according to the comparison result. Is set.
  • a plurality of unit pixels are arranged in a matrix, and are stored in a charge signal.
  • the reference signal is input via a charge storage unit having a variable capacitance, and is read from the unit pixels of the pixel array.
  • the signal level is compared with the input signal, and the capacity of the charge storage unit is set according to the comparison result.
  • an imaging device including a pixel array in which a plurality of unit pixels are arranged in a matrix of an electronic device
  • the charge is stored and input via a charge storage unit having a variable capacitance.
  • the signal level is compared between the reference signal and the input signal read from the unit pixel of the pixel array, and the capacity of the charge storage unit is set according to the comparison result.
  • the signal can be processed. Moreover, according to this technique, the increase in cost can be suppressed.
  • FIG. 8 is a flowchart following FIG. 7 for explaining an example of the flow of imaging processing. It is a timing chart explaining the example of the flow of an imaging process.
  • FIG. 10 is a timing chart following FIG.
  • FIG. 9 for explaining an example of the flow of imaging processing.
  • FIG. 12 is a timing chart following FIG. 11 for explaining another example of the flow of the imaging process.
  • It is a flowchart explaining the example of the flow of an imaging process.
  • It is a flowchart following FIG. 13 explaining the example of the flow of an imaging process.
  • It is a timing chart explaining the example of the flow of an imaging process.
  • 16 is a timing chart following FIG. 15 for explaining an example of the flow of imaging processing.
  • FIG. 18 is a flowchart following FIG. 17 for explaining an example of the flow of imaging processing. It is a timing chart explaining the example of the flow of an imaging process.
  • FIG. 20 is a timing chart illustrating an example of the flow of imaging processing, following FIG. 19. It is a figure which shows the main structural examples of a column A / D conversion part. It is a figure explaining the example of comparison of processing time. It is a figure which shows the example of the physical structure of an image sensor. It is a figure which shows the other structural example of an image sensor. It is a figure which shows the other structural example of an image sensor. It is a figure which shows the main structural examples of an imaging device.
  • ⁇ 2step type SS-ADC> Therefore, in recent years, as a technique for accelerating high-resolution A / D conversion, for example, a two-step single slope A / D conversion system (2-step SS-ADC) as described in Non-Patent Document 1 has been proposed. It was.
  • the 2-step SS-ADC performs A / D conversion of upper bits and performs A / D conversion of lower bits based on the result.
  • the 2-step SS-ADC has one of multiple ramp lines (reference signal (reference voltage)) for the lower bit after AD conversion of the upper bit (depending on the signal level of the signal to be A / D converted) A / D conversion.
  • the ramp wave serving as a reference signal is input directly to the comparator of the A / D converter or input to the comparator via a fixed capacitor. Therefore, the input range of the comparator must be designed to match the output voltage specification of the D / A converter that generates the reference signal, and the comparator and D / A converter can be designed independently of each other. could not. Therefore, the difficulty of these designs is increased, and there is a risk that the development and manufacturing costs increase.
  • the signal level is compared between the charge storage unit that stores charges and the capacitance is variable, the input signal, and the reference signal that is input through the charge storage unit, and outputs the comparison result.
  • a comparison unit that compares the signal levels a plurality of times, and the charge storage unit sets its own capacitance according to the output of the comparison unit (that is, the comparison result).
  • the offset and width of the signal level of the reference signal input to the comparison unit can be controlled by the capacitance of the charge storage unit. That is, regardless of the reference signal (that is, the specification of the D / A conversion unit that generates the reference signal), a signal having a desired signal level width and offset can be input to the comparison unit. That is, the D / A conversion unit and the comparison unit can be designed independently of each other. Therefore, these designs are facilitated, and an increase in development and manufacturing costs can be suppressed.
  • the configuration of the D / A converter can be further simplified, and an increase in circuit scale and power consumption can be suppressed.
  • the charge storage unit includes a plurality of capacitors that store charges, and a switch that controls connection between the reference signal line, which is a signal line for transmitting a reference signal, and the capacitor according to the output of the comparison unit. Also good.
  • the control can be performed more easily, and the increase in the circuit scale necessary for the control can be suppressed. it can.
  • the switch may reduce the capacitance between the reference signal line and the comparison unit by separating a part of the capacitor from the reference signal line.
  • the switch may disconnect a capacitor having a capacity corresponding to the resolution of the signal level comparison by the comparison unit from the reference signal line.
  • the input range of the reference signal in the next comparison can be more easily controlled according to the resolution of the current comparison.
  • the width of the signal level of the reference signal input to the comparison unit in the comparison of the second step can be more easily
  • the width can be set in accordance with the resolution of the comparison in the first step.
  • the switch may disconnect a part of the capacitor from the reference signal line at a timing according to the inversion timing of the output of the comparison unit.
  • the offset of the reference signal input to the comparison unit in the next comparison can be controlled more easily in accordance with the inversion timing of the current comparison result.
  • the offset of the reference signal input to the comparison unit in the comparison at the second step can be made easier. Can be set to an offset according to the comparison result (the inversion timing) of the first step.
  • the switch may disconnect a part of the capacitor from the reference signal line at the count timing immediately after the output of the comparison unit is inverted.
  • the reference signal described above is a ramp wave, and the switch disconnects a part of the capacitor from the reference signal line, thereby reducing the capacitance between the reference signal line and the comparison unit and reducing the slope of the waveform of the reference signal. It may be.
  • the signal level of the reference signal may be set to an initial value corresponding to the width of the signal level of the reference signal every time the signal level is compared.
  • the charge storage unit may further include a holding capacitor for holding the signal level of the reference signal, and the capacitor separated from the reference signal line by the switch may be connected to the holding capacitor.
  • the charge storage unit further includes an inter-capacitor switch that controls connection between the capacitors, the holding capacitor is connected to one of the plurality of capacitors, and the inter-capacitor switch is disconnected from the reference signal line by the switch.
  • the capacitors may be connected so that the capacitors are connected to the holding capacitor.
  • a holding capacitor may be provided for each of a plurality of capacitors.
  • a control unit that controls the capacitance between the reference signal line and the comparison unit by controlling the switch of the charge storage unit according to the output of the comparison unit may be further provided.
  • a count unit that counts until the output of the comparison unit is inverted may be further provided.
  • the input signal may be a signal read from the unit pixel.
  • the input signal is a signal read from a unit pixel to be processed in a predetermined unit pixel group (for example, a unit pixel column or a pixel unit) corresponding to a comparison unit in a pixel region in which unit pixels are arranged in a matrix. You may do it.
  • a predetermined unit pixel group for example, a unit pixel column or a pixel unit
  • a pixel array in which a plurality of unit pixels are arranged in a matrix, a charge storage unit that stores charges, a variable capacity, an input signal read from the unit pixels of the pixel array, and an input via the charge storage unit
  • a comparison unit that compares a signal level with a reference signal and outputs a comparison result, and the comparison unit performs signal level comparison a plurality of times, and a charge storage unit outputs to the output of the comparison unit.
  • the capacity may be set accordingly.
  • an electronic apparatus includes an imaging unit that images a subject and an image processing unit that performs image processing on image data obtained by imaging by the imaging unit, and the imaging unit includes a plurality of unit pixels arranged in a matrix.
  • the signal level is compared between the pixel array, the charge storage unit that stores charges and the capacitance is variable, the input signal read from the unit pixel of the pixel array, and the reference signal that is input through the charge storage unit.
  • a comparison unit that outputs the result, the comparison unit may perform signal level comparison a plurality of times, and the charge storage unit may set the capacitance according to the output of the comparison unit.
  • FIG. 2 shows a main configuration example of an image sensor which is an embodiment of an imaging device to which the present technology is applied.
  • An image sensor 100 shown in FIG. 2 is a device that photoelectrically converts light from a subject and outputs it as image data.
  • the image sensor 100 is configured as a CMOS image sensor using CMOS (Complementary Metal Oxide Semiconductor), a CCD image sensor using CCD (Charge Coupled Device), or the like.
  • CMOS Complementary Metal Oxide Semiconductor
  • CCD Charge Coupled Device
  • the image sensor 100 includes a pixel array 101, a reference voltage generation unit 102, an A / D conversion unit 103, a horizontal transfer unit 104, a storage unit 105, a calculation unit 106, a control unit 111, and vertical scanning. Part 112.
  • the pixel array 101 is a pixel region in which pixel configurations (unit pixels) having photoelectric conversion elements such as photodiodes are arranged in a planar shape or a curved shape. Although the details of the configuration of the pixel array 101 will be described later, an analog signal read from the unit pixel is sent to the A / D conversion unit 103 via any one of the vertical signal lines 121-1 to 121-N. Is transmitted.
  • the vertical signal lines 121-1 to 121 -N are referred to as vertical signal lines 121 when it is not necessary to distinguish them from each other.
  • the reference voltage generator 102 generates a reference signal (also referred to as a reference voltage) that serves as a reference signal for A / D conversion of the A / D converter 103.
  • the waveform of this reference signal is arbitrary.
  • the reference signal may be a ramp wave (sawtooth wave).
  • a case where a ramp wave (Ramp) is used as a reference signal will be described as an example.
  • the reference voltage generation unit 102 includes, for example, a D / A conversion unit, and generates a reference signal (Ramp) by the D / A conversion unit. This reference signal (Ramp) is supplied to the A / D conversion unit 103 via the reference signal line 122.
  • the A / D converter 103 uses the reference signal to A / D-convert an analog signal (read from each unit pixel) transmitted from the pixel array 101 via the vertical signal line 121, and The digital data is output to the horizontal transfer unit 104 via any one of the signal lines 123-1 to 123-N.
  • the signal lines 123-1 to 123 -N are referred to as signal lines 123 when it is not necessary to distinguish them from each other.
  • the horizontal transfer unit 104 sequentially transfers digital data supplied from the A / D conversion unit 103 via the signal line 123 to the storage unit 105 via the signal line 124.
  • the storage unit 105 stores and holds digital data supplied from the horizontal transfer unit 104.
  • the calculation unit 106 acquires (reads out) the digital data stored in the storage unit 105 via the signal line 126, performs simple image processing such as correlated double sampling (CDS (Correlated Sampling)), and the like. Generate data.
  • the calculation unit 106 outputs the generated pixel data to the outside of the image sensor 100 or the like via the signal line 126.
  • the control unit 111 controls the reference voltage generation unit 102 by supplying a control signal via the control line 131.
  • the control unit 111 controls the A / D conversion unit 103 by supplying a control signal via the control line 132.
  • the control unit 111 controls the horizontal transfer unit 104 by supplying a control signal through the control line 133.
  • the control unit 111 controls the arithmetic unit 106 by supplying a control signal via the control line 134, and the control unit 111 supplies a control signal via the control line 135 to thereby operate the vertical scanning unit. 112 is controlled.
  • the control unit 111 controls the operation of the entire image sensor 100 (operation of each part).
  • each of the control lines 131 to 135 described above is shown by one dotted line (dotted arrow), but these control lines are all configured by a plurality of control lines. It may be.
  • the vertical scanning unit 112 is controlled by the control unit 111 to control the operation of the transistors of each unit pixel of the pixel array 101 by supplying a control signal via the control lines 127-1 to 127-M.
  • the control lines 127-1 to 127 -M will be referred to as control lines 127 when it is not necessary to distinguish them from each other.
  • FIG. 1 A main configuration example of the pixel array 101 is shown in FIG. As described above, a plurality of unit pixels are arranged in a plane in the pixel region (pixel array 101).
  • M ⁇ N unit pixels 141 (unit pixels 141-11 to unit pixels 141-MN) are arranged in a matrix (array) of M rows and N columns (array). M and N are arbitrary natural numbers).
  • the unit pixels 141-11 to 141-MN are referred to as unit pixels 141 when it is not necessary to distinguish them from each other.
  • the arrangement of the unit pixels 141 is arbitrary, and may be an arrangement other than a matrix, such as a so-called honeycomb structure.
  • a vertical signal line 121 (vertical signal line 121-1 to vertical signal line 121-N) is formed for each column (column) of the unit pixel 141 (hereinafter also referred to as a unit pixel column). ing. Each vertical signal line 121 is connected to each unit pixel in a column (unit pixel column) corresponding to itself, and transmits a signal read from each unit pixel to the A / D conversion unit 103. Further, as shown in FIG. 3, a control line 127 (control lines 127-1 to 127-M) is formed for each row of unit pixels 141 (hereinafter also referred to as unit pixel row). Each control line 127 is connected to each unit pixel in the unit pixel row corresponding to itself, and transmits a control signal supplied from the vertical scanning unit 112 to each unit pixel.
  • the unit pixel 141 is connected to the vertical signal line 121 assigned to the column (unit pixel column) to which the unit pixel 141 belongs and the control line 127 assigned to the unit pixel row to which the unit pixel 141 belongs. Is driven based on a control signal supplied via the A, and supplies an electric signal obtained by itself to the A / D converter 103 via the vertical signal line 121.
  • control line 127 of each row is shown as a single line, but the control line 127 of each row may be composed of a plurality of control lines.
  • FIG. 4 is a diagram illustrating an example of a main configuration of the circuit configuration of the unit pixel 141.
  • the unit pixel 141 includes a photodiode (PD) 151, a transfer transistor 152, a reset transistor 153, an amplification transistor 154, and a select transistor 155.
  • PD photodiode
  • the photodiode (PD) 151 photoelectrically converts the received light into a photocharge (here, photoelectrons) having a charge amount corresponding to the light quantity, and accumulates the photocharge. The accumulated photocharge is read out at a predetermined timing.
  • the anode electrode of the photodiode (PD) 151 is connected to the ground (pixel ground) of the pixel region, and the cathode electrode is connected to the floating diffusion (FD) via the transfer transistor 152.
  • the cathode electrode of the photodiode (PD) 151 is connected to the power supply (pixel power supply) in the pixel region, the anode electrode is connected to the floating diffusion (FD) through the transfer transistor 152, and the photocharge is read as a photohole. It is good also as a system.
  • the transfer transistor 152 controls reading of photocharge from the photodiode (PD) 151.
  • the transfer transistor 152 has a drain electrode connected to the floating diffusion and a source electrode connected to the cathode electrode of the photodiode (PD) 151.
  • a transfer control line (TRG) for transmitting a transfer control signal supplied from the vertical scanning unit 112 is connected to the gate electrode of the transfer transistor 152. That is, this transfer control line (TRG) is included in the control line 127 of FIG.
  • the reset transistor 153 resets the potential of the floating diffusion (FD).
  • the reset transistor 153 has a drain electrode connected to the power supply potential and a source electrode connected to the floating diffusion (FD).
  • a reset control line (RST) that transmits a reset control signal supplied from the vertical scanning unit 112 is connected to the gate electrode of the reset transistor 153. That is, the reset control line (RST) is included in the control line 127 in FIG.
  • the amplification transistor 154 amplifies the potential change of the floating diffusion (FD) and outputs it as an electric signal (analog signal).
  • the amplification transistor 154 has a gate electrode connected to the floating diffusion (FD), a drain electrode connected to the source follower power supply voltage, and a source electrode connected to the drain electrode of the select transistor 155.
  • the amplification transistor 154 outputs the potential of the floating diffusion (FD) reset by the reset transistor 153 to the select transistor 155 as a reset signal (reset level).
  • the amplification transistor 154 outputs the potential of the floating diffusion (FD) to which the photocharge has been transferred by the transfer transistor 152 to the select transistor 155 as a light accumulation signal (signal level).
  • the select transistor 155 controls the output of the electrical signal supplied from the amplification transistor 154 to the vertical signal line (VSL) 121 (that is, the A / D conversion unit 103).
  • the select transistor 155 has a drain electrode connected to the source electrode of the amplification transistor 154 and a source electrode connected to the vertical signal line 121.
  • a select control line (SEL) for transmitting a select control signal supplied from the vertical scanning unit 112 is connected to the gate electrode of the select transistor 155. That is, this select control line (SEL) is included in the control line 127 of FIG.
  • the amplification transistor 154 and the vertical signal line 121 are electrically disconnected. Therefore, in this state, no reset signal, pixel signal, or the like is output from the unit pixel 141.
  • the select control line (SEL) is in the on state, the unit pixel 141 is in the selected state. That is, the amplification transistor 154 and the vertical signal line 121 are electrically connected, and a signal output from the amplification transistor 154 is supplied to the vertical signal line 121 as a pixel signal of the unit pixel 141. That is, a reset signal, a pixel signal, and the like are read from the unit pixel 141.
  • the A / D conversion unit 103 includes column A / D conversion units 161-1 to 161-N.
  • the column A / D conversion unit 161-1 to the column A / D conversion unit 161 -N are referred to as a column A / D conversion unit 161 when it is not necessary to distinguish them from each other.
  • the column A / D converter 161 is provided for each column (unit pixel column) of the pixel array 101.
  • each column A / D converter 161 receives a vertical signal of the column corresponding to itself.
  • the line 121 vertical signal line 121-1 to vertical signal line 121-N
  • the reference signal line 122 are connected.
  • Each column A / D converter 161 reads a signal read from the unit pixel 141 of the column corresponding to itself and supplied through the vertical signal line 121 of the column, and generates a reference voltage through the reference signal line 122.
  • a / D conversion is performed using the reference signal supplied from the unit 102.
  • each column A / D converter 161 is connected to a signal line 123 (signal line 123-1 to signal line 123-N) corresponding to itself.
  • Each column A / D conversion unit 161 supplies the A / D conversion result obtained by itself to the horizontal transfer unit 104 via the signal line 123 corresponding to the column A / D conversion unit 161.
  • a control line 132 (control line 132-1 to control line 132-N) is connected to each column A / D converter 161.
  • Each column A / D conversion unit 161 is driven based on a control signal (that is, control of the control unit 111) supplied from the control unit 111 via a control line 132 corresponding to the column A / D conversion unit 161.
  • the column A / D converter 161 performs A / D conversion by a two-step single slope A / D conversion method (two-step SS-ADC). More specifically, the column A / D converter 161 performs A / D conversion of upper bits in the low resolution mode (coarse mode) in the first step, and performs the high resolution mode (fine mode) in the second step. Performs A / D conversion of the lower bits with. That is, the column A / D conversion unit 161 specifies a range including the signal level of the input signal with coarse resolution, and then analyzes the signal level in detail with fine resolution for the range. By adopting such a two-step single slope A / D conversion method, the column A / D converter 161 is more efficient (faster) than the one-step single slope A / D conversion method. D conversion can be performed.
  • the column A / D conversion unit 161 includes a comparison unit 171, a counter 172, a capacitor 173, a charge storage unit 174, and a capacitance control unit 175.
  • the comparison unit 171 with two inputs and one output has its input terminal HiZ_VSL connected to the vertical signal line 121 of its corresponding column via the capacitor 173, and its input terminal HiZ_DAC is referenced via the charge storage unit 174. It is connected to the signal line 122 and its output terminal Vo is connected to the counter 172.
  • the comparison unit 171 receives an input signal (for example, an analog signal read from the unit pixel 141) input to the input terminal HiZ_VSL via the vertical signal line 121 and the capacitor 173, and the reference signal line 122 and the charge storage unit 174.
  • the reference signal input to the input terminal HiZ_DAC is compared (the signal level is compared), and the comparison result is output to the counter 172. That is, the comparison unit 171 outputs a signal indicating which signal level of the input signal or the reference signal is higher from the output terminal Vo and supplies the signal to the counter 172.
  • the signal indicating the comparison result is 1-bit digital data.
  • the value of the signal indicating the comparison result is “0”. In the opposite case, the value is “1”.
  • the method of taking the value of this signal may be reversed.
  • the bit length of the signal indicating the comparison result is arbitrary, and may be information composed of a plurality of bits.
  • the counter 172 has an input terminal connected to the output terminal Vo of the comparator 171 and an output terminal connected to the signal line 123 of the corresponding column.
  • the comparison result is supplied from the comparison unit 171 to the counter 172.
  • the counter 172 counts the time (for example, the number of clock signals) from the start of counting until the comparison result is inverted (the signal level of the output terminal Vo changes). Then, the counter 172 converts the count value up to that point when the comparison result is inverted as the A / D conversion result of the input signal (the signal input to the input terminal HiZ_VSL of the comparison unit 171) via the signal line 123. Output to the horizontal transfer unit 104.
  • the capacitor 173 is a capacitor having a fixed capacity (having a predetermined capacity) connected to the vertical signal line 121 and the input terminal HiZ_VSL of the comparison unit 171.
  • the charge storage unit 174 is a capacitor having a variable capacitance connected to the reference signal line 122 and the input terminal HiZ_DAC of the comparison unit 171.
  • the configuration of the charge storage unit 174 is arbitrary.
  • the charge storage unit 174 includes a plurality of capacitors (capacitors 181 to 185) having a fixed capacity and a plurality of switches (switches 191 to 195).
  • the capacitor 181 is a capacitor with a fixed capacity, one terminal of which is connected to the capacitor 185, the switch 191 and the switch 194 and the other terminal is connected to the input terminal HiZ_DAC of the comparison unit 171.
  • the capacitor 182 is a fixed-capacitance capacitor having one terminal connected to the switch 192, the switch 194, and the switch 195 and the other terminal connected to the input terminal HiZ_DAC of the comparison unit 171.
  • the capacitor 183 is a fixed capacitor having one terminal connected to the switch 193 and the switch 195 and the other terminal connected to the input terminal HiZ_DAC of the comparison unit 171.
  • the capacitor 184 is a capacitor with a fixed capacity, one terminal connected to the reference signal line 122 and the other terminal connected to the input terminal HiZ_DAC of the comparator 171.
  • the capacitor 185 is a capacitor with a fixed capacity, one terminal connected to the capacitor 181, the switch 191, and the switch 194, and the other terminal connected to the ground (GND).
  • the capacitance of these capacitors is
  • the switch 191 has one terminal connected to the reference signal line 122 and the other terminal connected to the capacitor 181, the capacitor 185, and the switch 194, and controls the connection between both terminals.
  • the switch 192 has one terminal connected to the reference signal line 122 and the other terminal connected to the capacitor 182, the switch 194, and the switch 195, and controls the connection between both terminals.
  • the switch 193 has one terminal connected to the reference signal line 122 and the other terminal connected to the capacitor 183 and the switch 195, and controls the connection between both terminals.
  • Switch 194 has one terminal connected to capacitor 181, capacitor 185, and switch 191, and the other terminal connected to capacitor 182, switch 192, and switch 195, and controls the connection between both terminals.
  • the switch 195 has one terminal connected to the capacitor 182, the switch 192, and the switch 194, and the other terminal connected to the capacitor 183 and the switch 193, and controls connection between both terminals.
  • the capacitors 181 to 184 are configured in parallel with each other between the reference signal line 122 and the input terminal HiZ_DAC of the comparator 171, and the switches 191 to 193 are respectively connected to the capacitors Connection between the reference numerals 181 to 183 and the reference signal line 122 is controlled. Then, when the switches 191 to 193 are turned on / off, the capacitance of the charge storage unit 174 (the capacitance between the reference signal line 122 and the input terminal HiZ_DAC of the comparison unit 171) is controlled.
  • the charge storage unit 174 having a variable capacity By applying the charge storage unit 174 having a variable capacity in this way, the signal level of the reference signal can be freely shifted as compared with the case of a fixed capacitor, so that the column A / D conversion unit 161 has a wider range.
  • a / D conversion can be performed using the reference signal.
  • the signal level of the reference signal can be arbitrarily shifted by the charge storage unit 174, so that the column A / D conversion unit 161 does not have any range of signals as the reference signal. / D conversion can be performed.
  • the column A / D converter 161 it is possible to design the column A / D converter 161 independently from the specification of the reference signal (that is, the specification of the reference voltage generator 102) (at least the reference signal of the design of the column A / D converter 161). Can be less dependent on specifications). Therefore, the degree of design freedom of the column A / D conversion unit 161 can be increased, the difficulty thereof can be reduced, and an increase in development and manufacturing costs can be suppressed.
  • the capacity control of the charge storage unit 174 can be performed at an arbitrary timing. For example, it can be performed for each step of A / D conversion (signal level comparison). Further, the slope of the waveform of the reference signal (ramp wave) can be controlled by controlling the capacity of the charge storage unit 174. That is, for example, the A / D conversion range of each step can be controlled by the capacity control of the charge storage unit 174. In other words, a multi-step single slope A / D conversion method can be realized by controlling the capacity of the charge storage unit 174.
  • the capacitance of the charge storage unit 174 (capacitance between the reference signal line 122 and the input terminal HiZ_DAC of the comparison unit 171) is the capacitance when the switches 191 to 193 are all in the on state (the two terminals are connected). It becomes the same as the capacity of 173. This state is referred to as state 0.
  • state 1 When only the switch 191 is turned off (between both terminals), the capacitor 181 is disconnected from the reference signal line 122.
  • state 1 In the case of state 1, the capacity of the charge storage unit 174 is 1 ⁇ 2 that of state 0. Therefore, in the case of the state 1, the range width and the slope of the reference signal (ramp wave) input to the input terminal HiZ_DAC of the comparison unit 171 are 1 ⁇ 2 of the state 0.
  • the charge storage unit 174 is set to state 0 in the first step (coarse mode) comparison, and the charge storage unit 174 is set to state 1 in the second step (fine mode) comparison.
  • the charge storage unit 174 is set to state 0 in the first step (coarse mode) comparison, and the charge storage unit 174 is set to state 1 in the second step (fine mode) comparison.
  • the offset of the reference signal of the second step according to the comparison result of the first step, the slope of the reference signal waveform is not changed between the first step and the second step.
  • a coarse mode a two-step single slope A / D conversion system that performs 1-bit A / D conversion can be realized.
  • the charge storage unit 174 is set to the state 0 and the comparison is started.
  • the charge storage portion 174 may be set to the state 1 at a timing corresponding to the inversion timing of. In this way, the signal level of the reference signal becomes a value corresponding to the inversion timing of the comparison result, and the value is reflected in the offset of the reference signal at the second step. That is, the offset of the reference signal at the second step is set according to the comparison result at the first step.
  • state 2 When the switch 191 and the switch 192 are turned off (between both terminals), the capacitor 181 and the capacitor 182 are disconnected from the reference signal line 122.
  • This state is referred to as state 2.
  • the capacity of the charge storage unit 174 is 1/4 that of the state 0. Therefore, in the case of the state 2, the range width and the slope of the reference signal (ramp wave) input to the input terminal HiZ_DAC of the comparison unit 171 are 1/4 of the state 0.
  • the charge storage unit 174 is set to state 0 in the first step (coarse mode) comparison, and the charge storage unit 174 is set to state 2 in the second step (fine mode) comparison.
  • the offset of the reference signal of the second step according to the comparison result of the first step, the slope of the reference signal waveform is not changed between the first step and the second step.
  • a coarse mode a two-step single slope A / D conversion system that performs 2-bit A / D conversion can be realized.
  • the charge storage unit 174 is set to the state 0 and the comparison is started.
  • the charge storage unit 174 may be set to the state 2 at a timing corresponding to the inversion timing of. In this way, the signal level of the reference signal becomes a value corresponding to the inversion timing of the comparison result, and the value is reflected in the offset of the reference signal at the second step. That is, the offset of the reference signal at the second step is set according to the comparison result at the first step.
  • state 3 When the switches 191 to 193 are turned off (between both terminals), the capacitors 181 to 183 are disconnected from the reference signal line 122.
  • This state is referred to as state 3.
  • the capacity of the charge storage unit 174 is 1/8 of the state 0. Therefore, the range width and slope of the reference signal (ramp wave) input to the input terminal HiZ_DAC of the comparison unit 171 are 1/8 of the state 0.
  • the charge storage unit 174 is set to state 0 in the first step (coarse mode) comparison, and the charge storage unit 174 is set to state 3 in the second step (fine mode) comparison.
  • the charge storage unit 174 is set to state 0 in the first step (coarse mode) comparison, and the charge storage unit 174 is set to state 3 in the second step (fine mode) comparison.
  • the offset of the reference signal of the second step according to the comparison result of the first step, the slope of the reference signal waveform is not changed between the first step and the second step.
  • a coarse mode a two-step single slope A / D conversion system that performs 3-bit A / D conversion can be realized.
  • the charge storage unit 174 is set to the state 0 and the comparison is started.
  • the charge storage unit 174 may be set to the state 3 at a timing corresponding to the inversion timing of. In this way, the signal level of the reference signal becomes a value corresponding to the inversion timing of the comparison result, and the value is reflected in the offset of the reference signal at the second step. That is, the offset of the reference signal at the second step is set according to the comparison result at the first step.
  • the column A / D converter 161 selects the switch to be turned off (selects which of the switches 191 to 193 is turned off), so that the resolution of the coarse mode is 1 as described above. From the case of bits to the case of 3 bits can be handled (a 2-step single slope A / D conversion method can be realized). That is, the column A / D converter 161 can cope with various resolutions in the coarse mode.
  • the configuration of the charge storage unit 174 is arbitrary, and the number of capacitors and switches is also arbitrary. That is, the column A / D conversion unit 161 can correspond to a coarse mode with an arbitrary resolution, and can also correspond to a coarse mode with an arbitrary number of resolutions.
  • state 4 in which the capacity of charge storage unit 174 is 1/16 of state 0 is set.
  • the charge storage unit 174 may be set to the state 4 in the comparison in the second step (fine mode).
  • the capacity of the charge storage unit 174 becomes 1/32 of the state 0.
  • the state 5 is provided, and the charge storage unit 174 may be set to the state 5 in the comparison of the second step (fine mode).
  • the column A / D conversion unit 161 can adopt a more appropriate A / D conversion method according to, for example, the operation mode and the like. A / D conversion can be performed.
  • the image sensor 100 can capture both a moving image and a still image.
  • still images are required to have higher image quality than moving images.
  • the A / D conversion of a still image has a higher resolution than the A / D conversion of a moving image.
  • the column A / D converter 161 selects a switch to be turned off, and the resolution of the coarse mode when A / D converting a still image is higher than the resolution of the coarse mode in the case of a moving image. By doing so, it is possible to improve the image quality of a still image more easily than a moving image.
  • a single slope A / D conversion method of 3 steps or more can be easily realized.
  • the charge storage unit 174 is set to state 0 in the first step comparison
  • the charge storage unit 174 is set to state 1 in the second step comparison
  • the charge storage unit 174 is set to state 2 in the third step comparison.
  • the offset of the reference signal at the second step is set according to the comparison result at the first step
  • the offset of the reference signal at the third step is set according to the comparison result at the second step.
  • a three-step single slope A / D conversion method can be easily realized without changing the slope of the waveform of the reference signal at each step.
  • the method of setting the offset is the same as in the above-described example.
  • the case of four steps or more can be similarly realized.
  • the range width and inclination of the reference signal (ramp wave) input to the input terminal HiZ_DAC of the comparison unit 171 can be arbitrarily controlled by the capacitance control of the charge storage unit 174. . Therefore, it is not necessary to change the slope of the waveform of the reference signal (ramp wave) output from the reference voltage generator 102 for each step. In other words, the reference voltage generator 102 may output a ramp wave having the same slope at each step. Therefore, the function required for the reference voltage generator 102 is reduced, and the design of the reference voltage generator 102 becomes easier. For example, since a special specification is unnecessary for the reference voltage generation unit 102, a more general-purpose reference voltage generation unit 102 can be applied. Further, the configuration of the reference voltage generation unit 102 can be further simplified, and an increase in circuit scale and power consumption can be suppressed.
  • the charge storage unit 174 by configuring the charge storage unit 174 with a plurality of capacitors and a plurality of switches, the above-described capacitance control can be more easily realized. Therefore, an increase in the circuit scale of the column A / D conversion unit 161 can be suppressed.
  • the capacitor 185 is a capacitor that holds the potential of the reference signal (sample and hold) in the initial state.
  • the capacitance of the capacitor 185 is arbitrary as long as it is sufficiently large (for example, it may be about 100 fF to 1 pF).
  • the switch 191 is turned off and the capacitor 181 disconnected from the reference signal line 122 is connected to the capacitor 185, so that kTC noise can be suppressed.
  • the switch 194 and the switch 195 control the connection between the capacitor 182 and the capacitor 183 and the capacitor 185 by controlling the connection between the capacitors 181 to 183.
  • the switch 191 and the switch 192 may be turned off and the switch 194 may be turned on. Thereby, the capacitor 181 and the capacitor 182 separated from the reference signal line 122 are connected to the capacitor 185, so that kTC noise can be suppressed.
  • the switches 191 to 193 may be turned off and the switches 194 and 195 may be turned on. Accordingly, the capacitors 181 to 183 separated from the reference signal line 122 are connected to the capacitor 185, so that kTC noise can be suppressed.
  • the capacity control unit 175 controls the switches 191 to 195 based on a control signal supplied from the control unit 111 via the control line 132 (in accordance with control of the control unit 111).
  • the capacity control unit 175 turns the switch 191 on or off by supplying a control signal to the switch 191 via the control line SW1.
  • the capacity control unit 175 turns the switch 192 on or off by supplying a control signal to the switch 192 via the control line SW2.
  • the capacity control unit 175 turns on or off the switch 193 by supplying a control signal to the switch 193 via the control line SW3.
  • the capacity control unit 175 turns the switch 194 on or off by supplying a control signal to the switch 194 via the control line SW2 ′.
  • the capacity control unit 175 supplies the control signal to the switch 195 via the control line SW3 ′, thereby turning on or off the switch 195.
  • the output terminal Vo of the comparison unit 171 is also connected to the capacity control unit 175. That is, the signal indicating the comparison result output from the comparison unit 171 is also supplied to the capacity control unit 175.
  • the capacity control unit 175 controls the switches 191 to 195 according to the comparison result.
  • the capacity control unit 175 can control the capacity of the charge storage unit 174 in the second step comparison, for example, based on the first step comparison result.
  • the resolution in the low resolution (coarse) mode is 1 bit
  • the resolution in the high resolution (fine) mode is Q bits (Q is an arbitrary natural number).
  • a post-trigger method in which capacity control is performed after the comparison result in the first step is reversed is applied.
  • the vertical scanning unit 112 sets a unit pixel row to be processed (also referred to as a processing target unit pixel row) from an unprocessed unit pixel row of the pixel array 101 in step S101 of FIG. Select a row.
  • a unit pixel row to be processed also referred to as a processing target unit pixel row
  • step S102 the vertical scanning unit 112 controls each unit pixel 141 in the processing target unit pixel row of the pixel array 101 in the reset period, causes the reset signal to be read from each unit pixel 141, and the A / D conversion unit. 103.
  • step S103 the capacity control unit 175 of each column A / D conversion unit 161 turns on the switches 191 to 193, turns off the switches 194 and 195, and sets all the capacitors (capacitors 181 to 181) of the charge storage unit 174.
  • the capacitor 184) is connected to the reference signal line (Ramp) 122.
  • step S104 the reference voltage generator 102 sets the signal level of the reference signal (Ramp) to an initial value for the low resolution mode. After the initial value is set (time T1 (FIG. 9)), the reference voltage generator 102 starts outputting a ramp wave reference signal (Ramp). In the case of the example in FIG. 9, the amplitude of the reference signal (Ramp) is A in the low resolution mode.
  • step S105 the comparison unit 171 and the counter 172 perform A / D conversion on the reset signal read in step S102 in the low resolution mode using the reference signal input via the charge storage unit 174 (time T1 to time T1). Time T3 (FIG. 9)).
  • step S106 the capacitance control unit 175 controls the switches 191 to 195 after the comparison result between the reset signal and the reference signal is inverted (the signal level of the output terminal Vo is changed), and among the capacitors 181 to 184, The capacitor is disconnected from the reference signal line 122 according to the resolution in the low resolution mode and connected to the sample and hold capacitor 185.
  • the capacity control unit 175 switches the time T2, which is the next count timing, to a timing corresponding to the inversion timing of the comparison result, and turns off the value of the control signal on the control line SW1 at the time T2. 191 is turned off, and the capacitor 181 is disconnected from the reference signal line 122.
  • the capacitance control unit 175 cuts only the capacitor 181 and reduces the capacitance of the charge storage unit 174 to 1 ⁇ 2. At that time, since the capacitor 181 is connected to the capacitor 185, kTC noise is suppressed.
  • the slope of the reference signal input to the input terminal HiZ_DAC of the comparison unit 171 after time T2 is 1 ⁇ 2 of that.
  • step S107 the counter 172 supplies the count value until the comparison result is inverted to the horizontal transfer unit 104 as the upper bits of the A / D conversion result in the reset period.
  • the horizontal transfer unit 104 supplies the high-order bits of the supplied A / D conversion result during the reset period of each column to the storage unit 105 for storage.
  • the reference voltage generator 102 sets the signal level of the reference signal (Ramp) to the initial value for the high resolution mode.
  • the initial value of the signal level of the reference signal (Ramp) is the count value immediately before the timing when the initial value of the input terminal HiZ_DAC signal level of the comparison unit 171 is inverted in the low resolution (coarse) mode.
  • the signal level may be higher than the signal level.
  • the initial value of the signal level of the reference signal (Ramp) is set so that the initial value of the signal level of the input terminal HiZ_DAC of the comparison unit 171 becomes larger than the signal level at the time T1.
  • the reference voltage generator 102 starts outputting the reference signal (Ramp).
  • the amplitude of the reference signal (Ramp) in the high resolution (fine) mode is set to A ⁇ (1 + 1/2).
  • the slope of the reference signal input to the input terminal HiZ_DAC of the comparison unit 171 is halved by the capacitance control of the charge storage unit 174, it is input to the input terminal HiZ_DAC of the comparison unit 171.
  • the amplitude of the reference signal is amplitude A ⁇ (1 + 1/2) / 2.
  • the amplitude of the reference signal (Ramp) in the high resolution (fine) mode is A ⁇ (1+ (2 N -1) / 2 N ).
  • the amplitude of the reference signal of the input terminal HiZ_DAC of the comparison unit 171 in the high resolution (fine) mode is at least the reference signal of the input terminal HiZ_DAC of the comparison unit 171 at the timing when the comparison result in the low resolution (coarse) mode is inverted.
  • the signal level may be included.
  • step S109 the comparison unit 171 and the counter 172 use the reference signal (Ramp) to A / D-convert the reset signal read in step S102 in the high resolution mode (from time T4 to time T5 (FIG. 9)).
  • step S110 the counter 172 supplies the count value until the comparison result is inverted (the signal level of the output terminal Vo changes) to the horizontal transfer unit 104 as the lower bits of the A / D conversion result in the reset period.
  • the horizontal transfer unit 104 supplies the low-order bits of the supplied A / D conversion result during the reset period of each column to the storage unit 105 for storage.
  • step S110 When the process of step S110 is completed, the process proceeds to FIG. The same processing is performed for the signal readout period.
  • the vertical scanning unit 112 controls each unit pixel 141 of the processing target unit pixel row of the pixel array 101 and reads out a pixel signal from each unit pixel 141 in the signal readout period. , Supplied to the A / D converter 103.
  • step S122 the capacity control unit 175 of each column A / D conversion unit 161 turns on the switches 191 to 193, turns off the switches 194 and 195, and sets all the capacitors (capacitors 181 to 181) of the charge storage unit 174.
  • the capacitor 184) is connected to the reference signal line (Ramp) 122.
  • step S123 the reference voltage generator 102 sets the signal level of the reference signal (Ramp) to the initial value for the low resolution mode. After the initial value is set (time T11 (FIG. 10)), the reference voltage generator 102 starts outputting the reference signal (Ramp). As shown in FIG. 10, the amplitude of the reference signal (Ramp) is B in the low-resolution mode in the signal readout period as in the reset period.
  • step S124 the comparison unit 171 and the counter 172 perform A / D conversion on the pixel signal read in step S121 in the low resolution mode using the reference signal input via the charge storage unit 174 (from time T11 to time T11). Time T13 (FIG. 10)).
  • step S125 the capacitance control unit 175 controls the switches 191 to 195 after the comparison result between the reset signal and the reference signal is inverted (the signal level of the output terminal Vo is changed), and among the capacitors 181 to 184, The capacitor is disconnected from the reference signal line 122 according to the resolution in the low resolution mode and connected to the sample and hold capacitor 185.
  • the comparison result is inverted (the signal level of the output terminal Vo is changed) between time T12 and time T13. Therefore, the capacitance control unit 175 turns off the switch 191 by turning off the value of the control signal on the control line SW1 at the next count timing T13, and disconnects the capacitor 181 from the reference signal line 122.
  • the capacitance control unit 175 cuts only the capacitor 181 and reduces the capacitance of the charge storage unit 174 to 1 ⁇ 2. At that time, since the capacitor 181 is connected to the capacitor 185, kTC noise is suppressed.
  • the slope of the reference signal input to the input terminal HiZ_DAC of the comparison unit 171 in the fine mode of the second step is 1 ⁇ 2 of that.
  • step S126 the counter 172 supplies the count value until the comparison result is inverted to the horizontal transfer unit 104 as the upper bits of the A / D conversion result in the signal readout period.
  • the horizontal transfer unit 104 supplies the high-order bits of the A / D conversion result of the supplied signal readout period of each column to the storage unit 105 for storage.
  • step S127 the reference voltage generation unit 102 sets the signal level of the reference signal (Ramp) to the initial value for the high resolution mode.
  • the initial value of the signal level of the reference signal (Ramp) is the count timing immediately before the timing when the initial value of the signal level of the input terminal HiZ_DAC of the comparator 171 is inverted in the low resolution (coarse) mode.
  • the signal level may be higher than the signal level at.
  • the initial value of the signal level of the reference signal (Ramp) may be set so that the initial value of the signal level of the input terminal HiZ_DAC of the comparison unit 171 is higher than the signal level at the time T12. .
  • the reference voltage generator 102 starts outputting the reference signal (Ramp).
  • the amplitude of the reference signal (Ramp) in the high resolution (fine) mode is B ⁇ (1+ (2N -1) / 2N).
  • the amplitude of this high resolution (fine) mode may be B as is the case with the amplitude of the low resolution (coarse) mode.
  • the amplitude of the reference signal of the input terminal HiZ_DAC of the comparison unit 171 in the high resolution (fine) mode is set to include at least the signal level of the reference signal at the timing when the comparison result in the low resolution (coarse) mode is inverted. That's fine.
  • step S128 the comparison unit 171 and the counter 172 perform A / D conversion on the reset signal read in step S102 in the high resolution mode using the reference signal (Ramp) (time T14 to time T14). T15 (FIG. 10)).
  • step S129 the counter 172 supplies the count value until the comparison result is inverted (the signal level of the output terminal Vo is changed) to the horizontal transfer unit 104 as the lower bits of the A / D conversion result in the signal readout period.
  • the horizontal transfer unit 104 supplies the storage unit 105 with the lower bits of the supplied A / D conversion result during the signal readout period of each column, and stores the result.
  • step S130 the arithmetic unit 106 stores the upper bits of the A / D conversion result in the reset period stored in step S107 and the lower bits of the A / D conversion result in the reset period stored in step S110. Are read out and combined to generate an A / D conversion result in the reset period. Further, the arithmetic unit 106 stores the upper bits of the A / D conversion result of the signal readout period stored in step S126 and the lower bits of the A / D conversion result of the signal readout period stored in step S129. Are combined and combined to generate an A / D conversion result in the signal readout period.
  • the calculation unit 106 further performs CDS by subtracting the A / D conversion result in the reset period from the A / D conversion result in the generated signal readout period, and obtains the A / D conversion result of the pixel signal.
  • the arithmetic unit 106 performs such processing for all the columns, and obtains an A / D conversion result of the pixel signal.
  • step S131 the vertical scanning unit 112 determines whether or not all unit pixel rows have been processed. If it is determined that there are unprocessed unit pixel rows, the process returns to step S101 in FIG. The subsequent processing is repeated.
  • each processing unit of the image sensor 100 repeats the processes in steps S101 to S131 for each unit pixel row. If it is determined in step S131 that all unit pixel rows have been processed, the imaging process ends.
  • the offset and width of the signal level of the reference signal input to the comparison unit can be controlled by the capacitance of the charge storage unit 174. That is, the reference voltage generation unit 102 and the column A / D conversion unit 161 can be designed independently of each other. Therefore, these designs are facilitated, and an increase in development and manufacturing costs can be suppressed.
  • Second Embodiment> ⁇ Coarse mode resolution>
  • the A / D conversion resolution (number of bits) in the low resolution mode (coarse mode) has been described as 1 bit.
  • the A / D conversion in the coarse mode is performed.
  • the resolution can be a plurality of bits.
  • the imaging process is executed as shown in the flowcharts of FIGS.
  • the timing chart of the signal level of each terminal in this case is shown in FIG. 11 and FIG.
  • processing is basically performed in the same manner as when the coarse mode A / D conversion resolution is 1 bit, but in the case of FIG. 11 (reset period), comparison is made between time T22 and time T23. The result is reversed. Therefore, the capacity control unit 175 sets time T23, which is the next count timing, as a timing corresponding to the inversion timing of the comparison result, and turns off the control signal values of the control line SW1 and the control line SW2 at the time T23.
  • the switch 191 and the switch 192 are turned off, the capacitor 181 and the capacitor 182 are disconnected from the reference signal line 122, and the capacitance of the charge storage portion 174 is set to 1/4.
  • the capacitor 181 is connected to the capacitor 185, and the capacitance control unit 175 turns on the switch 194 by turning on the value of the control signal of the control line SW 2 ′. Since the capacitor 185 is connected, kTC noise is suppressed.
  • the initial value of the signal level of the reference signal (Ramp) in the fine mode is set such that the initial value of the signal level of the input terminal HiZ_DAC of the comparison unit 171 is higher than the signal level at the time T22. Even in the fine mode, the range width and inclination of the reference signal input to the input terminal HiZ_DAC of the comparison unit 171 are 1/4 before time T23.
  • the capacitance control unit 175 sets the time T34, which is the next count timing, as a timing corresponding to the inversion timing of the comparison result, and turns off the control signal values of the control line SW1 and the control line SW2 at the time T34.
  • the switch 191 and the switch 192 are turned off, the capacitor 181 and the capacitor 182 are disconnected from the reference signal line 122, and the capacitance of the charge storage portion 174 is set to 1/4.
  • the capacitor 181 is connected to the capacitor 185, and the capacitance control unit 175 turns on the switch 194 by turning on the value of the control signal of the control line SW 2 ′. Since the capacitor 185 is connected, kTC noise is suppressed.
  • the initial value of the signal level of the fine mode reference signal (Ramp) is set so that the initial value of the signal level of the input terminal HiZ_DAC of the comparison unit 171 is higher than the signal level at the time T33. Even in the fine mode, the range width and slope of the reference signal input to the input terminal HiZ_DAC of the comparison unit 171 are 1/4 before time T34.
  • the image sensor 100 (column A / D conversion unit 161) can similarly suppress an increase in cost even when the resolution of the coarse mode is 2 bits.
  • the resolution in the low resolution (coarse) mode is 1 bit
  • the resolution in the high resolution (fine) mode is Q bits (Q is an arbitrary natural number).
  • a post-trigger method in which capacity control is performed after the comparison result in the first step is reversed is applied.
  • the imaging process is executed basically in the same manner as described with reference to the flowcharts shown in FIGS. That is, the processes in steps S301 to S307 in FIG. 13 are executed in the same manner as the processes in steps S101 to S107 in FIG.
  • step S308 the reference voltage generator 102 reverses the direction of the reference signal (Ramp) instead of setting the initial value of the reference signal.
  • step S309 and step S310 are performed similarly to each process of step S109 and step S110 of FIG.
  • the slope of the ramp wave of the reference signal is opposite to that in the coarse mode.
  • step S310 ends, the process proceeds to FIG.
  • step S327 the reference voltage generation unit 102 inverts the direction of the reference signal (Ramp) instead of setting the initial value of the reference signal.
  • step S328 to step S330 is executed in the same manner as each processing from step S128 to step S130 in FIG.
  • step S331 the reference voltage generator 102 reverses the direction of the reference signal (Ramp) instead of setting the initial value of the reference signal.
  • step S332 the vertical scanning unit 112 determines whether or not all unit pixel rows have been processed. If it is determined that there are unprocessed unit pixel rows, the process returns to step S301 in FIG. The subsequent processing is repeated.
  • each processing unit of the image sensor 100 repeats each process from step S301 to step S332 for each unit pixel row. If it is determined in step S332 that all unit pixel rows have been processed, the imaging process ends.
  • the signal level offset and range width of the reference signal input to the comparison unit 171 can be controlled by the capacitance of the charge storage unit 174 in this case as well. That is, the reference voltage generation unit 102 and the column A / D conversion unit 161 can be designed independently of each other. Therefore, these designs are facilitated, and an increase in development and manufacturing costs can be suppressed.
  • the count of the time until the comparison result is reversed is the time when the slope is changed as the start time.
  • the resolution in the low resolution (coarse) mode is 2 bits
  • the resolution in the high resolution (fine) mode is Q bits (Q is an arbitrary natural number).
  • a pre-trigger method in which the capacity control is performed before the comparison result in the second step is reversed is applied.
  • the imaging process is executed basically in the same manner as described with reference to the flowcharts shown in FIGS. That is, the processes in steps S401 to S403 in FIG. 17 are executed in the same manner as the processes in steps S101 to S103 in FIG.
  • step S404 the reference voltage generator 102 sets the signal level of the reference signal (Ramp) to an initial value.
  • step S405 the comparison unit 171 and the counter 172 A / D convert the reset signal read in step S302 in the low resolution mode (coarse mode) using the reference signal input via the charge storage unit 174. (Time T61 to Time T65 (FIG. 19)).
  • step S406 the counter 172 supplies the count value until the comparison result is inverted to the horizontal transfer unit 104 as the upper bits of the A / D conversion result in the reset period.
  • the horizontal transfer unit 104 supplies the high-order bits of the supplied A / D conversion result during the reset period of each column to the storage unit 105 for storage.
  • step S407 the reference voltage generation unit 102 sets the signal level of the reference signal (Ramp) to an initial value.
  • step S408 the comparison unit 171 and the counter 172 A / D convert the reset signal read in step S302 in the high resolution mode (fine mode) using the reference signal input through the charge storage unit 174. (Time T66 to Time T68 (FIG. 19)). However, at the time when the A / D conversion is started, the slope of the reference signal remains in the coarse mode.
  • step S409 the capacitance control unit 175 controls the switches 191 to 195 before the comparison result between the reset signal and the reference signal is inverted (the signal level of the output terminal Vo changes), and the capacitors 181 to 184 are controlled. Among them, the capacitor is disconnected from the reference signal line 122 in accordance with the resolution in the low resolution mode and connected to the sample and hold capacitor 185.
  • the capacity control unit 175 sets time T67, which is the previous count timing, as a timing according to the inversion timing of the comparison result, and turns off the control signal values of the control line SW1 and the control line SW2 at the time T67.
  • the switch 191 and the switch 192 are turned off, and the capacitor 181 and the capacitor 182 are disconnected from the reference signal line 122.
  • the capacitance control unit 175 disconnects the capacitor 181 and the capacitor 182 to make the capacitance of the charge storage unit 174 1/4.
  • the capacitor 181 is connected to the capacitor 185, and the capacitance control unit 175 further turns on the switch 194 and connects the capacitor 182 to the capacitor 185, so that kTC noise is suppressed.
  • step S410 the counter 172 obtains the lower bits of the A / D conversion result in the reset period from the count value until the comparison result is inverted, and supplies it to the horizontal transfer unit 104.
  • the horizontal transfer unit 104 supplies the high-order bits of the supplied A / D conversion result during the reset period of each column to the storage unit 105 for storage.
  • the processing in the signal readout period is basically the same as the processing in the reset period, except that a pixel signal is read from the unit pixel instead of the reset signal, and the pixel signal is A / D converted.
  • steps S421 to S429 in FIG. 18 are executed basically in the same manner as the processes in steps S402 to S410 in FIG.
  • a / D conversion of the pixel signal in the coarse mode is performed, and inversion of the comparison result is detected between time T72 and time T73. Then, fine mode A / D conversion is started from time T76 to time T78.
  • the capacity control unit 175 sets time T77, which is the previous count timing, as a timing according to the inversion timing of the comparison result, and turns off the control signal values of the control line SW1 and the control line SW2 at the time T77.
  • the switch 191 and the switch 192 are turned off, and the capacitor 181 and the capacitor 182 are disconnected from the reference signal line 122.
  • the capacitance control unit 175 disconnects the capacitor 181 and the capacitor 182 to make the capacitance of the charge storage unit 174 1/4.
  • the capacitor 181 is connected to the capacitor 185, and the capacitance control unit 175 further turns on the switch 194 and connects the capacitor 182 to the capacitor 185, so that kTC noise is suppressed.
  • step S430 the arithmetic unit 106 stores the upper bits of the A / D conversion result in the reset period stored in step S406 and the lower bits of the A / D conversion result in the reset period stored in step S410. Are read out and combined to generate an A / D conversion result in the reset period. Further, the arithmetic unit 106 stores the upper bits of the A / D conversion result of the signal readout period stored in step S425 and the lower bits of the A / D conversion result of the signal readout period stored in step S429. Are combined and combined to generate an A / D conversion result in the signal readout period.
  • the calculation unit 106 further performs CDS by subtracting the A / D conversion result in the reset period from the A / D conversion result in the generated signal readout period, and obtains the A / D conversion result of the pixel signal.
  • the arithmetic unit 106 performs such processing for all the columns, and obtains an A / D conversion result of the pixel signal.
  • step S431 the vertical scanning unit 112 determines whether or not all unit pixel rows have been processed. If it is determined that there are unprocessed unit pixel rows, the process returns to step S401 in FIG. The subsequent processing is repeated.
  • each processing unit of the image sensor 100 repeats each process from step S401 to step S431 for each unit pixel row. If it is determined in step S431 that all the unit pixel rows have been processed, the imaging process ends.
  • the signal level offset and range width of the reference signal input to the comparison unit 171 can be controlled by the capacitance of the charge storage unit 174 in this case as well. That is, the reference voltage generation unit 102 and the column A / D conversion unit 161 can be designed independently of each other. Therefore, these designs are facilitated, and an increase in development and manufacturing costs can be suppressed.
  • the configuration of the column A / D conversion unit 161 is not limited to the above-described example.
  • the capacitor 185 is used as a capacitor for holding the signal level of the reference signal.
  • a plurality of holding capacitors may exist.
  • the column A / D conversion unit 161 is provided with one storage capacitor (capacitor 581 to capacitor 583) for each of the capacitors 181 to 183.
  • a portion 574 may be included. In this case, the switch 194 and the switch 195 can be omitted.
  • the column A / D conversion unit 161 includes a capacity control unit 575 instead of the capacity control unit 175.
  • the capacitance control unit 575 controls the switches 191 to 193 of the charge storage unit 574. That is, since the switch 194 and the switch 195 are not present in the charge storage unit 574, the capacitance control unit 575 does not control them.
  • the column A / D converter 161 can suppress kTC noise without switch control.
  • the count time is 2 n .
  • the amplitude of the second step is twice the amplitude of the first step, that is, the count time. Is doubled. Therefore, for the count time 2 ⁇ ((n-1) / 2) of the first step, the count time of the second step is 2 ⁇ 2 ⁇ ((n-1) / 2), and the count time is 3/2 ⁇ 2 ⁇ ((n + 1) / 2).
  • the processing time can be greatly reduced compared to the case of the one-step type single slope A / D conversion method.
  • the difference in processing time increases as the A / D conversion resolution increases, as shown in the graph of FIG. For example, when the resolution is 14 bits, the count time is 16384 counts in the one-step single slope A / D conversion method, but 272 counts in the two-step single slope A / D conversion method. In this way, when the resolution is high bits, the processing time can be shortened significantly.
  • the capacity of the charge storage unit 174 may be changed for each column A / D conversion unit 161.
  • a part or all of the capacitors of the charge storage unit 174 of at least one column A / D conversion unit 161 may be different from the charge storage unit 174 of other column A / D conversion units 161.
  • the capacitor configuration (number, arrangement, etc.) of the charge storage unit 174 of at least one column A / D conversion unit 161 may be different from the charge storage unit 174 of other column A / D conversion units 161. Good.
  • the method of controlling the capacity of the charge storage unit 174 performed for each step as described above is different from the charge storage unit 174 of the other column A / D conversion units 161. It may be.
  • the resolution in the high resolution mode is Q bits, but the resolution in this mode is arbitrary.
  • the amplitude, slope, and count time of the reference signal in the high resolution mode are all arbitrary.
  • the clock width of the counter is also arbitrary. This clock width may be changed for each mode, or may be common to all modes. These parameters are related to each other, but other parameters may be set based on any parameter. It is sufficient that at least the signal level at which the comparison result is inverted can be A / D converted with high accuracy.
  • the image sensor 100 may not perform CDS.
  • the column A / D conversion unit 161 performs A / D conversion only on the pixel signal read from the pixel array 101.
  • the column A / D converter 161 performs A / D conversion in the coarse mode and the fine mode.
  • the charge storage unit 174 may include a capacitor with a variable capacitance instead of the above-described configuration including a plurality of capacitors and a plurality of switches.
  • the column A / D conversion unit 161 of each column has been described as having the counter 172.
  • the present invention is not limited to this, and the counter 172 is provided outside the column A / D conversion unit 161.
  • the column A / D converter 161 may share the same counter 172. By doing so, an increase in circuit scale can be suppressed.
  • the counting method of the counter 172 is a pre-counting method for counting until Vo is inverted.
  • the counting method of the counter 172 is arbitrary, and methods other than the pre-counting method It can also be adopted. For example, a post-count method that counts after Vo is inverted may be used, or a method that combines a plurality of methods (for example, a pre-count method and a post-count method) may be used.
  • an imaging element to which the present technology is applied can be realized, for example, as a package (chip) in which a semiconductor substrate is sealed, a module in which the package (chip) is installed on a circuit board, or the like.
  • the imaging element in the package (chip) may be configured by a single semiconductor substrate, or may be configured by a plurality of semiconductor substrates superimposed on each other. It may be.
  • FIG. 23 is a diagram illustrating an example of a physical configuration of the image sensor 100 that is an imaging device to which the present technology is applied.
  • the circuit configuration of the image sensor 100 described with reference to FIG. 2 and the like is all formed on a single semiconductor substrate.
  • output units 604-1 to 604-4 are arranged so as to surround the pixel / analog processing unit 601, the digital processing unit 602, and the frame memory 603.
  • the pixel / analog processing unit 601 is a region where an analog configuration such as the pixel array 101 and the A / D conversion unit 103 is formed.
  • the output units 604-1 to 604-4 are areas in which, for example, configurations such as I / O cells are arranged.
  • the circuit configuration of the image sensor 100 described with reference to FIG. 2 and the like includes two semiconductor substrates (laminated substrates (a pixel substrate 611 and a circuit substrate 612)) superimposed on each other. Formed.
  • a pixel / analog processing unit 601, a digital processing unit 602, an output unit 604-1 and an output unit 604-2 are formed on the pixel substrate 611.
  • the output unit 604-1 and the output unit 604-2 are regions in which, for example, configurations such as I / O cells are arranged.
  • a frame memory 603 is formed on the circuit board 612.
  • the pixel substrate 611 and the circuit substrate 612 overlap each other to form a multilayer structure (laminated structure).
  • the pixel / analog processing unit 601 formed on the pixel substrate 611 and the frame memory 603 formed on the circuit substrate 612 are formed in the via region (VIA) 613-1 and the via region (VIA) 614-1. They are electrically connected to each other through through vias (VIA) or the like.
  • the digital processing unit 602 formed on the pixel substrate 611 and the frame memory 603 formed on the circuit substrate 612 are formed in the via region (VIA) 613-2 and the via region (VIA) 614-2. They are electrically connected to each other through through vias (VIA) or the like.
  • the number (number of layers) of the semiconductor substrates (laminated chips) is arbitrary, and may be, for example, three or more layers as shown in FIG.
  • the image sensor 100 includes a semiconductor substrate 621, a semiconductor substrate 622, and a semiconductor substrate 623.
  • the semiconductor substrates 621 to 623 overlap with each other to form a multilayer structure (stacked structure).
  • a pixel / analog processing unit 601 is formed on the semiconductor substrate 621
  • a digital processing unit 602 an output unit 604-1, and an output unit 604-2 are formed on the semiconductor substrate 622, and a frame is formed on the semiconductor substrate 623.
  • a memory 603 is formed.
  • Each processing portion of each semiconductor substrate includes a via region (VIA) 624-1, a via region (VIA) 625-1, a through via (VIA) formed in the via region (VIA) 626-1, and a via region.
  • (VIA) 624-2, via region (VIA) 625-2, and via region (VIA) 626-2 are electrically connected to each other via through vias (VIA).
  • each semiconductor substrate is arbitrary, and is not limited to the example of FIG.
  • the A / D conversion unit 103 is provided with an A / D conversion unit (column A / D conversion unit 161) for each unit pixel column, and each column A / D conversion unit 161 includes the unit pixel.
  • the signal read from each unit pixel in the column has been described as being A / D converted, but the configuration example of the A / D conversion unit 103 is not limited to this.
  • a pixel unit is formed for each predetermined number of unit pixels, and the A / D converter 103 is provided with an A / D converter (area A / D converter) for each pixel unit.
  • Each area A / D conversion unit may perform A / D conversion on a signal read from each unit pixel belonging to the pixel unit assigned to itself.
  • the pixel unit and the area A / D converter may be formed on the same semiconductor substrate.
  • the pixel units 640-1 to 640-3 and the corresponding area A / D conversion units 641-1 to 641-3 are arranged on the same semiconductor substrate. Is formed.
  • the number of pixel units and area A / D converters is arbitrary.
  • pixel units 640 when it is not necessary to distinguish between the pixel units formed in the pixel array 101, they are referred to as pixel units 640, and the area A / D conversion units formed in the A / D conversion unit 103 are separated from each other.
  • the area A / D conversion unit 641 is referred to.
  • the configuration of the image sensor 100 may be formed on a plurality of semiconductor substrates.
  • the image sensor 100 may have two semiconductor substrates (laminated chips (a pixel substrate 651 and a circuit substrate 652)) that are superposed on each other.
  • N pixel units 640 (pixel units 640-1 to 640-N) in the pixel region (that is, the pixel array 101) are formed on the pixel substrate 651.
  • an area A / D converter 641 corresponding to the pixel unit 640 is formed at a position of the circuit board 652 that overlaps each pixel unit 640.
  • the signal read from the unit pixel of the pixel unit 640-K An A / D converter 641-K for A / D converting is formed.
  • the number of semiconductor substrates (number of layers) of the image sensor 100 is arbitrary, and may be three or more.
  • FIG. 26 is a block diagram illustrating a main configuration example of an imaging apparatus as an example of an electronic apparatus to which the present technology is applied.
  • An imaging apparatus 700 shown in FIG. 26 is an apparatus that images a subject and outputs an image of the subject as an electrical signal.
  • the imaging apparatus 700 includes an optical unit 711, a CMOS image sensor 712, an image processing unit 713, a display unit 714, a codec processing unit 715, a storage unit 716, an output unit 717, a communication unit 718, and a control unit 721. , An operation unit 722, and a drive 723.
  • the optical unit 711 includes a lens that adjusts the focus to the subject and collects light from the focused position, an aperture that adjusts exposure, a shutter that controls the timing of imaging, and the like.
  • the optical unit 711 transmits light (incident light) from the subject and supplies the light to the CMOS image sensor 712.
  • the CMOS image sensor 712 performs photoelectric conversion of incident light, A / D converts a signal for each pixel (pixel signal), performs signal processing such as CDS, and supplies the captured image data after processing to the image processing unit 713. .
  • the image processing unit 713 performs image processing on the captured image data obtained by the CMOS image sensor 712. More specifically, the image processing unit 713 performs, for example, color mixture correction, black level correction, white balance adjustment, demosaic processing, matrix processing, gamma correction on the captured image data supplied from the CMOS image sensor 712. And various image processing such as YC conversion.
  • the image processing unit 713 supplies the captured image data subjected to the image processing to the display unit 714.
  • the display unit 714 is configured, for example, as a liquid crystal display or the like, and displays an image of captured image data (for example, an image of a subject) supplied from the image processing unit 713.
  • the image processing unit 713 further supplies the captured image data subjected to the image processing to the codec processing unit 715 as necessary.
  • the codec processing unit 715 subjects the captured image data supplied from the image processing unit 713 to encoding processing of a predetermined method, and supplies the obtained encoded data to the storage unit 716. Further, the codec processing unit 715 reads the encoded data recorded in the storage unit 716, decodes it to generate decoded image data, and supplies the decoded image data to the image processing unit 713.
  • the image processing unit 713 performs predetermined image processing on the decoded image data supplied from the codec processing unit 715.
  • the image processing unit 713 supplies the decoded image data subjected to the image processing to the display unit 714.
  • the display unit 714 is configured as a liquid crystal display, for example, and displays an image of the decoded image data supplied from the image processing unit 713.
  • the codec processing unit 715 supplies the encoded data obtained by encoding the captured image data supplied from the image processing unit 713 or the encoded data of the captured image data read from the storage unit 716 to the output unit 717, You may make it output outside the imaging device 700.
  • the codec processing unit 715 supplies the captured image data before encoding or the decoded image data obtained by decoding the encoded data read from the storage unit 716 to the output unit 717, and the external of the imaging apparatus 700. You may make it output to.
  • the codec processing unit 715 may transmit the captured image data, the encoded data of the captured image data, or the decoded image data to another device via the communication unit 718. Further, the codec processing unit 715 may acquire captured image data and encoded data of the image data via the communication unit 718. The codec processing unit 715 appropriately performs encoding and decoding on the captured image data acquired through the communication unit 718 and the encoded data of the image data. The codec processing unit 715 supplies the obtained image data or encoded data to the image processing unit 713 as described above, or outputs it to the storage unit 716, the output unit 717, and the communication unit 718. May be.
  • the storage unit 716 stores the encoded data supplied from the codec processing unit 715 and the like.
  • the encoded data stored in the storage unit 716 is read and decoded by the codec processing unit 715 as necessary.
  • the captured image data obtained by the decoding process is supplied to the display unit 714, and a captured image corresponding to the captured image data is displayed.
  • the output unit 717 has an external output interface such as an external output terminal, and outputs various data supplied via the codec processing unit 715 to the outside of the imaging apparatus 700 via the external output interface.
  • the communication unit 718 supplies various types of information such as image data and encoded data supplied from the codec processing unit 715 to another device that is a communication partner of predetermined communication (wired communication or wireless communication). In addition, the communication unit 718 acquires various types of information such as image data and encoded data from another device that is a communication partner of predetermined communication (wired communication or wireless communication), and supplies the information to the codec processing unit 715. .
  • the control unit 721 controls the operation of each processing unit (each processing unit shown in the dotted line 720, the operation unit 722, and the drive 723) of the imaging apparatus 700.
  • the operation unit 722 is configured by an arbitrary input device such as a jog dial (trademark), a key, a button, or a touch panel, for example.
  • the operation unit 722 receives an operation input by a user or the like and supplies a signal corresponding to the operation input to the control unit 721. To do.
  • the drive 723 reads information stored in a removable medium 724 attached to the drive 723 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory.
  • the drive 723 reads various information such as programs and data from the removable medium 724 and supplies the information to the control unit 721. Further, when a writable removable medium 724 is attached to the drive 723, the drive 723 stores various information such as image data and encoded data supplied through the control unit 721 in the removable medium 724. be able to.
  • the present technology described above in each embodiment is applied. That is, the image sensor 100 described above is used as the CMOS image sensor 712. As a result, the CMOS image sensor 712 can be easily designed as described in the first embodiment and the like, and an increase in development and manufacturing costs can be suppressed. Therefore, the imaging apparatus 700 can also suppress an increase in development and manufacturing costs.
  • the series of processes described above can be executed by hardware or software.
  • a program constituting the software is installed from a network or a recording medium.
  • this recording medium includes a removable medium 724 on which a program is recorded, which is distributed to distribute the program to the user, separately from the apparatus main body.
  • the removable medium 724 includes a magnetic disk (including a flexible disk) and an optical disk (including a CD-ROM and a DVD). Further, magneto-optical disks (including MD (Mini-Disc)) and semiconductor memories are also included.
  • the program can be installed in the storage unit 716 by attaching the removable medium 724 to the drive 723.
  • This program can also be provided via a wired or wireless transmission medium such as a local area network, the Internet, or digital satellite broadcasting. In that case, the program can be received by the communication unit 718 and installed in the storage unit 716.
  • a wired or wireless transmission medium such as a local area network, the Internet, or digital satellite broadcasting.
  • the program can be received by the communication unit 718 and installed in the storage unit 716.
  • this program can be installed in advance in a ROM (Read Only Memory) or the like in the storage unit 716 or the control unit 721.
  • the program executed by the computer may be a program that is processed in time series in the order described in this specification, or in parallel or at a necessary timing such as when a call is made. It may be a program for processing.
  • the step of describing the program recorded on the recording medium is not limited to the processing performed in chronological order according to the described order, but may be performed in parallel or It also includes processes that are executed individually.
  • each step described above can be executed in each device described above or any device other than each device described above.
  • the device that executes the process may have the functions (functional blocks and the like) necessary for executing the process described above.
  • Information necessary for processing may be transmitted to the apparatus as appropriate.
  • the system means a set of a plurality of components (devices, modules (parts), etc.), and it does not matter whether all the components are in the same housing. Accordingly, a plurality of devices housed in separate housings and connected via a network and a single device housing a plurality of modules in one housing are all systems. .
  • the configuration described as one device (or processing unit) may be divided and configured as a plurality of devices (or processing units).
  • the configurations described above as a plurality of devices (or processing units) may be combined into a single device (or processing unit).
  • a configuration other than that described above may be added to the configuration of each device (or each processing unit).
  • a part of the configuration of a certain device (or processing unit) may be included in the configuration of another device (or other processing unit). .
  • the present technology can take a configuration of cloud computing in which one function is shared by a plurality of devices via a network and is jointly processed.
  • each step described in the above flowchart can be executed by one device or can be shared by a plurality of devices.
  • the plurality of processes included in the one step can be executed by being shared by a plurality of apparatuses in addition to being executed by one apparatus.
  • the present technology is not limited to this, and any configuration mounted on such a device or a device constituting the system, for example, a processor as a system LSI (Large Scale Integration), a module using a plurality of processors, a plurality of It is also possible to implement as a unit using other modules, a set obtained by further adding other functions to the unit (that is, a partial configuration of the apparatus), and the like.
  • a processor as a system LSI (Large Scale Integration)
  • a module using a plurality of processors a plurality of It is also possible to implement as a unit using other modules, a set obtained by further adding other functions to the unit (that is, a partial configuration of the apparatus), and the like.
  • this technique can also take the following structures.
  • a charge storage unit that stores charge and has a variable capacity;
  • a comparison unit that compares a signal level between an input signal and a reference signal input via the charge storage unit and outputs a comparison result; and
  • the comparison unit performs the signal level comparison a plurality of times,
  • the charge storage unit sets the capacitance according to an output of the comparison unit.
  • the charge storage unit includes: A plurality of capacitors for storing the charge;
  • the signal processing apparatus according to (1) further comprising: a switch that controls connection between a reference signal line, which is a signal line that transmits the reference signal, and the capacitor according to an output of the comparison unit.
  • the switch When the output of the comparison unit is inverted, the switch reduces the capacitance between the reference signal line and the comparison unit by disconnecting a part of the capacitor from the reference signal line.
  • the signal processing apparatus according to 2).
  • the switch disconnects a capacitor having a capacity corresponding to a resolution of comparison of the signal level by the comparison unit from the reference signal line.
  • the signal processing device according to (3), wherein the switch disconnects a part of the capacitor from the reference signal line at a timing according to an inversion timing of the output of the comparison unit.
  • (6) The signal processing device according to (5), wherein the switch disconnects a part of the capacitor from the reference signal line at a count timing immediately after the inversion of the output of the comparison unit.
  • the switch disconnects a part of the capacitor from the reference signal line at a count timing immediately before the inversion of the output of the comparison unit.
  • the reference signal is a ramp wave;
  • the switch reduces the capacitance between the reference signal line and the comparison unit by separating a part of the capacitor from the reference signal line, and reduces the slope of the waveform of the reference signal (3) Thru
  • the signal processing device wherein the signal level of the reference signal is set to an initial value corresponding to the width of the signal level of the reference signal every time the signal level is compared.
  • the charge storage unit further includes a holding capacitor for holding a signal level of the reference signal, The signal processing device according to any one of (3) to (10), wherein the capacitor separated from the reference signal line by the switch is connected to the holding capacitor.
  • the charge storage unit further includes an inter-capacitor switch that controls connection between the capacitors, The holding capacitor is connected to any one of the plurality of capacitors; The signal processing apparatus according to (11), wherein the inter-capacitor switch connects the capacitors so as to connect the capacitor separated from the reference signal line by the switch to the holding capacitor.
  • the signal processing device according to (11), wherein the holding capacitor is provided for each of the plurality of capacitors.
  • the system further includes a control unit that controls the capacitance between the reference signal line and the comparison unit by controlling the switch of the charge storage unit according to the output of the comparison unit. Thru
  • the signal processing device according to any one of (1) to (14), further including a count unit that counts until the output of the comparison unit is inverted.
  • the signal processing device according to any one of (1) to (15), wherein the input signal is a signal read from a unit pixel.
  • the input signal is a signal read from a unit pixel to be processed in a predetermined unit pixel group corresponding to the comparison unit in a pixel region in which the unit pixels are arranged in a matrix.
  • a signal processing device according to 1.
  • a signal level is compared between a reference signal and an input signal that are input via a charge storage unit that stores charge and has a variable capacitance; A control method for setting a capacity of the charge storage unit according to the comparison result.
  • a pixel array in which a plurality of unit pixels are arranged in a matrix;
  • a charge storage unit that stores charge and has a variable capacity;
  • a comparison unit that compares a signal level between an input signal read from the unit pixel of the pixel array and a reference signal input through the charge storage unit, and outputs a comparison result;
  • the comparison unit performs the signal level comparison a plurality of times,
  • the charge storage unit sets the capacitance according to an output of the comparison unit.
  • an imaging unit for imaging a subject An image processing unit that performs image processing on image data obtained by imaging by the imaging unit,
  • the imaging unit A pixel array in which a plurality of unit pixels are arranged in a matrix;
  • a charge storage unit that stores charge and has a variable capacity;
  • a comparison unit that compares a signal level between an input signal read from the unit pixel of the pixel array and a reference signal input through the charge storage unit, and outputs a comparison result;
  • the comparison unit performs the signal level comparison a plurality of times,
  • the charge storage unit is an electronic device that sets the capacity according to an output of the comparison unit.

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Abstract

La présente invention concerne un dispositif de traitement de signaux, un procédé de commande, un élément d'imagerie et un dispositif électronique qui sont susceptibles de limiter une augmentation de coût. Le dispositif de traitement de signaux selon la présente invention compare des niveaux de signal entre un signal de référence et un signal d'entrée qui sont introduits via une unité d'accumulation de charge électrique qui est dotée d'une capacitance variable et qui accumule une charge électrique, et règle la capacitance de l'unité d'accumulation de charge électrique en fonction du résultat de comparaison. Par exemple, l'unité d'accumulation de charge électrique peut comprendre: une pluralité de condensateurs qui accumulent une charge électrique; et un interrupteur qui commande la connexion entre une ligne de signal de référence, qui est une ligne de signal transmettant un signal de référence, et les condensateurs en fonction du résultat de comparaison. Cette caractéristique peut être appliquée, par exemple, à un élément d'imagerie et à un dispositif électronique.
PCT/JP2015/073653 2014-09-05 2015-08-24 Dispositif de traitement de signaux, procédé de commande, élément d'imagerie et dispositif électronique WO2016035587A1 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116318161A (zh) * 2023-03-23 2023-06-23 华中科技大学 用于图像传感器的多步式单斜模数转换电路及控制方法
CN116318161B (zh) * 2023-03-23 2024-02-02 华中科技大学 用于图像传感器的多步式单斜模数转换电路及控制方法

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