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WO2016013701A1 - Récepteur de radiodiffusion et processeur de signal associé - Google Patents

Récepteur de radiodiffusion et processeur de signal associé Download PDF

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Publication number
WO2016013701A1
WO2016013701A1 PCT/KR2014/006768 KR2014006768W WO2016013701A1 WO 2016013701 A1 WO2016013701 A1 WO 2016013701A1 KR 2014006768 W KR2014006768 W KR 2014006768W WO 2016013701 A1 WO2016013701 A1 WO 2016013701A1
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WO
WIPO (PCT)
Prior art keywords
memory
signal
iir filter
filter
iir
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Application number
PCT/KR2014/006768
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English (en)
Korean (ko)
Inventor
김연우
이정은
김진화
이주호
Original Assignee
주식회사 레이믹스
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 레이믹스 filed Critical 주식회사 레이믹스
Publication of WO2016013701A1 publication Critical patent/WO2016013701A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level

Definitions

  • the present invention relates to a broadcast receiver and a signal processor for the broadcast receiver, and more particularly, to a broadcast receiver and a signal processor for the broadcast receiver that can correspond to both an analog broadcast signal and a digital broadcast signal.
  • U.S. Patent No. 7,265,792 (hereinafter referred to as 'Primary Invention') discloses a television receiver capable of coping with both analog TV signals and digital TV signals.
  • DSP digital signal processor
  • the digital signal processor (DSP) of the present invention performs signal processing using a finite impulse response (FIR) filter.
  • FIR finite impulse response
  • FIR filters require more coefficients to maintain the same performance as Infinite Impulse Response (IIR) filters, requiring larger multipliers and shift registers. do. Therefore, the signal processing using the FIR filter increases the complexity of hardware and requires a larger hardware configuration.
  • IIR Infinite Impulse Response
  • the IIR filter unlike the FIR filter, it is possible to design a filter having the same performance as that of the FIR filter by using less co-election.
  • the IIR filter there is a problem in that there is a non-uniform group delay in the in-band frequency band.
  • an additional design circuit for compensating for group delay using an Arbitrary Group Delay Equalizer for example, All Pass Filter, APF
  • APF Arbitrary Group Delay Equalizer
  • the present invention has an object of solving the above technical problem, and the object of the present invention is to provide a broadcast receiver and a signal processor for the broadcast receiver, which simplify the hardware and improve the group delay characteristics by using an IIR filter. There is this.
  • the broadcast receiver includes a signal processor that digitally processes and outputs an inputted digitized intermediate frequency signal using a plurality of Infinite Impulse Response (IIR) filters.
  • IIR Infinite Impulse Response
  • the signal processor may include a first signal processor configured to digitally process and output an input digitized intermediate frequency signal for digital TV, wherein the first signal processor comprises: a first filter for filtering the input digitized intermediate frequency signal; It characterized in that it comprises a filter unit.
  • the first filter unit the 1-1 IIR filter; And a 1-2 IIR filter connected to the 1-1 IIR filter through a memory.
  • the first filter unit includes a 1-1 IIR filter, a 1-2 IIR filter, a 1-1 memory, and a 1-2 memory, wherein the digitized intermediate frequency signal is the 1-1 IIR filter.
  • the first frequency of the first memory, the 1-2 IIR filter, and the 1-2 memory are input and output, or the digitized intermediate frequency signal is the 1-1 memory, the 1-2 IIR filter. And input and output in the order of the 1-2 memory and the 1-1 IIR filter.
  • the 1-1 memory and the 1-2 memory are LIFO (Last-In First-Out) memory.
  • the signal processor may include a second signal processor configured to digitally process and output an inputted digitized intermediate frequency signal for analog TV, wherein the second signal processor may demodulate the inputted digitized intermediate frequency signal. Demodulator; And a second filter unit for filtering the demodulated signal by the demodulator.
  • the second filter unit the 2-1 IIR filter; And a 2-2 IIR filter connected through the 2-1 IIR filter and a memory.
  • the second filter unit includes a 2-1 IIR filter, a 2-2 IIR filter, a 2-1 memory, and a 2-2 memory, wherein the signal demodulated by the demodulator is the second-1.
  • a signal input and output in the order of an IIR filter, the 2-1 memory, the 2-2 IIR filter, and the 2-2 memory, or the signal demodulated by the demodulator is the 2-1 memory, the second It is characterized in that the input and output in the order of -2 IIR filter, the 2-2 memory and the 2-1 IIR filter.
  • the 2-1 memory and the 2-2 memory are LIFO (Last-In First-Out) memories.
  • an IIR filter can be used to improve group delay characteristics while simplifying hardware.
  • FIG. 1 is a block diagram of a broadcast receiver according to an embodiment of the present invention.
  • FIG. 2 is a block diagram of a signal processor of the present invention.
  • 3A and 3B are configuration diagrams of a first embodiment and a second embodiment of the first filter unit
  • 4A and 4B are configuration diagrams of a first embodiment and a second embodiment of the second filter unit
  • FIG. 5 is a characteristic diagram of filtering and group delay by coupling an IIR filter to the cascade of the present invention.
  • Figure 1 is a block diagram of a broadcast receiver 1000 according to an embodiment of the present invention.
  • the broadcast receiver 1000 according to an embodiment of the present invention, the frequency conversion circuit 100, IF amplification digitization circuit 200, the signal processor 300 and the signal output circuit ( 400).
  • the frequency conversion circuit 100 converts the input RF signal to have an intermediate frequency (IF).
  • the RF signal input here is a signal for digital or analog television.
  • the frequency conversion circuit 100 of the present invention may include a filter 120 and a mixer 130 implemented using a low noise amplifier (LNA) 110, a tracking filter, and a low pass filter. .
  • LNA low noise amplifier
  • the IF amplification digitizing circuit 200 includes a programmable gain amplifier (PGA, 210a, 210b) and an analog-to-digital converter (Analog to Digital Converter, ADC, 220a, 220b), and includes an input. It amplifies and digitizes the intermediate frequency signal.
  • PGA programmable gain amplifier
  • ADC Analog to Digital Converter
  • the signal processor 300 of the present invention may be implemented by including a digital signal processor (DSP), and digitally process the digital signal into a signal of a digital TV format or an analog TV format according to a format of an inputted digitized intermediate frequency signal. It plays a role of printing. That is, the signal processor 300 of the present invention outputs an audio signal and a video signal in the form of digital signals, respectively, for the analog TV format signal. In addition, the signal processor 300 of the present invention outputs an I signal and a Q signal in digital form, respectively, for a digital TV format signal.
  • DSP digital signal processor
  • the signal output circuit 400 serves to output signals of various TV formats.
  • the signal output circuit 400 uses an analog terminal to convert a TV signal in digital format by a first digital-to-analog converter 410 for converting an input digital signal into an analog signal and a low pass filter 420 for smoothing. Can be output via
  • the signal output circuit 400 of the present invention can be output as an analog format TV signal through an analog terminal using a second digital-to-analog converter 430 that converts an input digital signal into an analog signal.
  • each output terminal can output a signal in the form of a single or differential signal.
  • FIG. 2 shows a block diagram of the signal processor 300 of the present invention.
  • the signal processor 300 of the present invention includes a first signal processor 310 and a second signal processor 320.
  • the first signal processor 310 When the inputted digitized intermediate frequency signal is a digital TV signal, the first signal processor 310 outputs the digital signal in a digital TV format. In addition, when the inputted digitized intermediate frequency signal is an analog TV signal, the second signal processor 320 performs a digital signal processing and outputs the digital signal in an analog TV format.
  • the first signal processor 310 of the present invention includes a first filter unit 312 for filtering an inputted digitized intermediate frequency signal.
  • the first filter unit 312 may use a channel selection filter (CSF) as an Infinite Impulse Response (IIR) filter.
  • CSF channel selection filter
  • IIR Infinite Impulse Response
  • the first filter unit 312 includes a 1-1 IIR filter F11 and a 1-1 IIR filter F12 connected to the 1-1 IIR filter F11 via a memory.
  • the 1-2 delay IIR filter F12 having a memory connected to the front and rear ends compensates for the group delay of the 1-1 IIR filter F11.
  • the intermediate frequency signal digitized as shown in FIG. -2 may be configured to be input and output in the order of the memory M12.
  • the first filter unit 312 may include the first-first memory M11, the first-first memory M11, the first-first IIR filter F12, and the second-first memory M12 as illustrated in FIG. 3B.
  • 1-1 IIR filter (F11) in order to be input and output.
  • the 1-1 IIR filter F11 and the 1-2 IIR filter F12 may be used as I signal filters.
  • the first-first memory M11 and the first-second memory M12 use a last-in first-out (LIFO) memory to finally output data in the original order.
  • LIFO last-in first-out
  • the first filter unit 312 may use the first to third IIR filters F13 and the first to fourth IIR filters F14, which are IIR filters, as filters for Q signals.
  • the 1-3 memory M13 and the 1-4 memory M14 use a last-in first-out memory to finally output data in the original order.
  • the 1-1 IIR filter F11, the 1-2 IIR filter F12, the 1-3 IIR filter F13, and the 1-4 IIR filter F14 may be configured.
  • the second signal processor 320 includes a demodulator 321 for demodulating the input digitized intermediate frequency signal and a second filter unit 322 for filtering the demodulated signal by the demodulator 321. do.
  • the demodulator 321 may be an example demodulator for VSB (Vestigial sideband).
  • FIGS. 4A and 4B show configuration diagrams of the first and second embodiments of the second filter unit 322, respectively.
  • the second filter unit 322 uses an Infinite Impulse Response (IIR) filter as a low pass filter or a band pass filter. That is, the second filter unit 322 includes a 2-1 IIR filter F21 and a 2-2 IIR filter F22 connected to the 2-1 IIR filter F21 via a memory.
  • IIR Infinite Impulse Response
  • the 2-2 IIR filter F22 having a memory connected to the front and rear ends compensates for the group delay of the 2-1 IIR filter F21.
  • the second filter unit 322 has a signal demodulated by the demodulator 321 in the 2-1 IIR filter F21, the 2-1 memory M21, and the 2-2 IIR filter F22.
  • And 2-2 may be input and output in the order of the memory M22.
  • the signal demodulated by the demodulator 321 is a 2-1 memory M21, a 2-2 IIR filter F22, a 2-2 memory M22, and a 2-1 IIR filter. Input and output in the order of (F21).
  • the 2-1 IIR filter F21 and the 2-2 IIR filter F22 are used as filters for video signals.
  • the second-first memory M21 and the second-second memory M22 use a last-in first-out (LIFO) memory to finally output data in the original order.
  • LIFO last-in first-out
  • the second filter unit 322 filters the audio signal using the 2-3 IIR filter F23 and the 2-4 IIR filter F24 which are IIR filters.
  • the 2-3 memory M23 and the 2-4 memory M24 use a last-in first-out memory to finally output data in the original order.
  • the 2-1 IIR filter F21, the 2-2 IIR filter F22, the 2-3 IIR filter F23, and the 2-4 IIR filter F24 may be configured.
  • the group delay characteristics are improved.
  • the burden of the cost also increases, so it is desirable to select an appropriate size by trade off.
  • FIG. 5 shows a characteristic diagram of filtering and group delay by connecting an IIR filter to a cascade of the present invention, respectively.
  • the group delay canceling method of the present invention is for compensating the IIR filter F11 in which the memories M11 and M12 are connected before and after one IIR filter F11 and the IIR filter F12. Characterized in that the compensation portion.
  • the Arbitrary group delay method merely exhibits excellent filtering characteristics as two IIR filters are connected in series, as compared with simply canceling the group delay.
  • the signal processor 300 may be implemented with smaller hardware than the FIR filter, and excellent signal characteristics may be obtained in a digital TV system, and performance of video and audio signals may be improved in an analog TV system.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

La présente invention concerne un récepteur de radiodiffusion qui peut simplifier un matériel et améliorer des caractéristiques de retard de groupe à l'aide d'un filtre à réponse impulsionnelle infinie (IIR), et un processeur de signal associé. Le processeur de signal destiné à un récepteur de radiodiffusion comprend : une première unité de traitement de signal permettant de traiter un signal numérique et d'émettre un signal de fréquence intermédiaire numérisé d'entrée destiné à une télévision numérique ; et une seconde unité de traitement de signal permettant de traiter un signal numérique et d'émettre un signal de fréquence intermédiaire numérisé d'entrée pour une télévision analogique, la première unité de traitement de signal et la seconde unité de traitement de signal respectives traitant un signal à l'aide d'un ou de plusieurs filtres IIR.
PCT/KR2014/006768 2014-07-24 2014-07-24 Récepteur de radiodiffusion et processeur de signal associé WO2016013701A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2014-0093744 2014-07-24
KR1020140093744A KR20160012396A (ko) 2014-07-24 2014-07-24 방송용 수신기 및 그 방송용 수신기를 위한 신호처리기

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WO2016013701A1 true WO2016013701A1 (fr) 2016-01-28

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060083335A1 (en) * 2004-10-12 2006-04-20 Maxlinear, Inc. Receiver architecture with digitally generated intermediate frequency
US20070129034A1 (en) * 2003-07-17 2007-06-07 Adams Andrew R Adaptive agc in a wireless network receiver
JP2010011358A (ja) * 2008-06-30 2010-01-14 Sharp Corp 受信装置、チューナ、およびテレビジョン受像機
KR20120057246A (ko) * 2010-11-26 2012-06-05 주식회사 휴텍이일 밀리미터파를 이용한 씨프리 구조의 이동통신 기지국과 리모트 무선 헤드 간의 전송 시스템
JP2013120987A (ja) * 2011-12-06 2013-06-17 Sony Corp 信号処理装置、信号処理方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070129034A1 (en) * 2003-07-17 2007-06-07 Adams Andrew R Adaptive agc in a wireless network receiver
US20060083335A1 (en) * 2004-10-12 2006-04-20 Maxlinear, Inc. Receiver architecture with digitally generated intermediate frequency
JP2010011358A (ja) * 2008-06-30 2010-01-14 Sharp Corp 受信装置、チューナ、およびテレビジョン受像機
KR20120057246A (ko) * 2010-11-26 2012-06-05 주식회사 휴텍이일 밀리미터파를 이용한 씨프리 구조의 이동통신 기지국과 리모트 무선 헤드 간의 전송 시스템
JP2013120987A (ja) * 2011-12-06 2013-06-17 Sony Corp 信号処理装置、信号処理方法

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