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WO2016008226A1 - 薄膜晶体管及其制备方法、阵列基板和显示设备 - Google Patents

薄膜晶体管及其制备方法、阵列基板和显示设备 Download PDF

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WO2016008226A1
WO2016008226A1 PCT/CN2014/089037 CN2014089037W WO2016008226A1 WO 2016008226 A1 WO2016008226 A1 WO 2016008226A1 CN 2014089037 W CN2014089037 W CN 2014089037W WO 2016008226 A1 WO2016008226 A1 WO 2016008226A1
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electrode
drain electrode
source electrode
layer
film transistor
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PCT/CN2014/089037
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English (en)
French (fr)
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张锋
曹占锋
姚琪
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京东方科技集团股份有限公司
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Priority to US14/769,438 priority Critical patent/US9748276B2/en
Publication of WO2016008226A1 publication Critical patent/WO2016008226A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/86—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group II-VI materials, e.g. ZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/257—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO

Definitions

  • the present invention relates to the field of display, and more particularly to a Thin Film Transistor (TFT) and a method of fabricating the same, an array substrate including the same, and a display device.
  • TFT Thin Film Transistor
  • OLED displays occupy a dominant position in the current flat panel display device market because they can be made lighter and thinner, have larger viewing angles, no radiation, and can significantly save power. It is considered to be the most likely next-generation new flat panel display.
  • the active matrix OLED is provided with a thin film transistor for controlling the pixel as a switch for each pixel, and the thin film transistor generally includes a gate, a source and a drain, and a gate insulating layer and an active layer.
  • Oxides such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), and the like can be used as an active layer material of a thin film transistor, and an oxide thin film transistor is compared with an amorphous silicon thin film transistor.
  • the carrier concentration is about ten times that of the amorphous silicon thin film transistor, and the carrier mobility is 20-30 times that of the amorphous silicon thin film transistor. Therefore, the oxide thin film transistor can greatly increase the charge and discharge rate of the thin film transistor for the pixel electrode. , to improve the response speed of the pixel, thereby achieving a faster refresh rate.
  • Oxide thin film transistors are suitable for applications requiring fast response and high current, such as high frequency, high resolution, large size displays, and organic light emitting displays. Therefore, the oxide thin film transistor becomes a semiconductor component for a new generation of LCD and OLED display devices.
  • FIG. 1A is a schematic structural view of an etch barrier type oxide thin film transistor in the prior art
  • FIG. 1B is a cross-sectional view of the oxide thin film transistor shown in FIG. 1A along A-A'.
  • 11 is a substrate
  • 12 is a substrate.
  • the gate electrode 13 is a gate insulating layer
  • 14 is an active layer
  • 15 is an etch barrier layer
  • 16 is a source/drain electrode.
  • the oxide semiconductor layer is mostly an amorphous semiconductor oxide, there is a problem in ohmic contact with the source/drain (SD) metal layer, which tends to cause poor stability of the thin film transistor.
  • SD source/drain
  • the channel length of the thin film transistor affects the turn-on current of the thin film transistor.
  • the smaller the channel length the larger the turn-on current of the thin film transistor.
  • the etch stop layer is The source and drain electrodes are formed before, so that the channel length D1 (FIG. 1B) corresponding to the size of the etch barrier layer of the conventional oxide thin film transistor is large, and the turn-on current is small, which seriously degrades the performance of the thin film transistor, which is disadvantageous for Development of high performance display devices.
  • the present invention provides a thin film transistor and a method of fabricating the same, an array substrate including the same, and a display device.
  • a thin film transistor including an active layer, an etch barrier layer, a gate electrode, a gate insulating layer, a source electrode, and a drain electrode
  • the source electrode includes a first source electrode and a second source electrode
  • the drain electrode including a first drain electrode and a second drain electrode
  • the first source electrode and the first drain electrode being formed on the active layer
  • the etch barrier layer covering at least active a portion of the layer between the first source electrode and the first drain electrode and respectively covering portions of the first source electrode and the first drain electrode adjacent to each other
  • the second source electrode and the second drain electrode are formed at On the etch barrier layer, the first source electrode is electrically connected to the second source electrode, and the first drain electrode is electrically connected to the second drain electrode.
  • a first via and a second via corresponding to the first source electrode and the first drain electrode, respectively, may be formed in the etch barrier layer, and the second source electrode may be at least partially located Within a via and in electrical contact with the first source electrode, the second drain electrode can be at least partially within the second via and in electrical contact with the first drain electrode.
  • a separation distance between the first source electrode and the first drain electrode is smaller than a separation distance between the first via hole and the second via hole in the etch barrier layer.
  • the first source electrode and the first drain electrode are formed of the same first electrode material layer deposited on the active layer, and the second source electrode and the second drain electrode are deposited on the etch barrier layer
  • the same second electrode material layer is formed, and the thickness of the first electrode material layer may be smaller than the thickness of the second electrode material layer.
  • the thin film transistor may further include an oxide layer formed on the first source electrode and the first drain electrode, the oxide layer being a metal oxide layer formed by heat-treating the first source electrode and the first drain electrode.
  • the material of the first drain electrode and/or the first source electrode may include an alloy of aluminum or aluminum.
  • the active layer may be formed of a metal oxide semiconductor material.
  • the metal oxide semiconductor material may include a zinc oxide material.
  • the active layer may contain the same metal atom as the first source electrode and the first drain electrode.
  • an array substrate including a substrate and a thin film transistor as described above formed on the substrate is provided.
  • a display device comprising the array substrate as described above.
  • a method of fabricating a thin film transistor comprising the steps of:
  • first electrode material layer Forming a first electrode material layer on the substrate on which the active layer is obtained, and patterning the first electrode material layer to obtain a first source electrode and a first drain electrode on the active layer;
  • etch stop material layer Forming an etch stop material layer on the substrate, and patterning the etch stop material layer to form an etch stop layer, the etch stop layer covering at least the first source electrode and the first drain electrode of the active layer a portion that overlaps the first source electrode and the first drain electrode adjacent to each other;
  • the step of patterning the etch barrier material layer may include forming a first via hole exposing at least a portion of the first source electrode and exposing at least a portion of the first drain electrode in the etch barrier material layer a first via step, wherein the second source electrode is at least partially located within the first via of the etch stop layer and in electrical contact with the first source electrode, the second drain electrode being at least partially located The second via in the etch barrier layer is in electrical contact with the first drain electrode.
  • a separation distance between the first source electrode and the first drain electrode is smaller than a separation distance between the first via hole and the second via hole in the etch barrier layer.
  • the thickness of the first electrode material layer may be smaller than the thickness of the second electrode material layer.
  • the preparation method may further include performing heat treatment on the first source electrode and the first drain electrode to form a metal on the surfaces of the first source electrode and the first drain electrode The step of the oxide layer.
  • the first source electrode and the first drain electrode may be heat treated using an annealing process.
  • the material of the first drain electrode and/or the first source electrode may be an alloy of aluminum or aluminum.
  • the active layer may be formed of a metal oxide semiconductor material.
  • the metal oxide semiconductor material may include a zinc oxide material.
  • 1A is a top plan view of an oxide thin film transistor in the prior art
  • FIG. 1B is a cross-sectional view of the oxide thin film transistor of FIG. 1A taken along line A-A';
  • FIG. 2 is a schematic structural view of a thin film transistor according to an embodiment of the invention.
  • 3 is a graph showing a relationship between an Al 3+ doping concentration and an electrical conductivity of an active layer
  • 4A-4G are flow diagrams showing a process of fabricating a thin film transistor in accordance with an embodiment of the present invention.
  • FIG. 2 shows the structure of a thin film transistor according to an exemplary embodiment of the present invention.
  • the thin film transistor includes, for example, a gate electrode 2 formed on a substrate 1, a gate insulating layer 3, an active layer 4, an etch barrier layer 7, a source electrode, and a drain electrode.
  • the source electrode includes a first source electrode 5 and a second source electrode 8, the drain electrode including a first drain electrode 6 and a second drain electrode 9, the first source electrode 5 and the first drain electrode
  • the poles 6 are formed on the active layer 4 and spaced apart from each other by a distance D2.
  • the portion of the active layer 4 between the first source electrode 5 and the first drain electrode 6 is a channel portion or region, in this example, the length of the channel region, ie The channel length is equal to D2.
  • the active layer 4 may be a metal oxide semiconductor material, preferably an oxide semiconductor material having a high carrier mobility, such as zinc oxynitride (ZnON), indium gallium zinc oxide (IGZO), or indium zinc oxide (IZO), an oxide semiconductor material such as indium tin zinc oxide (ITZO).
  • ZnON zinc oxynitride
  • IGZO indium gallium zinc oxide
  • IZO indium zinc oxide
  • ITZO indium tin zinc oxide
  • the source electrode and the drain electrode are made of a conductive material.
  • the conductive material is a metal material, such as a common metal such as aluminum, zinc, tin, antimony, tungsten, titanium, or a metal alloy material, preferably aluminum or aluminum. Alloy.
  • the etch stop layer 7 covers at least the first source electrode 5 and the first drain electrode 6 of the active layer A portion, that is, a channel region, in which at least the channel region is covered by the etch barrier layer 7 to protect the active layer 4 between the first source electrode 5 and the first drain electrode 6
  • the area is not affected by the erosion of the developer and the etching solution.
  • the etch barrier layer 7 is made of a material capable of blocking the developer and the etching solution, such as silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx). And one or more of silicon oxynitrides (SiON).
  • the material such as silicon oxide (SiOx) is insensitive to the developer and the source and drain etching liquid.
  • the etch barrier layer 7 covers a portion of the first source electrode 5 and a portion of the first drain electrode 6, respectively, that is, the etch barrier layer 7 is formed in the first source electrode 5 and the first drain electrode. Formed after 6, as deposited on the substrate 1, covering a portion of the first source electrode 5 and a portion of the first drain electrode 6. As shown in FIG. 2, the etch barrier layer 7 covers at least a portion of the first source electrode 5 and the first drain electrode 6 adjacent to each other, so as to be formed in the prior art due to the formation of the etch barrier layer before the source and drain electrodes.
  • the channel length D2 of the thin film transistor formed according to the embodiment of the present invention is shorter than the longer channel length D1, that is, D2 ⁇ D1.
  • the source electrode of the thin film transistor may further include a second source electrode 8 electrically connected to the first source electrode 5, and the drain electrode may further include a second drain electrode 9 electrically connected to the first drain electrode 6, the second source electrode 8 and The second drain electrode 9 is formed on the etch barrier layer 7.
  • the second source electrode 8 is at least partially located in the first via hole 11 (see FIGS. 4E and 4F) in the etch barrier layer 7 and is in electrical contact with the first source electrode 5, and the drain electrode is further A second drain electrode 9 that is at least partially located in the second via 12 (see FIGS. 4E and 4F) in the etch barrier layer 7 and is in electrical contact with the first drain electrode 6 may be included.
  • the second source electrode 8 covers at least and contacts the portion of the first source electrode 5 exposed from the first via hole 11, and the second source electrode 8 covers at least the first drain electrode 6 and the second via hole 12 from the second via hole 12.
  • the second source electrode 8 and the second drain electrode 9 are formed after the etch stop layer 7 and thus may cover a portion of the etch stop layer 7.
  • the first source electrode 5 is electrically connected to the second source electrode 8, and the first drain electrode 6 is electrically connected to the second drain electrode 9 so as to be able to pass through the first source electrode 5 and the second source electrode 8, and the first leakage current.
  • the pole 6 and the second drain electrode 9 respectively apply respective voltages to the source region and the drain region in the active layer 4.
  • the source electrode and the drain electrode are electrically connected or electrically conducted through the active layer 4.
  • the separation distance D2 between the first source electrode 5 and the first drain electrode 6 is smaller than the interval between the first via hole 11 and the second via hole 12 in the etch stop layer 7.
  • Distance (ie, etching) The barrier layer 7 is located at a length D1 between the second source electrode 8 and the second drain electrode 9.
  • the present invention does not specifically require specific division of the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode, because the specific electrode at which position is the source electrode or the drain electrode depends on the connection relationship with the pixel electrode.
  • a drain electrode Connected to the pixel electrode in the present application is a drain electrode, the first source electrode corresponds to the position of the second source electrode, and the first drain electrode corresponds to the position of the second drain electrode.
  • the thin film transistor may further include an oxide layer 10 formed on the first source electrode 5 and the first drain electrode 6, the oxide layer 10 being passed through the first source electrode 5 and a metal oxide layer formed by heat treatment of the first drain electrode 6.
  • the first source electrode 5 and the first drain electrode 6 are heat-treated by a process such as annealing, and after the heat treatment, the first source electrode 5 A metal oxide layer 10 is formed on the surface of the first drain electrode 6.
  • the heat treatment is performed before the formation of the etch stop layer 7, and therefore, in the example shown in FIG. 2, the patterned metal oxide layer 10 is located at the etch stop layer 7 and the first source electrode 5 and the first Between the drain electrodes 6.
  • the active layer 4 contains the same metal atoms as the first source electrode 5 and the first drain electrode 6, thereby The conductivity of the active layer 4 is enhanced, thereby improving the ohmic contact problem between the source/drain electrodes and the active layer, and improving the stability of the oxide thin film transistor.
  • the first source electrode 5 and the first drain electrode 6 are subjected to heat treatment by an annealing process, for example, the annealing temperature is set between 200 and 300 degrees Celsius in an air atmosphere, and the time is 0.5. - 3 hours of annealing.
  • the surface of the metal aluminum exposed to the annealing environment is oxidized to aluminum oxide (Al 2 O 3 ) during annealing. While aluminum atoms in the first source electrode 5 and the first drain electrode 6 enter into the active layer 4 in contact with the first source electrode 5 and the first drain electrode 6, thereby enhancing the active The conductivity of layer 4.
  • the active layer is usually made of a zinc oxide material such as zinc oxynitride (ZnON), indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO), since Al 3+ is more active than
  • Zn 2+ in the layer is more than one valence electron, so that the electrons can be bound to form a shallow level trap near the bottom of the conduction band.
  • the trapping force of this trap is very small, and the adsorbed electrons can be excited and transition to the conduction band at normal temperature to form free electrons, which is why the doping of aluminum atoms can enhance the conductivity of the active layer 4.
  • the effect of the doping concentration of Al 3+ on the conductivity of the active layer is shown in FIG. 3.
  • the abscissa indicates the doping concentration of Al 3+ in the active layer, and the ordinate indicates the square of the active layer. Resistance (k ⁇ / ⁇ )".
  • the conditions of the heat treatment can be controlled such that an appropriate amount of Al atoms enter the active layer to form a suitable Al 3+ doping concentration to effectively reduce the sheet resistance of the active layer.
  • the thin film transistor further includes: over the second source electrode 8 and the second drain electrode 9 and covering at least the etch barrier layer 7 at the first source electrode 5 and the first A portion of the gate insulating layer 3 between the drain electrodes 6 and a gate electrode 2 over the gate insulating layer 3.
  • the thin film transistor further includes a gate electrode 2 formed on the substrate 1 and a gate insulating layer 3 formed on the gate electrode 2, that is, the gate insulating layer 3 is located Between the active layer 4 and the gate 2.
  • an array substrate comprising a substrate and a thin film transistor as described in any of the above embodiments formed on the substrate.
  • a display device comprising the array substrate as described above.
  • a method of fabricating a thin film transistor comprising the steps of:
  • Step 1 forming a semiconductor layer on the substrate 1, and patterning the semiconductor layer to obtain an active layer 4;
  • the material of the substrate 1 may include materials such as glass, silicon wafer, quartz, plastic, and silicon wafer, preferably glass.
  • the material of the active layer 4 may be a metal oxide, preferably an oxide semiconductor material having a high carrier mobility, such as zinc oxynitride (ZnON), indium gallium zinc oxide (IGZO), indium oxide.
  • An oxide semiconductor material such as zinc (IZO) or indium tin zinc oxide (ITZO).
  • the semiconductor layer may be formed by a sputtering technique or a plasma chemical vapor deposition (PECVD) technique, and the manner in which the semiconductor layer is formed in the present invention is not particularly limited.
  • PECVD plasma chemical vapor deposition
  • the semiconductor layer may be patterned by a gray scale mask exposure process to form the active layer 4.
  • Step 2 forming on the substrate on the active layer 4, such as deposition, a first electrode material layer, And patterning the first electrode material layer to obtain the first source electrode 5 and the first drain electrode 6 on the active layer 4;
  • the source electrode and the drain electrode are made of a conductive material.
  • the conductive material is a metal material, such as a common metal such as aluminum, zinc, tin, antimony, tungsten, titanium, or a metal alloy material, preferably aluminum. Or an alloy of aluminum.
  • the first electrode material layer may be a thin layer, such as a thickness, as compared to a conventional electrode material layer.
  • Step 3 forming on the substrate on which the active layer 4, the first source electrode 5 and the first drain electrode 6 have been formed, such as depositing, etching the barrier material layer, and patterning the etch barrier material layer, Forming an etch stop layer 7 , wherein the etch stop layer 7 covers at least a portion of the active layer 4 between the first source electrode 5 and the first drain electrode 6 , that is, covering the channel region, in other words, At least the channel region in the active layer 4 is covered by the etch barrier layer 7 to protect a portion of the active layer 4 located in the channel region between the first source electrode 5 and the first drain electrode 6 from the subsequent process The erosion effect of the developer and etchant used.
  • the etch barrier layer 7 is made of a material capable of blocking the developer and the etching solution, such as silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx). And one or more of silicon oxynitrides (SiON).
  • the material such as silicon oxide (SiOx) is insensitive to the developer and the source and drain etching liquid.
  • step 3 since the etch barrier layer 7 is formed or deposited on the substrate 1 after forming the first source electrode 5 and the first drain electrode 6, the etch barrier layer 7 covers a portion of the first source electrode 5, respectively. And a portion of the first drain electrode 6. As shown in FIG. 2, the etch barrier layer 7 covers at least portions of the first source electrode 5 and the first drain electrode 6 adjacent to each other such that the channel length D2 is smaller than the channel length D1 of the conventional thin film transistor.
  • step 3 when the etch barrier material layer is patterned, a first via 11 exposing at least a portion of the first source electrode 5 and at least a first drain electrode 6 may be formed in the etch barrier material layer.
  • a portion of the first via 12 is shown in Figures 4E and 4F.
  • the preparation method may further include a step 4, wherein a second electrode material layer is deposited on the substrate 1, and the second electrode material layer is patterned to obtain a second source electrode 8 and a second drain electrode 9, wherein The second source electrode 8 is at least partially located in the first via 11 in the etch barrier layer 7 and is in electrical contact with the first source electrode 5, and the second drain electrode 9 is at least partially located in the etch barrier layer
  • the second via 12 in the seventh via 12 is in electrical contact with the first drain electrode 6.
  • the second source electrode 8 and the second drain electrode 9 can be fabricated using a conventional source/drain electrode process. Alternatively, the second source electrode 8 and the second drain electrode 9 may be formed by processes such as exposure, development, etching, and the like.
  • the second electrode material layer may comprise a conventional electrode material of a semiconductor process, such as copper, and in one embodiment, the thickness of the second electrode material layer is greater than the thickness of the first electrode material layer, illustratively, the second electrode material layer Thickness is about 2000-4000 angstroms
  • the separation distance (ie, the channel length) D2 between the first source electrode 5 and the first drain electrode 6 is smaller than that in the etch stop layer 7.
  • the separation distance between the first via hole 11 and the second via hole 12 that is, the length of the etch barrier layer 7 between the second source electrode 8 and the second drain electrode 9) D1.
  • the present invention does not specifically require specific division of the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode, because the specific electrode at which position is the source electrode or the drain electrode depends on the connection relationship with the pixel electrode.
  • a drain electrode Connected to the pixel electrode in the present application is a drain electrode, the first source electrode corresponds to the position of the second source electrode, and the first drain electrode corresponds to the position of the second drain electrode.
  • the method further includes heat treating the first source electrode 5 and the first drain electrode 6 to A step of forming a metal oxide layer 10 on the surface of the first source electrode and the first drain electrode.
  • the portion of the oxide layer 10 at the corresponding position is also removed together to expose the first source electrode or the first drain electrode portion at the corresponding position.
  • the second source electrode formed subsequently can be electrically connected to the first source electrode, and the second drain electrode can be electrically connected to the first drain electrode.
  • the surface layers of the first source electrode 5 and the first drain electrode 6 may be heat treated by annealing or the like;
  • the annealing process may be: annealing in an air atmosphere at a temperature between 200 and 300 degrees Celsius for an annealing time of 0.5 to 3 hours.
  • the active layer 4 contains the same metal atoms as the first source electrode 5 and the first drain electrode 6, thereby enhancing the The conductivity of the active layer 4 improves the ohmic contact between the source/drain electrodes and the active layer, and improves the stability of the oxide thin film transistor.
  • the surface of the metal aluminum exposed to the annealing environment is oxidized to aluminum oxide (Al 2 O 3 ) during annealing. While aluminum atoms in the first source electrode 5 and the first drain electrode 6 enter the active layer 4 in contact with the first source electrode 5 and the first drain electrode 6, thereby enhancing the active layer 4 conductivity.
  • the active layer is usually made of a zinc oxide material such as zinc oxynitride (ZnON), indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO), since Al 3+ is more active than
  • Zn 2+ in the layer is more than one valence electron, so that the electrons can be bound to form a shallow level trap near the bottom of the conduction band.
  • the trapping force of this trap is small, and the adsorption electrons can be excited and transition to the conduction band at normal temperature to form free electrons, which is why the doping of aluminum atoms can enhance the conductivity of the active layer 4.
  • the effect of the doping concentration of Al 3+ atoms on the conductivity of the active layer is shown in FIG. 3.
  • the abscissa indicates the doping concentration of Al 3+ in the active layer, and the ordinate indicates the active layer. Square resistance (k ⁇ / ⁇ )”.
  • the second source electrode 8 and the second drain electrode 9 are further included on the second source electrode 8 and the second drain electrode 9 and at least covering the etch barrier layer 7 at the first source electrode 5 and the first drain electrode 6.
  • the portion between the portions forms the gate insulating layer 3, and the step of forming the gate electrode 2 on the gate insulating layer 3.
  • a step of forming the gate electrode 2 on the substrate 1 and forming the gate insulating layer 3 on the gate electrode 2, that is, the gate electrode, is also included.
  • the insulating layer 3 is located between the active layer 4 and the gate 2 as shown in FIGS. 2 and 4G.
  • the method for fabricating the thin film transistor of the bottom gate structure includes the following steps:
  • Step 1 sequentially forming a gate material layer and a gate insulating material layer on the substrate 1, and patterning to obtain a gate electrode 2 and a gate insulating layer 3, as shown in FIG. 4A;
  • the substrate 1 is made of a material such as glass, silicon wafer, quartz, plastic, or silicon wafer, preferably glass.
  • the gate 2 is made of a conductive material, preferably a metal material.
  • the gate insulating layer 3 may be deposited by a CVD method, and the material of the material is preferably an insulating material, which may be silicon dioxide, silicon nitride, silicon oxynitride, or the like, or a combination of the above materials.
  • Step 2 forming a semiconductor layer on the gate insulating layer 3, and patterning to obtain an active layer 4, as shown in FIG. 4B;
  • the active layer 4 is a metal oxide semiconductor material, preferably an oxide semiconductor material having a high carrier mobility, such as zinc oxynitride (ZnON), indium gallium zinc oxide (IGZO), indium zinc oxide. (IZO), an oxide semiconductor material such as indium tin zinc oxide (ITZO).
  • ZnON zinc oxynitride
  • IGZO indium gallium zinc oxide
  • IZO indium zinc oxide
  • ITZO indium tin zinc oxide
  • the semiconductor layer may be formed by a sputtering technique or a plasma chemical vapor deposition (PECVD) technique, and the manner in which the semiconductor layer is formed in the present invention is not particularly limited.
  • PECVD plasma chemical vapor deposition
  • the semiconductor layer is patterned by a gray scale mask exposure process to form the active layer 4.
  • Step 3 forming a first electrode material layer on the active layer 4, and patterning to obtain a first source electrode 5 and a first drain electrode 6, as shown in FIG. 4C;
  • the source electrode and the drain electrode are made of a conductive material.
  • the conductive material is a metal material, such as a common metal such as aluminum, zinc, tin, antimony, tungsten, titanium, or a metal alloy material, preferably aluminum. Or an alloy of aluminum.
  • Step 4 heat treatment of the first source electrode 5 and the first drain electrode 6, forming a metal oxide layer 10 on the surface of the first source electrode 5 and the first drain electrode 6, as shown in FIG. 4D;
  • the first source electrode 5 and the first drain electrode 6 may be heat treated by annealing or the like;
  • the annealing process is: annealing in an air atmosphere at a temperature between 200 and 300 degrees Celsius for an interval of 0.5 to 3 hours.
  • the active layer 4 contains the same metal atoms as the first source electrode 5 and the first drain electrode 6, thereby enhancing the The conductivity of the active layer 4 improves the ohmic contact between the source/drain electrodes and the active layer, and improves the stability of the oxide thin film transistor.
  • the first electrode material layer may be a thin layer, such as a thickness, as compared to a subsequently formed second electrode material layer, as compared to a conventional electrode material layer.
  • Step 5 forming an etch barrier material layer on the substrate 1 after forming the oxide layer 10, and patterning to form an etch barrier layer 7, as shown in FIG. 4E, the etch barrier layer 7 covering at least the active layer a portion of the 4 located between the first source electrode 5 and the first drain electrode 6, that is, covering the channel region, in other words, At least the channel region in the active layer 4 is covered by the etch barrier layer 7 to protect a portion of the active layer 4 located in the channel region between the first source electrode 5 and the first drain electrode 6 from the subsequent process
  • step 5 since the etch barrier layer 7 is formed or deposited on the substrate 1 after forming the first source electrode 5 and the first drain electrode 6, the etch barrier layer 7 covers a portion of the first source electrode 5, respectively. And a portion of the first drain electrode 6. As shown in FIGS. 2 and 4G, the etch barrier layer 7 covers at least portions of the first source electrode 5 and the first drain electrode 6 adjacent to each other such that the channel length D2 is smaller than the channel length D1 of the conventional thin film transistor.
  • step 5 when the etch barrier material layer is patterned, the first via hole 11 exposing at least a portion of the first source electrode 5 and the first drain electrode 6 may be exposed in the etch barrier material layer 7. At least a portion of the first via 12 is shown in Figures 4E and 4F.
  • a first source electrode or a first drain electrode portion such that a subsequently formed second source electrode can be electrically connected to the first source electrode, and the second drain electrode can be electrically connected to the first drain electrode, ultimately causing the source and drain electrodes Electrical connection is achieved by the active layer.
  • the etch barrier layer 7 is made of a material capable of blocking the developer and the etching solution, such as silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx). And one or more of silicon oxynitrides (SiON).
  • the material such as silicon oxide (SiOx) is insensitive to the developer and the source and drain etching liquid.
  • Step 6 forming (eg, depositing) a second electrode material layer on the substrate 1 on which the etch barrier layer 7 is formed, and patterning the second electrode material layer to obtain a second source electrode 8 and a second drain electrode 9, As shown in FIG. 4G, wherein the second source electrode 8 is at least partially located in the first via hole 11 in the etch barrier layer 7 and is in electrical contact with the first source electrode 5, and the second drain electrode 9 is at least partially Partially located in the second via 12 in the etch stop layer 7 and in electrical contact with the first drain electrode 6.
  • the second source electrode 8 and the second drain electrode 9 may be formed by processes such as exposure, development, etching, and the like.
  • the second electrode material layer forming the second source and the drain electrode may include a conductive material such as copper, and the thickness thereof may be, for example,
  • a separation distance between the first source electrode 5 and the first drain electrode 6, that is, a channel length D2, is smaller than a first via 11 in the etch barrier layer 7.
  • the separation distance between them i.e., the length of the etch barrier layer 7 at the second source electrode 8 and the second drain electrode 9) D1 is as shown in Figs. 2 and 4G.
  • the present invention does not specifically require specific division of the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode, because the specific electrode at which position is the source electrode or the drain electrode depends on the connection relationship with the pixel electrode.
  • a drain electrode Connected to the pixel electrode in the present application is a drain electrode, the first source electrode corresponds to the position of the second source electrode, and the first drain electrode corresponds to the position of the second drain electrode.
  • the present invention first forms a first source electrode and a first drain electrode on the active layer, followed by forming the first source electrode and the first An etch stop layer is formed on the substrate of the drain electrode, the etch stop layer covering at least a portion of the active layer between the first source electrode and the first drain electrode and covering a portion of the first source electrode and the first drain electrode, respectively Forming a second source electrode and a second drain electrode on the etch barrier layer, the second source electrode being at least partially located in the first via hole and electrically contacting the first source electrode to form a primary electrode of the thin film transistor, and second The drain electrode is at least partially located within the second via and is in electrical contact with the first drain electrode to form a drain electrode of the thin film transistor.
  • a region between the first source and the drain electrode forms a channel, such that a partial overlap between the first source electrode and the first drain electrode and the etch barrier layer is partially covered by the etch barrier layer, Therefore, the formation of the first source electrode and the first drain electrode shortens the transmission distance of carriers between the source and drain electrodes, thereby reducing the channel length of the thin film transistor, so that the film produced according to the above technical solution of the present invention
  • the channel length D2 of the transistor is smaller than the channel length D1 of the thin film transistor fabricated in the prior art.
  • the shorter channel length can reduce the size of the thin film transistor, increase the aperture ratio of the liquid crystal panel, and reduce the power consumption; and the shorter channel length can increase the turn-on current of the thin film transistor and improve the charging efficiency, thereby greatly improving the thin film transistor.
  • Overall performance is conducive to the development of high-resolution products.
  • the first source electrode and the first drain electrode are annealed, in the first source electrode and the first drain electrode in the annealing process.
  • the metal atoms enter into the active layer in contact with the first source electrode and the first drain electrode, thereby enhancing the conductivity of the active layer, thereby improving the ohmic contact problem between the source and drain electrodes and the active layer, and improving oxidation.
  • the stability of the thin film transistor is conducive to the development of high-resolution products.

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Abstract

一种薄膜晶体管，包括栅极（2）、栅极绝缘层（3）、有源层（4）、刻蚀阻挡层（7）、源电极和漏电极，其中源电极包括第一源电极（5）和与第一源电极电连接的第二源电极（8），漏电极包括第一漏电极（6）和与第一漏电极电连接的第二漏电极（9），第一源电极和第一漏电极形成在有源层上，刻蚀阻挡层至少覆盖有源层的位于第一源电极和第一漏电极之间的部分并分别覆盖第一源电极和第一漏电极的彼此邻近的部分，第二源电极和第二漏电极形成在刻蚀阻挡层上。一种薄膜晶体管的制备方法、包括该薄膜晶体管的阵列基板和显示设备。该薄膜晶体管的沟道长度短，从而提高了薄膜晶体管的开启电流，同时还改善了源、漏电极与有源层的欧姆接触问题，提高了薄膜晶体管的稳定性。

Description

薄膜晶体管及其制备方法、阵列基板和显示设备 技术领域
本发明涉及显示领域，尤其是一种薄膜晶体管(Thin Film Transistor，TFT)及其制备方法、包括该薄膜晶体管的阵列基板和显示设备。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示器由于可以做得更轻更薄，可视角度更大，无辐射，并且能够显著节省电能，从而在当前的平板显示设备市场占据了主导地位，被认为是最可能的下一代新型平面显示器。有源矩阵OLED为每一个像素配备了用于控制该像素的薄膜晶体管作为开关，所述薄膜晶体管通常包括栅极、源极和漏极以及栅绝缘层和有源层。
氧化物，如铟镓锌氧化物(IGZO)、铟锡锌氧化物(ITZO)等和非晶硅均可作为薄膜晶体管的有源层材料，与非晶硅薄膜晶体管相比，氧化物薄膜晶体管的载流子浓度是非晶硅薄膜晶体管的十倍左右，载流子迁移率是非晶硅薄膜晶体管的20-30倍，因此，氧化物薄膜晶体管可以大大地提高薄膜晶体管对于像素电极的充放电速率，提高像素的响应速度，进而实现更快的刷新率。氧化物薄膜晶体管能够满足需要快速响应和较大电流的应用场合，如高频、高分辨率、大尺寸的显示器以及有机发光显示器等。因此，氧化物薄膜晶体管成为用于新一代LCD、OLED显示设备的半导体组件。
图1A为现有技术中刻蚀阻挡型氧化物薄膜晶体管的结构示意图，图1B为图1A所示氧化物薄膜晶体管沿A-A’的截面图，在图1B中，11为基板，12为栅极，13为栅极绝缘层，14为有源层，15为刻蚀阻挡层，16为源/漏电极。现有的氧化物薄膜晶体管中，由于氧化物半导体层多为非晶半导体氧化物，因此，其与源漏(SD)金属层的欧姆接触存在问题，从而容易导致薄膜晶体管的稳定性不良。另外，薄膜晶体管的沟道长度会影响薄膜晶体管的开启电流，沟道长度越小薄膜晶体管的开启电流就越大，然而现有的刻蚀阻挡型氧化物薄膜晶体管中，由于刻蚀阻挡层在源、漏电极之前形成，使得现有氧化物薄膜晶体管的与刻蚀阻挡层的尺寸对应的沟道长度D1(图1B)较大，开启电流较小，严重降低了薄膜晶体管的性能，不利于高性能显示设备的开发。
发明内容
为了解决现有技术中存在的上述和其它问题中的一种，本发明提出一种薄膜晶体管及其制备方法、包括该薄膜晶体管的阵列基板和显示设备。
根据本发明的一个方面，提供了一种薄膜晶体管，包括有源层、刻蚀阻挡层、栅极、栅极绝缘层、源电极和漏电极，其中，所述源电极包括第一源电极和第二源电极，所述漏电极包括第一漏电极和第二漏电极，所述第一源电极和第一漏电极形成在所述有源层上，所述刻蚀阻挡层至少覆盖有源层的位于第一源电极和第一漏电极之间的部分并分别覆盖所述第一源电极和第一漏电极的彼此邻近的部分，并且所述第二源电极和第二漏电极形成在所述刻蚀阻挡层上，所述第一源电极与第二源电极电连接，所述第一漏电极与第二漏电极电连接。
在上述薄膜晶体管中，所述刻蚀阻挡层中可以形成有位置分别与第一源电极和第一漏电极对应的第一过孔和第二过孔，第二源电极可以至少部分地位于第一过孔内并与所述第一源电极电接触，第二漏电极可以至少部分地位于第二过孔内并与所述第一漏电极电接触。
在上述薄膜晶体管中，所述第一源电极与所述第一漏电极之间的间隔距离小于所述刻蚀阻挡层中的第一过孔与第二过孔之间的间隔距离。
在上述薄膜晶体管中，第一源电极和第一漏电极由沉积在有源层上的相同的第一电极材料层形成，第二源电极和第二漏电极由沉积在刻蚀阻挡层上的相同的第二电极材料层形成，并且第一电极材料层的厚度可以小于第二电极材料层的厚度。
上述薄膜晶体管还可以包括形成在所述第一源电极和第一漏电极上的氧化层，所述氧化层为通过对所述第一源电极和第一漏电极进行热处理形成的金属氧化层。
在上述薄膜晶体管中，所述第一漏电极和/或第一源电极的材料可以包括铝或铝的合金。
在上述薄膜晶体管中，所述有源层可以由金属氧化物半导体材料形成。所述金属氧化物半导体材料可以包括锌氧化物材料。
在上述薄膜晶体管中，所述有源层可以中含有与所述第一源电极和第一漏电极相同的金属原子。
根据本发明的另一个方面，提供了一种阵列基板，包括基板和形成在基板上的如上所述的薄膜晶体管。
根据本发明的又一个方面，提供了一种显示设备，包括如上所述的阵列基板。
根据本发明的再一个方面，提供了一种薄膜晶体管的制备方法，该制备方法包括以下步骤：
在基板上形成半导体层，并对半导体层进行图形化，得到有源层；
在得到所述有源层的基板上形成第一电极材料层，并对第一电极材料层进行图形化，得到位于有源层上的第一源电极和第一漏电极；
在基板上形成刻蚀阻挡材料层，并对刻蚀阻挡材料层进行图形化，形成刻蚀阻挡层，所述刻蚀阻挡层至少覆盖有源层的位于第一源电极和第一漏电极之间的部分并覆盖所述第一源电极和第一漏电极的彼此邻近的部分；以及
在形成有所述刻蚀阻挡层的基板上形成第二电极材料层，并对第二电极材料层进行图形化，得到第二源电极和第二漏电极，其中，所述第一源电极与第二源电极电连接，所述第一漏电极与第二漏电极电连接。
在上述制备方法中，对刻蚀阻挡材料层进行图形化的步骤可以包括在刻蚀阻挡材料层中形成露出第一源电极的至少一部分的第一过孔和露出第一漏电极的至少一部分的第一过孔的步骤，其中第二源电极可以至少部分地位于所述刻蚀阻挡层中的第一过孔内并与所述第一源电极电接触，第二漏电极至少部分地位于所述刻蚀阻挡层中的第二过孔内并与所述第一漏电极电接触。
在上述制备方法中，所述第一源电极与所述第一漏电极之间的间隔距离小于所述刻蚀阻挡层中的第一过孔与第二过孔之间的间隔距离。
在上述制备方法中，第一电极材料层的厚度可以小于第二电极材料层的厚度。
在形成第一源电极和第一漏电极之后，该制备方法还可以包括对所述第一源电极和第一漏电极进行热处理，以在第一源电极和第一漏电极的表面上形成金属氧化层的步骤。可以利用退火工艺对所述第一源电极和第一漏电极进行热处理。
在上述制备方法中，所述第一漏电极和/或第一源电极的材料可以为铝或铝的合金。
在上述制备方法中，所述有源层可以由金属氧化物半导体材料形成。所述金属氧化物半导体材料可以包括锌氧化物材料。
附图说明
图1A为现有技术中的氧化物薄膜晶体管的俯视图；
图1B为图1A所示氧化物薄膜晶体管沿A-A’线的截面图；
图2为根据本发明一实施例的薄膜晶体管的结构示意图；
图3为说明Al3+掺杂浓度与有源层的导电性能之间的关系的曲线示意图；以及
图4A-4G为根据本发明一实施例的薄膜晶体管的制备工艺的流程图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明进一步详细说明。
另外，在下面的详细描述中，为便于说明，阐述了许多具体的细节以提供对本公开内容的实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其他情况下，公知的结构和装置以图示的方式体现以简化附图。
图2示出了根据本发明的一个示例性实施例的薄膜晶体管的结构。如图2所示，该薄膜晶体管包括例如形成在基板1上的栅极2、栅极绝缘层3、有源层4、刻蚀阻挡层7、源电极和漏电极。
在一个示例中，所述源电极包括第一源电极5和第二源电极8，所述漏电极包括第一漏电极6和第二漏电极9，所述第一源电极5和第一漏电极6形成在所述有源层4上并彼此隔开一距离D2。如本领域技术人员已知的那样，有源层4位于第一源电极5和第一漏电极6之间的部分是沟道部分或区域，在此示例中，该沟道区域的长度，即沟道长度等于D2。
所述有源层4可以为金属氧化物半导体材料，优选为载流子迁移率较高的氧化物半导体材料，比如氮氧化锌(ZnON)、铟镓锌氧化物(IGZO)、氧化铟锌(IZO)、铟锡锌氧化物(ITZO)等氧化物半导体材料。
所述源电极和漏电极由导电材料制成，优选地，所述导电材料为金属材料，比如铝、锌、锡、镆、钨、钛等常用金属，或者金属合金材料，优选为铝或铝的合金。
所述刻蚀阻挡层7至少覆盖有源层的位于第一源电极5和第一漏电极6之 间的部分，即沟道区域，在有源层4中至少沟道区域被刻蚀阻挡层7覆盖，以保护有源层4处于第一源电极5和第一漏电极6之间的沟道区域不受显影液和刻蚀液的侵蚀影响。
其中，所述刻蚀阻挡层7由能够对显影液和刻蚀液起阻挡作用的材料制成，比如硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)和硅的氮氧化物(SiON)中的一种或多种。硅的氧化物(SiOx)等材料对显影液和源、漏刻蚀液不敏感，采用上述材料制作刻蚀阻挡层7时，能够阻挡显影液和源、漏极刻蚀液对有源层4造成的不利影响，满足氧化物薄膜晶体管的基本要求。
根据本发明的实施例，刻蚀阻挡层7分别覆盖第一源电极5的一部分和第一漏电极6的一部分，即，刻蚀阻挡层7是在形成第一源电极5和第一漏电极6之后形成，如沉积在基板1上的，从而覆盖第一源电极5的一部分和第一漏电极6的一部分。如图2所示，刻蚀阻挡层7至少覆盖第一源电极5和第一漏电极6的彼此邻近的部分，从而与现有技术中由于刻蚀阻挡层在源、漏电极之前形成导致的较长的沟道长度D1相比，根据本发明的实施例形成的薄膜晶体管的沟道长度D2较短，即D2＜D1。
上述薄膜晶体管的源电极还可以包括与第一源电极5电连接的第二源电极8，漏电极还可以包括与第一漏电极6电连接的第二漏电极9，第二源电极8和第二漏电极9形成在刻蚀阻挡层7上。如图2所示，第二源电极8至少部分地位于刻蚀阻挡层7中的第一过孔11(参见图4E和4F)内并与第一源电极5电接触的，并且漏电极还可以包括至少部分地位于刻蚀阻挡层7中的第二过孔12(参见图4E和4F)内并与第一漏电极6电接触的第二漏电极9。
如图2所示，第二源电极8至少覆盖并接触第一源电极5从第一过孔11露出的部分，第二源电极8至少覆盖并接触第一漏电极6从第二过孔12露出的部分。所述第二源电极8和第二漏电极9在所述刻蚀阻挡层7之后形成并且因此可以覆盖刻蚀阻挡层7的一部分。所述第一源电极5与第二源电极8电连接，所述第一漏电极6与第二漏电极9电连接，从而能够通过第一源电极5和第二源电极8、第一漏电极6和第二漏电极9分别向有源层4中的源极区域和漏极区域施加相应的电压。
所述源电极和漏电极通过所述有源层4电连接或电导通。
可以看出，所述第一源电极5与所述第一漏电极6之间的间隔距离D2小于所述刻蚀阻挡层7中的第一过孔11与第二过孔12之间的间隔距离(即，刻蚀 阻挡层7位于第二源电极8和第二漏电极9之间的长度)D1。
本发明对于第一源电极、第一漏电极、第二源电极、第二漏电极的具体区分不作特殊要求，因为具体哪个位置的电极是源电极还是漏电极根据与像素电极的连接关系而定，本申请中定义与像素电极连接的是漏电极，第一源电极与第二源电极的位置相对应，第一漏电极与第二漏电极的位置相对应。
在本发明一实施例中，所述薄膜晶体管还可以包括形成在所述第一源电极5和第一漏电极6上的氧化层10，所述氧化层10为通过对所述第一源电极5和第一漏电极6进行热处理形成的金属氧化层。例如，在所述第一源电极5和第一漏电极6形成之后，通过退火等工艺对所述第一源电极5和第一漏电极6进行热处理，热处理后，所述第一源电极5和第一漏电极6的表面上形成金属氧化层10。该热处理是在刻蚀阻挡层7的形成之前进行的，因此，在图2中示出的示例中，图案化后的金属氧化层10位于刻蚀阻挡层7与第一源电极5和第一漏电极6之间。
需要特别说明的是，在对所述第一源电极5和第一漏电极6进行热处理的过程中，所述第一源电极5和第一漏电极6中的金属原子会掺杂进入到与所述第一源电极5和第一漏电极6接触的有源层4中，使得所述有源层4中含有与所述第一源电极5和第一漏电极6相同的金属原子，从而增强所述有源层4的导电性，进而改善源/漏电极与有源层之间的欧姆接触问题，提高氧化物薄膜晶体管的稳定性。
可选地，利用退火工艺对第一源电极5和第一漏电极6进行热处理，所述退火工艺例如为：在空气氛围下，将退火温度设置在200～300摄氏度之间，进行时间为0.5-3个小时的退火。
比如，若选用金属铝作为制作第一源电极5和第一漏电极6的材料，则在退火过程中，暴露在退火环境中的金属铝表面被氧化成铝的氧化物(Al2O3)，同时所述第一源电极5和第一漏电极6中的铝原子会进入到与所述第一源电极5和第一漏电极6接触的有源层4中，从而增强所述有源层4的导电性。
具体地，在退火过程中，铝原子通过扩散到达有源层4，进入氧化物晶格内部，生成铝代锌原子，进而产生氧空位以及自由电子载流子。有源层通常采用氮氧化锌(ZnON)、铟镓锌氧化物(IGZO)、氧化铟锌(IZO)、铟锡锌氧化物(ITZO)等锌氧化物材料制作，由于Al3+比有源层中的Zn2+多一个价电子，因此可以在靠近导带底部的位置，束缚电子形成浅能级陷阱。但是这种陷阱的束缚力很小， 吸附电子常温下就可以被激发并跃迁到导带，形成自由电子，这就是掺杂铝原子能够增强有源层4导电性的原因。Al3+的掺杂浓度对于有源层导电性能的影响如图3所示，图3中，横坐标表示Al3+在有源层中的掺杂浓度，纵坐标表示有源层的“方块电阻(kΩ/□)”。从图3中可以看出，可以控制热处理的条件，使适当数量的Al原子进入有源层以形成合适的Al3+掺杂浓度，以有效地降低有源层的方块电阻。
此外，对于顶栅结构的薄膜晶体管，所述薄膜晶体管还包括：位于所述第二源电极8和第二漏电极9之上并至少覆盖刻蚀阻挡层7位于第一源电极5和第一漏电极6之间的部分的栅极绝缘层3，以及位于所述栅极绝缘层3之上的栅极2。
对于底栅结构的薄膜晶体管，如图2所示，所述薄膜晶体管还包括形成在基板1上的栅极2和形成在栅极2上的栅极绝缘层3，即栅极绝缘层3位于所述有源层4和栅极2之间。
根据本发明的另一方面，还提出一种阵列基板，所述阵列基板包括基板和形成基板上的如上述任一实施例所述的薄膜晶体管。
根据本发明的另一方面，还提出一种显示设备，所述显示设备包括如上所述的阵列基板。
根据本发明的再一方面，还提出一种薄膜晶体管的制备方法，所述制备方法包括以下步骤：
步骤1，在基板1上形成半导体层，并对半导体层进行图形化，得到有源层4；
可选地，所述基板1的制作材料可以包括玻璃、硅片、石英、塑料以及硅片等材料，优选为玻璃。
其中，所述有源层4的材料可以为金属氧化物，优选为载流子迁移率较高的氧化物半导体材料，比如氮氧化锌(ZnON)、铟镓锌氧化物(IGZO)、氧化铟锌(IZO)、铟锡锌氧化物(ITZO)等氧化物半导体材料。
其中，所述半导体层可采用溅射技术或等离子体化学气相沉积(PECVD)技术形成，本发明对于所述半导体层的形成方式不作特殊限定。
可选地，可以通过灰阶掩膜曝光工艺来对半导体层进行图形化，形成有源层4。
步骤2，在形成所述有源层4上的基板上形成，如沉积，第一电极材料层， 并对第一电极材料层进行图形化，得到位于有源层4上的第一源电极5和第一漏电极6；
其中，所述源电极和漏电极由导电材料制成，优选地，所述导电材料为金属材料，比如铝、锌、锡、镆、钨、钛等常用金属，或者金属合金材料，优选为铝或铝的合金。在一个示例中，例如，与常规电极材料层相比，第一电极材料层可以为一薄层，如厚度约为
Figure PCTCN2014089037-appb-000001
步骤3，在已经形成有有源层4、所述第一源电极5和第一漏电极6的基板上形成，如沉积，刻蚀阻挡材料层，并对刻蚀阻挡材料层进行图形化，形成刻蚀阻挡层7，其中，所述刻蚀阻挡层7至少覆盖有源层4的位于第一源电极5和第一漏电极6之间的部分，即覆盖沟道区域，换句话说，在有源层4中至少沟道区域被刻蚀阻挡层7覆盖，以保护有源层4位于第一源电极5和第一漏电极6之间的沟道区域中的部分不受后续工艺中使用的显影液和刻蚀液的侵蚀影响。
其中，所述刻蚀阻挡层7由能够对显影液和刻蚀液起阻挡作用的材料制成，比如硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)和硅的氮氧化物(SiON)中的一种或多种。硅的氧化物(SiOx)等材料对显影液和源、漏刻蚀液不敏感，采用上述材料制作刻蚀阻挡层7时，能够阻挡显影液和源、漏极刻蚀液对有源层4造成的不利影响，满足氧化物薄膜晶体管的基本要求。
在步骤3中，由于刻蚀阻挡层7是在形成第一源电极5和第一漏电极6之后形成或沉积在基板1上的，因此刻蚀阻挡层7分别覆盖第一源电极5的一部分和第一漏电极6的一部分。如图2所示，刻蚀阻挡层7至少覆盖第一源电极5和第一漏电极6的彼此邻近的部分，从而沟道长度D2小于现有薄膜晶体管的沟道长度D1。
在步骤3中，在刻蚀阻挡材料层进行图形化时，还可以在刻蚀阻挡材料层中形成露出第一源电极5的至少一部分的第一过孔11和露出第一漏电极6的至少一部分的第一过孔12，如图4E和4F所示。
该制备方法还可以包括步骤4，其中在基板1上形成如沉积第二电极材料层，并对第二电极材料层进行图形化，得到第二源电极8和第二漏电极9，其中，第二源电极8至少部分地位于所述刻蚀阻挡层7中的第一过孔11内并与所述第一源电极5电接触，第二漏电极9至少部分地位于所述刻蚀阻挡层7中的第二过孔12内并与所述第一漏电极6电接触。
可以采用常规的源/漏电极工艺来制作第二源电极8和第二漏电极9。可选地，可通过曝光、显影、刻蚀等工艺来形成第二源电极8和第二漏电极9。第二电极材料层可以包括半导体工艺的常规电极材料，如铜，并且在一个实施例中，第二电极材料层的厚度大于第一电极材料层的厚度，示例性地，第二电极材料层的厚度约为2000～4000埃
Figure PCTCN2014089037-appb-000002
如上所述，在本发明的实施例中，所述第一源电极5与所述第一漏电极6之间的间隔距离(即，沟道长度)D2小于所述刻蚀阻挡层7中的第一过孔11与第二过孔12之间的间隔距离(即，刻蚀阻挡层7位于第二源电极8和第二漏电极9之间的长度)D1。
本发明对于第一源电极、第一漏电极、第二源电极、第二漏电极的具体区分不作特殊要求，因为具体哪个位置的电极是源电极还是漏电极根据与像素电极的连接关系而定，本申请中定义与像素电极连接的是漏电极，第一源电极与第二源电极的位置相对应，第一漏电极与第二漏电极的位置相对应。
在本发明的一实施例中，所述制备方法在形成第一源电极5和第一漏电极6之后，还包括对所述第一源电极5和第一漏电极6进行热处理，，以在第一源电极和第一漏电极的表面上形成金属氧化层10的步骤。
对于该实施例，在后续进行图形化处理形成刻蚀阻挡层7时，需将对应位置处的氧化层10部分也一并去除，暴露出相应位置处的第一源电极或者第一漏电极部分，如图4F所示，以使得后续形成的第二源电极能够与第一源电极电连接，第二漏电极能够与第一漏电极电连接。
可选地，可通过退火等工艺对所述第一源电极5和第一漏电极6的表层进行热处理；
可选地，所述退火工艺可以为：在空气氛围下，将退火温度设置在200～300摄氏度之间，进行时间为0.5-3个小时的退火。
需要特别说明的是，在对所述第一源电极5和第一漏电极6进行热处理的过程中，所述第一源电极5和第一漏电极6中的金属原子会进入到与所述第一源电极5和第一漏电极6接触的有源层4中，使得所述有源层4中含有与所述第一源电极5和第一漏电极6相同的金属原子，从而增强所述有源层4的导电性，进而改善源/漏电极与有源层之间的欧姆接触问题，提高氧化物薄膜晶体管的稳定性。
比如，若选用金属铝作为制作第一源电极5和第一漏电极6的材料，则在 退火过程中，暴露在退火环境中的金属铝表面被氧化成铝的氧化物(Al2O3)，同时所述第一源电极5和第一漏电极6中的铝原子会进入与所述第一源电极5和第一漏电极6接触的有源层4中，从而增强所述有源层4的导电性。
具体地，在退火过程中，铝原子通过扩散到达有源层4，进入氧化物晶格内部，生成铝代锌原子，进而产生氧空位以及自由电子载流子。有源层通常采用氮氧化锌(ZnON)、铟镓锌氧化物(IGZO)、氧化铟锌(IZO)、铟锡锌氧化物(ITZO)等锌氧化物材料制作，由于Al3+比有源层中的Zn2+多一个价电子，因此可以在靠近导带底部的位置，束缚电子形成浅能级陷阱。但是这种陷阱的束缚力很小，吸附电子常温下就可以被激发并跃迁到导带，形成自由电子，这就是掺杂铝原子能够增强有源层4导电性的原因。Al3+原子的掺杂浓度对于有源层导电性能的影响示意图如图3所示，图3中，横坐标表示Al3+在有源层中的掺杂浓度，纵坐标表示有源层“方块电阻(kΩ/□)”。
此外，在制备顶栅结构的薄膜晶体管时，还包括在所述第二源电极8和第二漏电极9上并至少覆盖刻蚀阻挡层7位于第一源电极5和第一漏电极6之间的部分形成栅极绝缘层3，以及在所述栅极绝缘层3上形成栅极2的步骤。
在制备底栅结构的薄膜晶体管时，在形成所述有源层4之前，还包括在在基板1上形成栅极2和在栅极2上形成栅极绝缘层3，的步骤，即栅极绝缘层3位于所述有源层4和栅极2之间，如图2和4G所示。
下面以底栅结构的薄膜晶体管为例更详细的说明本发明的实施例。如图4A-4G所示，所述底栅结构的薄膜晶体管的制备方法包括以下步骤：
步骤1，在基板1上依次形成栅极材料层和栅极绝缘材料层，并进行图形化，得到栅极2和栅极绝缘层3，如图4A所示；
可选地，所述基板1的制作材料包括玻璃、硅片、石英、塑料以及硅片等材料，优选为玻璃。
其中，所述栅极2由导电材料制成，优选为金属材料。
可选地，所述栅极绝缘层3可通过CVD方法来沉积，其制作材料优选为绝缘材料，可以为二氧化硅、氮化硅、氮氧化硅等，或者以上材料的组合。
步骤2，在所述栅极绝缘层3上形成半导体层，并进行图形化，得到有源层4，如图4B所示；
其中，所述有源层4为金属氧化物半导体材料，优选为载流子迁移率较高的氧化物半导体材料，比如氮氧化锌(ZnON)、铟镓锌氧化物(IGZO)、氧化铟锌 (IZO)、铟锡锌氧化物(ITZO)等氧化物半导体材料。
其中，所述半导体层可采用溅射技术或等离子体化学气相沉积(PECVD)技术形成，本发明对于所述半导体层的形成方式不作特殊限定。
可选地，通过灰阶掩膜曝光工艺来对半导体层进行图形化，形成有源层4。
步骤3，在所述有源层4上形成第一电极材料层，并进行图形化，得到第一源电极5和第一漏电极6，如图4C所示；
其中，所述源电极和漏电极由导电材料制成，优选地，所述导电材料为金属材料，比如铝、锌、锡、镆、钨、钛等常用金属，或者金属合金材料，优选为铝或铝的合金。
步骤4，对所述第一源电极5和第一漏电极6进行热处理，在第一源电极5和第一漏电极6的表面上形成金属氧化层10，如图4D所示；
可选地，可通过退火等工艺对所述第一源电极5和第一漏电极6进行热处理；
可选地，所述退火工艺为：在空气氛围下，将退火温度设置在200～300摄氏度之间，进行时间为0.5-3个小时的退火。
需要特别说明的是，在对所述第一源电极5和第一漏电极6进行热处理的过程中，所述第一源电极5和第一漏电极6中的金属原子会进入到与所述第一源电极5和第一漏电极6接触的有源层4中，使得所述有源层4中含有与所述第一源电极5和第一漏电极6相同的金属原子，从而增强所述有源层4的导电性，进而改善源/漏电极与有源层的欧姆接触问题，提高氧化物薄膜晶体管的稳定性。
比如，若选用金属铝作为制作第一源电极5和第一漏电极6的材料，则在退火过程中，暴露在退火环境中的金属铝表面被氧化成铝的氧化物(Al2O3)，同时所述第一源电极5和第一漏电极6中的铝原子会进入与所述第一源电极5和第一漏电极6接触的有源层4中，从而增强所述有源层4的导电性。在一个示例中，例如，与常规电极材料层相比，如与后续形成的第二电极材料层相比，第一电极材料层可以为一薄层，如厚度约为
Figure PCTCN2014089037-appb-000003
从而便于热处理和金属原子到有源层中的扩散。
步骤5，在形成所述氧化层10后的基板1上形成刻蚀阻挡材料层，并进行图形化，形成刻蚀阻挡层7，如图4E所示，刻蚀阻挡层7至少覆盖有源层4的位于第一源电极5和第一漏电极6之间的部分，即覆盖沟道区域，换句话说， 在有源层4中至少沟道区域被刻蚀阻挡层7覆盖，以保护有源层4位于第一源电极5和第一漏电极6之间的沟道区域中的部分不受后续工艺中使用的显影液和刻蚀液的侵蚀影响；
在步骤5中，由于刻蚀阻挡层7是在形成第一源电极5和第一漏电极6之后形成或沉积在基板1上的，因此刻蚀阻挡层7分别覆盖第一源电极5的一部分和第一漏电极6的一部分。如图2和4G所示，刻蚀阻挡层7至少覆盖第一源电极5和第一漏电极6的彼此邻近的部分，从而沟道长度D2小于常规薄膜晶体管的沟道长度D1。
在步骤5中，在对刻蚀阻挡材料层进行图形化时，还可以在刻蚀阻挡材料层7中形成露出第一源电极5的至少一部分的第一过孔11和露出第一漏电极6的至少一部分的第一过孔12，如图4E和4F所示。
需要特别说明的是，在对刻蚀阻挡材料层进行图形化处理形成刻蚀阻挡层7时，同时将对应位置处的氧化层10部分也一并去除，如图4F所示，暴露出相应位置处的第一源电极或者第一漏电极部分，以使得后续形成的第二源电极能够与第一源电极电连接，第二漏电极能够与第一漏电极电连接，最终使得源、漏电极通过有源层实现电连接。
其中，所述刻蚀阻挡层7由能够对显影液和刻蚀液起阻挡作用的材料制成，比如硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)和硅的氮氧化物(SiON)中的其中一种或多种。硅的氧化物(SiOx)等材料对显影液和源、漏刻蚀液不敏感，采用上述材料制作刻蚀阻挡层7时，能够阻挡显影液和源、漏极刻蚀液对有源层4造成的不利影响，满足氧化物晶体管的基本要求。
步骤6，在形成有刻蚀阻挡层7的基板1上形成(如沉积)第二电极材料层，并对第二电极材料层进行图形化，得到第二源电极8和第二漏电极9，如图4G所示，其中，第二源电极8至少部分地位于所述刻蚀阻挡层7中的第一过孔11内并与所述第一源电极5电接触，第二漏电极9至少部分地位于所述刻蚀阻挡层7中的第二过孔12内并与所述第一漏电极6电接触。
可选地，可通过曝光、显影、刻蚀等工艺来形成第二源电极8和第二漏电极9。形成第二源、漏电极的第二电极材料层可以包括铜等导电材料，其厚度例如可以为
Figure PCTCN2014089037-appb-000004
在本发明的实施例中，所述第一源电极5与所述第一漏电极6之间的间隔距离，即沟道长度D2，小于所述刻蚀阻挡层7中的第一过孔11与第二过孔12 之间的间隔距离(即，刻蚀阻挡层7位于第二源电极8和第二漏电极9的长度)D1，如图2和4G所示。
本发明对于第一源电极、第一漏电极、第二源电极、第二漏电极的具体区分不作特殊要求，因为具体哪个位置的电极是源电极还是漏电极根据与像素电极的连接关系而定，本申请中定义与像素电极连接的是漏电极，第一源电极与第二源电极的位置相对应，第一漏电极与第二漏电极的位置相对应。
根据上述任一实施例所描述的制备方法及其得到的薄膜晶体管，一方面，本发明首先在有源层上形成第一源电极和第一漏电极，随后在形成有第一源电极和第一漏电极的基板上形成刻蚀阻挡层，刻蚀阻挡层至少覆盖有源层的位于第一源电极和第一漏电极之间的部分并分别覆盖第一源电极和第一漏电极的一部分，再在刻蚀阻挡层上形成第二源电极和第二漏电极，第二源电极至少部分地位于第一过孔内并与第一源电极电接触以构成薄膜晶体管的原电极，第二漏电极至少部分地位于第二过孔内并与第一漏电极电接触以构成薄膜晶体管的漏电极。在通电的情况下，第一源、漏电极之间的区域形成沟道，这样由于第一源电极和第一漏电极与刻蚀阻挡层之间存在部分重叠或被刻蚀阻挡层部分覆盖，因此，第一源电极和第一漏电极的形成缩短了源、漏电极之间载流子的传输距离，进而减小了薄膜晶体管的沟道长度，使得根据本发明上述技术方案制得的薄膜晶体管的沟道长度D2小于现有技术制得的薄膜晶体管的沟道长度D1。较短的沟道长度能够减小薄膜晶体管的尺寸，提高液晶面板的开口率，减少能耗；并且较短的沟道长度能够提高薄膜晶体管的开启电流，提高充电效率，从而大大提高薄膜晶体管的整体性能，有利于高分辨产品的开发。另一方面，本发明还在第一源电极和第一漏电极形成后，对第一源电极和第一漏电极进行退火处理，在退火过程中，第一源电极和第一漏电极中的金属原子会进入与第一源电极和第一漏电极接触的有源层中，从而增强了有源层的导电性，进而改善源、漏电极与有源层之间的欧姆接触问题，提高氧化物薄膜晶体管的稳定性。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (20)

  1. 一种薄膜晶体管，包括有源层(4)、刻蚀阻挡层(7)、栅极、栅极绝缘层、源电极和漏电极，其中：
    所述源电极包括第一源电极(5)和第二源电极(8)，所述漏电极包括第一漏电极(6)和第二漏电极(9)，所述第一源电极(5)和第一漏电极(6)形成在所述有源层(4)上；
    所述刻蚀阻挡层(7)至少覆盖有源层的位于第一源电极和第一漏电极之间的部分并分别覆盖所述第一源电极(5)和第一漏电极(6)的彼此邻近的部分；并且所述第二源电极(8)和第二漏电极(9)形成在所述刻蚀阻挡层(7)上，所述第一源电极(5)与第二源电极(8)电连接，所述第一漏电极(6)与第二漏电极(9)电连接。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述刻蚀阻挡层中形成有位置分别与第一源电极和第一漏电极对应的第一过孔(11)和第二过孔(12)，第二源电极(8)至少部分地位于第一过孔内并与所述第一源电极(5)电接触，第二漏电极(9)至少部分地位于第二过孔内并与所述第一漏电极(6)电接触。
  3. 根据权利要求2所述的薄膜晶体管，其中，所述第一源电极(5)与所述第一漏电极(6)之间的间隔距离小于所述刻蚀阻挡层(7)中的第一过孔与第二过孔之间的间隔距离。
  4. 根据权利要求2所述的薄膜晶体管，其中
    第一源电极和第一漏电极由沉积在有源层上的相同的第一电极材料层形成，第二源电极和第二漏电极由沉积在刻蚀阻挡层上的相同的第二电极材料层形成，并且
    第一电极材料层的厚度小于第二电极材料层的厚度。
  5. 根据权利要求1-4中任一项所述的薄膜晶体管，还包括形成在所述第一源电极(5)和第一漏电极(6)上的氧化层(10)，所述氧化层(10)为通过对所述第一源电极(5)和第一漏电极(6)进行热处理形成的金属氧化层。
  6. 根据权利要求5所述的薄膜晶体管，其中，所述第一漏电极(5)和/或第一源电极(6)的材料包括铝或铝的合金。
  7. 根据权利要求1-6中任一项所述的薄膜晶体管，其中，所述有源层(4)由金属氧化物半导体材料形成。
  8. 根据权利要求7所述的薄膜晶体管，其中所述金属氧化物半导体材料 包括锌氧化物材料。
  9. 根据权利要求7或8所述的薄膜晶体管，其中，所述有源层(4)中含有与所述第一源电极(5)和第一漏电极(6)相同的金属原子。
  10. 一种阵列基板，包括基板和形成在基板上的如权利要求1-9中任一项所述的薄膜晶体管。
  11. 一种显示设备，包括如权利要求10所述的阵列基板。
  12. 一种薄膜晶体管的制备方法，该制备方法包括以下步骤：
    在基板(1)上形成半导体层，并对半导体层进行图形化，得到有源层(4)；
    在得到所述有源层(4)的基板上形成第一电极材料层，并对第一电极材料层进行图形化，得到位于有源层上的第一源电极(5)和第一漏电极(6)；
    在基板上形成刻蚀阻挡材料层，并对刻蚀阻挡材料层进行图形化，形成刻蚀阻挡层(7)，所述刻蚀阻挡层(7)至少覆盖有源层的位于第一源电极和第一漏电极之间的部分并覆盖所述第一源电极(5)和第一漏电极(6)的彼此邻近的部分；以及
    在形成有所述刻蚀阻挡层(7)的基板上形成第二电极材料层，并对第二电极材料层进行图形化，得到第二源电极(8)和第二漏电极(9)，其中，所述第一源电极(5)与第二源电极(8)电连接，所述第一漏电极(6)与第二漏电极(9)电连接。
  13. 根据权利要求12所述的制备方法，其中对刻蚀阻挡材料层进行图形化的步骤包括在刻蚀阻挡材料层中形成露出第一源电极的至少一部分的第一过孔和露出第一漏电极的至少一部分的第一过孔的步骤，
    其中第二源电极(8)至少部分地位于所述刻蚀阻挡层(7)中的第一过孔内并与所述第一源电极(5)电接触，第二漏电极(9)至少部分地位于所述刻蚀阻挡层(7)中的第二过孔内并与所述第一漏电极(6)电接触。
  14. 根据权利要求13所述的制备方法，其中，所述第一源电极(5)与所述第一漏电极(6)之间的间隔距离小于所述刻蚀阻挡层(7)中的第一过孔与第二过孔之间的间隔距离。
  15. 根据权利要求13所述的制备方法，其中第一电极材料层的厚度小于第二电极材料层的厚度。
  16. 根据权利要求10-15中任一项所述的制备方法，其中，在形成第一源电极(5)和第一漏电极(6)之后，该制备方法还包括对所述第一源电极(5)和第一漏电极(6)进行热处理，以在第一源电极和第一漏电极的表面上形成金属氧化层 (10)的步骤。
  17. 根据权利要求16所述的制备方法，其中，利用退火工艺对所述第一源电极(5)和第一漏电极(6)进行热处理。
  18. 根据权利要求17所述的制备方法，其特征在于，所述第一漏电极(5)和/或第一源电极(6)的材料为铝或铝的合金。
  19. 根据权利要求12-18中任一项所述的制备方法，其特征在于，所述有源层(4)由金属氧化物半导体材料形成。
  20. 根据权利要求19所述的薄膜晶体管，其中所述金属氧化物半导体材料包括锌氧化物材料。
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