+

WO2016002846A1 - Dispositif semi-conducteur - Google Patents

Dispositif semi-conducteur Download PDF

Info

Publication number
WO2016002846A1
WO2016002846A1 PCT/JP2015/069017 JP2015069017W WO2016002846A1 WO 2016002846 A1 WO2016002846 A1 WO 2016002846A1 JP 2015069017 W JP2015069017 W JP 2015069017W WO 2016002846 A1 WO2016002846 A1 WO 2016002846A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
metal plate
semiconductor device
insulating resin
resin layer
Prior art date
Application number
PCT/JP2015/069017
Other languages
English (en)
Japanese (ja)
Inventor
俊佑 望月
和哉 北川
洋次 白土
啓太 長橋
美香 津田
憲也 平沢
素美 黒川
Original Assignee
住友ベークライト株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 住友ベークライト株式会社 filed Critical 住友ベークライト株式会社
Priority to JP2016531422A priority Critical patent/JP6635034B2/ja
Publication of WO2016002846A1 publication Critical patent/WO2016002846A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Definitions

  • the present invention relates to a semiconductor device.
  • a type in which the semiconductor chip is mounted on one surface of the metal plate and an insulating resin layer is provided on the other surface of the metal plate There are things.
  • Patent Document 1 a semiconductor chip is mounted on one surface of a metal plate (the lead frame of the same document), an insulating resin layer is provided on the other surface of the metal plate, and the metal plate side in the insulating resin layer is A semiconductor device in which a metal layer (a heat sink of the same document) is provided on the opposite surface is described.
  • the insulating resin layer of the same literature is comprised including the secondary aggregation particle
  • the film thickness of the insulating resin layer when the average particle diameter of the flaky boron nitride secondary agglomerated particles contained in the insulating resin layer is too large compared to the film thickness of the insulating resin layer, the film thickness of the insulating resin layer.
  • the electric field is most concentrated in the plane of the insulating resin layer as the package of the semiconductor device becomes larger, even if such deterioration in insulation does not become a problem. The electric field at the location becomes stronger.
  • the present invention has been made in view of the above-described problems, and a semiconductor device having an insulating resin layer in which the film thickness is uniformly made uniform, the generation of voids is suppressed, and the thermal conductivity is good
  • the purpose is to provide.
  • the present invention A metal plate, A semiconductor chip provided on the first surface side of the metal plate; An insulating resin layer bonded to a second surface opposite to the first surface of the metal plate; Mold resin sealing the semiconductor chip and the metal plate; With The insulating resin layer includes secondary aggregated particles formed by isotropic aggregation of primary particles of flaky boron nitride, When the thickness of the insulating resin layer is D and the average particle diameter of the secondary aggregated particles is d, A semiconductor device having d / D of 0.05 or more and 0.8 or less is provided.
  • the insulating resin layer can have a structure with good thermal conductivity. Furthermore, since d / D is 0.8 or less, the insulating resin layer can be made to have a structure in which the film thickness is made uniform and has good insulating properties and the generation of voids is suppressed. .
  • the present invention it is possible to provide a semiconductor device having an insulating resin layer in which the film thickness is made uniform and the generation of voids is suppressed and the thermal conductivity is good.
  • 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. It is typical sectional drawing of the insulating resin layer of the semiconductor device which concerns on 1st Embodiment. It is typical sectional drawing of the semiconductor device which concerns on 2nd Embodiment. It is typical sectional drawing of the semiconductor device which concerns on 3rd Embodiment. It is typical sectional drawing of the semiconductor device which concerns on 4th Embodiment. It is typical sectional drawing of the semiconductor device which concerns on 5th Embodiment. It is typical sectional drawing of the semiconductor device which concerns on 6th Embodiment.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor device 100 according to the first embodiment.
  • FIG. 2 is a schematic cross-sectional view of the insulating resin layer 140 of the semiconductor device 100 according to the first embodiment.
  • the positional relationship (vertical relationship, etc.) of each component of the semiconductor device 100 may be described as the relationship shown in each drawing.
  • the positional relationship in this description is independent of the positional relationship when the semiconductor device 100 is used or manufactured.
  • the semiconductor device 100 is bonded to the heat sink 130, the semiconductor chip 110 provided on the first surface 131 side of the heat sink 130, and the second surface 132 opposite to the first surface 131 of the heat sink 130. And an insulating resin layer 140 and a mold resin 180 sealing the semiconductor chip 110 and the heat sink 130.
  • the insulating resin layer 140 includes secondary agglomerated particles 144 formed by isotropic aggregation of the scaly boron nitride primary particles 143. When the thickness of the insulating resin layer 140 is D and the average particle diameter of the secondary aggregated particles 144 is d, d / D is 0.05 or more and 0.8 or less. Details will be described below.
  • the semiconductor device 100 includes, for example, a conductive layer 120, an electrode terminal portion 135, a metal layer 150, a lead 160, and a wire (metal wiring) 170 in addition to the above configuration.
  • An electrode pattern (not shown) is formed on the upper surface 111 of the semiconductor chip 110, and a conductive pattern (not shown) is formed on the lower surface 112 of the semiconductor chip 110.
  • the lower surface 112 of the semiconductor chip 110 is bonded to the first surface 131 of the heat sink 130 via a conductive layer 120 such as silver paste.
  • the electrode pattern on the upper surface 111 of the semiconductor chip 110 is electrically connected to the electrode 161 of the lead 160 via the wire 170.
  • the mold resin 180 constitutes a housing by sealing the wires 170, the conductive layer 120, and portions of the leads 160 in addition to the semiconductor chip 110 and the heat sink 130 inside. Another part of each lead 160 protrudes from the side surface of the mold resin 180 to the outside of the mold resin 180.
  • the lower surface 182 of the mold resin 180 and the second surface 132 of the heat sink 130 are located on the same plane.
  • One end portion of the electrode terminal portion 135 is located in the mold resin 180 and is electrically connected to the heat sink 130, and the other end portion protrudes outside the mold resin 180. For this reason, the heat sink 130 plays a role as an electrode that receives external power supply.
  • the heat sink 130 is made of metal.
  • the electrode terminal portion 135 is formed integrally with the heat sink 130. That is, the electrode terminal portion 135 is a part of the heat sink 130. In this case, the electrode terminal portion 135 is in a state of being electrically connected to the heat sink 130 by itself. However, the electrode terminal portion 135 may be formed separately from the heat sink 130. In this case, one end portion of the electrode terminal portion 135 is electrically connected to, for example, the first surface 131 of the heat sink 130 via a conductive layer (not shown).
  • the insulating resin layer 140 is a heat conducting material having heat dissipation.
  • a heat conductive sheet heat radiating resin sheet
  • a heat conductive filler filler
  • the upper surface 141 of the insulating resin layer 140 is bonded to the second surface 132 of the heat sink 130 and the lower surface 182 of the mold resin 180. That is, the mold resin 180 is in contact with the surface (upper surface 141) of the insulating resin layer 140 on the heat sink 130 side around the heat sink 130.
  • the upper surface 151 of the metal layer 150 is joined to the lower surface 142 of the insulating resin layer 140. That is, one surface (upper surface 151) of the metal layer 150 is bonded to a surface (lower surface 142) on the opposite side of the heat sink 130 side of the insulating resin layer 140.
  • the outline of the upper surface 151 of the metal layer 150 and the outline of the surface of the insulating resin layer 140 opposite to the heat sink 130 (the lower surface 142) preferably overlap.
  • the entire surface of the metal layer 150 opposite to the one surface (upper surface 151) (lower surface 152) is exposed from the mold resin 180.
  • the insulating resin layer 140 is bonded to the second surface 132 of the heat sink 130 and the lower surface 182 of the mold resin 180, the insulating resin layer 140 is , Except for the upper surface 141, it is exposed to the outside of the mold resin 180. The entire metal layer 150 is exposed to the outside of the mold resin 180.
  • the second surface 132 and the first surface 131 of the heat sink 130 are each formed flat, for example.
  • the mounting floor area of the semiconductor device 100 is not particularly limited, but can be 10 ⁇ 10 mm or more and 100 ⁇ 100 mm or less as an example.
  • the mounting floor area of the semiconductor device 100 is the area of the lower surface 152 of the metal layer 150. That is, the planar shape of the metal layer 150 can be a rectangular shape with a side length of 10 mm or more and 100 mm or less, and the lower surface 152 thereof has a rectangular shape with a side length of 10 mm or more and 100 mm or less. Can do.
  • the number of semiconductor chips 110 mounted on one heat sink 130 is not particularly limited. There may be one or more. For example, it may be 3 or more (6 etc.). That is, as an example, three or more semiconductor chips 110 are provided on the first surface 131 side of one heat sink 130, and the mold resin 180 collectively seals these three or more semiconductor chips 110.
  • the semiconductor device 100 is, for example, a power semiconductor device. That is, the semiconductor chip 110 is, for example, a power semiconductor chip.
  • the semiconductor device 100 for example, 2 in 1 in which two semiconductor chips 110 are sealed in a mold resin 180, 6 in 1 in which six semiconductor chips 110 are sealed in a mold resin 180, or 7 in 7 in a mold resin 180.
  • a 7-in-1 configuration in which individual semiconductor chips 110 are sealed can be employed.
  • the insulating resin layer 140 includes a filler in the thermosetting resin 145.
  • the film thickness of the insulating resin layer 140 is, for example, 50 ⁇ m or more and 500 ⁇ m or less.
  • thermosetting resin 145 examples include an epoxy resin, a polyimide resin, a benzoxazine resin, an unsaturated polyester resin, a phenol resin, a melamine resin, a silicone resin, a bismaleimide resin, and an acrylic resin. Examples thereof include resins and cyanate resins. As the thermosetting resin 145, one of these may be used alone, or two or more may be used in combination. As the thermosetting resin 145, an epoxy resin is preferable. By using an epoxy resin, the glass transition temperature can be increased and the thermal conductivity of the insulating resin layer 140 can be improved. Moreover, since glass transition temperature can be raised by using cyanate resin, the heat resistance of the insulating resin layer 140 can be improved.
  • epoxy resin examples include bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol E type epoxy resin, bisphenol S type epoxy resin, bisphenol M type epoxy resin (4,4 ′-(1,3-phenylenediiso Pridiene) bisphenol type epoxy resin), bisphenol P type epoxy resin (4,4 ′-(1,4-phenylenediisopridiene) bisphenol type epoxy resin), bisphenol Z type epoxy resin (4,4′-cyclohexyl) Diene bisphenol type epoxy resin), etc .; phenol novolac type epoxy resin, cresol novolac type epoxy resin, tetraphenol group ethane type novolac type epoxy resin, novo having condensed ring aromatic hydrocarbon structure Novolak epoxy resins such as epoxy resins; biphenyl epoxy resins; arylalkylene epoxy resins such as xylylene epoxy resins and biphenyl aralkyl epoxy resins; naphthylene ether epoxy resins, naphthol epoxy resins, naphthal
  • epoxy resin one of these may be used alone, or two or more may be used in combination.
  • epoxy resins bisphenol type epoxy resin, novolac type epoxy resin, biphenyl type epoxy resin, arylalkylene type epoxy resin, naphthalene type epoxy from the viewpoint of further improving the heat resistance and insulation reliability of the obtained insulating resin layer 140
  • epoxy resins bisphenol type epoxy resin, novolac type epoxy resin, biphenyl type epoxy resin, arylalkylene type epoxy resin, naphthalene type epoxy from the viewpoint of further improving the heat resistance and insulation reliability of the obtained insulating resin layer 140
  • One or more selected from the group consisting of resins, anthracene type epoxy resins, and dicyclopentadiene type epoxy resins are preferred.
  • the cyanate resin is not particularly limited.
  • the cyanate resin is a compound having an —OCN group in the molecule, and forms a three-dimensional network structure by the reaction of the —OCN group by heating, and is cured. Resin.
  • Specific examples include 1,3-dicyanatobenzene, 1,4-dicyanatobenzene, 1,3,5-tricyanatobenzene, 1,3-dicyanatonaphthalene, 1,4-dicyanatonaphthalene, 1, 6-dicyanatonaphthalene, 1,8-dicyanatonaphthalene, 2,6-dicyanatonaphthalene, 2,7-dicyanatonaphthalene, 1,3,6-tricyanatonaphthalene, 4,4'-dicyanatobiphenyl, bis (4-cyanatophenyl) methane, bis (3,5-dimethyl-4-cyanatophenyl) methane, 2,2-bis (4-cyanatophenyl) propane, 2,2-bis (3,5-dibromo -4-Cyanatophenyl) propane, bis (4-cyanatophenyl) ether, bis (4-cyanatophenyl) thioether, bis (4-cyanatophenyl) s And ruthenes, tris (4-cyan
  • a prepolymer having a triazine ring formed by trimerizing a cyanate group can also be used.
  • This prepolymer is obtained by polymerizing the above-mentioned polyfunctional cyanate resin monomer using, for example, an acid such as mineral acid or Lewis acid, a base such as sodium alcoholate or tertiary amine, or a salt such as sodium carbonate as a catalyst. It is done.
  • an acid such as mineral acid or Lewis acid
  • a base such as sodium alcoholate or tertiary amine
  • a salt such as sodium carbonate as a catalyst. It is done.
  • cyanate resin especially novolak-type cyanate resin
  • the content of the thermosetting resin 145 contained in the insulating resin layer 140 is not particularly limited as long as it is appropriately adjusted according to the purpose, but it is 1% by mass or more and 30% by mass with respect to 100% by mass of the insulating resin layer. The following is preferable, and 5 mass% or more and 20 mass% or less are more preferable.
  • the content of the thermosetting resin 145 is equal to or more than the lower limit value, handling properties are improved, and the insulating resin layer 140 can be easily formed.
  • the content of the thermosetting resin 145 is not more than the above upper limit value, the strength and flame retardancy of the insulating resin layer 140 are further improved, and the thermal conductivity of the insulating resin layer 140 is further improved.
  • the insulating resin layer 140 preferably further includes a curing agent.
  • a curing agent one or more selected from a curing catalyst and a phenol-based curing agent can be used.
  • the curing catalyst include organic metal salts such as zinc naphthenate, cobalt naphthenate, tin octylate, cobalt octylate, bisacetylacetonate cobalt (II), and trisacetylacetonate cobalt (III); triethylamine, tributylamine, Tertiary amines such as 1,4-diazabicyclo [2.2.2] octane; 2-phenyl-4-methylimidazole, 2-ethyl-4-methylimidazole, 2,4-diethylimidazole, 2-phenyl-4 -Imidazoles such as methyl-5-hydroxyimidazole and 2-phenyl-4,5-dihydroxymethylimi
  • the curing catalyst (C-1) one kind including these derivatives can be used alone, or two or more kinds including these derivatives can be used in combination.
  • the content of the curing catalyst contained in the insulating resin layer 140 is not particularly limited, but is preferably 0.001% by mass or more and 1% by mass or less with respect to 100% by mass of the insulating resin layer.
  • phenolic curing agents include phenol novolak resins, cresol novolak resins, naphthol novolak resins, aminotriazine novolak resins, novolak resins and other novolak type phenol resins; terpene modified phenol resins, dicyclopentadiene modified phenol resins and the like.
  • Resin Aralkyl type resin such as phenol aralkyl resin having phenylene skeleton and / or biphenylene skeleton, naphthol aralkyl resin having phenylene skeleton and / or biphenylene skeleton; Bisphenol compound such as bisphenol A and bisphenol F; Resol type phenol resin and the like These may be used alone or in combination of two or more.
  • the phenolic curing agent is preferably a novolac type phenol resin or a resol type phenol resin.
  • curing agent is not specifically limited, 1 to 30 mass% is preferable with respect to 100 mass% of insulating resin layers, and 5 to 15 mass% is more preferable.
  • secondary aggregated particles 144 formed by agglomerating primary particles 143 of flaky boron nitride isotropically (that is, in a state of being oriented in a random direction).
  • the insulating resin layer 140 includes, for example, secondary aggregated particles 144 formed by isotropic aggregation of the scaly boron nitride primary particles 143.
  • the primary particles 143 mean individual particles that are not aggregated.
  • the shape of the secondary agglomerated particles 144 is, for example, spherical.
  • the insulating resin layer 140 may include primary particles 143 arranged isotropically (that is, in a random direction) in the thermosetting resin 145 in addition to the secondary aggregated particles 144 as a filler. , It does not have to be included. Further, as the filler, for example, one or more of silica, alumina, aluminum nitride, silicon carbide and the like may be included.
  • Secondary agglomerated particles 144 can be formed, for example, by agglomerating scaly boron nitride using a spray drying method or the like and then firing the agglomerated particles.
  • the firing temperature is, for example, 1200 to 2500 ° C.
  • dicyclohexane is used as the thermosetting resin. It is particularly preferable to use a pentadiene type epoxy resin or a novolac type epoxy resin.
  • the average particle size of the secondary agglomerated particles 144 is preferably 5 ⁇ m or more and 180 ⁇ m or less, for example. Thereby, the insulating resin layer 140 excellent in the balance between thermal conductivity and electrical insulation can be realized.
  • the content of the filler with respect to the entire insulating resin layer 140 is, for example, preferably 65% by mass or more and 90% by mass or less, and more preferably 70% by mass or more and 85% by mass or less.
  • the content of the filler is, for example, preferably 65% by mass or more and 90% by mass or less, and more preferably 70% by mass or more and 85% by mass or less.
  • the thickness of the insulating resin layer 140 is D and the average particle diameter of the secondary aggregated particles 144 is d, d / D is 0.05 or more and 0.8 or less.
  • the thickness D of the insulating resin layer 140 can be, for example, an average value of thicknesses at a plurality of locations (5 locations, 10 locations, etc.).
  • the average particle diameter d of the secondary aggregated particles 144 can be an average value of the particle diameters of a plurality of (5, 10, etc.) secondary aggregated particles 144 in the insulating resin layer 140.
  • the average particle diameter d is the particle diameter d1 to d10. It can be an average value.
  • d / D is preferably less than 0.5.
  • the thermal conductivity in the thickness direction of the insulating resin layer 140 is preferably 6 W / m ⁇ K or more and 50 W / m ⁇ K or less, more preferably 7 W / m ⁇ K or more and 50 W / m ⁇ K or less, and more preferably 8 W / m ⁇ K or more. 50 W / m ⁇ K or less is more preferable, and 9 W / m ⁇ K or more and 50 W / m ⁇ K or less is more preferable. By doing so, it is possible to obtain the insulating resin layer 140 exhibiting better characteristics in terms of thermal resistance.
  • the thermal conductivity in the thickness direction of the insulating resin layer 140 can be measured by, for example, a laser flash method.
  • the heat sink 130 and the semiconductor chip 110 are prepared, and the lower surface 112 of the semiconductor chip 110 is bonded to the first surface 131 of the heat sink 130 via the conductive layer 120 such as silver paste.
  • a lead frame (not shown) including the lead 160 is prepared, and the electrode pattern on the upper surface of the semiconductor chip 110 and the electrode 161 of the lead 160 are electrically connected to each other through the wire 170.
  • the semiconductor chip 110, the conductive layer 120, the heat sink 130, the wire 170, and a part of the lead 160 are collectively sealed with the mold resin 180.
  • thermosetting resin constituting the thermally conductive sheet is a B stage. Furthermore, one surface (upper surface 151) of the metal layer 150 is attached to the surface (lower surface 142) on the side opposite to the heat sink 130 side of the insulating resin layer 140. Then, by thermosetting the thermosetting resin constituting the heat conductive sheet to form a C stage, the heat conductive sheet becomes the insulating resin layer 140, the second surface 132 of the heat sink 130, and the mold resin 180. The upper surface 151 of the metal layer 150 is bonded to the lower surface 182 with the insulating resin layer 140 interposed therebetween.
  • each lead 160 is cut from the frame (not shown) of the lead frame.
  • the semiconductor device 100 having the structure as shown in FIG. 1 is obtained.
  • the semiconductor device 100 includes the heat sink 130, the semiconductor chip 110 provided on the first surface 131 side of the heat sink 130, and the opposite side of the first surface 131 of the heat sink 130.
  • the insulating resin layer 140 bonded to the second surface 132 and the mold resin 180 that seals the semiconductor chip 110 and the heat sink 130 are provided.
  • the insulating resin layer 140 includes secondary agglomerated particles 144 formed by isotropic aggregation of the scaly boron nitride primary particles 143. When the thickness of the insulating resin layer 140 is D and the average particle diameter of the secondary aggregated particles 144 is d, d / D is 0.05 or more and 0.8 or less.
  • the insulating resin layer 140 can have a structure with good thermal conductivity. Furthermore, since d / D is 0.8 or less, the insulating resin layer 140 should have a structure in which the film thickness is made uniform and has good insulation and the generation of voids is suppressed. it can. Moreover, it can suppress that the thermal resistance of the insulating resin layer 140 increases locally because the film thickness of the insulating resin layer 140 is made uniform uniformly.
  • the insulating resin layer 140 containing the secondary aggregated particles 144 can be easily and stably produced.
  • the electric field at the location where the electric field is most concentrated becomes stronger. For this reason, it is thought that the deterioration of the insulation property by the slight fluctuation
  • the semiconductor device 100 includes the insulating resin layer 140 having the above structure even when the mounting floor area is a large package having a mounting floor area of 10 ⁇ 10 mm to 100 ⁇ 100 mm. Therefore, it can be expected to obtain a sufficient withstand voltage.
  • the semiconductor device 100 for example, three or more semiconductor chips 110 are provided on the first surface 131 side of one heat sink 130, and the mold resin 180 bundles these three or more semiconductor chips together. Even if the semiconductor device 100 has a large sealing package, that is, even if the semiconductor device 100 is a large package, by providing the insulating resin layer 140 having the above structure, sufficient withstand voltage can be obtained. Can be expected.
  • the semiconductor device 100 further includes a metal layer 150 having one surface (upper surface 151) bonded to the surface (lower surface 142) opposite to the heat sink 130 side of the insulating resin layer 140, the metal layer 150 is provided. Therefore, the heat dissipation of the semiconductor device 100 is improved.
  • the upper surface 151 of the metal layer 150 is smaller than the lower surface 142 of the insulating resin layer 140, the lower surface 142 of the insulating resin layer 140 is exposed to the outside, and a crack may occur in the insulating resin layer 140 due to protrusions such as foreign matters. Occurs.
  • the upper surface 151 of the metal layer 150 is larger than the lower surface 142 of the insulating resin layer 140, the end portion of the metal layer 150 floats in the air, and the metal layer 150 is handled during the manufacturing process. May come off.
  • the entire lower surface 152 of the metal layer 150 is exposed from the mold resin 180, heat can be radiated on the entire lower surface 152 of the metal layer 150, and high heat dissipation of the semiconductor device 100 can be obtained.
  • FIG. 3 is a schematic cross-sectional view of the semiconductor device 100 according to the second embodiment.
  • the semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the first embodiment in the points described below, and otherwise the semiconductor device 100 according to the first embodiment described above. It is configured in the same way.
  • the semiconductor device 100 according to the present embodiment includes a second heat sink 230 and a second insulating resin layer 240 in addition to the configuration of the semiconductor device 100 according to the first embodiment.
  • the second insulating resin layer 240 is the same as the insulating resin layer 140.
  • the second heat sink 230 is made of metal.
  • the second heat sink 230 is disposed to face the heat sink 130 with the semiconductor chip 110 interposed therebetween.
  • the semiconductor chip 110 is provided on one surface (lower surface 232) side of the second heat sink 230, and the semiconductor chip 110 is sandwiched between the heat sink 130 and the second heat sink 230.
  • the second insulating resin layer 240 is bonded to the surface (upper surface 231) of the second heat sink 230 opposite to the semiconductor chip 110 side.
  • the mold resin 180 seals the second heat sink 230 and is in contact with the second heat sink 230 side surface (lower surface 242) of the second insulating resin layer 240 around the second heat sink 230.
  • the upper surface 181 of the mold resin 180 and the upper surface 231 of the second heat sink 230 are located on the same plane.
  • the second insulating resin layer 240 further includes a second surface (lower surface 252) bonded to a surface (upper surface 241) opposite to the second heat sink 230 side.
  • a metal layer 250 is further provided. The entire surface of the surface (upper surface 251) opposite to the one surface (lower surface 252) of the second metal layer 250 is exposed from the mold resin 180. Moreover, it is preferable that the outline of the lower surface 252 of the second metal layer 250 and the outline of the upper surface 241 of the second insulating resin layer 240 overlap in plan view.
  • the semiconductor device 100 further includes, for example, a metal block 220 disposed between the semiconductor chip 110 and the second heat sink 230.
  • the lower surface 222 of the metal block 220 is bonded to a partial region of the upper surface 111 of the semiconductor chip 110 via a conductive layer 211 such as silver paste.
  • a conductive pattern (not shown) is formed in the partial region of the semiconductor chip 110.
  • the lower surface 232 of the second heat sink 230 is joined to the upper surface 221 of the metal block 220 via a conductive layer 212 such as silver paste.
  • the semiconductor device 100 further includes a second heat sink 230 disposed opposite the heat sink 130 with the semiconductor chip 110 interposed therebetween, and a second insulating resin layer 240.
  • the semiconductor chip 110 is provided on one surface (lower surface 232) side of the second heat sink 230, and the semiconductor chip 110 is sandwiched between the heat sink 130 and the second heat sink 230.
  • the second insulating resin layer 240 is bonded to the surface (upper surface 231) of the second heat sink 230 opposite to the semiconductor chip 110 side.
  • the mold resin 180 seals the second heat sink 230.
  • heat sinks heat sink 130 and second heat sink 230
  • heat sink 130 and second heat sink 230 are provided on both surfaces of the semiconductor chip 110, heat can be radiated from both surfaces of the semiconductor chip 110, and the semiconductor device 100 has excellent heat dissipation. be able to.
  • the semiconductor device 100 further includes a second metal layer 250 in which one surface (lower surface 252) is bonded to a surface (upper surface 241) opposite to the second heat sink 230 side in the second insulating resin layer 240.
  • the second metal layer 250 can radiate heat suitably, so that the heat dissipation of the semiconductor device 100 is improved.
  • the lower surface 252 of the second metal layer 250 is smaller than the upper surface 241 of the second insulating resin layer 240, the upper surface 241 of the second insulating resin layer 240 is exposed to the outside, and projections such as foreign matter cause the second insulating resin. There is a concern that cracks may occur in the layer 240.
  • the lower surface 252 of the second metal layer 150 is larger than the upper surface 241 of the second insulating resin layer 240, the end of the second metal layer 150 is in a suspended structure, and is handled during the manufacturing process. In such a case, the second metal layer 250 may be peeled off.
  • the second insulating resin layer has a structure in which the outline of the lower surface 252 of the second metal layer 250 and the outline of the upper surface 241 of the second insulating resin layer 240 overlap in plan view. Generation of cracks in 240 and peeling of the second metal layer 250 can be suppressed.
  • FIG. 4 is a schematic cross-sectional view of a semiconductor device 100 according to the third embodiment.
  • the semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the first embodiment in the points described below, and otherwise the semiconductor device 100 according to the first embodiment described above. It is configured in the same way.
  • the semiconductor device 100 includes a heat dissipating grease layer 310 formed on the lower surface 152 of the metal layer 150 and a cooling fin 320 fixed to the lower surface 152 of the metal layer 150 via the heat dissipating grease layer 310.
  • a heat dissipating grease layer 310 formed on the lower surface 152 of the metal layer 150 and a cooling fin 320 fixed to the lower surface 152 of the metal layer 150 via the heat dissipating grease layer 310.
  • the cooling fins 320 are made of metal, for example.
  • the cooling fin 320 includes, for example, a flat plate-like main body portion and a large number of protrusions that protrude downward from the lower surface side of the main body portion.
  • the semiconductor device 100 includes a heat dissipating grease layer 310 formed on a surface (lower surface 152) opposite to one surface (upper surface 151) of the metal layer 150, and a metal layer via the heat dissipating grease layer 310. 150, and a cooling fin 320 fixed to the opposite surface (lower surface 152) of 150. Therefore, heat can be radiated with high heat radiating efficiency by the cooling fins 320, so that the heat radiating property of the semiconductor device 100 is improved.
  • FIG. 5 is a schematic cross-sectional view of a semiconductor device 100 according to the fourth embodiment.
  • the semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the second embodiment in the points described below, and otherwise the semiconductor device 100 according to the second embodiment described above. It is configured in the same way.
  • the semiconductor device 100 includes a heat dissipating grease layer 310 formed on the lower surface 152 of the metal layer 150, a cooling fin 320 fixed to the lower surface 152 of the metal layer 150 via the heat dissipating grease layer 310, A second heat dissipating grease layer 410 formed on the upper surface 251 of the second metal layer 250; and a second cooling fin 420 fixed to the upper surface 251 of the second metal layer 250 via the second heat dissipating grease layer 410. ing.
  • the second cooling fin 420 is the same as the cooling fin 320 described in the third embodiment, and is arranged upside down with respect to the cooling fin 320.
  • the metal layer 150, the second metal layer 250, the cooling fins 320, and the second cooling fins 420 are made of the same kind of metal, for example. More specifically, for example, the metal layer 150, the second metal layer 250, the cooling fin 320, and the second cooling fin 420 are each made of aluminum.
  • the semiconductor device 100 includes a heat dissipating grease layer 310 formed on a surface (lower surface 152) opposite to one surface (upper surface 151) of the metal layer 150, and a metal layer via the heat dissipating grease layer 310. And a cooling fin 320 fixed to the opposite surface (lower surface 152) of 150. Therefore, heat can be radiated with high heat radiating efficiency by the cooling fins 320, so that the heat radiating property of the semiconductor device 100 is improved.
  • a second heat dissipating grease layer 410 formed on a surface (upper surface 251) opposite to one surface (lower surface 252) of the second metal layer 250, and the second metal through the second heat dissipating grease layer 410.
  • a second cooling fin 420 fixed to the opposite surface (upper surface 251) of the layer 250. Therefore, since heat can be radiated with high heat radiation efficiency by the second cooling fins 420, the heat radiation performance of the semiconductor device 100 is improved.
  • the metal layer 150, the second metal layer 250, the cooling fin 320, and the second cooling fin 420 are made of the same kind of metal, the potential difference between the metal layer 150 and the cooling fin 320, and the second metal layer 250. And corrosion degradation due to the potential difference between the second cooling fin 420 and the second cooling fin 420 can be suppressed.
  • the metal layer 150, the second metal layer 250, the cooling fins 320, and the second cooling fins 420 may be made of aluminum so that these structures are inexpensive and have excellent workability and heat dissipation. it can.
  • FIG. 6 is a schematic cross-sectional view of a semiconductor device 100 according to the fifth embodiment.
  • the semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the second embodiment in the points described below, and otherwise the semiconductor device 100 according to the second embodiment described above. It is configured in the same way.
  • the peripheral edge of the metal layer 150 and the peripheral edge of the second metal layer 250 are each curved toward the mold resin 180 side. Note that a fillet or the like protruding from the resin may be formed around the metal layer 150. Similarly, a fillet or the like may be formed around the second metal layer 250.
  • the semiconductor device 100 according to the present embodiment can be obtained, for example, by pressing the semiconductor device 100 according to the second embodiment (FIG. 3) evenly from above and below.
  • the peripheral portion of the metal layer 150 and the peripheral portion of the second metal layer 250 are curved toward the mold resin 180, respectively.
  • the peeling of the layer 150 and the second metal layer 250 can be suppressed.
  • the insulating resin layer 140 and the second insulating resin layer 240 are less likely to come into direct contact with outside air or moisture, and the long-term reliability of the semiconductor device 100 is stabilized.
  • the peripheral portion of the metal layer 150 and the peripheral portion of the second metal layer 250 of the semiconductor device 100 according to the second embodiment are curved toward the mold resin 180 side, respectively.
  • the peripheral portion of the metal layer 150 of the semiconductor device 100 according to the first embodiment may be curved toward the mold resin 180 side.
  • FIG. 7 is a schematic cross-sectional view of a semiconductor device 100 according to the sixth embodiment.
  • the semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the first embodiment in the points described below, and otherwise the semiconductor device 100 according to the first embodiment described above. It is configured in the same way.
  • the insulating resin layer 140 is sealed in the mold resin 180.
  • the metal layer 150 is also sealed in the mold resin 180 except for the lower surface 152 thereof.
  • the lower surface 152 of the metal layer 150 and the lower surface 182 of the mold resin 180 are located on the same plane.
  • FIG. 7 shows an example in which at least two or more semiconductor chips 110 are mounted on the first surface 131 of the heat sink 130.
  • the electrode patterns on the upper surface 111 of the semiconductor chip 110 are electrically connected to each other through a wire 610.
  • a total of six semiconductor chips 110 are mounted on the first surface 131. That is, for example, two semiconductor chips 110 are arranged in three rows in the depth direction of FIG.
  • a power module including the substrate and the semiconductor device 100 can be obtained by mounting the semiconductor device 100 according to each of the above embodiments on a substrate (not shown).
  • the metal plate is a heat sink
  • the metal plate may be a depressed lead or a heat dissipation plate.
  • each thickness is represented by an average film thickness.
  • Example 1> Preparation of secondary agglomerated particles composed of primary particles of scaly boron nitride
  • this slurry was supplied to a spray granulator and sprayed under the conditions of an atomizer rotation speed of 15000 rpm, a temperature of 200 ° C., and a slurry supply amount of 5 ml / min, thereby producing composite particles.
  • the obtained composite particles were fired under a nitrogen atmosphere at 2000 ° C. for 10 hours to obtain aggregated boron nitride (filler 1) having an average particle diameter d of 70 ⁇ m.
  • the average particle size of the agglomerated boron nitride was determined by measuring the particle size distribution of the particles on a volume basis with a laser diffraction particle size distribution analyzer (LA-500, manufactured by HORIBA), and the median diameter (D 50 ). .
  • thermosetting resin and a curing agent were added to methyl ethyl ketone as a solvent, and this was stirred to obtain a solution of a thermosetting resin composition.
  • an inorganic filler was put into this solution and premixed, and then kneaded with a three roll to obtain a resin composition in which the inorganic filler was uniformly dispersed.
  • aging was performed on the obtained resin composition under conditions of 60 ° C. and 15 hours. Subsequently, after apply
  • a semiconductor device shown in FIG. 1 was fabricated using the obtained insulating resin layer.
  • the mounting floor area of the semiconductor device was 30 ⁇ 40 mm.
  • Example 2 A semiconductor device was produced in the same manner as in Example 1 except that a B-stage insulating resin layer was produced so that the film thickness D was 80 ⁇ m.
  • Epoxy resin 1 biphenyl type epoxy resin (YL6121, manufactured by Mitsubishi Chemical Corporation)
  • Epoxy resin 2 bisphenol A type epoxy resin (JER828, manufactured by Mitsubishi Chemical Corporation)
  • Curing agent Trisphenol methane type novolak resin (MEH-7500, manufactured by Meiwa Kasei Co., Ltd.)
  • Curing catalyst 2-phenyl-4,5-dihydroxymethylimidazole (2PHZ-PW, manufactured by Shikoku Chemicals)
  • Example 1 and Comparative Examples 1 and 2 For each of the insulating resin layers obtained in Example 1 and Comparative Examples 1 and 2, whether or not voids were present in the insulating resin layer was observed with a scanning electron microscope. Specifically, it measured by the following procedures. First, the insulating resin layer was cut with a microtome to produce a cross section. Next, a cross-sectional photograph of the insulating resin layer magnified several thousand times was taken with a scanning electron microscope, and the presence or absence of voids was evaluated. ⁇ : No void ⁇ : Void present
  • the film thickness of each insulating resin layer obtained in Example 1 and Comparative Examples 1 and 2 was observed with a scanning electron microscope. Specifically, it measured by the following procedures. First, the insulating resin layer was cut with a microtome to produce a cross section. Next, a cross-sectional photograph of the insulating resin layer magnified several thousand times was taken with a scanning electron microscope to evaluate whether the film thickness of the insulating resin layer was uniform. ⁇ : The film thickness is uniformly made uniform. X: The film thickness varies.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

L'invention concerne un dispositif semi-conducteur (100) comprenant : une plaque métallique (par exemple, un dissipateur de chaleur (130)) ; une puce semi-conductrice (110) disposée du côté première surface (131) de la plaque métallique ; une couche de résine isolante (140) reliée à une deuxième surface (132) du côté opposé à la première surface (131) de la plaque métallique ; et une résine moulée (180) scellant la puce semi-conductrice (110) et la plaque métallique. La couche de résine isolante (140) contient des particules agrégées secondaires (144) résultant de l'agrégation isotrope de particules primaires (143) de nitrure de bore écailleux. Lorsque l'épaisseur de la couche de résine isolante (140) est D et la taille moyenne des particules agrégées secondaires (144) est d, d/D est de 0,05 à 0,8 inclus.
PCT/JP2015/069017 2014-07-02 2015-07-01 Dispositif semi-conducteur WO2016002846A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2016531422A JP6635034B2 (ja) 2014-07-02 2015-07-01 半導体装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014-137234 2014-07-02
JP2014137234 2014-07-02

Publications (1)

Publication Number Publication Date
WO2016002846A1 true WO2016002846A1 (fr) 2016-01-07

Family

ID=55019376

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2015/069017 WO2016002846A1 (fr) 2014-07-02 2015-07-01 Dispositif semi-conducteur

Country Status (2)

Country Link
JP (1) JP6635034B2 (fr)
WO (1) WO2016002846A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020072094A (ja) * 2018-10-29 2020-05-07 京セラ株式会社 パワーユニット、パワーユニットの製造方法及びパワーユニットを有する電気装置
JP2023070012A (ja) * 2021-11-03 2023-05-18 ウェスタン デジタル テクノロジーズ インコーポレーテッド スタック型ｓｓｄ半導体デバイス

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002069392A (ja) * 2000-08-31 2002-03-08 Polymatech Co Ltd 熱伝導性接着フィルムおよびその製造方法ならびに電子部品
JP2011135069A (ja) * 2009-11-26 2011-07-07 Nitto Denko Corp Ｌｅｄ実装用基板
WO2012133587A1 (fr) * 2011-03-28 2012-10-04 日立化成工業株式会社 Composition de résine, feuille de résine, feuille de résine durcie, laminé de feuille de résine, laminé de feuille de résine durcie et leur procédé de fabrication, dispositif semi-conducteur et dispositif à del
WO2013030998A1 (fr) * 2011-08-31 2013-03-07 日立化成工業株式会社 Composition de résine, feuille de résine, feuille de résine dotée d'une feuille métallique, feuille de résine durcie, structure et dispositif à semi-conducteur pour une source d'énergie ou de lumière
JP2014051553A (ja) * 2012-09-05 2014-03-20 Mitsubishi Chemicals Corp 三次元積層型半導体装置用の層間充填材組成物、三次元積層型半導体装置、および三次元積層型半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002069392A (ja) * 2000-08-31 2002-03-08 Polymatech Co Ltd 熱伝導性接着フィルムおよびその製造方法ならびに電子部品
JP2011135069A (ja) * 2009-11-26 2011-07-07 Nitto Denko Corp Ｌｅｄ実装用基板
WO2012133587A1 (fr) * 2011-03-28 2012-10-04 日立化成工業株式会社 Composition de résine, feuille de résine, feuille de résine durcie, laminé de feuille de résine, laminé de feuille de résine durcie et leur procédé de fabrication, dispositif semi-conducteur et dispositif à del
WO2013030998A1 (fr) * 2011-08-31 2013-03-07 日立化成工業株式会社 Composition de résine, feuille de résine, feuille de résine dotée d'une feuille métallique, feuille de résine durcie, structure et dispositif à semi-conducteur pour une source d'énergie ou de lumière
JP2014051553A (ja) * 2012-09-05 2014-03-20 Mitsubishi Chemicals Corp 三次元積層型半導体装置用の層間充填材組成物、三次元積層型半導体装置、および三次元積層型半導体装置の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020072094A (ja) * 2018-10-29 2020-05-07 京セラ株式会社 パワーユニット、パワーユニットの製造方法及びパワーユニットを有する電気装置
JP2023070012A (ja) * 2021-11-03 2023-05-18 ウェスタン デジタル テクノロジーズ インコーポレーテッド スタック型ｓｓｄ半導体デバイス
JP7375108B2 (ja) 2021-11-03 2023-11-07 ウェスタン デジタル テクノロジーズ インコーポレーテッド スタック型ｓｓｄ半導体デバイス

Also Published As

Publication number Publication date
JPWO2016002846A1 (ja) 2017-04-27
JP6635034B2 (ja) 2020-01-22

Similar Documents

Publication Publication Date Title
WO2017014238A1 (fr) Composition de résine thermoconductrice, feuille thermoconductrice, et dispositif semi-conducteur
JP6627303B2 (ja) 熱伝導性樹脂組成物、回路基板用積層体、回路基板および半導体装置
JP6634717B2 (ja) 熱伝導性シート、熱伝導性シートの硬化物および半導体装置
JP6657616B2 (ja) 熱伝導性シート、熱伝導性シートの硬化物および半導体装置
US11459443B2 (en) Resin material, method for producing resin material, and laminate
KR102737282B1 (ko) 적층체 및 전자 장치
US11884039B2 (en) Insulating sheet and laminate
US11383500B2 (en) Insulating sheet and laminate
CN106133900B (zh) 导热片和半导体装置
JP6458433B2 (ja) 造粒粉、放熱用樹脂組成物、放熱シート、半導体装置、および放熱部材
JP5854062B2 (ja) 熱伝導性シートおよび半導体装置
JP6579105B2 (ja) 熱伝導性シートおよび半導体装置
JP2016094599A (ja) 熱伝導性シート用樹脂組成物、基材付き樹脂層、熱伝導性シートおよび半導体装置
JP6508384B2 (ja) 熱伝導性シートおよび半導体装置
WO2016002846A1 (fr) Dispositif semi-conducteur
JP6579106B2 (ja) 熱伝導性シートおよび半導体装置
JP2016117836A (ja) 熱伝導性シート、熱伝導性シートの硬化物および半導体装置
JP6572643B2 (ja) 熱伝導性シート、熱伝導性シートの硬化物および半導体装置
WO2022176448A1 (fr) Composition de résine thermodurcissable, substrat pour modules de puissance et module de puissance
WO2023090013A1 (fr) Carte de circuit imprimé dotée de dissipateur thermique, son procédé de fabrication, dispositif à semi-conducteur et son procédé de fabrication
JP6795285B2 (ja) 熱伝導性シート、熱伝導性シートの硬化物および半導体装置
WO2023002789A1 (fr) Composition de résine thermodurcissable, substrat pour modules de puissance, carte de circuit imprimé et feuille de dissipation de chaleur

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15815745

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2016531422

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15815745

Country of ref document: EP

Kind code of ref document: A1

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载