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WO2016001182A2 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

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Publication number
WO2016001182A2
WO2016001182A2 PCT/EP2015/064771 EP2015064771W WO2016001182A2 WO 2016001182 A2 WO2016001182 A2 WO 2016001182A2 EP 2015064771 W EP2015064771 W EP 2015064771W WO 2016001182 A2 WO2016001182 A2 WO 2016001182A2
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WO
WIPO (PCT)
Prior art keywords
region
anode
pilot
doping concentration
maximum
Prior art date
Application number
PCT/EP2015/064771
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English (en)
Other versions
WO2016001182A3 (fr
Inventor
Liutauras Storasta
Arnost Kopta
Manuel LE-GALLO
Munaf Rahimo
Original Assignee
Abb Technology Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Publication of WO2016001182A2 publication Critical patent/WO2016001182A2/fr
Publication of WO2016001182A3 publication Critical patent/WO2016001182A3/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
    • H10D62/142—Anode regions of thyristors or collector regions of gated bipolar-mode devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions

Definitions

  • the invention relates to the field of power electronics and more particularly to a semiconductor device according to the preamble of claim 1 .
  • Prior art IGBTs comprise a semiconductor chip, part of which chip forms an (n- ) doped base layer with a base layer doping concentration and a base layer thickness.
  • the IGBT comprises an anode side and a cathode side, whereas the anode side is arranged opposite of the cathode side of the chip.
  • n doped source region, a p doped well layer and a gate electrode are arranged at the cathode side.
  • n doped buffer layer of higher doping concentration than the drift layer and on that, a p doped anode layer are arranged on the anode side.
  • the turn-off characteristics has a prominent feature of current snap-off, might causing high overshoot voltages and/or triggering high frequency voltage and current oscillations. Abrupt current snap-off could also complicate series connection of the devices which would require additional snubbers for dynamic voltage sharing to provide the necessary charge during the turn-off tail. This is especially critical for high voltage IGBTs with high resistivity silicon design and punch-though voltage values well below the nominal DC-link voltage. The occurrence of the snap-off is also preventing any further thinning of the IGBT base layer for reduction of IGBT losses.
  • the turn-off softness can be adjusted to some extent by the anode strength (doping), but this method is very limited and has a strong influence on the conduction/switching losses trade-off and turn-off SOA capability.
  • RC-IGBT reverse conducting insulated gate bipolar transistor
  • BiGT Insulated Gate Transistor
  • the base layer thickness 102 is the minimum vertical distance between the collector and cathode side 103 and 104 of that part of the chip 100 with the base layer doping concentration.
  • n doped source region 3 a p doped well layer 4 and a gate electrode having an electrically conductive gate layer 5 and an insulating layer 6, which insulates the gate layer 5 from any doped layer and a cathode electrode 8, are arranged at the cathode side 104.
  • an n doped cathode layer 12 of higher doping concentration than the base layer doping concentration of the base layer and a p doped anode layer 2 are alternately arranged on the anode side 103.
  • the cathode layer 12 comprises at least one or a plurality of n doped first regions 14, wherein each first region 14 has a first region width 15.
  • the anode layer 2 comprises at least one or a plurality of p doped second regions 24 and at least one or a plurality of p doped pilot regions 26, wherein each second region 24 has a second region width 25 and each pilot region 26 has a pilot region width 27 (FIG 3).
  • Any region has a region width and a region area, which is surrounded by a region border.
  • a shortest distance is the minimum length between a point within said region area and a point on said region border.
  • each region width is defined as two times the maximum value of any shortest distance within said region.
  • the reverse-conducting semiconductor device comprises an active region 1 10, which is an area in the chip 100, which includes and is arranged below any of the source region 3, well layer 4 or gate layer 5.
  • Each pilot region 26 is a p doped area, in which a maximum value of the shortest distance to any border point (on which first regions are arranged) is bigger than the base layer thickness 102.
  • the at least one second region 24 is that part of the anode layer 2, which is not the at least one pilot region 26.
  • the at least one pilot region 26 is arranged in the central part of the active region 1 10 in such a way that there is a minimum distance between the pilot region border to the active region border 1 12 of at least one time the base layer thickness 102 (FIG 3).
  • the pilot region 26 represents a pilot IGBT region, which is surrounded by shorted regions with alternating first and second doped regions 14, 24 (mixed region).
  • FIG 2 shows a cut through the line A' - A' of FIG 1 showing such a mixed region.
  • pilot region 26 By the introduction of the pilot region 26 with much increased dimensions compared to the first and second regions 14, 24, a region is created which is dedicated as sole IGBT region and not operating in the diode mode.
  • the p-type pilot region 26 ensures snap-back free operation of the BIGT.
  • the pilot region 26 can also be used to give more freedom to determine the IGBT to diode area ratio and decouple this design aspect from the standard approach involving the small second regions 24 only.
  • the first and second regions 14, 24 form the main shorted region in which the silicon area included is utilized in both IGBT and diode mode. These regions also influence the main IGBT electrical properties.
  • the n doped anode shorts conduct electron current during the turn-off and give rise to the FCE effect which greatly improves turn-off softness of the BIGT device.
  • Anode shorts could also be utilized in an IGBT to improve turn-off softness, however, the anode shorts will remove any reverse blocking capability of the IGBT. While this is the design goal for the BIGT, in standard IGBT/diode implementation the IGBT with shorts will act as a parallel diode connected to the freewheeling diode, thus adding to the turn-on losses. Disclosure of Invention
  • IGBT insulated gate bipolar transistor
  • the inventive insulated gate bipolar transistor (IGBT) having an anode side and a cathode side opposite to the anode side comprises a chip (FIG 4). Part of the chip forms a base layer of a first conductivity type with a base layer doping
  • the base layer thickness is the minimum vertical distance between the anode and cathode side of such part of the chip with the base layer doping concentration.
  • an anode layer of a second conductivity type which is different from the first conductivity type, is arranged.
  • the anode layer comprises a mixed region having at least one first anode region and at least one second anode region.
  • Each of the first anode regions has a maximum first doping concentration and a first anode region width, wherein each first anode region width is smaller than the base layer thickness.
  • Each of the second anode regions has a second anode region width and a maximum second doping concentration, wherein each maximum second doping concentration is higher than each maximum first doping concentration.
  • the first and second anode region thickness is at most 2 ⁇ .
  • each first anode region has a thickness, which is lower than a thickness of each second anode region.
  • the anode doping and doping profile are designed in such a way that the first anode regions have very low injection efficiency, making those regions transparent anode regions.
  • Any region has a region width and a region area, which is surrounded by a region border.
  • a shortest distance shall be a minimum length between a point within said region area and a point on said region border.
  • Each region width is defined as two times the maximum value of all shortest distances within said region, i.e. the width is two times the greatest possible shortest distance that a point can have from the border of the region.
  • the region width corresponds to the maximum diameter of a circle that can be laid into the region over the whole region area width in a plane parallel to the anode side.
  • the borders of the first and second anode regions are defined by the area, in which the region has the maximum first or second doping concentration.
  • the base layer thickness is the minimum vertical distance between the collector and cathode side of that part of the chip with the base layer doping concentration.
  • the base layer thickness is the thickness as shown in FIG 4 by a dashed line.
  • the inventive IGBT comprises an electrically active region, which active region is an area in the device, which includes and is arranged below (i.e. in projection of) any of the source region, well layer or gate layer.
  • active region is an area in the device, which includes and is arranged below (i.e. in projection of) any of the source region, well layer or gate layer.
  • the carrier plasma might spread beyond the active region as defined above, but for the purpose of this patent application, the active region shall be restricted to the area below the source region, well layer or gate layer, i.e.
  • the inventive IGBT comprises at least one pilot anode region, each of which pilot anode region having a pilot anode region width and a maximum pilot doping concentration, wherein each maximum pilot doping concentration is higher than each maximum first doping concentration, in particular, equivalent to the maximum second doping concentration.
  • Each pilot anode region width is at least once the base layer thickness, exemplarily at least twice the base layer thickness and the at least one second region width is at least five times lower than the pilot anode region width.
  • the sum of the areas of the at least one pilot anode region is between 10 % and 30 % of the area of the active region.
  • the at least one second anode region is a part of the anode layer having a higher maximum doping concentration than the maximum first doping concentration of the at least one first anode region and which is not a pilot anode region.
  • the electron current flows preferentially towards these regions and causes the lateral current flow above the higher doped second anode regions to forward-bias them and inject additional carriers to avoid snap-off.
  • the highly doped large pilot anode region the softness of the device increases.
  • the p- doped region area would have to be increased to keep the before mentioned effect of the lowly doped p- regions. This, however, would degrade the short circuit ruggedness of the device.
  • the inventive structure having a or a plurality of pilot anode regions and a mixed region of smaller alternating highly and lowly doped anode regions allows to combine the positive effects of the highly doped and lowly doped regions without having negative impact on the electrical properties.
  • the inventive IGBT can be manufactured on its anode side by applying a first p- type dopant having a high dose for creating the highly doped part of the anode layer (second anode region and, if present, also the pilot anode region).
  • the first dopant is removed in those areas, in which a lower doped first anode region shall be arranged, e.g. by etching.
  • a second p-type dopant is applied, e.g. by implantation, having a lower second dose for the creation of the lowly doped first anode region.
  • the implanted dopants may be diffused into the chip or activated by applying a heating step simultaneously or each implanted dopant is diffused/activated separately, i.e.
  • the first dopant is diffused before the second dopant is applied. Due to the lower dose in the first anode regions or lower diffusion/activation temperature, the dopant diffuses less deep into the chip, thereby resulting in a shallower depth of the first anode region.
  • the width of the first anode region is made smaller than the width of the higher doped second anode regions to avoid extreme doping of the second anode region and problems with short circuit failures, which often occur at devices having a continuous weak, i.e. lowly doped anode layers covering the whole anode side.
  • a larger width of the second anode regions is preferred for improved turn-off softness.
  • the figures 7 to 10 shows device simulation comparison of inventive IGBTs with a second maximum doping concentration of 4 * 10 17 cm 3 .
  • the first maximum doping concentration is 2 * 10 16 cm 3 or 1 * 10 17 cm 3 , respectively.
  • the prior art IGBT has the same maximum doping concentration of the anode layer of 4 * 10 17 cm 3 in the whole device area and the RC-IGBT has maximum doping concentration of 4 * 10 17 cm 3 in the p regions and 1 * 10 18 cm 3 in the n-regions (shorts).
  • the width of the first regions 14 (n anode shorts, i.e. first regions, in case of the prior art RC-IGBT) in the above simulations was equal to 160 ⁇ , and the width of the second regions 24 was set to 800 ⁇ .
  • the prior art IGBT has the lowest on-state losses.
  • the introduction of the lower p doped first anode regions in the inventive IGBT (designated as “2 * 10 16 cm “ 3 p" and “1 * 10 17 cm 3 p" for the maximum first doping concentration in the figure) causes a small on-state loss increase, depending on the maximum doping concentration of the lowly doped p first anode regions which can be compensated by adjusting, i.e. increasing, the maximum doping concentration of the higher doped p+ second anode regions.
  • the prior art RC-IGBT (designated as "1 * 10 18 cm 3 n" in the figure) has the highest losses of the curves shown in the figure due to the efficient anode shorting.
  • the inventive device having the lower maximum second doping concentration shows softest turn-off characteristics and is approaching the performance of prior art RC-IGBT.
  • FIG 13 shows the blocking curves of an IGBT with continuous and structured anode designs. The only visible effect is an increase of the leakage in the structure of the lower doped second anode region (second maximum doping concentration of 2 * 10 16 cm 3 ).
  • the BiGT and RC- IGBT does not have reverse blocking capability (conducts in the diode mode) and are, therefore, not shown in this figure.
  • the required degree of softness effect can be adjusted by appropriately dimensioning the second p+ and first p regions, as shown in FIG 14.
  • the doping concentrations are as mentioned above for the prior art IGBT and the inventive devices with a maximum first doping concentration of 2 * 10 16 cm 3 .
  • the device indicated as "large 1 . anode, narrow 2. anode” in the graph has a first anode region width of 800 ⁇ and a second anode region width of 160 ⁇ .
  • the device indicated as "with pilot anode region” in the graph comprises a first anode region width of 40 ⁇ , a second anode region width of 200 ⁇ and a pilot region width of 460 ⁇ .
  • anode in the graph comprises a first anode region width of 160 ⁇ and a second anode region width of 800 ⁇ .
  • the layout with wide p+ pilot anode regions introduces a controlled smoothly decaying current tail and only marginal increase of the turn-off losses. Further preferred embodiments of the inventive subject matter are disclosed in the dependent claims.
  • FIG 1 shows a cross sectional view on a prior art reverse-conducting BiGT
  • FIG 2 shows a plan view of the structures of a mixed region comprising anode and cathode regions of a reverse-conducting prior art BiGT;
  • FIG 3 shows a plan view of the structures of cathode and anode regions of prior art reverse-conducting BiGT;
  • FIG 4 to 6 cross sectional views of different IGBTs according to the invention.
  • FIG 7 shows a plan view of the structures of a mixed region comprising first and second anode regions of an inventive IGBT
  • FIG 8 - 10 show plan views of the structures of the anode layer with various pilot anode region designs of different IGBTs according to the invention.
  • FIG 1 1 shows on-state characteristics of a prior art IGBT, a prior art RC-IGBT, and of two IGBTs according to the invention having different maximum first doping concentrations;
  • FIG 12 shows turn-off characteristics of a prior art IGBT, a prior art RC-IGBT, and of two IGBTs according to the invention having different maximum first doping concentrations;
  • FIG 13 shows reverse blocking characteristics of a prior art IGBT and of two
  • IGBTs according to the invention having different maximum first doping concentrations
  • FIG 14 shows turn-off characteristics of a prior art IGBT and different IGBTs according to the invention having different widths for the first, second and pilot anode regions;
  • FIG 15 showing a detail of FIG 1 1 magnified for small voltages/currents.
  • FIG 4 a first embodiment of an inventive semiconductor device 1 , also named insulated gate bipolar transistor (IGBT) is shown.
  • the inventive IGBT 1 comprises an n type base layer 101 with a first main side, which forms the cathode side 104 of the inventive IGBT, and a second main side opposite the first main side, which forms the anode side 103 of the inventive IGBT.
  • the base layer 101 is that part of an (n-) doped semiconductor chip 100, which has a low base layer doping concentration, typically the un-amended doping in the finalized IGBT.
  • the base layer 101 has a constant low doping concentration.
  • the device 1 could also be manufactured starting from a p doped chip (also called wafer), on which the base layer 101 is created, e.g. by epitaxial growing.
  • the base layer thickness 102 is the minimum vertical distance between the collector and cathode sides 103 and 104 of that part of the chip with the base layer doping concentration (i.e. of the base layer 101 ).
  • the base layer thickness 102 is between 50 to 1000 ⁇ or between 380 to 800 ⁇ , depending on the voltage class of the device.
  • a p type well layer 4 is arranged on the cathode side 104. At least one n type source region 3 is also arranged on the cathode side 104 and it is surrounded by the well layer 4. The at least one source region 3 has a higher doping than the base layer 101 .
  • An electrically insulating layer 6 is arranged on the cathode side 104 on top of the base layer 101 , the well and source region 4, 3. It at least partially covers the at least one source region 3, the well layer 4 and the base layer 101 .
  • An electrically conductive gate layer 5 is arranged on the cathode side 104 electrically insulated from the at least one well layer 4, the source region 3 and the base layer 101 by an insulating layer 6. Exemplarily, the gate layer 5 is completely insulated by the insulating layer 6.
  • the insulating layer 6 comprises a first electrically insulating layer 61 , preferably made of a silicon dioxide, and a second electrically insulating layer 62, exemplarily made of a phosphosilicate glass.
  • the second electrically insulating layer 62 covers the first electrically insulating layer 61 .
  • the first electrically insulating layer 61 is arranged on top of the cathode side 104. In between the first and second electrically insulating layers 61 , 62, which form the insulating layer 6, the gate layer 5 is embedded, typically it is completely embedded.
  • the gate layer 5 is separated from the base layer 101 , the source region 3 and the well layer 4 by the first electrically insulated layer 61 .
  • the gate layer 5 is typically made of a heavily doped polysilicon or a metal like aluminum.
  • a planar gate electrode comprises the planar gate layer 5' and the insulating layer 6.
  • the at least one source region 3, the gate layer 5 and the insulating layer 6 are formed in such a way that an opening is created above the well layer 4. The opening is surrounded by the at least one source region 3, the gate layer 5 and the insulating layer 6.
  • a cathode electrode 8 is arranged on the cathode side 104 within the opening so that it is in direct electrical contact to the well layer 4 and the source region 3.
  • This cathode electrode 8 typically also covers the insulating layer 6, but is separated and thus electrically insulated from the gate layer 5 by the second electrically insulating layer 62.
  • a p type anode layer 2 is arranged on the anode side 103.
  • the inventive IGBT 1 may further comprise an n type buffer layer 7, which is arranged between the base layer 101 and the anode layer 2, which buffer layer 7 has a higher doping concentration than the base layer 101 .
  • the buffer layer 7 has exemplarily a maximum doping concentration of at most 1 * 10 16 cm 3 .
  • the semiconductor device 1 comprises an active region 1 10 (central region) and a termination region 1 1 1 , which surrounds the active region 1 10 up to the edge of the substrate or chip (FIG 8).
  • the active region 1 10 is the area in which the device conducts current during on-state, in the case of an IGBT this is the MOS cell.
  • the active region 1 10 is that area within the device 100, which includes the source region 3 and well layer 4 and is arranged below the source region 3, well layer 4 and gate layer 5. With below the area is meant which is arranged in the chip 100 between the cathode side 104 and the anode side 103, in which area any of the source region 3, well layer 4 or gate layer 5 are arranged.
  • first and second anode regions 10, 20 are arranged on the anode side 103, but alternatively this region may also consist of a single, p doped region or an n doped region.
  • this region may also consist of a single, p doped region or an n doped region.
  • neither a source region 3, a well layer 4 nor a gate electrode is arranged on the cathode side 104.
  • An anode electrode 9 is arranged on the anode side 103 and it is in direct electrical contact to the at least one anode layers 10, 20.
  • Al, Ti, Ni, or Au are chosen as a material for the anode electrode 9 (and/or the cathode electrode 8).
  • the inventive IGBT 1 may comprise a gate layer 5, formed as trench gate layer 5" as shown in FIG 5.
  • the trench gate layer 5" is arranged in the same plane as the well layer 4 and adjacent to the source region 3, separated from each other by a first insulating layer 61 , which also separates the gate layer 5" from the base layer 101 .
  • a second insulating layer 62 is arranged on top of the trench gate layer 5", thus insulating the gate layer 5" from the cathode electrode 8. Insulating layer 6 and trench gate layer 5" form a trench gate electrode.
  • an n doped enhancement layer 41 is arranged between the well layer 4 and the base layer 101 for having lower on-state losses.
  • the enhancement layer 41 separates the well layer 4 from the base layer 101 and it has higher doping concentration than the base layer 101 .
  • the enhancement layer 41 can be present in planar gate designs as well as in trench gate designs.
  • the p type anode layer 2 comprises at least one or a plurality of first anode regions 10 and second anode regions 20, which form a mixed region. Exemplarily. in the mixed region the at least one first anode region 10 is arranged such that a minimum distance between closest neighbored areas having the maximum first doping concentration is smaller than the base layer thickness 102.
  • Each first anode region 10 has a maximum first doping concentration and a first anode region width 1 1 , wherein each first anode region width 1 1 is smaller than the base layer thickness 102. That means that in a plane parallel to the anode side 103 within the first anode region 10 the maximum diameter of a circle that can be laid at any place in the region area is smaller than the base layer thickness 102, i.e. with the region area the largest circle that can be laid into the area has a diameter smaller than the base layer thickness 102.
  • Each maximum first doping concentration may be at most 1 * 10 17 cm 3 .
  • FIG 7 shows an exemplary layout of such a mixed region where the FIG 4 corresponds to a cut through the line A - A.
  • the first anode regions 10 may have a width of at most 500 ⁇ , exemplarily between 100 ... 200 ⁇ .
  • Each second anode region 20 has a second anode region width 21 and a maximum second doping concentration, wherein each maximum second doping concentration is higher than each maximum first doping concentration.
  • the maximum second doping concentration of the second anode regions may be at least 1 * 10 15 cm 3 , but always fulfilling the condition that the maximum second doping concentration is higher than the maximum first doping concentration
  • each second anode region width 23 may be larger than half the base layer thickness 102, exemplarily between 300 ... 800 ⁇ . In another exemplary embodiment, the second anode region width 23 may be smaller than twice the base layer thickness 102.
  • the maximum first doping concentration may be in an exemplary embodiment at least five times lower than the maximum second doping concentration.
  • the thickness of the first and second regions 10, 20 is measured as the maximum extension of the p type doping of the region 10, 20 in a direction perpendicular to the collector side 103.
  • the first anode region 10 and the second anode region 20 have a thickness of at most 2.0 ⁇ .
  • the thickness of both anode regions is at most 1 .0 urn.
  • each first anode region 10 has a thickness, which is lower than a thickness of each second anode region 20.
  • the thickness of the first and second anode regions is at most 2.0 ⁇
  • the thickness of the second anode region is at most 2.0 ⁇
  • the thickness of the first anode region is at most 1 .0 ⁇ .
  • the first and second region 10, 20 may form a common, straight boundary plane within the chip, i.e. at the pn junction, which is in this case towards the n doped layer, which is either the buffer layer 7 or the base layer 101 .
  • the first regions 10 On the collector side, 103, i.e. towards the collector electrode 9, the first regions 10 may be arranged recessed from the anode sided surface of the second anode regions 20.
  • any of the first, second and pilot anode regions 10, 20, 22 has a region width and a region area, which is surrounded by a region border.
  • a shortest distance is the minimum length between a point within said region area and a point on said region border.
  • the region width is measured in a plane parallel to the anode side 103.
  • Each region width in this exemplary embodiment is defined as two times the maximum value of any shortest distance within said region.
  • a region width is the maximum diameter of a circle that can be laid into the region over the whole region area width in a plane parallel to the anode side 103.
  • the figures 8 to 10 show another embodiment of an inventive IGBT comprising an anode layer 2 having at least one or a plurality of pilot anode regions 22, which has a pilot anode region width 23.
  • the IGBT 1 does not have the same structure for the lower and higher doped parts of the anode layer 2 over the whole plane of the chip 100.
  • the anode layer 2 only comprises first and second anode regions 10, 20 as shown in FIG 7.
  • the anode layer 2 only comprises a pilot anode region 22.
  • the pilot anode region 22 has a pilot anode region width 23 and a maximum pilot doping concentration, wherein each maximum pilot doping concentration is higher than each maximum first doping concentration.
  • Each pilot anode region width 23 is larger than the second anode width and at least once the base layer thickness, exemplarily at least two times, 2.5 times or even three times base layer thickness.
  • each pilot anode region 22 may have a pilot anode region width of at least 2 mm.
  • the pilot region width in a plane parallel to the anode side 103 is the maximum diameter of a circle that can be laid into the region over the whole region area.
  • the maximum pilot doping concentration of each pilot anode region may be at least 1 * 10 15 cm 3 .
  • the second anode regions 20 have the same maximum doping concentration as the pilot anode regions 22. Also the
  • the at least one second region width 21 is at least four times or even five times lower than the pilot anode region width 23. That means that all second anode regions may have the same widths or all second anode regions have a maximum value, which is at least four or five times lower than the width of the pilot anode region(s) (in case all pilot regions have the same width) or of the smallest pilot region width in case that the pilot anode regions have different widths.
  • the sum of the areas of the at least one pilot anode region 22 may be between 10 % and 30 % of the active region area. In a further exemplary embodiment the sum of the areas of the at least one pilot anode region 22 is between 15 to 25 % and exemplarily between 18 to 22 % to the active region area.
  • each first anode region width 1 1 is smaller than the base layer thickness 102.
  • the total area of the second and pilot anode regions 20, 22 to total area of the device 100 is between 70 % up to 90 %.
  • the total area of the first anode regions 10 to total area of the device 100 is between 10 % up to 30 %.
  • Exemplary designs for the first and second anode regions 10, 20 are a square design (FIG 7), rectangular design or a circular design, in which at least the first and/or second region 10, 20 have this shape and the other region may have the same shape or is enclosing the other shape.
  • termination region 1 1 1 are exemplarily first and second anode regions 10, 20 arranged, but alternatively this region may also consist of an n doped region or of a p doped region, which surrounds the active region 1 10.
  • the widths 1 1 , 21 of the first and/or second anode regions 10, 20 can be constant over the whole chip area so that the first and second anode regions 10, 20 are arranged in a regular geometrical manner over the chip 100 as e.g. shown in the FIG 7, but their widths may also vary over the chip 100.
  • the stripes can be surrounded be first anode regions 10, but the first and second anode regions 10, 20 can also extend from one side of the border of the active region 1 10 to the other.
  • the pilot anode region 22 consists of a single region (as shown in the FIG.s 8 to 10).
  • the pilot anode region may alternatively also comprise a plurality of pilot regions, which are separated from each other, exemplarily by at most twice the base layer thickness 102, exemplarily by at most one time the base layer thickness 102.
  • first anode regions 10 are arranged between two regions belonging to the pilot anode region 22 or at least the intermediate space comprises first anode regions 10, i.e. the intermediated space comprises alternating first and second anode regions 10, 20.
  • the pilot anode region or regions 22 has in another preferred embodiment a square, rectangular design, circular design, star, diamond, tri-star or polygonal shape like a hexagon or another polyangular design.
  • FIG 8 shows such a pilot anode region 22 with a square shape
  • FIG 9 shows a pilot anode region 22 with a circular shape
  • the first and second anode regions 10, 20 are only indicated by hatching of the area designated with 10, 20 for clarity reasons, but the hatched area is meant to be an area of alternating first and second anode regions 10, 20 as e.g. shown in FIG 7.
  • Star shape shall mean any central area of a region, which is surrounded by protrusions (fingers) with at least three such protrusions. Fingers shall be understood as areas, in which the width is smaller than the length of that area (in a plane parallel to the anode side). A cross as shown in FIG 10 is formed by four such protrusions. Of course, also another number of fingers than four can be used in a star design as three fingers in a triangle (three armed star or tri-star shape) or five or more fingers in the star design.
  • a shortest distance is the minimum length between a point within said region area and a point on said region border.
  • the maximum value of all possible shortest distances within said region is for a square design (FIG 8) the distance between the central point of the square to the middle point of any of the border lines. This is the longest distance to equalize charge during switching of the device in the highly p doped area.
  • the region width is defined as two times this maximum value, i.e. the width is the length of the edge of the square.
  • pilot anode region width 23 corresponds to the diameter of the pilot anode region (again the maximum value is measured from the central point of the circle to any point on the border of the circular pilot anode region).
  • pilot anode region width 23 For explaining what the maximum value (pilot anode region width 23) of the shortest distance is for the second pilot anode region 22 in form of a cross (FIG 10), the cross is hypothetical ⁇ divided into four outer rectangles and a central rectangle. The maximum value of any shortest distance between a point within the cross region to the border of the cross region exists from the middle point of the central rectangle of the cross to one of the four points, on which two adjacent outer rectangles adjoin.
  • the pilot anode region width 23, which is two times this maximum value i.e. the diameter of the maximum diameter of a circle laid into the cross through the central point
  • the maximum value is the longest way an electron or hole has to flow in order to charge or discharge the region if the device is switched between on/off or vice versa.
  • the orientation of the cross is the same as of the edges of the device, but it is also possible to rotate the cross, i.e. by 45°, so that the fingers point to the corners of the device.
  • the device may also have various forms like a rectangle, exemplarily having a square main side (collector side of the IGBT) or a circle.
  • the conductivity types of the layers are switched, i.e. all layers of the first conductivity type are p type (e.g. the base layer 101 ) and all layers of the second conductivity type are n type (e.g. the well layer 4).
  • the inventive semiconductor device 1 can for example be used in a converter.
  • Reference List

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne un IGBT (1) qui comprend une puce à semi-conducteur (100), une partie de ladite puce (100) formant une couche de base (101). Une pluralité de régions sources (3) du premier type de conductivité, une couche à puits (4) du second type de conductivité et une électrode grille sont disposées sur le côté cathode (104). Sur le côté anode (103), une couche d'anode (2) d'un second type de conductivité est agencée, qui comprend une région mélangée qui comporte au moins une première région d'anode (10) et au moins une seconde région d'anode (20) et au moins une région d'anode pilote (22). La largeur (11) de chaque première région d'anode est plus petite que l'épaisseur (102) de la couche de base. Chaque seconde concentration en dopage maximum est supérieure à chaque première concentration en dopage maximum. Toutes les premières et secondes régions d'anode (10) possèdent une épaisseur qui est inférieure à 2 µm. Chaque concentration en dopage pilote maximum est supérieure à chaque première concentration en dopage maximum et chaque largeur de région d'anode pilote est au moins une fois l'épaisseur (102) de la couche de base. La largeur (21) de la ou des secondes régions est au moins cinq fois inférieure à la largeur (23) de la région d'anode pilote.
PCT/EP2015/064771 2014-06-30 2015-06-30 Dispositif à semi-conducteur WO2016001182A2 (fr)

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CN109728082A (zh) * 2017-10-30 2019-05-07 奥特润株式会社 功率半导体器件及其制造方法
DE102019115503A1 (de) * 2019-06-07 2020-12-10 Infineon Technologies Ag IGBT mit strukturiertem Rückseitenemitter
DE102023116868B3 (de) 2023-06-27 2024-10-17 Infineon Technologies Ag RC-IGBT und Verfahren zum Betreiben einer Halbbrückenschaltung

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JPH0430476A (ja) * 1990-05-25 1992-02-03 Fuji Electric Co Ltd 絶縁ゲートバイポーラトランジスタ
JP4506808B2 (ja) * 2007-10-15 2010-07-21 株式会社デンソー 半導体装置
US9153674B2 (en) * 2009-04-09 2015-10-06 Infineon Technologies Austria Ag Insulated gate bipolar transistor
JP2015023118A (ja) * 2013-07-18 2015-02-02 株式会社東芝 半導体装置

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US8212283B2 (en) 2009-04-29 2012-07-03 Abb Technology Ag Reverse-conducting semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109728082A (zh) * 2017-10-30 2019-05-07 奥特润株式会社 功率半导体器件及其制造方法
US11164964B2 (en) 2017-10-30 2021-11-02 Hyundai Mobis Co., Ltd. Power semiconductor device and method of fabricating the same
CN109728082B (zh) * 2017-10-30 2022-04-29 现代摩比斯株式会社 功率半导体器件及其制造方法
DE102019115503A1 (de) * 2019-06-07 2020-12-10 Infineon Technologies Ag IGBT mit strukturiertem Rückseitenemitter
DE102019115503B4 (de) 2019-06-07 2024-07-25 Infineon Technologies Ag IGBT mit strukturiertem Rückseitenemitter
DE102023116868B3 (de) 2023-06-27 2024-10-17 Infineon Technologies Ag RC-IGBT und Verfahren zum Betreiben einer Halbbrückenschaltung

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