WO2015008843A1

WO2015008843A1 - Scan bist lfsr seed generation method and memory medium for storing program for same

Info

Publication number: WO2015008843A1
Application number: PCT/JP2014/069103
Authority: WO
Inventors: 哲史大竹; 本田　太郎; 孝憲森保
Original assignee: 国立大学法人大分大学
Priority date: 2013-07-17
Filing date: 2014-07-17
Publication date: 2015-01-22
Also published as: JP2015038473A; JP6391336B2

Abstract

Provided is a scan BIST LFSR seed generation method that is provided with procedures for forming a scan BIST seed generation model and for generating an LFSR seed by performing target fault test generation on the formed seed model. The seed generation model is provided with an XOR network configured by subjecting the scan BIST LFSR to time development for the length of a scan pass in a scan FF of a circuit to be inspected, and with a combinational circuit portion for the circuits to be inspected. The XOR network output is connected to the combinational circuit portion.

Description

Scan BIST LFSR seed generation method and storage medium for storing the program

The present invention is a seed generation method for built-in self test of a semiconductor integrated circuit, and more specifically, high failure detection rate can be obtained, seed generation can be performed at high speed, and the number of seeds can be reduced. The present invention relates to a scan BIST LFSR seed generation method and a storage medium for storing the program.

Recent advances in device technology have made it possible to increase the degree of integration of digital integrated circuits and to implement large-scale systems on LSIs. However, with the increase in circuit scale, testing becomes increasingly difficult, and the increase in test cost, such as the increase in test generation time, has become a problem. There is a correlation between test cost and testability, and it may be considered to facilitate testing to reduce the increased test cost. In order to facilitate testing, incorporating additional circuits in a circuit is called testability design, and one of them is scan design. In scan design, states can be freely set from the outside to the respective flip flops constituting the sequential circuit, and the states of those flip flops can be observed from the outside. The test generation problem of scan-designed sequential circuits can be treated as a test generation problem of combinational circuits, which improves the test generation ease.

There is a built-in self test (BIST) as a design method for simplifying the external test device. BIST uses a circuit that generates a test pattern and a circuit that examines the output response to the test pattern. A linear feedback shift register (LFSR) that generates a pseudorandom pattern is mainly used as a pattern generation circuit in BIST, and a circuit that checks an output response uses MISR (multiple-input signature register) . The MISR is a circuit for compressing the output response of the circuit, but in the present invention, only the pattern generation circuit and the circuit to be inspected are handled.

The LFSR of the pattern generation circuit can pseudo-randomly generate all patterns except the pattern of all 0 depending on the feedback position. However, since the operation of the LFSR is critical, some circuits can not achieve high fault coverage with pseudorandom patterns. A fault that is resistant to testing with pseudorandom patterns is called a random pattern tolerant fault. In order to achieve high fault coverage in circuits with such faults, reset the initial value of the LFSR's register (called the seed to be set initially to the LFSR's register) (reseed). Is known to be effective.

Specifically, several patterns are generated from a certain seed and a test is performed, and retesting is performed on a seed that can detect each fault for undetected faults in the test applied so far, and the test is repeated.

JP, 2009-156761, A Japanese Patent Laid-Open No. 6-52005 JP, 2008-117383, A

As a conventional LFSR seed generation method, there is a method of test generation for the failure and converting the obtained test pattern into a seed of LFSR, but conversion is not always possible and the failure detection rate may be lowered. is there. In addition, there is a problem that the number of seeds increases due to the generation of a test with don't care to improve the conversion rate to seeds. An object of the present invention is to provide a new LFSR seed generation method for improving the failure detection rate of the scan BIST in consideration of these problems.

In the first aspect of the present invention, in order to solve the above-mentioned problem, a seed generation model of scan BIST is formed, and a test generation of a target fault is performed on the formed seed generation model to generate a seed of the LFSR. The seed generation model includes an XOR network configured by expanding the time of the scan path length in the scan FF of the circuit under test, and the combinational circuit portion of the circuit under test. A scan BIST LFSR seed generation method, comprising: a configuration in which the XOR network output is connected to the combinational circuit portion.

In the first aspect, in the seed generation model, a phase shifter group may be connected between the XOR network and a combinational circuit portion of the test circuit. Also, a random inversion circuit group may be connected between the XOR network and the combinational circuit portion of the circuit under test. Each of the random inversion circuits of the random inversion circuit group includes an inversion logic circuit inserted between the XOR network and the combinational circuit portion of the circuit under test, a second XOR network, and a second XOR network. And an inversion control circuit for controlling the operation of the inversion logic circuit using an output. The target failure may be a stuck-at failure. Also, test generation of the target failure may be performed using an automatic test pattern generation tool.

Furthermore, in the first aspect, the seed generation model further includes a multiplexer for temporally switching the XOR network output and the scan FF output and inputting the same to the combinational circuit portion, and timing of switching of the multiplexer. A timing generator may be provided to control. The seed generation model may further include a phase shifter group or a random inversion circuit group.

Furthermore, in the first aspect, the seed generation model further includes a second combinational circuit portion that is a duplicate of the combinational circuit portion, and an input of the second combinational circuit portion is an output of the XOR network and The output of the combinational circuit portion may be connected.

Furthermore, in the first aspect, the seed generation model further includes: a second XOR network configured by expanding a scan path length in the scan FF of the circuit under test + 1 scan shift in time with the LFSR of the scan BIST; A multiplexer for temporally switching between the network output and the second XOR network output and inputting the same to the combinational circuit portion may be provided, and a timing generator for controlling the switching timing of the multiplexer.

In the second aspect of the present invention, in order to solve the above-mentioned problems, the LFSR of the scan BIST is expanded by time for the scan path length in the scan FF of the circuit under test to form an XOR network, and the XOR network is subjected to the test In order to cause a computer to execute a procedure of forming a seed generation model by connecting to a combinational circuit portion of a circuit, and a procedure of generating a test of a target fault on the seed generation model to generate a seed of the LFSR A storage medium for storing the program of

In a third aspect of the present invention, in order to solve the above-mentioned problem, an XOR network constructed by expanding a scan BIST LFSR for a scan path length in a scan FF of a circuit under test, the XOR network output and the scan A procedure for forming a seed generation model by a multiplexer that temporally switches between the FF output and applies it to the combinational circuit part of the circuit under test, and a timing generator that controls the switching timing of the multiplexer, the seed generation model A storage medium is provided for storing a program for causing a computer to execute a test generation of a target fault with respect to the above to form a seed of the LFSR.

In a fourth aspect of the present invention, in order to solve the above problem, an XOR network constructed by expanding a scan BIST LFSR for a scan path length in a scan FF of a circuit under test, and copying the combined circuit portion A second combinational circuit portion, the XOR network output connected to the input of the combinational circuit portion, and the XOR network output and the combinational circuit portion output connected to the input of the second combinational circuit portion A storage medium storing a program for causing a computer to execute a procedure for forming a seed generation model and a procedure for performing test generation of a target fault on the seed generation model to form a seed of the LFSR provide.

In a fifth aspect of the present invention, in order to solve the above problems, an XOR network constructed by expanding a scan BIST LFSR for a scan path length in a scan FF of a circuit under test and a combinational circuit of the circuit under test Part, the second XOR network configured by expanding the scan path length in the scan FF + 1 scan shift time in the scan FF, and the combinational circuit by temporally switching the output of the XOR network or the second XOR network A procedure for forming a seed generation model by a multiplexer applied to a part and a timing generator for controlling switching timing of the multiplexer, and a test generation of a target fault on the seed generation model to seed the LFSR The steps to form the computer Storing a program for executing, it provides a storage medium.

According to the scan BIST LFSR seed generation method of the present invention, a high failure detection rate can be obtained, seeds can be generated at high speed, and the number of seeds can be reduced. That is, according to the method of the present invention, the same operation as the scan BIST circuit in the test mode can be simulated for the circuit under test. And since it is possible to directly obtain the seed, it is not necessary to generate a test with don't care, and the number of patterns can be reduced compared to the conventional method. In addition, it is not necessary to perform failure simulation again in order to confirm how much failure the seed generated in the process of generating the seed can detect. Therefore, there is also an advantage that the test time can be reduced.

The figure which shows the conventional seed production | generation method. FIG. 2 is a diagram showing a seed generation method according to the present invention. A diagram showing a BIST model. The figure which shows the seed production | generation model which concerns on the 1st Embodiment of this invention. The figure which shows the seed production | generation model which concerns on the 2nd Embodiment of this invention. The figure which shows the other Example of the model shown to FIG. 5 (A). FIG. 6 is a timing chart showing a test operation of the LoC method targeted by the model of FIG. 5 (B). The figure which shows the seed production | generation model which concerns on the 3rd Embodiment of this invention. The figure which shows the seed production | generation model which concerns on the 4th Embodiment of this invention. FIG. 8 is a timing chart showing a test operation of the LoS method targeted by the model of FIG. 7 (A). The figure which shows the sample circuit of 3 stages LFSR, the number of external inputs 2, and scan path length 3. The figure which shows an example of the time expansion | deployment of LFSR. The figure which shows an example of XOR network. The figure which shows an example of a seed production | generation model. The figure which shows an example of the sample circuit which has a stuck-at fault. The figure which shows the example of seed production concerning one embodiment of the present invention. The figure which shows an example of the test production | generation and seed conversion by a conventional method. The figure which shows a combination circuit. FIG. 7 shows a sequential circuit. The figure which shows D type flip flop. The figure which shows the 0 stuck-at fault of AND gate input. Diagram showing test generation. The figure which shows the flip-flop designed scan. The figure which shows the sequential circuit by which the scan design was carried out. The figure which shows the structure of LFSR. The figure which shows the structure of 3 stage LFSR. Block diagram showing the structure of BIST. The figure which shows BIST of the circuit by which scan design was carried out. FIG. 7 shows a circuit with random pattern tolerant failure. The figure which shows the BIST model provided with the phase shifter. The figure which shows the BIST model provided with the random inversion circuit. The figure which shows the seed production | generation model (static) with a phase shifter. The figure which shows the seed production | generation model (delay) with a phase shifter. The figure which shows the seed production | generation model (random) with a random inversion. The figure which shows the seed production | generation model (delay) with a random inversion. The figure for demonstrating a transition failure. Timing chart of LoC (Broadside) method. Time expansion model representation of LoC test (Broadside test). Timing chart of LoS (skewed load) method. The figure which shows the seed production | generation model 1 for delay faults. 6 is a timing chart of a seed generation model 1. b21-A diagram showing the transition of detection rate for all faults. The figure which shows the detection rate transition with respect to the undetected failure after b21-10k application. The figure which shows the detection rate transition with respect to the undetected failure after b19-50k application. The figure which shows the detection rate transition with respect to the undetected failure after b19-50k application.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following embodiments are provided for the purpose of illustrating the present invention, and do not limit the present invention, and the present invention is limited only by the claims.

FIG. 1 is a block diagram conceptually showing a conventional scan BIST LFSR seed generation method. In the conventional method, first, a test pattern is generated by processing a netlist of a circuit under test (CUT) with an automatic test pattern generation tool (ATPG). Next, the test pattern thus obtained is subjected to seed conversion to obtain a seed of LFSR. As described above, in the conventional method, the seed of the LFSR is obtained through two-step processing (two-pass) of test pattern generation and seed generation. However, in this method, a test pattern may not be converted into a seed, and as a result, there is a problem that the fault detection rate is lowered.

In contrast to such a conventional two-pass seed generation method, the present inventors considered that it is possible to create all seeds if ATPG can directly generate seeds without creating a test pattern from a netlist. .

FIG. 2 is a block diagram conceptually showing the procedure of the one-pass seed creation method proposed by the present inventors. In this method, in order to create a seed directly by ATPG, a circuit obtained by artificially converting a circuit to be manufactured (CUT to be tested, CUT) from a netlist into a circuit suitable for producing a seed and converting the same Apply ATPG to generate seeds. In FIG. 2, the converted circuit is shown as a seed generation model. By implementing this one-pass seed generation method, complete seed generation can be performed, and improvement in seed quality can be expected. In addition, since the effect of simulation can be expected, the number of seeds may be reduced.

In the present invention, in order to realize the one-pass seed generation shown in FIG. 2, the LFSR used as a test pattern generator in the BIST and the state information of each scan FF of the sequential circuit which is a test circuit are temporally expanded. Then, we construct an XOR (Exclusive-OR) network and propose a seed generation model of the configuration in which this XOR network is connected to the combinational circuit part of the CUT.

FIG. 3 is a block diagram showing a subject BIST model. In FIG. 3, 1 indicates an LFSR, 2 indicates a circuit under test (CUT), and 3 indicates a response compressor (MISR). The CUT 2 is composed of a combinational circuit portion 20 of a sequential circuit and a scan FF chain 30. In the present invention, the response compressor 3 is not considered.

FIG. 4 is a diagram showing the configuration of a seed generation model according to the first embodiment of the present invention. The model of this embodiment is a base model, and targets static faults. As shown, in the seed generation model of this embodiment, the combination circuit part of the sequential circuit is constructed by temporally expanding the BSR LFSR 1 by the longest scan path length of the scan FF 30 (see FIG. 3). Configured to connect to 20 inputs. Here, when the scan FF 30 is removed from the circuit under test (CUT) 2 shown in FIG. 3, the input from the original scan FF 30 to the combinational circuit portion 20 is a pseudo external input (PPIs). The outputs to the scan FF 30 of the above are assumed to be pseudo external outputs (PPOs). This model can simulate the same operation as the scan BIST circuit in the test mode. Therefore, if ATPG for a single stuck-at fault model or the like is applied to this seed generation model, as shown in FIG. 2, a seed for detecting a fault of the fault model without generating a test pattern for the CUT Can be determined directly. The XOR network will be described later with reference to FIGS. 8-10.

FIGS. 5 (A), 5 (B), 6 and 7 (A) below show seed generation models for delay fault detection. The seed generation model shown in FIG. 5A is a seed generation model 1 for delay fault LoC test, and FIG. 6 shows a seed generation model 2 for delay fault LoC test. Further, the model shown in FIG. 7A is a seed generation model for the delay fault LoS test.

The model shown in FIG. 5A is a seed generation model for testing delay faults in a launch-off capture (or broadside, hereinafter LoC) method, and shows a model corresponding to multi-clock capture. This model has a configuration in which a multiplexer 40 and a timing generation circuit 50 for temporally switching the input of the multiplexer 40 are added to the base model (XOR network 10 and combinational circuit portion 20) shown in FIG. The multiplexer 40 serves to switch the input signal to the combinational circuit portion 20 between the output of the XOR network 10 and the output of the scan FF 30. The multiplexer 40 is set to 1 during scan shift and during application of the first pattern, and to 0 during application of the second pattern (0 during capture in multi-cycle capture).

FIG. 5B is a diagram showing another example of the model shown in FIG. 5A, which is a model for detecting delay faults in a two-pattern test (two-cycle capture). The circuit indicated by the dotted line 52 is an example of the timing generation circuit in the case of the two pattern test. FIG. 5C is a timing chart of test pattern loading in the LoC test corresponding to the two pattern test.

In the LoC test, first, set the scan enable signal (SE) to 1 (scan shift mode) and apply the scan clock for a cycle of scan path length (the number of scan FFs in the longest scan path when there are multiple scan paths) By setting (shifting in) the test pattern to the scan FF from the scan input (SI), the value of the scan FF (response to the two pattern test) is observed (shifted out) from the scan output (SO). The pattern set here corresponds to the first pattern of the two-pattern test. Next, the normal clock is applied for two cycles with SE set to 0 (normal operation mode). At this time, the value loaded to the FF in the first cycle becomes the second pattern of the two pattern test. Also, the value loaded to the FF in the second cycle becomes the response to the two pattern test. Perform the test by repeating this. A test in which a normal clock is input for two or more cycles in the normal operation mode is called a multi-cycle capture test.

FIG. 6 shows a seed generation model 2 for LoC test. This model comprises an XOR network 10, a combinational circuit portion 20 of the circuit to be detected, and a second combinational circuit portion 20 'duplicating the combinational circuit portion 20. It is known that test generation of stuck-at faults can generate two pattern tests for delay faults. This uses a two-time expansion model. Duplicate two combination circuit parts, connect PI to both outputs of XOR network together, connect PPO of the first circuit and PPI of the second circuit and test two patterns only in combination circuit Can be generated. For example, in order to consider that test generation of a rising transition fault is performed on a signal line of a target circuit, the first combinational circuit is the same portion as the signal line assuming a failure of the target circuit. It may be set to 0, and in the second combinational circuit, test generation may be performed on the same site assuming a 0 stuck-at fault.

FIG. 7A shows a seed generation model for testing delay faults by a launch off shift (or skewed load, hereinafter, LoS) method. In this model, a second XOR network 10 'configured by temporally expanding the LFSR 1 of FIG. 3 by the length of the longest scan path length of one scan FF 30 plus one scan shift with respect to the base model of FIG. And the second XOR network 10 ′ has a configuration in which a multiplexer 40 and a timing generation circuit 50 are added to temporally select the output of either XOR network 10 ′ and apply it to the combination circuit portion 20. The model shown corresponds to multi-clock capture, but if a circuit that outputs 1 when applying the first pattern and outputs 0 in synchronization with the second pattern capture clock is used as a timing generation circuit, it supports 2 pattern test Model.

FIG. 7B shows a timing chart of test pattern loading in the LoS test corresponding to the two pattern test. In the LoS test, first, in scan shift mode, apply the scan clock for the scan path length cycle to shift in the first pattern of the 2 pattern test from the scan input and simultaneously shift out the response to the 2 pattern test. Do. Next, the scan clock is applied for one more cycle in the scan shift mode. Here, the value set for the scan FF is the second pattern of the two pattern test. Then, SE is set to 0 (normal operation mode) and a normal clock is applied for one cycle. Here, the value loaded to the FF becomes a response to the two pattern test. However, the period from the last scan clock application to the normal clock application should be equal to the normal clock. Perform the test by repeating this.

The seed generation model according to each embodiment of the present invention shown in FIGS. 4 to 7 will be described in more detail below.
First, an XOR network will be described.
FIG. 8 is a diagram showing a sample circuit of 3-stage LFSR, 2 external inputs, and 3 scan path lengths. In the figure, 81 indicates a 3-stage LFSR, 82 indicates a CUT, 83 indicates a combination circuit portion of the

CUT

82, and 84 indicates a scan path of the CUT 82. The LFSR is configured by XOR and FF. Therefore, when the state information of the scan path 84 is temporally expanded, the circuit to be inspected can be considered as a combination circuit without an FF. Therefore, the values of each scan FF at a certain time and the external input can be expressed as a function of the seed.

In FIG. 9, assuming that the seed of the LFSR 81 in FIG. 8 is (FF 0, FF 1, FF 2) = (S 0, S 1, S 2), each FF of PI 0, PI 1 and scan path 84 when the value is filled in the scan path 84 It is the figure which expanded the value of SFF0, SFF1, SFF2) temporally as mentioned above, and expressed only with the seed. As shown, the value of the seed input to the LFSR 81 and the value of the external input to the combinational circuit portion 83 have a dependency, and this relationship can therefore be expressed in a logic circuit. A time-expanded structure of the LFSR and scan path in this manner is called an XOR network. FIG. 10 shows an XOR network 101 formed based on the input / output relationship of FIG.

FIG. 11 is a diagram showing a seed generation model configured by connecting the XOR network 101 shown in FIG. 10 to the combinational circuit portion 83 of the CUT, and the base model shown in FIG. 4 is applied to the sample circuit of FIG. It is a thing. Thus, by extracting only the combinational circuit portion 83 of the CUT and connecting the XOR network 101 to its input, the same operation as the scan BIST circuit in the test mode can be simulated, and ATPG is applied to this model. Can directly determine the seed. As a result, it is not necessary to generate a test with don't care, and the number of patterns can be reduced compared to the conventional method. In addition, it is not necessary to perform failure simulation again in order to confirm how much failure the seed generated in the process of generating the seed can detect. Therefore, there is also an advantage of reducing the seed generation time. These points are evaluated by experiments. The effectiveness of the method of the present invention is introduced by the results of evaluation by experiments using the ITC'99 benchmark circuit in the experimental examples described later.

FIG. 12 is a diagram showing a sample circuit of a 3-stage LFSR, 2 external inputs, and a scan path length of 3 and has 1 stuck-at fault in the combinational circuit portion. FIG. 13 shows an example of generating a seed for a target failure by the seed generation model formed for the circuit of FIG. FIG. 14 shows an example of test generation and seed conversion according to the conventional method, and shows a case where a test pattern: (0, X, X, 1, 1) can not be converted into a seed.

Hereinafter, in order to facilitate understanding of the present invention, definitions such as scan BIST: built-in self test method, LFSR: linear feedback shift register (LFSR), and examples related to the present invention Will be explained.

FIG. 15A shows a combinational circuit, and FIG. 15B shows a sequential circuit. A circuit that can be expressed as a combination of an input value, an output value, and an internal state value of 0 or 1 is called a logic circuit. Logic circuits can be further classified into combinational circuit (a) and sequential circuit (b). In the combinational circuit, the output value of the circuit is determined only by the input value at that time, and in the sequential circuit, it is not determined only by the input value but depends on the internal state of the circuit. The combinational circuit consists only of the combinational component 152 as shown in FIG. 15 (A). PI and PO represent an external input and an external output, respectively. The sequential circuit, as shown in FIG. 15B, comprises a state storage portion constituted by a combinational circuit portion 152 and a plurality of flip-flops (Flip-Flop, FF) 155. In a sequential circuit, the output is determined by the value of the input currently applied and the value of the internal state. Also, the internal state changes to the internal state at the next time according to the current input and the internal state. In the present embodiment, the D-type flip-flop 166 shown in FIG. 16 is handled. The FF 166 has a data input (D), a data output (Q) and a clock input (CLK), and takes in data by the clock signal.

If there is a physical defect in the elements that make up the circuit, the circuit will not operate correctly. Such physical defects are called circuit failures. Failures are treated as failure models that model the effects of circuit failures. A failure model in which a logic function of a logic circuit changes to another logic function due to a failure is called a logic (static) failure. A typical static fault model is stuck-at-fault. A stuck-at fault is a fault in which the value of the signal line in the circuit is fixed to 1 or 0, and a fault fixed to 1 is referred to as a stuck-at fault (stuck-at-1, sa-1), and is set to 0 The fixed fault is called a stuck-at 0 fault (stuck-at-0, s-a-0). As an example of a stuck-at fault, consider the circuit shown in FIG.

In the AND circuit 177 of FIG. 17, when 1 is applied to the signal lines x and y, 1 is output to the signal line z if there is no failure, but if sa−0 exists on x. 0 is output. In addition to stuck-at faults, many models such as bridge faults, delay faults, and transistor faults are considered as fault models.

Testing is to make sure that the logic circuit is manufactured as designed. A test consists of two processes of test generation (test generation) and test execution (test application), assuming a failure in test generation, setting the value of the failure point opposite to the failure value (activation), Find a test pattern that propagates the value to the external output. In test execution, a test pattern obtained by test generation is applied to a circuit, and the presence or absence of a failure is determined by comparing the output response with an expected value.

For example, consider test generation of a circuit in which the signal line F shown in FIG. 18 is sa-0. A and B become 1 to activate s-a-0. It is necessary to set G to 0 and I to 1 in order to propagate the value as an error signal to the external output. To set G to 0, either C or D is 0, the other is don't care (X), and to set I to 1, E is 0. From the above, it can be seen that one of the test patterns for detecting s-a-0 of the signal line F is (A, B, C, D, E) = (1, 1, 0, X, 0).

Test metrics include fault coverage and fault coverage. The failure detection rate is the number of failures that can be detected among the target failures, and is expressed by equation 1.

The fault detection efficiency indicates how many faults have been detected among the targeted faults, as well as how many faults identified as faults that can not be detected by the I / O response called redundant faults are identified. It is a ratio and is expressed by equation 2.

FIG. 19 shows an example of the scan designed FF. One of the testability designs is scan design. In scan design, FF 191 is provided with a scan input (scan in) so that it can be directly input from the outside, and multiplexer (MUX) 192 switches data input (Din) and scan input during normal operation so that they can be input to FF 191 . The output of the FF 191 can be observed from the scan out to the outside. If a scan input output terminal is prepared for each FF 191, an extra terminal is required twice as many as the number of FFs 191, which is not practical. Therefore, the FFs 191 are connected in a line so that they can operate as shift registers. A set of scan designed FFs in this way is called a scan path.

FIG. 20 shows an example of a scan-designed sequential circuit. In the scan-designed sequential circuit, the FF 191 can be operated as a shift register, so that each FF 191 can be easily set to an arbitrary state, and at the same time, those states can be observed. Therefore, the problem of test generation of scan-designed circuits can be treated as a problem of combinational circuits.

FIG. 21 shows an example of the LFSR.
A linear feed-back shift register (LFSR) is mainly used as a test pattern generation circuit of the built-in self-test system (BIST). In the model of the illustrated LFSR, when ci = 0, there is no feedback to XOR, and when ci = 1, there is feedback to XOR. The feedback position to XOR can be expressed by a polynomial, and the polynomial is called a characteristic polynomial. The characteristic polynomial of the LFSR in FIG. 21 can be expressed as Equation 3.

When primitive polynomials are used in this equation, all patterns can be generated pseudorandomly except for all zero patterns. Therefore, the LFSR can be used to perform a pseudorandom test or an exhaustive test in which a pattern other than all zeros is applied.

In the LFSR shown in FIG. 21, the value of the FF at the next time t + 1 can be expressed by the following equation 4 using the value of the FF at a certain time t and the characteristic polynomial.

As an example of the LFSR, FIG. 22 shows a 3-bit LFSR. At this time, the value of FF at time 0 is used as a seed, and the operation result when the value is set as (FF0, FF1, FF2) = (0, 1, 0) is shown in Table 1.

It can be seen from the results of Table 1 that all non-zero patterns can be generated.

A design method that simplifies external test equipment is the built-in self-test (BIST) method. The BIST method uses a circuit that generates a test pattern and a circuit that examines an output response to the test pattern, and the pattern generation circuit mainly uses an LFSR.

FIG. 23 shows a schematic view of BIST. In BIST, a test pattern is generated by the pattern generation circuit 230, applied to the circuit under test 231, and the output is compared with an expected value by the response analyzer (MISR) 231 to determine the presence or absence of a failure or a failure state. Check. As the pattern generation circuit 230, for example, the above-mentioned LFSR is used.

FIG. 24 shows the BIST of the scan designed circuit. Reference numeral 244 denotes an LFSR as a pattern generator, 246 denotes a combination circuit part in the sequential circuit, 248 denotes a scan path formed of FFs in the sequential circuit, and 250 denotes an MISR as a response analyzer. In this BIST, a pseudorandom test is performed by moving the LFSR 244 until the scan path 248 is satisfied, and the values of the scan path 248 and PI at that time are applied to the combinational circuit portion 246 of the circuit under test . In the present invention, the BIST of this structure is used as the BIST model of the present application, as shown in FIG.

One problem with BIST is that it is difficult to detect random pattern tolerant faults. As an example, a circuit in which the signal line E in FIG. 25 is sa-0 is shown. The pattern for detecting a fault needs a pattern in which all four inputs are 1; however, in the case of a 4-bit LFSR, the probability that this pattern is generated is 1/15. Among the patterns that can be generated by the LFSR, a failure that can be detected with only a limited number of patterns is called a random pattern tolerant failure. It is known that re-seeding of LFSR (referred to as reseed) is effective for detecting random pattern tolerant failure in BIST.

In the pseudo random pattern test based on the LFSR, in general, there is a dependency of the values between the FFs in the scan path, and between the external input and the scan path. One of the techniques for reducing this dependency is to use a phase shifter. A phase shifter is a circuit created using an XOR arranged at the output of the LFSR, and it changes the order of patterns generated by the LFSR. Further, there is a method using a random inversion circuit as a technique for reducing the dependency between the FF, the external input, and the scan path as in the phase shifter.

A schematic diagram of an example of the BIST configuration in the case of using a phase shifter is shown in FIG. In FIG. 26A, reference numeral 200 denotes a phase shifter, which serves to change the order of patterns generated by the LFSR 1 as described above.

A schematic diagram of an example of the BIST configuration in the case of using a random inversion circuit is shown in FIG. The BIST includes a circuit under test (CUT) 2, a scan path for enabling the scan, and a first pattern generation circuit 1 for forming a test pattern supplied to the scan path. The random inversion circuit controls pattern generation for changing the pattern generated by the first pattern generation circuit 1 using a pattern generated by the second pattern generation circuit 1 b provided separately from the first pattern generation circuit 1. The pattern control circuit includes an inversion logic unit 266 capable of inverting the logic of the output value of the first pattern generation circuit 1, and the inversion logic unit using a pattern generated by the second pattern generation circuit 1b. An inversion control circuit 268 capable of controlling the operation of the circuit 266 is included, and the output signal of the inversion logic unit 266 is supplied to the circuit under test 2. Specifically, whether the value generated by the first pattern generation circuit 1b is inverted is determined by the number of 1 values generated by the second pattern generation circuit 1b and the value of the inversion condition setting REG 270. The random inversion circuit is formed of the second pattern generation circuit 1b, the inversion logic unit 266, the inversion control circuit 268, and the inversion condition setting REG 270.

26 (C) and 26 (D) show a seed generation model corresponding to the BIST model with phase shifter shown in FIG. 26 (A). FIG. 26C shows a seed generation model with a phase shifter for static failure, in which a phase shifter group 200a is inserted between the XOR network 10 and the combinational circuit portion 20 with respect to the base model shown in FIG. Have. The phase shifter group 200a is a circuit in which the phase shifter 200 shown in FIG. 26A is copied in the scan path length and arranged in parallel. Strictly speaking, the phase shifter group 200a in FIGS. 26C and 26D has the phase shifter 200 shown in FIG. 26A and the XOR connected to PI of the phase shifter 200 removed (connected to SI This circuit is a circuit in which the XOR only) is copied by one scan path length. FIG. 26D shows a seed generation model with phase shifter for delay fault LoC test, in which the phase shifter group 200a is connected to the output of the XOR network 10 with respect to the seed generation model shown in FIG. 5A. It has composition.

FIGS. 26E and 26F show a seed generation model corresponding to the BIST model with a random inversion circuit shown in FIG. 26B. FIG. 26E shows a seed generation model with a random inversion circuit for static failure, which is different from the base model shown in FIG. 4 in the second XOR network 10a, the inversion logic circuit group 266a, and the inversion control circuit group 268a. Equipped with The inversion logic circuit group 266a is a circuit in which the inversion logic unit 266 shown in FIG. 26B is copied in parallel for the scan path length and similarly arranged in the inversion control circuit group 268a. This is a circuit in which long copies are arranged in parallel. The second XOR network 10a is configured by expanding the time of the LFSR constituting the second pattern generation circuit 1b by the scan path length of the scan FF. The first seed input to the (first) XOR network 10 is the seed of the first pattern generation circuit 1 of FIG. 26B, and the second seed input to the second XOR network 10a. Is a seed to be input to the second pattern generation circuit 1b of FIG.

FIG. 26F shows a seed generation model with a random inversion circuit for delay fault LoC test, and the second XOR network 10a and the inversion control circuit group 268a with respect to the seed generation model shown in FIG. 5A. , And a configuration in which a random inversion circuit group consisting of inversion logic circuit groups 266a is added. As in the model of FIG. 26E, the seed input to the (first) XOR network 10 is the seed of the first pattern generation circuit 1, and the seed of the second XOR network 10a is the second pattern. It becomes a seed of the generation circuit 1b.

The seed generation model for delay fault detection shown in FIGS. 5 (A) to 7 (B) will be described in more detail below.
[Delayed fault model and test method]
Recent VLSI speeds have increased the importance of not only logic faults but also delay faults that are timing models. A delay fault is a fault model in which a signal can not be propagated within a specified time due to the delay of a gate or a signal line and a malfunction occurs. Delay faults include transition faults, gate delay faults, and path delay faults. The following description is directed to transition faults, but is not limited thereto.

FIG. 27 shows an example of transition failure. It is assumed that a transition fault causes a delay fault to occur in a certain signal line in a circuit, and that a delay large enough to be observed by an external output or an FF occurs regardless of a path propagating the delay. There are two types of transition faults: rising transition faults that delay the rise of the signal and falling transition faults that delay the fall.

In the transition fault test, first, the value of the signal at the target point is set, then the value is changed, and the value is propagated to the external output or the FF, and the response is observed. For example, apply a pattern to set the signal line in the first pattern to 0 (low), apply a pattern to set the signal line to 1 (high) to the second pattern, and propagate it to the external output or FF By observing the change in value, it is possible to detect the rising transition fault of the signal line. Such a test method is called a two-pattern test.

There are the LoC method and the LoS method as representative methods for performing two-pattern test at an actual speed (at-speed) in a scan-designed circuit. In the LoC test, after the first pattern is set by the scan operation, the second pattern is set and the response is stored in the FF at the actual speed by the system clock (FIG. 28). This action is called capture. The first pattern is set in consideration of using the internal state for the signal set as the second pattern FF. A time expansion model in which the operation of the LoC method test is expanded for each time is shown in FIG. The timing chart of the LoC method shown in FIG. 28 corresponds to the timing chart for explaining the operation of the delay fault LoC test seed generation model 1 shown in FIG. 5 (C).

FIG. 30 shows a basic timing chart of the delay fault test according to the LoS method. This timing chart is basically the same as the timing chart (FIG. 7B) for explaining the operation of the seed generation model for delay fault LoS test according to the embodiment of the present invention shown in FIG. 7A. Therefore, it is possible to use the operation details of the LoS test as described in the description of FIGS. 7A and 7B.

Delay fault seed generation model 1
FIG. 31 shows a seed generation model 1 for delay failure. The delay of the control signal m1 of the multiplexer of the seed generation circuit in the LoC test is shown in FIG. The delay fault seed generation model 1 of FIG. 31 is another embodiment of the delay fault seed generation model of FIG. 5 (A).

It is necessary to consider 2 time to generate 2 pattern test for LoC test. Therefore, a circuit is added to the scan enable terminal of the target circuit and the scan FF, and the XOR network 10 is connected. An OR gate and an FF are sequentially added and connected to the scan enable terminal, the output of the added FF is branched, a NOT gate is added, and another input of the OR gate is added through this. These OR gates, FFs and NOT gates form a timing generation circuit.

Also, a multiplexer is added to the output of the scan FF. The control signal of the multiplexer is the output of the FF added to the scan enable. The inputs of the multiplexer are the external input connecting the XOR network and the output from the scan FF. By the addition of the circuit, the XOR network 10 can be selected for PPI in the first pattern in the two-pattern test, and the scan FF can be selected in the second pattern.

In the case of a BIST configuration using a phase shifter and a random inversion circuit, a seed generation model for LoC delay fault corresponding to them is required. These models are as described above with reference to FIGS. 26 (D) and 26 (F).

Delay fault

seed generation models

2 and 3
FIG. 6 shows the delay fault seed generation model 2 and FIG. 7 (A) shows the delay fault seed generation model 3 for the LoS test.

According to the LFSR seed generation method of the present invention using the seed generation model (base model) for static failure and the seed generation models 1 to 3 for delay failure described above, seed generation is impossible in the seed generation model It is guaranteed that the failure (which turned out to be non-seed) could not be detected even by the original BIST circuit. Therefore, the fault detection capability of the BIST mechanism can be known. In addition, even if the test pattern once generated is not converted to the seed, the test generation tool can be used to directly generate the seed by setting constraints on the test generation. In the conventional method, test generation and seed conversion operations are repeated until seed conversion can be performed. Therefore, in order to obtain the same failure detection rate as the proposed method, test generation is frequently retried and it takes time.

[Evaluation]
First, the effectiveness of the proposed method based on the seed generation model for static faults is shown by experiments.
The experimental environment is shown in Table 2. We used the ITC '99 benchmark circuit for the experiment target circuit, and conducted seed generation experiments for random pattern tolerant failure (RPRF). RPRF applies 10,000 patterns to make it an undetected fault. Table 3 shows the circuit characteristics of the ITC'99 benchmark circuit.

In Table 3, #PIs, #POs, #Gates, and #FFs respectively represent the number of external inputs, the number of external outputs, the number of gates, and the number of FFs.

For the benchmark circuit b_19, a circuit in which the number of scan paths is divided into 6, 13, and 22 is prepared, and the circuit names are represented as b19_scan6, b19_scan13, and b19_scan22, respectively.

The experimental method is shown below. First, 10,000 pseudo-random patterns are generated by LFSR using appropriate seeds, and failure simulation is performed on the circuit under test using the generated patterns. Next, as a result of failure simulation, the failure not detected is regarded as random pattern tolerant failure (RPRF), and the seed is obtained for each failure by the conventional method and the proposed method, and the failure detection rate and failure detection efficiency of both methods , Seed generation time, Seed number compared. In addition, the case where a phase shifter was attached to the LFSR was also evaluated. For test generation in this experiment, the abort time was set to 10 seconds. The abort time is the upper limit of the time taken to generate one pattern. The used LFSRs were 100 stages LFSR for the first pattern generation circuit without and with the random inversion circuit, and 10 stages for the second pattern generation circuit of the random inversion circuit. In addition, the phase shifter with the phase shifter is designed so that the input of each scan path is out of phase by more than the scan path length so that the same partial series generated from the LFSR does not enter the plurality of scan paths. The conversion to seed in the conventional method adopted the method of solving SAT, and used MiniSAT as a SAT solver.

Table 4 shows the results of failure simulation with 10,000 pseudo random patterns using LFSR.

When seeds were generated by the conventional method and the proposed method for the undetected faults in Table 4, the results shown in Table 5 were obtained.

In the experiments, it was confirmed that the conventional method can not convert a part of the test generated pattern to the seed, and the failure detection rate is lowered. Table 5 also shows that the proposed method has higher fault coverage for all circuits. Also in terms of seed generation time, it can be seen that the proposed method is better for most circuits.

Next, we will consider the conventional method and the proposed method when the phase shifter is attached to the LFSR. Table 6 shows the results of failure simulation with 10,000 pseudo random patterns using the LFSR with a phase shifter.

Table 7 shows the results of seed generation using the conventional method and the proposed method for the undetected faults in Table 6.

From Table 7, it can be seen that even with the phase shifter, the proposed method can obtain seeds faster in most circuits and the number of seeds can be smaller than that of the conventional method in most circuits. Furthermore, it is understood that the proposed method is superior also in the fault detection rate.

Next, we will consider the conventional method and the proposed method when a random inversion circuit is attached to the LFSR. Table 8 shows the results of failure simulation with 10,000 pseudo random patterns using LFSR with a random inversion circuit.

Table 9 shows the results of seed generation using the conventional method and the proposed method for undetected faults in Table 8.

Next, the effectiveness of the proposed method using the seed generation model 1 for delay faults is shown by experiments. The circuits used for the experiments are ITC'99 benchmark circuits b14, b17, b18, b19, b20, b21 and b22. The experimental environment is identical to that shown in Table 2.

In Tables 10 to 15 below, evaluation of seed single-piece quality by the seed generation model 1 for delay fault is described. Tables 10 and 11 show the evaluation environment and the circuit characteristics of the benchmark circuits b14, b17, b18, b19, b20, b21 and b22.

Table 11 shows seed generation target faults. It shows the number of undetected failures after the initial pseudo random pattern application.

Table 12 shows the results of experiments on seed single quality. Here, an undetected fault after application of 10,000 pseudo random patterns is a seed generation target.

In Table 12,
Conventional% FC: Failure simulation results when one pattern is expanded from each seed% FC of the proposed method,% FE: A report of ATPG at the time of seed generation is shown.

Table 13 shows test generation with don't care and seed conversion, and undetected faults after application of 10,000 pseudo random patterns are targets for seed generation. This shows the loss of fault coverage due to the inability to convert to seeds by the conventional method.

Table 14 shows the cumulative failure detection rate / detection efficiency. This result shows the case including 10,000 pseudo random pattern application. Undetected faults after application of 10,000 pseudo random patterns are targets for seed generation.

Tables 15 to 20 and FIGS. 33 to 36 below show experimental results of the seed deployment quality of the seeds generated using the delay generation function 1 for seed generation for delay faults.

Table 15 shows the experimental result of seed quality (128 pattern expansion). In this experiment, the seeds are rearranged so that the rise of the detection rate becomes the fastest, the target generation target failure (only representative failure), the total failure and the undetected failure after applying 10,000 (10 k) pseudo random patterns for b21 For the b19, 50,000 (50 k) pseudo random pattern is not detected after application of the pseudo random pattern.

Table 16 shows the status of seed generation.

FIG. 33 shows the transition of the detection rate for the total failure of b21.

The experimental results in Table 16 show the transition of the detection rate for all failures in b21. From this table, the maximum detection rate reached by the conventional method was 86%, and the proposed method was able to reduce the number of seeds required to reach the same detection rate by 12% (12% reduction in test time).

The experimental result shown in FIG. 34 shows the transition of the detection rate with respect to the undetected failure after applying the 10 k pseudo random pattern of b21.

The experimental results in Table 18 show the transition of the detection rate for undetected faults after application of the 10 k pseudo random pattern of b21. The maximum detection rate reached by the conventional method is 85%, and the proposed method can reduce the number of seeds required to reach the same detection rate by 44% (44% reduction in test time).

The experimental result shown in FIG. 35 is a figure which shows transition of the detection rate with respect to the undetected failure after 50k pseudo random pattern application of b19.

The experimental result shown in Table 19 shows the transition of the detection rate for the undetected failure after applying the 50 k pseudo random pattern of b19. The maximum detection rate reached by the conventional method was 65%, and the proposed method was able to reduce the number of seeds required to reach this detection rate by 25% (25% reduction in test time).

The experimental result shown in FIG. 36 shows the transition of the detection rate with respect to the undetected failure after applying the 50 k pseudo random pattern of b19.

The experimental result shown in Table 19 has shown the transition of the detection rate with respect to the undetected failure after 50k pseudo random pattern application of b19. Because in this experiment it took time to sort all the seeds, only the 5,000 (5 k) seeds initially generated were used.

From Table 20, it can be seen that the proposed method is significant even when using only the 5 k seeds generated initially. The maximum detection rate reached by the conventional method was 56%, and the proposed method was able to reduce the number of seeds required to reach this detection rate by 28% (a 28% reduction in test time).

1 LFSR
2 Circuit under test (CUT)
3 response compressor (MISR)
10 XOR network 20 combination circuit part 30 scan FF
40 multiplexer 50 timing generator

Claims

Form a scan BIST seed generation model,
Each procedure for performing test generation of a target fault on the formed seed generation model to generate a seed of LFSR;
The seed generation model includes an XOR network configured by expanding the time of the scan path length in the scan FF of the circuit under test, and the combinational circuit portion of the circuit under test; A scan BIST LFSR seed generation method having a configuration in which the XOR network outputs are connected.
The method according to claim 1, wherein the seed generation model is a scan BIST LFSR seed generation method in which a phase shifter group is connected between the XOR network and a combinational circuit portion of the circuit under test.
The method according to claim 1, wherein the seed generation model is a scan BIST LFSR seed generation method in which a random inversion circuit group is connected between the XOR network and the combinational circuit portion of the circuit under test.
4. The method according to claim 3, wherein each of the random inversion circuits of the random inversion circuit group is an inversion logic circuit inserted between the XOR network and the combinational circuit portion of the circuit under test, and a second XOR. A scan BIST LFSR seed generation method, comprising: a network; and an inversion control circuit for controlling the operation of the inversion theory circuit using an output of a second XOR network.
5. A method according to any one of the preceding claims, wherein the target fault is a static fault.
The method according to claim 1, wherein the seed generation model further includes a multiplexer for temporally switching the XOR network output and the scan FF output and inputting the same to the combinational circuit portion, and timing of switching of the multiplexer. A scan BIST LFSR seed generation method, comprising:
7. The method according to claim 6, wherein the seed generation model further comprises a phase shifter group connected to the XOR network output, the output of the phase shifter group being input to the combinational circuit portion of the circuit under test and the multiplexer. The scan BIST's LFSR seed generation method.
7. The method according to claim 6, wherein the seed generation model further comprises a random inversion circuit group connected to the XOR network output, the output of the random inversion circuit group being the combinational circuit portion of the circuit under test and the multiplexer. A scan BIST LFSR seed generation method that is input to.
9. The method according to claim 8, wherein each of the random inversion circuits of the random inversion circuit group is an inversion logic circuit inserted between the XOR network and the combinational circuit portion of the circuit under test, and a second XOR. A scan BIST LFSR seed generation method, comprising: a network; and an inversion control circuit for controlling an operation of the inversion logic circuit using an output of a second XOR network.
The method according to claim 1, wherein the seed generation model further comprises a second combinational circuit portion which is a duplicate of the combinational circuit portion, the output of the XOR network being at the input of the second combinational circuit portion. A scan BIST LFSR seed generation method, wherein the combination circuit portion and the output of the combinational circuit portion are connected.
The method according to claim 1, wherein the seed generation model further comprises: a second XOR network configured by expanding the LFSR for the scan path length + 1 scan shift time, the XOR network output, and the second XOR. A scan BIST LFSR seed generation method, comprising: a multiplexer for temporally switching to a network output and inputting the combinational circuit portion; and a timing generator for controlling switching timing of the multiplexer.
A method according to any of the claims 6-11, wherein the target failure is a delayed failure.
A method according to any one of the preceding claims, wherein the test generation of the target fault is performed using an automatic test pattern generation tool, with scan BIST's LFSR seed generation.
Procedure for forming a seed generation model by expanding the time of the scan path length in the scan FF of the circuit under test to form the XOR network and connecting the XOR network to the combinational circuit part of the circuit under test. When,
A storage medium storing a program for causing a computer to execute a test generation of a target failure on the seed generation model to generate a seed of the LFSR.
An XOR network configured by expanding a scan path length in the scan FF of the circuit under test for the scan BIST LFSR, and a combinational circuit portion of the circuit under test by temporally switching between the XOR network output and the scan FF output Forming a seed generation model by a multiplexer applied to the circuit and a timing generator controlling the switching timing of the multiplexer;
A storage medium storing a program for causing a computer to execute a test generation of a target failure on the seed generation model to form a seed of the LFSR.
XOR network configured by expanding scan SR length of scan BIST by scan path length in scan FF of test circuit, combined circuit portion of test circuit, and LFSR by scan path length + 1 scan shift time The XOR network output connected to the input of the combinational circuit portion, and the XOR network output and the combinational circuit portion output at the input of the second combinational circuit portion Connecting to form a seed generation model;
A storage medium storing a program for causing a computer to execute a test generation of a target failure on the seed generation model to form a seed of the LFSR.
XOR network configured by expanding scan SR length of scan BIST by scan path length in scan FF of test circuit, combined circuit portion of test circuit, and LFSR by scan path length + 1 scan shift time A multiplexer configured to temporally switch the output of the XOR network or the second XOR network and apply the same to the combinational circuit portion, and a timing generator that controls switching timing of the multiplexer , Forming a seed generation model,
A storage medium storing a program for causing a computer to execute a test generation of a target failure on the seed generation model to form a seed of the LFSR.