WO2013137267A1 - Nitride compound semiconductor element - Google Patents

Abstract

The present invention is a nitride compound semiconductor element that is capable of effectively discharging a two-dimensional hole gas hole. In other words, a partially recessed structure (an opening part) is made by etching an undoped cap layer and a p-type cap layer that have a 2DHG layer, and is configured so as to easily make Ohmic contact with a base electrode. This configuration enables the effective discharge of a 2DHG hole. Also, making the channel layer an undoped layer enables the suppression of current collapses while maintaining forward characteristics and backward characteristics, and enables short circuit resistance.

Description

Nitride compound semiconductor device

The present invention relates to a nitride compound semiconductor device, and more particularly to a nitride compound semiconductor device having a two-dimensional electron gas layer and a two-dimensional hole gas layer.

A GaN-based electronic device, which is a nitride-based compound semiconductor element, has a larger band gap energy than a GaAs-based material, and has a high heat resistance and excellent high-temperature operation. For this reason, development of heterojunction field effect transistors (HFETs) using these materials, particularly GaN / AlGaN semiconductors, is being advanced in nitride compound semiconductor devices. In recent years, a structure in which an HFET structure epilayer is effectively used and an insulating film is formed by etching only in the vicinity of the gate to form a normally-off type has been proposed (see, for example, US Pat. No. 7,038,253). This structure is called a hybrid MOSHFET structure.

On the other hand, in recent years, a nitride-based compound semiconductor device using a two-dimensional hole gas formed at the interface of AlGaN / GaN polarization junction (PJ: Polarization Junction) has been proposed (for example, JP-A-2011-82331). reference). FIG. 11 shows an example of the structure of such a nitride compound semiconductor device. The conventional nitride-based compound semiconductor element shown in FIG. 11 has a so-called lateral element structure in which current flows in parallel with the main surface. According to this structure, the conventional channel layer 118 / barrier layer 120 in the channel layer 118 (GaN) / barrier layer 120 (AlGaN) / cap layer 122 (GaN) / p-type cap layer 124 (GaN) from the substrate 112 side. In addition to the two-dimensional electron gas layer formed on the channel layer 118 side, a two-dimensional hole gas is formed on the cap layer 122 side by increasing the Al composition ratio and film thickness of the barrier layer 120. It has been announced that the breakdown voltage of nitride compound semiconductors and the current collapse can be improved by using these. (For example, see Nakajima et al., In Proc. ISPSD, 2011, pp.280-283.)

However, there is a problem with the structure of the nitride compound semiconductor device illustrated in FIG. That is, in this structure, the p-type layer has a low activation rate, so that it is difficult to make an ohmic contact on the growth surface using a particularly fine p-type electrode. Due to this, the structure has a problem because the two-dimensional hole gas cannot be effectively discharged.

An object of the present invention is to provide a nitride-based compound semiconductor device that can effectively discharge holes of a two-dimensional hole gas.

1st aspect of this invention is a nitride type compound semiconductor element, Comprising: The two-dimensional electron gas layer formed in the interface of an electron transit layer, an electron supply layer, this electron transit layer, and this electron supply layer A first nitride-based semiconductor layer comprising: a second nitride-based semiconductor layer formed on the first nitride-based semiconductor layer and having a two-dimensional hole gas layer formed at a polarization junction interface; A base electrode formed in contact with the second nitride-based semiconductor layer and in electrical contact with the two-dimensional hole gas layer in which a surface having an orientation different from that of at least one epitaxial growth surface is exposed; Is provided.

In a second aspect of the present invention, in the first aspect, the second nitride semiconductor layer has an opening contacting the two-dimensional hole gas layer.

According to a third aspect of the present invention, in the second aspect, the opening reaches the surface of the electron supply layer of the first nitride-based semiconductor layer.

According to a fourth aspect of the present invention, in the second aspect or the third aspect, an angle formed between a side surface and a bottom surface of the opening is 45 ° or more and 175 ° or less, and the base electrode is the opening. It is formed so as to cover the part.

According to a fifth aspect of the present invention, in the second or third aspect, an angle formed between a side surface and a bottom surface of the opening is 90 ° or more and 150 ° or less, and the base electrode defines the opening. It is formed to cover.

According to a sixth aspect of the present invention, in any one of the first to fifth aspects, the gate electrode, the drain electrode, the source electrode, and the region between the gate electrode and the drain electrode are arranged in the region. A field effect transistor including a second nitride-based semiconductor layer and performing a normally-off operation.

According to a seventh aspect of the present invention, in any one of the first to fifth aspects, the gate electrode, the drain electrode, the source electrode, and the region between the gate electrode and the drain electrode are arranged in the region. A field effect transistor including a second nitride-based semiconductor layer and having a normally-on operation.

According to an eighth aspect of the present invention, in the sixth aspect or the seventh aspect, an average concentration of the two-dimensional hole gas layer in the electric field relaxation layer decreases from the gate electrode toward the drain electrode. It is going.

According to a ninth aspect of the present invention, in the eighth aspect, the electric field relaxation layer includes a nitride-based semiconductor layer having p-type carriers, and the first electrode is directed from the gate electrode toward the drain electrode. It arrange | positions so that the area which touches 1 nitride type semiconductor layer may be reduced.

According to a tenth aspect of the present invention, in any one of the first to fifth aspects, the second nitride may be disposed in an anode electrode, a cathode electrode, and a region between the anode electrode and the cathode electrode. And a field relaxation layer including a semiconductor layer.

According to an eleventh aspect of the present invention, in the tenth aspect, the electric field relaxation layer includes a nitride-based semiconductor layer having p-type carriers, and the first electrode is directed from the anode electrode toward the cathode electrode. It arrange | positions so that the area which touches 1 nitride type semiconductor layer may be reduced.

In a twelfth aspect of the present invention, in any one of the sixth to ninth aspects, the source electrode or the gate electrode and the base electrode have the same potential.

In a thirteenth aspect of the present invention, in the tenth aspect or the eleventh aspect, the anode electrode and the base electrode have the same potential.

According to a fourteenth aspect of the present invention, in the twelfth aspect, the gate electrode is formed so as to cover at least a part of the base electrode.

According to a fifteenth aspect of the present invention, in the thirteenth aspect, the anode electrode is formed so as to cover at least a part of the base electrode.

According to the above aspect of the present invention, there is an effect that holes of the two-dimensional hole gas can be effectively discharged.

BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic block diagram which shows an example of schematic structure of the normally-off type field effect transistor of 1st Example, The schematic top view (1) seen from the upper surface, BB sectional drawing (2) of a top view, FIG. 3C is a sectional view taken along the line CC of the plan view (3). It is explanatory drawing for demonstrating the 1st manufacturing process of the field effect transistor of a 1st Example. It is explanatory drawing for demonstrating the 2nd manufacturing process of the field effect transistor of a 1st Example. It is explanatory drawing for demonstrating the 3rd manufacturing process of the field effect transistor of a 1st Example. It is explanatory drawing for demonstrating the 4th manufacturing process of the field effect transistor of a 1st Example. It is explanatory drawing for demonstrating angle (theta) of the side surface and bottom face in the opening part of an undoped cap layer and a p-type cap layer, and has shown the case where angle (theta) is about 90 degrees. It is explanatory drawing for demonstrating angle (theta) of the side surface and bottom face in the opening part of an undoped cap layer and a p-type cap layer, and has shown the case where angle (theta) is less than 90 degrees. It is explanatory drawing for demonstrating angle (theta) of the side surface and bottom face in the opening part of an undoped cap layer and a p-type cap layer, and has shown the case where angle (theta) exceeds 90 degrees. It is a schematic block diagram which shows an example of schematic structure of the field effect transistor of 2nd Example, the schematic top view (1) seen from the upper surface, the BB sectional drawing (2) of a top view, and a top view FIG. 3 shows a cross-sectional view (3) along the line CC of FIG. It is a schematic block diagram which shows an example of schematic structure of the field effect transistor of 3rd Example, The schematic top view (1) seen from the upper surface, BB sectional drawing (2) of a top view, and a top view FIG. 3 shows a cross-sectional view (3) along the line CC of FIG. It is a schematic block diagram which shows an example of schematic structure of the diode of 4th Example, The schematic top view (1) seen from the upper surface, BB sectional drawing (2) of a top view, and C of a top view -C sectional view (3) is shown. FIG. 10 is a schematic configuration diagram illustrating an example of a schematic configuration of a normally-on type field effect transistor according to a fifth embodiment, which is a schematic plan view as viewed from above (1), and a cross-sectional view along line BB of the plan view (2). And a sectional view taken along line CC of the plan view (3) is shown. It is sectional drawing which shows an example of schematic structure of the conventional nitride type compound semiconductor element.

The nitride compound semiconductor device of the present embodiment will be described in detail with reference to the drawings. This embodiment is an example of the nitride compound semiconductor element of the present invention, and the present invention is not limited to this embodiment.

[First embodiment]
In the first embodiment, the case where the nitride compound semiconductor element of the present invention is a normally-off field effect transistor will be described.

First, the structure of the field effect transistor will be described. FIG. 1 is a schematic configuration diagram showing an example of a schematic configuration of the field effect transistor of the present embodiment. FIG. 1 shows a schematic plan view (1) viewed from above, a cross-sectional view taken along line BB of the plan view (2), and a cross-sectional view taken along line CC of the plan view (3).

The field effect transistor 10 shown in FIG. 1 is a normally-off GaN-based field effect transistor. The field effect transistor 10 includes a substrate 12, a buffer layer 14, a high resistance layer 16, a channel layer 18, a barrier layer 20, an undoped cap layer 22, a p-type cap layer 24, a dielectric film 26, a source electrode 30, a drain electrode 32, A base electrode 34 and a gate electrode 36 are provided.

The substrate 12 is a substrate made of silicon (Si) having a (111) plane as a main surface. The buffer layer 14 formed on the substrate 12 is a buffer layer having a stacked structure in which, for example, an AlN layer and a GaN layer are stacked. The high resistance layer 16 formed on the buffer layer 14 has a higher electrical resistance than the channel layer 18 and is, for example, a GaN layer (GaN: C layer) to which C is added.

The channel layer 18 formed on the high resistance layer 16 is an undoped GaN (uid-GaN) layer. The channel layer 18 functions as an electron transit layer of the field effect transistor. The barrier layer 20 formed on the channel layer 18 is an undoped AlGaN layer (barrier layer). The barrier layer 20 functions as an electron supply layer. Here, a barrier layer (undoped AlGaN layer) 20 is heterojunction with the surface of the channel layer (undoped GaN layer) 18 corresponding to the channel length L. Therefore, a two-dimensional electron gas (2DEG) is generated at the interface of the heterojunction portion, and a 2DEG layer is formed. A dielectric film 26, which is a MOS gate insulating film, is formed below the gate electrode 36. The field effect transistor 10 has a structure in which a channel is formed by partially removing the barrier layer 20 by etching under the field effect transistor 10. In the field effect transistor 10, the two-dimensional electron gas plays a role of reducing the access resistance, and thus exhibits a low on-resistance.

Further, the undoped cap layer 22 and the p-type cap layer 24 are disposed between the gate electrode 36 and the drain electrode 32. The undoped cap layer 22 and the p-type cap layer 24 function as an electric field relaxation layer. The undoped cap layer 22 is composed of an undoped In _X Ga _1-X N (0 ≦ X <1) layer. The p-type cap layer 24 is composed of a p-In _X Ga _1-X N (0 ≦ X <1) layer doped with an impurity such as Mg. Since the undoped cap layer 22 and the p-type cap layer 24 are polarization-bonded, two-dimensional hole gas (2DHG) is generated at the interface of the bonded portions to form a 2DHG layer. Further, the undoped cap layer 22 and the p-type cap layer 24 of the present embodiment have an opening 40 (details will be described later).

The base electrode 34 is formed on the p-type cap layer 24 so as to cover the opening 40. The source electrode 30 and the drain electrode 32 are formed in the order of Ti, an alloy of Al and Si, and W from the region closest to the barrier layer 20.

Next, an example of a method for manufacturing the field effect transistor 10 of this embodiment will be described. In manufacturing the field effect transistor 10, a growth apparatus was an MOCVD (Metal Organic Chemical Deposition) apparatus, and the substrate 12 was silicon (111).

1) A first step of manufacturing an epitaxial substrate will be described with reference to FIG.

First, in the first step, the silicon (111) substrate 12 is introduced into the MOCVD apparatus, and the vacuum degree in the MOCVD apparatus is reduced to 1 × 10 ⁻⁶ hPa or less with a turbo pump, and then the degree of vacuum is set to 100 hPa. The substrate 12 is heated to 1050 ° C. When the temperature is stabilized, the substrate 12 is rotated at 900 rpm, trimethylaluminum (TMA) as a raw material is introduced into the surface of the substrate 12 at a flow rate of 100 cm ³ / min, and ammonia is 12 liters / min. A part of the AlN layer is epitaxially grown. The growth time is 4 min, and the thickness of the AlN layer 2 is about 50 nm.

Thereafter, in the first step, 20 to 80 layers of a laminated film in which, for example, a GaN layer with a thickness of 5 to 100 nm and an AlN layer with a thickness of 1 to 10 nm are laminated are stacked on the AlN layer. A buffer layer is formed. The buffer layer 14 is not limited to this configuration, and may be variously modified depending on the material such as the channel layer 18 and other conditions. Further, in the first step, the high resistance layer 16 is epitaxially grown on the buffer layer 14 using TMG as a raw material, and C is doped.

Next, in the first step, trimethylgallium (TMG) is introduced onto the high resistance layer 16 at a flow rate of 300 cm ³ / min and ammonia is 12 liters / min, and the channel layer 18 made of a GaN layer is epitaxially grown. The channel layer 18 functions as an electron transit layer. The growth time of the channel layer 18 was 200 sec, and the film thickness of the channel layer 18 was 300 nm.

Next, in the first step, TMA and 50 cm ³ / min, TMG and 100 cm ³ / min, and ammonia was introduced at a flow rate 12 liter / _min, a barrier layer 20 made of Al 0.3 _{Ga 0.7} N layer Epitaxial growth was performed. The barrier layer 20 functions as an electron supply layer. The growth time of the barrier layer 20 is 40 sec, and the thickness of the barrier layer 20 is 30 nm.

Next, in the first step, TMG is introduced onto the barrier layer 20 at a flow rate of 300 cm ³ / min and ammonia is 12 liter / min to epitaxially grow the undoped cap layer 22 made of a GaN layer. The growth time of the undoped cap layer 22 is 40 sec, and the film thickness of the undoped cap layer 22 is 30 nm.

Further, in the first step, a p-type cap layer 24 made of a p-GaN layer is introduced by introducing TMG at a flow rate of 300 cm ³ / min, ammonia at 12 liters / min, and biscyclopentadienyl magnesium at a flow rate of 300 cm ³ / min. Is epitaxially grown. The growth time of the p-type cap layer 24 is 40 sec, and the film thickness of the p-type cap layer 24 is 20 nm. In the second step, in order to perform activation annealing of the p layer, annealing is performed at 800 ° C. for about 5 minutes in a nitrogen atmosphere.

2) The second step will be described with reference to FIG.

Next, in the second step, an isolation mesa is formed for element isolation using chlorine gas or the like. Thereafter, the p-type cap layer 24 and the undoped cap layer 22 are masked with a resist or the like, and dry etching is performed using chlorine gas or the like until the surface of the barrier layer 20 is exposed. At this time, element formation with good reproducibility and yield can be realized by performing selective etching by mixing a fluorine-based gas or an oxygen-based gas. In the second step, the opening 40 is simultaneously formed inside the portion left as an island as a layer for forming the base electrode 34 at that time. The opening 40 is formed in a stripe shape in parallel with the direction of current flow (lateral direction) in the p-type cap layer 24 and the undoped cap layer 22 to form a recess etching portion that comes into contact with the base electrode 34 in the future. . In FIG. 3, the opening 40 is shown for convenience of explanation.

It is sufficient that at least the p-type cap layer 24 is removed by etching in the recess etching portion, preferably the undoped cap layer 22 is removed, and more preferably at least the surface of the barrier layer 20 is removed by etching. Further, even if the etching proceeds more than the surface of the barrier layer 20, it is desirable because the cap layer 22 (2DHG layer) is exposed to obtain a lower contact specific resistance. If the barrier layer 20 is completely removed, the base electrode 34 to be formed later and the channel layer 18 (2DEG layer) are in contact with each other. Therefore, better electrical characteristics can be obtained than in the case of no contact. It will disappear. Therefore, it is desirable not to completely remove the barrier layer 20.

The opening width W of the stripe-shaped opening 40 may be at least 0.1 μm or more, and if there is at least one opening 40, the effect of the present invention is exhibited.

3) A third step of forming the source electrode 30 and the drain electrode 32 will be described with reference to FIG.

Next, in the third step, the barrier layer 20 is removed by etching only in the region where the gate electrode 36 is formed using chlorine gas or the like. Thereafter, in a third step, 40 nm of SiO ₂ is formed as the dielectric film 26 which is a gate insulating film. The dielectric film 26 of SiO ₂ is formed by PCVD or the like using SiH ₄ gas and N ₂ O gas. The method may be PECVD or APCVD. Thereafter, in a third step, a region where the source electrode 30 and the drain electrode 32 are to be formed is opened using a resist or the like to expose the surface of the barrier layer 20. In the exposed region, Ti, Al and Si alloy film, and W are sequentially deposited to form the source electrode 30 and the drain electrode 32 by a lift-off method or the like.

4) A fourth step of forming the base electrode 34 will be described with reference to FIG.

Next, in the fourth step, patterning is performed by using a resist or the like, patterning is performed by providing an opening using a resist or the like in a region where the base electrode 34 is to be formed, and Ni / Au (60 nm / 40 nm) is deposited. Thus, the base electrode 34 was formed. The base electrode 34 is further formed by annealing at 500 ° C. to 600 ° C. in an oxygen atmosphere or an oxygen-nitrogen mixed atmosphere.

The base electrode 34 is formed so as to cover the opening 40. Since the surface different from the epitaxial growth surface of the 2DHG layer is exposed on the side surface of the opening 40, the base electrode 34 and the 2DHG layer are electrically connected by forming the base electrode 34 in this way.

Here, the relationship between the shape of the opening 40 (the recess etching portion of the undoped cap layer 22 and the p-type cap layer 24) and the base electrode 34 will be described with reference to FIGS. 6A, 6B, and 6C. 6A, 6B, and 6C, the angle between the side surface 40A of the opening 40 and the bottom surface 40B will be described as θ. 6A, 6B, and 6C, the angle θ is illustrated on the base electrode 34 formed so as to cover the opening 40. However, since the angle θ is substantially the same, no problem occurs.

As shown in FIG. 6A, when the angle θ is about 90 °, the adhesion of the base electrode 34 is improved. On the other hand, as shown in FIG. 6B, when the angle θ is smaller than 90 °, the base electrode 34 formed on the side surface 40A may be thinner than others. Therefore, there is a concern that the base electrode 34 is interrupted on the side surface 40A, such as when the angle θ is significantly smaller than 90 °. Further, as shown in FIG. 6C, when the angle θ is larger than 90 °, the adhesion of the base electrode 34 is improved, but there is a concern that 2DHG may be thinned. From such a viewpoint, the angle θ of the opening 40 is preferably 45 ° or more and 175 ° or less, and more preferably 90 ° or more and 150 ° or less.

5) A fifth step for forming the gate electrode 36 will be described.

Next, in the fifth step, patterning is performed using a resist or the like, patterning is performed in which an opening is formed using a resist or the like in a region where the gate electrode 36 is to be formed, and Ni or Ti or the like is evaporated to form a gate electrode. 36 was formed. The gate electrode 36 may be made of polysilicon or the like. As a result, the field effect transistor 10 shown in FIG. 1 is manufactured.

[Second Embodiment]
In FIG. 7, the schematic block diagram which shows an example of schematic structure of a present Example is shown. FIG. 7 shows a schematic plan view (1) viewed from above, a cross-sectional view taken along line BB of the plan view (2), and a cross-sectional view taken along line CC of the plan view (3). Since the second embodiment has substantially the same configuration and process as the first embodiment, the same reference numerals are given to substantially the same parts, and detailed description thereof is omitted.

In the field effect transistor 10 of this example and the field effect transistor 10 of the first example, as shown in the plan view (1) of FIG. 7, the shapes (upper surface) of the p-type cap layer 24 and the undoped cap layer 22 are shown. The shape seen from) is different.

In the field effect transistor 10 of this example, the undoped cap layer 22 and the p-type cap layer 24 are formed so that the area in contact with the barrier layer 20 decreases from the gate electrode 36 side to the drain electrode 32 side. The portion where the p-type cap layer 24 is left (the tip portion where the area is reduced) may be separated from the drain electrode 32 by 0.1 μm or more, and preferably 1/3 or more between the gate electrode 36 and the drain electrode 32. It is desirable that there is an interval. For example, the portion where the p-type cap layer 24 is left may be at least about 4 μm if the distance between the gate electrode 36 and the drain electrode 32 is 12 μm.

Next, an example of a method for manufacturing the field effect transistor 10 of this embodiment will be described.

First, in the first step of the present embodiment, the epi substrate (substrate 12, buffer layer 14, high resistance layer 16, channel layer 18, barrier layer 20, cap layer 22, And a substrate on which the cap layer 24 is laminated).

Thereafter, in the second step of this embodiment, isolation mesa formation for element isolation is performed on the prepared epitaxial substrate using chlorine gas or the like. Thereafter, in the second step, the base electrode 34 is masked with a resist or the like, and dry etching is performed using chlorine gas or the like until the surface of the barrier layer 20 is exposed. At this time, element formation with good reproducibility and yield can be realized by performing selective etching by mixing a fluorine-based gas or an oxygen-based gas. At that time, in the second step, the area to be etched is relatively increased from the gate electrode 36 toward the drain electrode 32 inside the portion left as an island as a layer for forming the base electrode 34. Then, a recess etching portion (opening 40) that comes into contact with the base electrode 34 is formed in the future.

Here, the portion where the p-type cap layer 24 is left only needs to be separated from the drain electrode 32 by 0.1 μm or more, and preferably a space of 1/3 or more between the gate electrode 36 and the drain electrode 32 is left. Is desirable. For example, the portion where the p-type cap layer 24 is left may be at least about 4 μm if the distance between the gate electrode 36 and the drain electrode 32 is 12 μm.

Thereafter, in the manner from the third step to the fifth step of the first embodiment, the gate recess etching, the source electrode 30, the drain electrode 32, the base electrode 34, and the gate electrode 36 are formed, respectively. The illustrated field effect transistor 10 is manufactured.

In the field effect transistor 10 of the present embodiment, the area of the p-type cap layer 24 and the undoped cap layer 22 is gradually reduced from the gate electrode 36 toward the drain electrode 32 side, so that the average two-dimensional hole gas is reduced. The concentration can be reduced little by little. As a result, in the field effect transistor 10 of this embodiment, the electric field concentration at the end of the p-type cap layer 24 and the undoped cap layer 22 on the drain electrode 32 side can be suppressed. Compared with this, leakage current and breakdown voltage can be improved. Further, in the field effect transistor 10 of the present embodiment, the current collapse can be effectively suppressed.

[Third embodiment]
In FIG. 8, the schematic block diagram which shows an example of schematic structure of a present Example is shown. FIG. 8 shows a schematic plan view (1) viewed from above, a cross-sectional view taken along line BB of the plan view (2), and a cross-sectional view taken along line CC of the plan view (3). Since the third embodiment has substantially the same configuration and process as the first embodiment, the same reference numerals are given to substantially the same parts, and detailed description thereof is omitted.

Unlike the field effect transistor 10 of the first embodiment, the field effect transistor 10 of the present embodiment is such that the base electrode 34 and the gate electrode 36 have the same potential as shown in the sectional view (2) of FIG. That is, it is formed so as to be short-circuited.

By short-circuiting the base electrode 34 and the gate electrode 36 in this way, the on-resistance similar to that of the first embodiment can be obtained as the on-characteristic. As for the drain current, conductivity modulation occurs when holes are injected through the p-type layer, so that a drain current that is about 20% larger than that of the first embodiment can be obtained. Further, as the off characteristics, since the electric field relaxation effect can be obtained as in the first embodiment, the same breakdown voltage and leakage current can be obtained. In manufacturing, if the base electrode 34 and the gate electrode 36 are short-circuited, they behave as one electrode, so that electrical control can be performed with three terminals of a source, a gate, and a drain. In the field effect transistor 10 of the present embodiment, it is not necessary to take a terminal called a base electrode, so that the element size can be made more compact.

An example of a method for manufacturing the field effect transistor 10 of this embodiment will be described.

First, in the first step of the present embodiment, the epi substrate (substrate 12, buffer layer 14, high resistance layer 16, channel layer 18, barrier layer 20, cap layer 22, And a substrate on which the cap layer 24 is laminated).

Thereafter, in the second step of the present embodiment, isolation mesa formation for element isolation is performed on the prepared epitaxial substrate using chlorine gas or the like. Thereafter, in the second step, the base electrode 34 is masked with a resist or the like, and dry etching is performed using chlorine gas or the like until the surface of the barrier layer 20 is exposed. At this time, element formation with good reproducibility and yield can be realized by performing selective etching by mixing a fluorine-based gas or an oxygen-based gas. In the second step, the opening 40 is simultaneously formed inside the portion left as an island as a layer for forming the base electrode 34 at that time. The openings 40 are formed in a stripe shape in parallel with the direction of current flow in the p-type cap layer 24 and the undoped cap layer 22 to form a recess etching portion that comes into contact with the base electrode 34 in the future.

Thereafter, the gate recess etching, the source electrode 30, the drain electrode 32, and the base electrode 34 are formed in the manner up to the third step and the fourth step of the first embodiment, respectively.

Thereafter, in the fifth step of this embodiment, the gate electrode 36 is formed by patterning so as to straddle the base electrode 34. Thereby, the field effect transistor 10 shown in FIG. 8 is manufactured.

[Fourth embodiment]
In FIG. 9, the schematic block diagram which shows an example of schematic structure of a present Example is shown. FIG. 9 shows a schematic plan view (1) viewed from above, a cross-sectional view taken along line BB of the plan view (2), and a cross-sectional view taken along line CC of the plan view (3). Since the fourth embodiment has substantially the same configuration and process as the first embodiment, the same reference numerals are given to substantially the same parts, and detailed description thereof is omitted.

The nitride compound semiconductor device of this embodiment is configured as a diode 60 having a cathode electrode 62 and an anode electrode 64 instead of the source electrode 30, the drain electrode 32, and the gate electrode 36 of the first embodiment. .

An example of a manufacturing method of the diode 60 of this embodiment will be described.

First, in the first step of the present embodiment, the epi substrate (substrate 12, buffer layer 14, high resistance layer 16, channel layer 18, barrier layer 20, cap layer 22, And a substrate on which the cap layer 24 is laminated).

Thereafter, in the second step of the present embodiment, isolation mesa formation for element isolation is performed on the prepared epitaxial substrate using chlorine gas or the like. Thereafter, in the second step, the base electrode 34 is masked with a resist or the like, and dry etching is performed using chlorine gas or the like until the surface of the barrier layer 20 is exposed. At this time, element formation with good reproducibility and yield can be realized by performing selective etching by mixing a fluorine-based gas or an oxygen-based gas. In the second step, the opening 40 is simultaneously formed inside the portion left as an island as a layer for forming the base electrode 34 at that time. The openings 40 are formed in a stripe shape in parallel with the direction of current flow in the p-type cap layer 24 and the undoped cap layer 22 to form a recess etching portion that comes into contact with the base electrode 34 in the future.

Thereafter, in the third step of this embodiment, a region where the cathode electrode 62 is to be formed is opened using a resist or the like to expose the surface of the barrier layer 20. In the exposed region, Ti, an alloy film of Al and Si, and W are sequentially deposited, and the cathode electrode 62 is formed by a lift-off method or the like.

Next, in the fourth step of the present embodiment for forming the base electrode 34, patterning is performed using a resist or the like, and patterning is performed in which an opening is formed using a resist or the like in a region where the base electrode 34 is to be formed. Then, Ni / Au (60 nm / 40 nm) is deposited to form the base electrode 34. The base electrode 34 is further formed by annealing at 500 ° C. to 600 ° C. in an oxygen atmosphere or an oxygen-nitrogen mixed atmosphere.

Thereafter, in the fifth step of the present embodiment, patterning is performed using a resist or the like, patterning is performed by providing an opening using a resist or the like in a region where the anode electrode 64 is to be formed, and Ni or Pd is deposited. Thus, the anode electrode A is formed. The anode electrode 64 may be made of polysilicon or the like. As a result, the diode shown in FIG. 9 is manufactured.

[Fifth embodiment]
In FIG. 10, the schematic block diagram which shows an example of schematic structure of a present Example is shown. FIG. 10 shows a schematic plan view (1) viewed from above, a cross-sectional view taken along line BB of the plan view (2), and a cross-sectional view taken along line CC of the plan view (3). Since the fifth embodiment has substantially the same configuration and process as the first embodiment, the same reference numerals are given to substantially the same parts, and detailed description thereof is omitted.

In this embodiment, unlike the field effect transistor 10 of the first embodiment, a case where the nitride compound semiconductor element of the present invention is configured as a normally-on type field effect transistor will be described.

An example of a method for manufacturing the field effect transistor 70 of this embodiment will be described.

First, in the first step of the present embodiment, the epi substrate (substrate 12, buffer layer 14, high resistance layer 16, channel layer 18, barrier layer 20, cap layer 22, And a substrate on which the cap layer 24 is laminated).

Thereafter, in the second step of the present embodiment, isolation mesa formation for element isolation is performed on the prepared epitaxial substrate using chlorine gas or the like. Thereafter, in the second step, a region for forming the base electrode 34 is masked with a resist or the like, and dry etching is performed using chlorine gas or the like until the surface of the barrier layer 20 is exposed. At this time, element formation with good reproducibility and yield can be realized by performing selective etching by mixing a fluorine-based gas or an oxygen-based gas. In the second step, the opening 40 is simultaneously formed inside the portion left as an island as a layer for forming the base electrode 34 at that time. The openings 40 are formed in a stripe shape in parallel with the direction of current flow in the p-type cap layer 24 and the undoped cap layer 22 to form a recess etching portion that comes into contact with the base electrode 34 in the future.

Next, in the third step of the present embodiment, the source electrode 30 and the drain electrode 32 are formed in the same manner as the third step of the first embodiment. Since the field effect transistor 70 of this embodiment is normally on, a gate recess is not formed unlike the first embodiment.

Next, in the fourth step of the present embodiment for forming the base electrode 34, patterning is performed using a resist or the like, and patterning is performed by providing an opening using a resist or the like at a position where the base electrode 34 is to be formed. Ni / Au (60 nm / 40 nm) is deposited to form the base electrode 34. The base electrode 34 is further formed by annealing at 500 ° C. to 600 ° C. in an oxygen atmosphere or an oxygen-nitrogen mixed atmosphere.

Further, in the third step, patterning is performed using a resist or the like, patterning is performed in which an opening is formed using a resist or the like in a region where the gate electrode 36 is to be formed, and Ni or Ti or the like is evaporated to form the gate electrode 36. Form. The gate electrode 36 may be made of polysilicon or the like. In addition, a part of the dielectric film 26 in a region where the gate electrode 36 is formed can be removed to form a gate portion for Schottky junction. As a result, the field effect transistor 70 shown in FIG. 10 is manufactured.

As described above, in the nitride-based compound semiconductor device according to the present invention as described in the above embodiments, the undoped cap layer 22 and the p-type cap layer 24 having the 2DHG layer are partially recessed by etching. The base electrode 34 is formed so as to cover the opening 40 where the surface different from the epitaxial growth surface of the 2DHG layer is exposed. Therefore, the nitride-based compound semiconductor device according to the present invention can easily make ohmic contact with the base electrode 34. In the nitride-based compound semiconductor device according to the present invention, 2DHG holes can be effectively discharged by this configuration. In the nitride-based compound semiconductor device according to the present invention, the channel layer 18 is an undoped layer, so that current collapse can be suppressed and the short-circuit tolerance can be maintained while maintaining forward characteristics and reverse characteristics.

For example, in the conventional nitride-based compound semiconductor device shown in FIG. 11, in the device having an on-resistance of 5 mΩcm ² , the increase rate of the on-resistance as a current collapse deteriorated to 1.5 times or more at 600 V. It was confirmed that the field effect transistor 10 of this example was improved to 1.1 times or less. Further, since the discharge of holes can be improved, the load short-circuit withstand capability is also improved, and the conventional nitride-based compound semiconductor device shown in FIG. Then, the withstand voltage at 100 A / cm ² and 600 V was improved to 700 mJ.

Also, as a normally-off type element, a hybrid MOSHFET structure is desirable. In this structure, 2DEG carriers under the gate electrode 36 can be removed by recess etching of the gate electrode 36. This etching and design conditions have the effect that they can be designed independently without affecting the design parameters of 2DHG. Of course, it is needless to say that the present invention can also be applied to a method of forming the dielectric film 26, which is a gate insulating film, without removing the barrier layer 20 and leaving several nm.

Therefore, the nitride-based compound semiconductor device according to the present invention can be applied to a high voltage inverter or converter. From the above, it is possible to realize a GaN field effect transistor having a high breakdown voltage and high reliability.

It should be noted that the shape of the opening 40 shown in each of the above embodiments is a specific example, and is not limited to this. As described above, in the nitride-based compound semiconductor device according to the present invention, if at least one opening is provided, ohmic contact can be easily obtained compared to the case where no opening is provided. The effect that it can do is acquired. For example, the opening 40 may have other shapes such as a circular shape instead of the stripe shape. In the second embodiment, the opening 40 is formed so that the areas of the undoped cap layer 22 and the p-type cap layer 24 are reduced from the gate electrode 36 side toward the drain electrode 32 side. Absent. For example, the opening 40 may be formed to have the same area (alphabet “E” shape) toward the drain side. Further, the undoped cap layer 22 and the p-type cap layer 24 may be formed in stripes with a plurality of intervals (corresponding to the opening 40). Needless to say, various modifications can be made without departing from the gist of the present invention.

In each of the above embodiments, the case where the substrate 12 is a silicon substrate has been exemplified. However, any substrate capable of crystal growth of GaN such as a SiC substrate other than a silicon substrate, a sapphire substrate, a GaN substrate, an MgO substrate, and a ZnO substrate can be used. Needless to say, the elements on the substrate also hold true.

In addition, the configuration and manufacturing method of the nitride-based compound semiconductor device described in each of the above-described embodiments are examples, and it can be changed according to the situation without departing from the gist of the present invention. Not too long.

The entire disclosure of the Japanese application 2012-054985 is incorporated herein by reference.

All documents, patent applications, and technical standards mentioned in this specification are to the same extent as if each individual document, patent application, and technical standard were specifically and individually stated to be incorporated by reference, Incorporated herein by reference.

Claims (15)

A first nitride-based semiconductor layer having an electron transit layer, an electron supply layer, and a two-dimensional electron gas layer formed at an interface between the electron transit layer and the electron supply layer;
A second nitride based semiconductor layer formed on the first nitride based semiconductor layer and having a two-dimensional hole gas layer formed at the interface of the polarization junction;
A base electrode formed in contact with the second nitride-based semiconductor layer and in electrical contact with the two-dimensional hole gas layer in which a surface having an orientation different from that of at least one epitaxial growth surface is exposed;
A nitride compound semiconductor device comprising: The nitride-based compound semiconductor element according to claim 1, wherein the second nitride-based semiconductor layer has an opening that contacts the two-dimensional hole gas layer. The nitride-based compound semiconductor device according to claim 2, wherein the opening reaches a surface of the electron supply layer of the first nitride-based semiconductor layer. The angle formed between the side surface and the bottom surface of the opening is 45 ° or more and 175 ° or less, and the base electrode is formed to cover the opening. The nitride-based compound semiconductor device according to claim 2 or 3. The angle formed between the side surface and the bottom surface of the opening is 90 ° or more and 150 ° or less, and the base electrode is formed to cover the opening. The nitride-based compound semiconductor device according to claim 2 or 3. A gate electrode;
A drain electrode;
A source electrode;
An electric field relaxation layer including the second nitride-based semiconductor layer in a region between the gate electrode and the drain electrode;
The nitride-based compound semiconductor device according to claim 1, wherein the nitride-based compound semiconductor device is a field effect transistor that normally operates. A gate electrode;
A drain electrode;
A source electrode;
An electric field relaxation layer including the second nitride-based semiconductor layer in a region between the gate electrode and the drain electrode;
The nitride-based compound semiconductor device according to claim 1, wherein the nitride-based compound semiconductor device is a field effect transistor that normally operates. The nitride compound semiconductor element according to claim 6 or 7, wherein an average concentration of the two-dimensional hole gas layer in the electric field relaxation layer decreases from the gate electrode toward the drain electrode. The electric field relaxation layer includes a nitride-based semiconductor layer having p-type carriers, and is arranged so as to reduce an area in contact with the first nitride-based semiconductor layer from the gate electrode toward the drain electrode. The nitride compound semiconductor device according to claim 8. An anode electrode;
A cathode electrode;
An electric field relaxation layer including the second nitride-based semiconductor layer in a region between the anode electrode and the cathode electrode;
The nitride-based compound semiconductor device according to claim 1, wherein the nitride-based compound semiconductor device is a diode comprising: The electric field relaxation layer includes a nitride-based semiconductor layer having p-type carriers, and is arranged so as to reduce an area in contact with the first nitride-based semiconductor layer from the anode electrode toward the cathode electrode. The nitride compound semiconductor device according to claim 10. The nitride compound semiconductor element according to any one of claims 6 to 9, wherein the source electrode or the gate electrode and the base electrode have the same potential. The nitride compound semiconductor device according to claim 10 or 11, wherein the anode electrode and the base electrode have the same potential. The nitride-based compound semiconductor device according to claim 12, wherein the gate electrode is formed so as to cover at least a part of the base electrode. The nitride-based compound semiconductor element according to claim 13, wherein the anode electrode is formed so as to cover at least a part of the base electrode.

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