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WO2013115672A1 - Procédé de traitement d'informations et de calcul et dispositif "généralisateur" pour mettre en oeuvre ce procédé - Google Patents

Procédé de traitement d'informations et de calcul et dispositif "généralisateur" pour mettre en oeuvre ce procédé Download PDF

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Publication number
WO2013115672A1
WO2013115672A1 PCT/RU2012/000092 RU2012000092W WO2013115672A1 WO 2013115672 A1 WO2013115672 A1 WO 2013115672A1 RU 2012000092 W RU2012000092 W RU 2012000092W WO 2013115672 A1 WO2013115672 A1 WO 2013115672A1
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WO
WIPO (PCT)
Prior art keywords
signal processing
triangle
matrix device
base
structural elements
Prior art date
Application number
PCT/RU2012/000092
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English (en)
Russian (ru)
Inventor
Петр Петрович КУВЫРКОВ
Андрей Александрович МАКАРОВ
Original Assignee
Kuvyrkov Petr Petrovich
Makarov Andrey Aleksandrovich
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kuvyrkov Petr Petrovich, Makarov Andrey Aleksandrovich filed Critical Kuvyrkov Petr Petrovich
Publication of WO2013115672A1 publication Critical patent/WO2013115672A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17362—Indirect interconnection networks hierarchical topologies

Definitions

  • N m is the record of the number N in the t-th number system, represented by a sequence of digits or a code (K p _ x , K p _ 2 , ..., K ..., K x , K 0 ) t
  • an octal number system is also used, converting binary numbers to octal and then to decimal:
  • a computing device including a series-connected block of triggers of the input register; matrix device, the intersection of the tires of which form the nodes of the matrix lattice; block of logical elements, mainly logical elements "AND"; block of triggers of the output register.
  • the spatial arrangement of the tires of the aforementioned matrix device corresponds to the arrangement of the sides of at least one right-angled triangle and is selected based on the geometric model of signal processing, which is a set of graphs forming at least one right-angled triangle.
  • Rectangular triangles of the geometric model of signal processing are arranged in a hierarchical order, and the vertices of the right angles of the triangles, which are ranked lower in the hierarchy, are adjacent to the vertices of the acute angles of the base of the rectangular triangle, which occupies a higher rank in the hierarchy.
  • a right-angled triangle of the geometric model of signal processing can be divided into three parts by lines emanating from the vertices of the corners of the triangle.
  • FIG. 2, 3 An example of a geometric model for converting a number expressed in a binary number system to a number expressed in a decimal number system.
  • the proposed computing device (Fig. 1) consists of series-connected: a block of triggers of the input register; matrix device, the intersection of the tires of which form the nodes of the matrix lattice; block of logical elements, mainly logical elements "AND"; block triggers the output register.
  • the spatial arrangement of the tires of the aforementioned matrix device corresponds to the arrangement of the sides of rectangular triangles and is selected based on the geometric model of signal processing, consisting of a set of graphs forming a hierarchical order of rectangular triangles (Fig. 2, 3).
  • the degree of generalization and reverse generalization is determined through the value of the height of the triangle and the number of heterogeneous structural elements at the base of the triangle.
  • the message expressed in the original positional number system, is converted into the final message expressed in the positional number system with the required base.
  • the number of heterogeneous structural elements reflects the number of elements of the alphabet of the positional number system. Using such a transformation, integration, logical operations, etc. can be used to perform arithmetic operations.
  • the geometric model of signal processing is a hierarchical order of right triangles. Smaller triangles are hierarchically arranged in accordance with the presence of lower levels of generalization; each of the triangles can be further divided by lines or rays emanating from its center into three component parts (Figs. 2, 3). In the corners of the base of the triangles are messages of a lower level of generalization, at their apex are messages of a higher level of generalization. Correspondingly, the edges of the triangles at the convergence represent the generalization process, and with the reverse movement, branching, the reverse generalization (degeneralization) process is displayed.
  • the directions of the spatial arrangement of the buses of the matrix of the computing device are determined by the directions of the spatial arrangement of the sides or edges of the right-angled triangle of the geometric model emanating from its vertex Sf to the angles Sfj ⁇ l and S ⁇ ⁇ l -
  • the directions of the spatial arrangement of the sides to the angles S ⁇ ⁇ l and S ⁇ "1 determine respectively the zero and unit signs of spatial matrix tire directions: the zero sign of the tires is determined by their parallelism to the side of the triangle Sf S ⁇ ⁇ l , single - Sfi Sj 7 "1 -
  • the outputs of the triggers of the input register of the generator will be connected to the inputs of the buses of its matrix device as follows: the zero outputs of the triggers To and ⁇ are connected respectively to the inputs of the buses of the zero and single signs with even serial numbers, the individual outputs of the triggers T 0 and ⁇ are connected respectively, with bus inputs of zero and single signs with odd serial numbers; the zero outputs of the triggers T 2 and T 3 are connected respectively to the inputs of the common buses of the zero and single signs of the zero and first serial numbers, the first outputs of the triggers T 2 and T 3 are connected to the inputs of the common buses of the zero and single signs of the second and third serial numbers.
  • the results of calculating the addition and subtraction of binary numbers are obtained directly in decimal form, performing bitwise decimal addition and subtraction of their components, followed by conversion in accordance with the proposed method into decimal form with parallel calculations and a significantly smaller number of clock cycles and computational operations:

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Image Generation (AREA)
  • Complex Calculations (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)

Abstract

L'invention proposée concerne le domaine de l'informatique et des équipements de calcul et peut s'utiliser dans des technologies nécessitant le traitement de signaux, par exemple, des technologies de traitement et de conversion de messages de données; elle permet d'augmenter la vitesse de traitement des signaux tout en préservant la fiabilité des résultats du traitement. Le procédé de calcul proposé prévoit le traitement parallèle et séquentiel du signal dans une unité de déclencheurs du registre d'entrée; dans un dispositif matriciel; dans une unité d'éléments logiques, prioritairement d'éléments logiques "ET"; et dans une unité de déclencheurs du registre de sortie. Le traitement du signal dans le dispositif matriciel s'effectue conformément au modèle géométrique de traitement de signal qui se présente comme un ensemble de graphes formant au moins un triangle rectangle. Pour mettre en œuvre ce procédé, on propose un dispositif de calcul dans lequel la disposition spatiale des bus du dispositif matriciel correspond au moins à la disposition des côtés d'au moins un triangle rectangle et est sélectionnée sur la base du modèle géométrique susmentionné de traitement du signal.
PCT/RU2012/000092 2012-01-31 2012-02-13 Procédé de traitement d'informations et de calcul et dispositif "généralisateur" pour mettre en oeuvre ce procédé WO2013115672A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
RU2012103075 2012-01-31
RU2012103075/08A RU2494445C1 (ru) 2012-01-31 2012-01-31 Способ обработки информации и вычисления кувыркова (варианты) и устройство "генерализатор" для осуществления способа

Publications (1)

Publication Number Publication Date
WO2013115672A1 true WO2013115672A1 (fr) 2013-08-08

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RU (1) RU2494445C1 (fr)
WO (1) WO2013115672A1 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10784989B2 (en) 2018-03-14 2020-09-22 Cypress Semiconductor Corporation Bit error correction for wireless retransmission communications systems

Citations (4)

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Publication number Priority date Publication date Assignee Title
SU1695319A1 (ru) * 1989-09-25 1991-11-30 Физико-механический институт им.Г.В.Карпенко Матричное вычислительное устройство
WO2007018066A1 (fr) * 2005-08-10 2007-02-15 Mitsubishi Electric Corporation Procédé de génération de matrice de test, procédé de codage, procédé de décodage, appareil de communication, système de communication, codeur et décodeur
RU2371766C1 (ru) * 2008-04-14 2009-10-27 Государственное образовательное учреждение высшего профессионального образования Курский государственный технический университет Устройство для исследования графов
RU2379749C1 (ru) * 2008-08-06 2010-01-20 Государственное образовательное учреждение высшего профессионального образования Курский государственный технический университет Устройство для подсчета минимального значения интенсивности размещения в системах с древовидной организацией

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU868747A1 (ru) * 1979-08-30 1981-09-30 Пензенский Завод-Втуз При Заводе Вэм Преобразователь двоичного кода в дес тичный
JPS5858645A (ja) * 1981-09-30 1983-04-07 Fujitsu Ltd １０進数と２進数の変換方式

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU1695319A1 (ru) * 1989-09-25 1991-11-30 Физико-механический институт им.Г.В.Карпенко Матричное вычислительное устройство
WO2007018066A1 (fr) * 2005-08-10 2007-02-15 Mitsubishi Electric Corporation Procédé de génération de matrice de test, procédé de codage, procédé de décodage, appareil de communication, système de communication, codeur et décodeur
RU2371766C1 (ru) * 2008-04-14 2009-10-27 Государственное образовательное учреждение высшего профессионального образования Курский государственный технический университет Устройство для исследования графов
RU2379749C1 (ru) * 2008-08-06 2010-01-20 Государственное образовательное учреждение высшего профессионального образования Курский государственный технический университет Устройство для подсчета минимального значения интенсивности размещения в системах с древовидной организацией

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RU2012103075A (ru) 2013-08-10
RU2494445C1 (ru) 2013-09-27

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