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WO2013108477A1 - Dispositif à semi-conducteur et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2013108477A1
WO2013108477A1 PCT/JP2012/079835 JP2012079835W WO2013108477A1 WO 2013108477 A1 WO2013108477 A1 WO 2013108477A1 JP 2012079835 W JP2012079835 W JP 2012079835W WO 2013108477 A1 WO2013108477 A1 WO 2013108477A1
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WO
WIPO (PCT)
Prior art keywords
layer
conductive layer
semiconductor device
coil antenna
conductive
Prior art date
Application number
PCT/JP2012/079835
Other languages
English (en)
Japanese (ja)
Inventor
裕紀 若菜
内山　博幸
哲史 河村
太亮 尾崎
孝徳 山添
Original Assignee
株式会社日立製作所
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Filing date
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Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Publication of WO2013108477A1 publication Critical patent/WO2013108477A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2208—Supports; Mounting means by structural association with other equipment or articles associated with components used in interrogation type services, i.e. in systems for information exchange between an interrogator/reader and a tag/transponder, e.g. in Radio Frequency Identification [RFID] systems
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/40—Radiating elements coated with or embedded in protective material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q7/00—Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a technique effectively applied to a semiconductor device including a coil antenna and a method for manufacturing the same.
  • TFT thin film transistor
  • RFID Radio Frequency IDentification
  • semiconductor materials and transistor structures that realize IC tags and new functions of IC tags that are difficult to achieve with conventional silicon-based MOSFETs. For example, by using a thin film transistor, it is possible to realize a thin IC tag that has been impossible in the past.
  • a non-contact electronic device equipped with an antenna and a semiconductor integrated circuit device a so-called IC tag
  • IC tag enables individual identification by wireless communication, and is used for production and management of identification objects.
  • the IC tag exchanges information and power with the reader / writer device, transmits the data held by the IC tag to the reader / writer device, and transmits the data transmitted from the reader / writer device to the IC Implement various functions such as holding tags.
  • the antenna and the IC chip are formed by different processes and mounted in a later process. For this reason, for example, it has been difficult to realize an IC tag with a thickness of about several ⁇ m, which is difficult to detect unevenness with a human fingertip. Further, when the mounting yield is poor, the cost is increased. In addition, for example, when an IC tag is attached to paper or the like, if a large number of papers to which IC tags are attached are stacked, the thickness may increase significantly only by the IC chip portion. In addition, when an IC tag is created on the back surface of a seal or the like, the shape of the IC chip or antenna may appear as a step on the surface portion of the seal.
  • an IC part using a TFT and an antenna are formed on the same substrate by a thin film process.
  • the mounting process can be omitted, the yield can be improved and the manufacturing cost can be reduced.
  • the entire IC tag can be thinned. For this reason, even when the IC tag is affixed to paper or the like, or even when the IC tag is created on the back surface of a sticker or the like, it is possible to prevent the protrusion from being felt.
  • the antenna When the IC part and the antenna are formed on the same substrate, it is necessary to form the antenna as a coil antenna and connect the coil antenna to the IC part on the substrate.
  • an overlapping portion where the two antenna layers overlap through an insulating film between layers is generated, and a capacitive component is generated at the overlapping portion. This capacitance component operates as a capacitance parasitic on the coil antenna.
  • the coil antenna formation process is performed in alignment with the IC part formation process (for example, TFT formation process).
  • the film thickness of the insulating film between the antenna layers is reduced. For this reason, since the capacity increases as the capacity insulating film between the electrodes becomes thinner, the capacity component generated in the overlapping portion increases, which may adversely affect the performance (antenna characteristics) of transmitting and receiving signals with the coil antenna. This deteriorates the performance of a semiconductor device including a coil antenna such as an IC tag.
  • Patent Document 1 discloses a technique for forming an IC portion and a coil antenna on the same substrate, although not an IC tag.
  • a technique for reducing the capacitance component of the overlapping portion using an interlayer film is disclosed.
  • the thickness of each layer is limited. If the interlayer insulating film of the coil antenna is made thin, a large capacity is generated at the intersection of the coil antenna, and the performance of transmitting and receiving signals with the coil antenna Will fall.
  • an interlayer insulating film (8) having a thickness of 2.5 ⁇ m is introduced at the intersection to reduce the large capacitance generated at the intersection of the antennas, and the width of the antenna (10) is narrowed.
  • an antenna device is formed.
  • the countermeasure of Patent Document 1 is insufficient, and the performance of transmitting and receiving signals with the coil antenna is reduced due to the capacitance generated at the intersection of the coil antenna.
  • An object of the present invention is to provide a technique capable of improving the performance of a semiconductor device.
  • a semiconductor device is a semiconductor device in which an IC unit and a coil antenna connected to the IC unit are formed on the same substrate, and at the intersection of the coil antennas, The widths of both the upper conductive layer and the lower conductive layer are reduced.
  • the method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device in which an IC portion having a thin film transistor and a coil antenna connected to the IC portion are formed on the same substrate. At this time, the width of both the upper conductive layer and the lower conductive layer of the coil antenna is reduced at the intersection of the coil antennas. Further, an interlayer insulating film between the upper conductive layer and the lower conductive layer of the coil antenna is formed of the same insulating layer as the gate insulating film or protective film of the thin film transistor.
  • the performance of the semiconductor device can be improved.
  • 1 is a partially enlarged plan view of a semiconductor device according to an embodiment of the present invention. It is principal part sectional drawing of the semiconductor device of one embodiment of this invention. It is principal part sectional drawing of the semiconductor device of one embodiment of this invention. It is principal part sectional drawing of the semiconductor device of one embodiment of this invention. It is principal part sectional drawing of the semiconductor device of one embodiment of this invention. It is a principal part enlarged plan view which shows the cross
  • FIG. 26 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 25; FIG.
  • FIG. 27 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 26;
  • FIG. 28 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 27;
  • FIG. 29 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 28;
  • FIG. 30 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 29; It is a graph which shows the characteristic of a coil antenna. It is a graph which shows the characteristic of a coil antenna. It is a graph which shows the characteristic of a coil antenna. It is a graph which shows the characteristic of a coil antenna. It is a graph which shows the characteristic of a coil antenna. It is principal part sectional drawing in the manufacturing process of the semiconductor device of other embodiment of this invention.
  • FIG. 28 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 27
  • FIG. 28 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG.
  • FIG. 36 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 35;
  • FIG. 37 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 36;
  • FIG. 38 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 37;
  • FIG. 39 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 38;
  • FIG. 40 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 39; It is principal part sectional drawing in the manufacturing process of the semiconductor device of other embodiment of this invention.
  • FIG. 42 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 41; It is principal part sectional drawing in the manufacturing process of the semiconductor device of other embodiment of this invention.
  • FIG. 45 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 44;
  • FIG. 46 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 45;
  • FIG. 47 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 46;
  • hatching may be omitted even in a cross-sectional view in order to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.
  • the semiconductor device of this embodiment is a semiconductor device (antenna integrated semiconductor device) provided with an antenna (coil antenna) for performing transmission (transmission, reception, or both) of power or signals, but the same substrate.
  • An antenna (coil antenna) and a circuit (semiconductor integrated circuit) connected to the antenna are formed on the top.
  • FIG. 1 is a circuit diagram showing a typical example of a communication system between an IC tag TG1 and a reader / writer device RW1.
  • the IC tag (RFID device) TG1 includes a coil antenna A1
  • the reader / writer device RW1 includes a coil antenna A2
  • the IC tag TG1 and the reader / writer device RW1 include a coil antenna. They are connected by magnetic field coupling (magnetic flux coupling) via A1 and coil antenna A2.
  • a coil antenna ANT described later corresponds to the coil antenna A1.
  • the IC tag TG1 also includes a resonance capacitor (capacitor) C1 and an IC unit (integrated circuit unit, circuit unit) 11a.
  • the coil antenna A1 is connected to the IC unit 11a via the resonance capacitor C1. Are connected at terminals LA and LB.
  • one end of the coil antenna A1 is connected to the terminal LA of the IC part 11a, and the other end of the coil antenna A1 is connected to the terminal LB of the IC part 11a.
  • one electrode of the resonance capacitor C1 is connected to the terminal LA, and the other electrode of the resonance capacitor C1 is connected to the terminal LB. Since the IC tag TG1 (coil antenna A1) and the reader / writer device RW1 (coil antenna A2) are magnetically coupled, the high-frequency signal generated by the reader / writer device RW1 is changed to IC It is transmitted to the tag TG1.
  • the IC tag TG1 can exchange signals (information) or power (send / receive and transmit) with the reader / writer device RW1 via the coil antennas A1 and A2. For example, data can be transmitted from the reader / writer device RW1 to the IC tag TG1 and held in the IC tag TG1, or data held by the IC tag TG1 can be transmitted to the reader / writer device RW1.
  • FIG. 2 is a circuit diagram showing a typical example of the circuit configuration of the IC section 11a of the IC tag TG1.
  • the IC unit 11a has a rectifying element composed of a transistor T1 and a smoothing capacitor C2 connected to terminals (antenna terminals) LA and LB, and the reader / writer device.
  • the high-frequency signal transmitted from RW1 (that is, the high-frequency signal received by the coil antenna A1) is rectified and smoothed by the transistor T1 and the smoothing capacitor C2, and the power supply voltage VDD is generated.
  • the IC unit 11a further includes a logic circuit unit L1 that operates with the power supply voltage VDD and a load modulation transistor T2 that performs a switching operation with a modulation signal (MOD) from the logic circuit unit L1.
  • the logic circuit unit L1 includes a plurality of semiconductor elements (transistors and the like). In the return operation from the IC tag TG1 to the reader / writer device RW1, the power consumption of the IC unit 11a is changed by switching the load modulation transistor T2, and the change is transmitted by the mutual inductance.
  • the voltage between the terminal (antenna terminal) LA and the terminal (antenna terminal) LB be equal to or higher than the minimum operating voltage.
  • the voltage between the terminal LA and the terminal LB is the power consumption of the IC unit 11a, the transmission power of the reader / writer device RW1, the mutual inductance between the coil antenna A1 and the coil antenna A2, and the resonance frequency / Q value of the coil antenna A1.
  • Etc. the maximum output power of the reader / writer device RW1 is regulated by the Radio Law and the like.
  • the power consumption of the IC unit 11a is reduced and the coil antenna A1 is designed. Is important.
  • FIG. 3 is a plan view schematically showing a configuration example of the semiconductor device (antenna integrated semiconductor device, here, an IC tag) SM1 of the present embodiment.
  • FIG. 4 is a partially enlarged plan view of a region RG1 surrounded by a two-dot chain line in FIG. 5 to 7 are principal part sectional views of the semiconductor device SM1 of the present embodiment.
  • FIG. 5 corresponds to the sectional view taken along the line AA ′ of FIG. 4
  • FIG. 7 corresponds to the cross-sectional view taken along the line ⁇ B ′
  • the semiconductor device SM1 of the present embodiment corresponds to the IC tag TG1 shown in FIG.
  • FIG. 3 is a plan view, the conductive layers ANT1 and ANT2 are hatched for easy viewing of the drawing. Further, cross-sectional views taken along line AA ′ in FIGS. 8, 14, 17 and 22 to be described later are also the same as those in FIG. 5, and BB in FIGS. 8, 14, 17 and 22 to be described later. The sectional view taken along the line 'is also the same as FIG.
  • the semiconductor device SM1 of the present embodiment is an antenna integrated semiconductor device provided with a coil antenna ANT for transmitting power or signals.
  • the semiconductor device SM1 of the present embodiment includes a coil antenna (antenna coil) ANT and an IC unit (integrated circuit unit, circuit unit) in which the coil antenna ANT is connected to the same substrate SUB. ) 11 is formed. That is, the semiconductor device SM1 includes the substrate SUB and the coil antenna ANT and the IC unit 11 formed on the substrate SUB, and the coil antenna ANT is connected to the IC unit 11.
  • the coil antenna ANT corresponds to the coil antenna A1.
  • the IC unit 11 corresponds to a combination of the IC unit 11a and the resonance capacitor C1. That is, the IC section 11 is formed with the resonance capacitor C1 and a circuit corresponding to the IC section 11a shown in FIG. Specifically, in the IC unit 11, the resonance capacitor C1, the smoothing capacitor C2, the transistors T1 and T2, the logic circuit unit L1, and wirings connecting them are formed. Therefore, the IC section 11 includes the resonance capacitor C1, the smoothing capacitor C2, the transistors T1 and T2, and the semiconductor elements (transistors and the like) constituting the logic circuit portion L1. Since the coil antenna ANT and the IC unit 11 are formed on the substrate SUB by a thin film process, TFTs (thin film transistors) constituting the IC unit 11 are also formed on the substrate SUB.
  • the coil antenna ANT is an antenna formed by a coiled (looped) conductor pattern.
  • the coil antenna ANT can also be regarded as a coil (coil pattern) that functions as an antenna.
  • the coil antenna ANT includes a conductive layer (antenna layer, conductor layer, conductor pattern, coil portion) ANT1 and a conductive layer (antenna layer, conductor layer, (Conductor pattern, lead-in wiring portion) ANT2 and contact portions (connection portions) CNT connecting these conductive layers ANT1 and ANT2.
  • the coil antenna ANT is located between the conductive layer ANT1, the conductive layer ANT2 which is a layer above or below the conductive layer ANT1, and the conductive layer ANT1 and the conductive layer ANT2. And a contact portion CNT that electrically connects the two.
  • An insulating layer (here, an interlayer insulating film IL) is interposed between the conductive layer ANT1 and the conductive layer ANT2.
  • the conductive layer ANT1 is a conductor pattern that circulates in a coil shape (loop shape) and functions as an antenna (coil antenna).
  • the conductive layer ANT2 is the inner peripheral side where the IC portion 11 is formed on the outer peripheral end of the conductive layer ANT1. This is a conductor pattern that is drawn into (drawn around).
  • FIGS. 5 to 7 A brief explanation of the cross-sectional structure of the coil antenna ANT is as follows. As shown in FIGS. 5 to 7, a conductive layer ANT2 of the coil antenna ANT is formed on the substrate SUB, and an interlayer insulating film (interlayer insulating layer) IL is formed as an insulating layer on the substrate SUB so as to cover the conductive layer ANT2.
  • the conductive layer ANT1 of the coil antenna ANT is formed on the interlayer insulating film IL, and a protective film (protective layer) PA is formed as an insulating layer on the interlayer insulating film IL so as to cover the conductive layer ANT1.
  • the interlayer insulating film IL is interposed between the conductive layer ANT1 and the conductive layer ANT2, and the conductive layer ANT1 and the conductive layer ANT2 are not connected except for the contact portion CNT.
  • the contact portion CNT is formed of a conductor that fills a contact hole (through hole) CNT1 formed in the interlayer insulating film IL.
  • a part of the conductive layer ANT1 is embedded in the contact hole CNT1 and is in contact with the conductive layer ANT2, thereby forming the contact portion CNT.
  • the upper conductive layer ANT1 and the lower conductive layer ANT2 are electrically connected via the contact portion CNT, and the entire coil antenna ANT is formed.
  • the conductive layer ANT1 is formed above the conductive layer ANT2.
  • the conductive layer ANT2 and the conductive layer ANT2 are interchanged so that the conductive layer ANT2 Can also be formed above the conductive layer ANT1.
  • the conductive layer ANT1 has a longer extension distance than the conductive layer ANT2, it is more preferable to form the conductive layer ANT1 in an upper layer than the conductive layer ANT2, as shown in FIGS. This is because the upper conductive layer is easier to increase the thickness.
  • the thickness of the conductive layer ANT1 is made larger than the thickness of the conductive layer ANT2. This is because the resistance of the entire coil antenna ANT can be reduced by increasing the thickness.
  • a TFT thin film transistor constituting the IC unit 11 is also formed on the substrate SUB on which the coil antenna ANT is formed.
  • This TFT is shown in FIG.
  • the conductive layer ANT2 of the coil antenna ANT may be formed using the same conductive layer as the gate electrode (gate electrode layer GE described later) or the source / drain electrode (source / drain electrode layer SD described later) of the TFT.
  • a new conductive layer can be formed separately from the conductive layer for forming the TFT.
  • the interlayer insulating film IL can be formed by using an insulating film in the same layer as the gate insulating film of the TFT (gate insulating layer GI described later) or a protective film (protective film PA1 described later).
  • a new insulating layer can be used.
  • the conductive layer ANT1 of the coil antenna ANT can be formed using the same conductive layer as the TFT gate electrode (gate electrode layer GE described later) or the source / drain electrode (source / drain electrode layer SD described later).
  • a new conductive layer can be used separately from the conductive layer for forming the TFT. Therefore, the functions of the gate electrode layer GE, the gate insulating layer GI, the source / drain electrode layer SD, and the protective film PA1 are not interpreted as being limited to the above designations.
  • the coil antenna ANT is mainly composed of a conductive layer ANT1, and the conductive layer ANT1 is formed on the substrate SUB so as to circulate in a coil shape (loop shape) in plan view.
  • the plan view refers to a case where the substrate is viewed in a plane parallel to the main surface of the substrate SUB.
  • the number of turns (number of turns) of the conductive layer ANT1 is three turns (three turns).
  • the number of turns (number of turns) is not limited to this.
  • the conductive layer ANT ⁇ b> 2 is formed by drawing the outer peripheral end (end portion on the outer peripheral side) of the conductive layer ANT ⁇ b> 1 to the inner peripheral side where the IC portion 11 is formed (by routing) the IC portion. 11 and the conductive layer ANT2 needs to be a layer different from the conductive layer ANT1. That is, if the coil antenna ANT is formed only of the same conductive layer, it is difficult to connect both ends of the coil antenna ANT to the IC portion 11 (terminals corresponding to the terminals LA and LB).
  • both ends of the coil antenna ANT are formed. It becomes easy to connect the end portions of the layers ANT1 and ANT2) to the IC portion 11 (terminals corresponding to the terminals LA and LB).
  • one end (end on the inner peripheral side) of the conductive layer ANT1 is connected to the IC unit 11 (a terminal corresponding to one of the terminal LA and the terminal LB), and the other end of the conductive layer ANT1 ( The outer peripheral end) is connected to one end of the conductive layer ANT2 via the contact portion CNT.
  • the other end of the conductive layer ANT2 is connected to the IC unit 11 (a terminal corresponding to the other of the terminal LA and the terminal LB).
  • the coil antenna ANT formed by the conductive layers ANT1 and ANT2 and the contact part CNT can be connected to the IC part 11.
  • the conductive layer ANT1 can be regarded as a coil antenna ANT
  • the conductive layer ANT2 can be regarded as a wiring (wiring that connects the outer peripheral end of the conductive layer ANT1 and the IC portion 11).
  • the conductive layer ANT2 is different from the conductive layer ANT1 (that is, the conductive layer ANT2 is a layer above or below the conductive layer ANT1) when the conductive layer ANT2 crosses the conductive layer ANT1 in plan view. This is to prevent the conductive layer ANT2 from contacting the conductive layer ANT1.
  • the conductive layer ANT2 can cross the conductive layer ANT1 in plan view without contacting the conductive layer ANT2 and the conductive layer ANT1, so that the coil antenna ANT Both ends can be easily connected to the IC unit 11.
  • overlapping portion OVL a portion where the conductive layer ANT2 and the conductive layer ANT1 overlap in plan view.
  • the conductive layer ANT1 and the conductive layer ANT2 face each other in the thickness direction (a direction substantially perpendicular to the main surface of the substrate SUB) via the interlayer insulating film IL, and the capacitance using the conductive layers ANT1 and ANT2 as electrodes. Ingredients are generated.
  • a portion where the conductive layer ANT1 and the conductive layer ANT2 overlap in plan view is referred to as an overlapping portion (overlap portion) OVL.
  • the conductive layer ANT1 and the conductive layer ANT2 have an overlapping portion OVL that overlaps with the interlayer insulating film IL in a direction substantially perpendicular to the main surface of the substrate SUB.
  • the overlapping portion OVL is generated at one or a plurality of locations depending on the number of turns of the coil antenna ANT.
  • the overlapping portion OVL is a portion (region) where the conductive layer ANT1 and the conductive layer ANT2 of the coil antenna ANT intersect in plan view, and thus can be regarded as a crossing portion of the coil antenna ANT.
  • FIG. 8 is an essential part enlarged plan view showing the intersection (overlapping portion OVL) of the coil antenna ANT and its vicinity region in the semiconductor device SM1 of the present embodiment, and is a region surrounded by a two-dot chain line in FIG. This corresponds to a partially enlarged plan view of RG2.
  • 9 is a plan view showing only the conductive layer ANT2 with the conductive layer ANT1 omitted from FIG. 8
  • FIG. 10 is a plan view showing only the conductive layer ANT1 with the conductive layer ANT2 omitted from FIG. is there.
  • FIG. 11 is an enlarged plan view of a main part showing the crossing portion of the coil antenna of the first comparative example and its vicinity region, and FIG.
  • FIG. 12 is a main portion showing the crossing portion of the coil antenna of the second comparative example and its vicinity region.
  • FIG. 13 is an enlarged plan view, and FIG. 13 is an enlarged plan view of a main part showing an intersecting portion of the coil antenna of the third comparative example and its vicinity region. 11 to 13 all show the same region as FIG. 8 to 13 are plan views, but each conductive layer is hatched for easy viewing of the drawings.
  • the conductive layer ANT101 shown in the first comparative example of FIG. 11, the conductive layer ANT201 shown in the second comparative example of FIG. 12, and the conductive layer ANT301 shown in the third comparative example of FIG. This corresponds to the layer ANT1.
  • the conductive layers ANT101 and ANT301 are different from the conductive layer ANT1 of this embodiment in the shape of the intersection (overlapping portion OVL) of the coil antenna and the vicinity thereof.
  • the conductive layers ANT102, ANT202, and ANT302 are different from the conductive layer ANT2 of the present embodiment in the shape of the intersection (overlapping portion OVL) of the coil antenna and the vicinity thereof.
  • the width of the conductive layers ANT1, ANT2, ANT101, ANT102, ANT201, ANT202, ANT301, and ANT302 of the coil antenna corresponds to the extending direction of the conductive layer (the extending direction substantially corresponds to the direction of current flow in the coil antenna). Corresponds to the width (dimension) in the direction perpendicular to In addition, the widths of the conductive layers ANT1, ANT2, ANT101, ANT102, ANT201, ANT202, ANT301, and ANT302 of the coil antenna are substantially perpendicular to the thickness of the conductive layer.
  • the width of the conductive layers ANT1, ANT2, ANT101, ANT102, ANT201, ANT202, ANT301, and ANT302 of the coil antenna may vary slightly due to the formation process of the conductive layer, etc. In that case, it shall be represented by an average value. Accordingly, the widths W1, W3, W101, W103, W201, W203, W301, and W303 of the conductive layers ANT1, ANT2, ANT101, ANT102, ANT201, ANT301, and ANT302 in the overlapping portions OVL, OVL101, OVL201, and OVL301 are overlapped. This corresponds to the width of the conductive layer in the portion (average value when there is variation).
  • the widths W2, W4, W102, W104, W202, W204, W302, and W304 of the conductive layers ANT1, ANT2, ANT101, ANT102, ANT201, ANT202, ANT301, and ANT302 in the portions other than the overlapping portions OVL, OVL101, OVL201, and OVL301 are This corresponds to the width (average value if there is variation) of the conductive layer in a section where the conductive layer is continuously present (excluding the overlapping portion).
  • the width of the conductive layer ANT102 is substantially uniform, and the width W103 of the conductive layer ANT102 at the crossing portion (overlapping portion OVL101) of the coil antenna is the other portion (overlapping portion).
  • the conductive layer ANT202 is the same as the conductive layer ANT102 of the first comparative example of FIG. 11, and the width of the conductive layer ANT202 is substantially uniform.
  • W203 W204
  • the width of the conductive layer ANT201 is not the same at the crossing portion (overlapping portion OVL201) of the coil antenna and other portions, and the conductive layer at the crossing portion (overlapping portion OVL201).
  • the width W201 of the ANT201 is smaller than the width W202 of the conductive layer ANT201 in other portions (portions other than the overlapping portion OVL201) (W201 ⁇ W202).
  • the width of the conductive layer ANT302 is not the same at the crossing portion (overlapping portion OVL301) of the coil antenna and other portions, and the conductive layer at the crossing portion (overlapping portion OVL301).
  • the width W303 of the ANT302 is smaller than the width W304 of the conductive layer ANT302 in other portions (portions other than the overlapping portion OVL301) (W303 ⁇ W304).
  • the overlapping portions of the conductive layers ANT201 and ANT301 and the conductive layers ANT202 and ANT302 are compared with the case of the first comparative example in FIG.
  • the areas of the OVL 201 and OVL 301 can be reduced, and the capacity component generated in the overlapping portions OVL 201 and OVL 301 can be reduced.
  • a semiconductor device such as an IC tag
  • the capacitance component generated at (the overlapping portion of the two conductive layers constituting the coil antenna).
  • the insulating layer (corresponding to the interlayer insulating film IL) interposed between the conductive layers ANT201 and ANT301 and the conductive layers ANT202 and ANT302 is thin, the capacitance component generated in the overlapping portions OVL201 and OVL301. As this increases, further measures are required.
  • the width of the conductive layer ANT1 is not the same in the overlapping portion OVL and the other portions, and the width W1 of the conductive layer ANT1 in the overlapping portion OVL is: It is smaller than the width W2 of the conductive layer ANT1 in other portions (portions other than the overlapping portion OVL) (W1 ⁇ W2).
  • the width of the conductive layer ANT2 is not the same between the overlapping portion OVL and the other portion, and the width W3 of the conductive layer ANT2 in the overlapping portion OVL is the width of the conductive layer ANT2 in the other portion (a portion other than the overlapping portion OVL).
  • W4 W3 ⁇ W4. That is, for both the conductive layer ANT1 and the conductive layer ANT2, the width (W1, W3) is reduced at the overlapping portion OVL, and the width (W2, W4) is increased at other portions (portions other than the overlapping portion OVL). Yes. In other words, the width (W1, W3) of both the conductive layer ANT1 and the conductive layer ANT2 is locally reduced at a portion where the conductive layer ANT1 and the conductive layer ANT2 intersect in plan view.
  • the conductive layer ANT1 and the conductive layer ANT2 are both provided with a portion where the width is locally reduced, and the conductive layer ANT1 and the conductive layer ANT2 intersect each other in plan view at the portion where the width is reduced. Yes.
  • the area of the overlapping portion OVL can be reduced while securing the widths (W2, W4) of the conductive layers ANT1, ANT2 in the portion other than the overlapping portion OVL.
  • the area of the overlapping portion OVL between the conductive layer ANT1 and the conductive layer ANT2 can be reduced. For this reason, the performance of the semiconductor device SM1 (IC tag or the like) including the coil antenna ANT can be further improved.
  • the entire width of the conductive layers ANT1 and ANT2 is not reduced, but a portion where the conductive layers ANT1 and ANT2 intersect in plan view
  • the widths (W1, W3) of both the conductive layer ANT1 and the conductive layer ANT2 are reduced.
  • the area of the overlapping portion OVL can be reduced without reducing the widths (W2, W4) of the conductive layers ANT1 and ANT2 in the portion other than the overlapping portion OVL, so that the resistance of the coil antenna ANT increases. It is possible to reduce the area of the overlapping portion OVL while suppressing.
  • this embodiment compares the second comparative example of FIG. 12 and the above diagram as compared with the case where the areas of the overlapping portions OVL, OVL201, and OVL301 are the same (that is, the capacities of the overlapping portions are the same). Compared to the 13th comparative example, the resistance of the coil antenna can be reduced.
  • the widths W1 and W3 of the conductive layers ANT1 and ANT2 of the present embodiment can be made considerably larger than the widths W201 and W303 if the areas of the overlapping portions OVL, OVL201, and OVL301 are the same. It is. For this reason, in the present embodiment, compared with the second comparative example of FIG. 12 and the third comparative example of FIG. 13, the capacitance of the crossing portion (overlapping portion OVL) of the coil antenna is reduced and the resistance of the coil antenna is reduced. It is advantageous both in terms of reduction.
  • the manufacturing yield may be reduced.
  • the widths W201 and W303 are made too thin, and the manufacturing is performed. Yield may be reduced.
  • the widths W1 and W3 of the conductive layers ANT1 and ANT2 are set to be equal to or larger than the manufacturing limit, the capacity of the intersection (overlapping portion OVL) of the coil antenna can be efficiently reduced. The production yield can be improved.
  • FIGS. 8 to 10 Next, the configuration of FIGS. 8 to 10 will be described in more detail.
  • the conductive layer ANT1 has a portion with a large width (a portion with a constant width of W2) on both sides of a portion with a small width (a portion with a constant width of W1).
  • the conductive layer ANT2 has a portion with a large width (a portion with a constant width of W4) on both sides of a portion with a narrow width (a portion with a constant width of W3).
  • a portion where the width of the conductive layer ANT1 is narrow (a portion where the width is constant at W1) and a portion where the width of the conductive layer ANT2 is thin (a portion where the width is constant at W3) are in plan view.
  • the intersection OVL between the conductive layer ANT1 and the conductive layer ANT2 is generated so as to intersect.
  • the conductive layer ANT1 has a slightly narrower portion (a portion having a constant width W1) that is slightly longer than the width W4 of the conductive layer ANT2. Then, the portion where the width of the conductive layer ANT2 is thick (the portion where the width is constant at W4) is brought close to the portion where the width of the conductive layer ANT1 is thin (the portion where the width is constant at W1), and the conductive layer The length of the portion where the width of ANT2 is narrow (the portion where the width is constant at W3) is larger than the width W1 and smaller than the width W2. As a result, the area of the overlapping portion OVL can be reduced, and the resistance of the conductive layers ANT1, ANT2 can be reduced.
  • FIG. 14 is an essential part enlarged plan view showing a crossing portion (overlapping portion OVL) of the coil antenna ANT and its vicinity region in another example (second example) of the semiconductor device SM1 of the present embodiment. 14 corresponds to a partially enlarged plan view of the region RG2 surrounded by the two-dot chain line in FIG. 4 as in FIG. 8, but FIG. 8 is a first example of the present embodiment.
  • FIG. 14 shows a second example of the present embodiment.
  • 15 is a plan view showing only the conductive layer ANT2 with the conductive layer ANT1 omitted from FIG. 14, and
  • FIG. 16 is a plan view showing only the conductive layer ANT1 with the conductive layer ANT2 omitted from FIG. is there.
  • FIG. 17 is an essential part enlarged plan view showing a crossing portion (overlapping portion OVL) of the coil antenna ANT and its vicinity region in another example (third example) of the semiconductor device SM1 of the present embodiment.
  • FIG. 17 corresponds to a partially enlarged plan view of the region RG2 surrounded by the two-dot chain line in FIG. 4 as in FIG. 8, but FIG. 17 is a third example of the present embodiment. is there.
  • 18 is a plan view showing only the conductive layer ANT2 with the conductive layer ANT1 omitted from FIG. 17, and
  • FIG. 19 is a plan view showing only the conductive layer ANT1 with the conductive layer ANT2 omitted from FIG. is there.
  • FIG. 14 to 19 are plan views, but each conductive layer is hatched for easy viewing of the drawings.
  • 20 is a plan view showing four conductive patterns having different planar shapes (pattern shapes)
  • FIG. 21 is a graph showing the resistance of each conductive pattern CDP1, CDP2, CDP3, CDP4 shown in FIG. is there.
  • the horizontal axis of the graph of FIG. 21 corresponds to the frequency
  • the vertical axis of the graph of FIG. 21 corresponds to the resistance of each conductive pattern CDP1, CDP2, CDP3, CDP4 (resistance between the terminals TE1, TE2).
  • the area of the overlapping portion OVL between the conductive layer ANT1 and the conductive layer ANT2 is the same. . That is, the width W1 of the conductive layer ANT1 in the overlapping portion OVL is the same in the first example of FIG. 8, the second example of FIG. 14, and the third example of FIG.
  • the width W3 of the conductive layer ANT2 is the same in the first example of FIG. 8, the second example of FIG. 14, and the third example of FIG.
  • the resistance of the coil antenna ANT is smaller in the third example of FIG. 17 than in the first example of FIG. 8 and the second example of FIG. 14. For the reason, see FIGS. 20 and 21. To explain.
  • a conductive pattern CDP1 shown in FIG. 20A has a planar shape (pattern shape) substantially corresponding to the vicinity of the overlapping portion OVL101 in the conductive layers ANT101 and ANT102 of the first comparative example of FIG. .
  • a conductive pattern CDP2 shown in FIG. 20B is a plane substantially corresponding to the region near the overlapping portion OVL in the conductive layer ANT2 of the first example of FIG. 8 and the conductive layer ANT1 of the second example of FIG. It has a shape (pattern shape).
  • the conductive pattern CDP3 shown in FIG. 20C is substantially equivalent to the region near the overlapping portion OVL in the conductive layer ANT1 of the first example of FIG.
  • the conductive pattern CDP4 shown in FIG. 20D has a planar shape (pattern shape) substantially corresponding to the region near the overlapping portion OVL in the conductive layers ANT1 and ANT2 of the third example of FIG. .
  • the dimensions shown in FIG. 20 are set for simulation for calculating the resistance of each of the conductive patterns CDP1, CDP2, CDP3, and CDP4 (resistance between the terminals TE1 and TE2). That is, the width of the conductive pattern CDP1 in FIG. 20A is set to 0.5 mm, and the width is reduced in the conductive patterns CDP2, CDP3, and CDP4 in FIGS. 20B, 20C, and 20D. The width of the portion that is present is set to 0.03 mm, and the width of the portion that is wider is set to 0.5 mm. Note that the conductive pattern CDP2 in FIG. 20B and the conductive pattern CDP3 in FIG.
  • the conductive pattern CDP2 in FIG. 20B and the conductive pattern CDP4 in FIG. 20D have the same length of the portion having a width of 0.03 mm.
  • each conductive pattern CDP1, CDP2, CDP3, CDP4 in FIG. 20 is shown in the graph of FIG.
  • the conductive pattern CDP1 of FIG. 20A has a constant width of 0.5 mm, and thus has a small resistance.
  • the conductive patterns CDP2, CDP3, and CDP4 in FIGS. 20B, 20C, and 20D have a thin portion with a width of 0.03 mm, so the conductive pattern in FIG. The resistance is larger than that of CDP1.
  • the conductive pattern CDP3 in FIG. 20C has a greater resistance than the conductive pattern CDP2 in FIG. 20B because the length of the portion having a width of 0.03 mm is longer.
  • the resistance of the conductive pattern CDP4 in FIG. 20D is close to the resistance of the conductive pattern CDP2 in FIG. 20B, and is slightly larger than the resistance of the conductive pattern CDP2. Then, the resistance of the conductive pattern CDP4 in FIG. 20D is considerably smaller than the resistance of the conductive pattern CDP3 in FIG.
  • the reason why the resistance does not change so much between the conductive pattern CDP4 in FIG. 20D and the conductive pattern CDP2 in FIG. 20B is as follows. That is, in the conductive pattern CDP2 in FIG. 20B, the region RG3 surrounded by the dotted line marked with RG3 in FIG. 20 hardly contributes as a current path, and there is no region RG3. (Ie, even if the region RG3 is deleted), the resistance of the conductive pattern CDP2 does not change much.
  • the resistance of the conductive pattern CDP4 having a shape similar to that obtained by removing the region RG3 from the conductive pattern CDP2 is not much different from that of the conductive pattern CDP2, and the resistance of the conductive pattern CDP4 is slightly larger than the resistance of the conductive pattern CDP2.
  • the resistance of the conductive pattern CDP4 of FIG. 20D (about 0.15 ⁇ when the value of the graph of FIG. 21 is applied) is the resistance of the conductive pattern CDP2 of FIG. 20B (of the graph of FIG. 21).
  • the value is close to about 0.13 ⁇ when the value is applied, and is considerably lower than the resistance of the conductive pattern CDP3 of FIG. 20C (about 0.44 ⁇ when the value of the graph of FIG. 21 is applied).
  • the conductive pattern CDP3 of FIG. 20C is applied to the planar shape of the conductive layer ANT1 in the region near the overlapping portion OVL, and the planar shape of the conductive layer ANT2 of FIG. ) Conductive pattern CDP2 is applied.
  • the conductive pattern CDP2 of FIG. 20B is applied to the planar shape of the conductive layer ANT1 in the region near the overlapping portion OVL, and the planar shape of the conductive layer ANT2 of FIG.
  • the conductive pattern CDP3 of C) is applied. Therefore, in the first example of FIG. 8 and the second example of FIG.
  • the resistance value of the conductive pattern CDP2 (about 0.13 ⁇ when the value of the graph of FIG. 21 is applied) in the vicinity of the overlapping portion OVL.
  • a resistance value of the conductive pattern CDP3 (approx. 0.44 ⁇ when the value of the graph of FIG. 21 is applied) (approx. 0.57 ⁇ when the value of the graph of FIG. 21 is applied).
  • This total resistance (approximately 0.57 ⁇ ) is a large value mainly due to the resistance value (approximately 0.44 ⁇ ) of the conductive pattern CDP3 in FIG.
  • the conductive pattern CDP4 of FIG. 20D is applied to the planar shape of both the conductive layer ANT1 and the conductive layer ANT2 in the region near the overlapping portion OVL.
  • a resistance graph of FIG. 21
  • This resistance value is approximately equal to the resistance generated in the vicinity of the overlap portion OVL in the first example of FIG. 8 and the second example of FIG. Much smaller than 0.57 ⁇ ).
  • the resistance of the conductive pattern CDP4 in FIG. 20D is close to the resistance of the conductive pattern CDP2 in FIG. 20B, and the conductive pattern CDP4 in FIG. This is because the value is considerably lower than the resistance of the pattern CDP3.
  • the total resistance generated in the conductive layers ANT1 and ANT2 in the region near the overlapping portion OVL is greater in the third example of FIG. 17 than in the first example of FIG. 8 and the second example of FIG. , Get smaller. Therefore, the resistance of the coil antenna ANT is more effective when the third example of FIG. 17 is applied than when the first example of FIG. 8 is applied or when the second example of FIG. 14 is applied. Can be made smaller. Further, the number of intersections between the conductive layer ANT1 and the conductive layer ANT2 (where the overlapping portion OVL is generated) increases as the number of turns of the coil antenna ANT increases, and the resistance components at the intersections are stacked.
  • both the conductive layer ANT1 and the conductive layer ANT2 become smaller (narrower and narrower) as the width (each width of the conductive layers ANT1 and ANT2) approaches the overlapping portion OVL. ing. Then, the conductive layer ANT1 and the conductive layer ANT2 intersect each other in a plan view in a region where the width is minimum (W1, W3) and is almost constant, and an overlapping portion OVL between the conductive layer ANT1 and the conductive layer ANT2 is generated. is doing.
  • the conductive layer ANT1 is between a region having a substantially constant width W2 and a region having a substantially constant width W1 (W2> W1).
  • the width of the conductive layer ANT1 decreases continuously (slowly) from the width W2 to the width W1.
  • the conductive layer ANT2 has a continuous width from the width W4 to the width W3 between the region having the substantially constant width W4 and the region having the substantially constant width W3 (W4> W3). It is decreasing (slowly).
  • the conductive layer ANT1 and the conductive layer ANT2 do not overlap in plan view. That is, as the conductive layer ANT1 and the conductive layer ANT2 do not overlap in plan view except for the overlapping portion OVL, the width of the conductive layer ANT1 is continuously increased from the width W1 to the width W2 as the distance from the overlapping portion OVL increases (away from). The width of the conductive layer ANT2 increases continuously (slowly) from the width W3 to the width W4.
  • the conductive layer ANT1 and the conductive layer ANT2 intersect the region where the width of the conductive layer ANT1 is the width W1 and the region where the width of the conductive layer ANT2 is the width W3, and the overlapping portion OVL is the width of the conductive layer ANT1. Is formed by a portion where the region having the width W1 and the region having the width W3 of the conductive layer ANT2 overlap in a plan view.
  • the overlapping portion OVL is generated in the region where the width of each of the conductive layers ANT1 and ANT2 is small (preferably, the region where the width is minimum).
  • the area of the OVL can be reduced, and the widths of the conductive layers ANT1 and ANT2 are increased so that the conductive layers ANT1 and ANT2 do not overlap with each other (away from) the overlapping portion OVL. Thereby, the increase in resistance of the conductive layers ANT1 and ANT2 can be suppressed.
  • FIG. 22 is an essential part enlarged plan view showing the intersection (overlapping portion OVL) of the coil antenna ANT and the vicinity thereof in another example (fourth example) of the semiconductor device SM1 of the present embodiment.
  • FIG. 22 corresponds to a partially enlarged plan view of the region RG2 surrounded by the two-dot chain line in FIG. 4 as in FIG. 8, but FIG. 22 is a modification of the third example of FIG. This is an example, and this will be referred to as a fourth example of the present embodiment.
  • 23 is a plan view showing only the conductive layer ANT2 with the conductive layer ANT1 omitted from FIG. 22, and
  • FIG. 24 is a plan view showing only the conductive layer ANT1 with the conductive layer ANT2 omitted from FIG. is there. Note that FIGS. 22 to 24 are plan views, but each conductive layer is hatched for easy viewing of the drawings.
  • both the conductive layer ANT1 and the conductive layer ANT2 are overlapped portions.
  • the width (each width of the conductive layers ANT1 and ANT2) becomes smaller (narrower and narrower) as it approaches OVL.
  • how the widths of the conductive layers ANT1 and ANT2 change (the width of the conductive layer ANT1 from the width W1 to the width W2).
  • the method of changing the width of the conductive layer ANT2 from the width W3 to the width W4) are different.
  • the widths (each width of the conductive layers ANT1 and ANT2) of both the conductive layer ANT1 and the conductive layer ANT2 are continuously (slowly) as they approach the overlapping portion OVL. ) It is small (narrow).
  • the width (each width of the conductive layers ANT1 and ANT2) is gradually increased (steps) as both the conductive layer ANT1 and the conductive layer ANT2 approach the overlapping portion OVL. It is small (narrow).
  • the conductive layer ANT1 is between a region having a substantially constant width W2 and a region having a substantially constant width W1 (W2> W1),
  • the width of the conductive layer ANT1 decreases stepwise (stepwise) from the width W2 to the width W1.
  • the conductive layer ANT2 has a stepwise width from the width W4 to the width W3 between the region having the substantially constant width W4 and the region having the substantially constant width W3 (W4> W3). It is decreasing (in a staircase).
  • the conductive layer ANT1 and the conductive layer ANT2 do not overlap in the plan view. That is, as the conductive layer ANT1 and the conductive layer ANT2 do not overlap with each other in plan view except for the overlapping portion OVL, the width of the conductive layer ANT1 gradually increases from the width W1 to the width W2 as the distance from the overlapping portion OVL increases.
  • the width of the conductive layer ANT2 increases stepwise (stepwise) from the width W3 to the width W4.
  • the conductive layer ANT1 and the conductive layer ANT2 intersect the region where the width of the conductive layer ANT1 is the width W1 and the region where the width of the conductive layer ANT2 is the width W3, and the overlapping portion OVL is the width of the conductive layer ANT1. Is formed by a portion where the region having the width W1 and the region having the width W3 of the conductive layer ANT2 overlap in a plan view.
  • the overlapping portion OVL is generated in the region where the width of each of the conductive layers ANT1 and ANT2 is small (preferably, the region where the width is minimum).
  • the area of the OVL can be reduced, and the widths of the conductive layers ANT1 and ANT2 are increased (in this case, increased step by step) so that the conductive layers ANT1 and ANT2 do not overlap as the distance from the overlapping portion OVL increases. Thereby, the increase in resistance of the conductive layers ANT1 and ANT2 can be suppressed.
  • the fourth example shown in FIGS. 22 to 24 When the fourth example shown in FIGS. 22 to 24 is applied, it is generated in the conductive layers ANT1 and ANT2 in the vicinity of the overlapping portion OVL, similarly to the case where the third example shown in FIGS. 17 to 19 is applied.
  • the total resistance to be reduced is smaller than the first example of FIG. 8 and the second example of FIG. Therefore, as in the case of applying the third example of FIGS. 17 to 19, when the fourth example of FIGS. 22 to 24 is applied, the capacitance component generated in the overlapping portion OVL is reduced, Since the resistance of the coil antenna ANT can be further reduced, the performance of the semiconductor device SM1 (IC tag or the like) including the coil antenna ANT can be further improved.
  • the width of the overlapping portion OVL is smaller than the width of other portions of both the conductive layer ANT1 and the conductive layer ANT2. That is, for both the conductive layer ANT1 and the conductive layer ANT2, a portion where the width is locally reduced is provided so that the conductive layer ANT1 and the conductive layer ANT2 intersect each other (overlapping portion OVL is generated). Yes.
  • the widths (W2, W4) of the conductive layers ANT1 and ANT2 in the portion other than the overlapping portion OVL is efficiently reduced to reduce the capacitance component generated in the overlapping portion OVL. be able to. Therefore, the performance of the semiconductor device SM1 (IC tag or the like) including the coil antenna ANT can be improved.
  • the third example in FIGS. 17 to 19 and the fourth example in FIGS. 22 to 24 are common in that the conductive layer ANT1 and the conductive layer ANT have a width as they approach the overlapping portion OVL. Is reduced (in other words, the width increases as the distance from the overlap portion OVL increases).
  • increase in resistance of the conductive layer ANT1 and the conductive layer ANT2 can be efficiently suppressed while reducing the area of the overlapping portion OVL. That is, the area reduction of the overlapping portion OVL (that is, the capacity reduction of the overlapping portion OVL) and the resistance reduction of the coil antenna ANT can be achieved more effectively. Therefore, it is possible to further improve the performance of the semiconductor device SM1 (IC tag or the like) including the coil antenna ANT.
  • 25 to 30 are cross-sectional views of the main part during the manufacturing process of the semiconductor device of the present embodiment.
  • the gate electrode layer GE of the TFT (thin film transistor) is used as the conductive layer (antenna layer) ANT2 of the coil antenna ANT
  • the gate insulating layer GI of the TFT is used as the conductive layer (antenna layer) of the coil antenna ANT.
  • 25 to 30 are cross-sectional views of the main part of the TFT formation region where the TFT is formed on the right side of each figure, and the main part cross-sectional view of the antenna formation region where the antenna ANT is formed on the left side of each figure ( A cross-sectional view corresponding to FIG. 5 is shown.
  • the TFT formation process is understood by referring to the right side of each figure, and the antenna formation process can be understood by referring to the left side of each figure.
  • a glass substrate is prepared as the substrate SUB.
  • a Si substrate, a sapphire substrate, a quartz substrate, a flexible resin sheet (so-called plastic film), or the like can also be used.
  • the plastic film include polyethylene terephthalate, polyethylene naphthalate, polyetherimide, polyacrylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. If necessary, a substrate in which an insulating film is coated on the surface on which the gate electrode layer GE is formed may be used.
  • a conductive layer (conductive film) for the gate electrode layer GE is deposited on the substrate SUB by, for example, a sputtering method, and the conductive layer is patterned into a predetermined shape, thereby forming the gate electrode layer GE.
  • antenna layer ANT2a is formed (refer FIG. 25).
  • the gate electrode layer GE and the antenna layer ANT2a are formed in the same step by the same conductive layer (conductive film).
  • the antenna layer ANT2a corresponds to the conductive layer (antenna layer) ANT2 of the coil antenna ANT.
  • the gate electrode material that is, the material of the conductor layer for the gate electrode layer GE
  • molybdenum (Mo) molybdenum
  • Cr chromium
  • W tungsten
  • Al aluminum
  • Cu copper
  • Ti titanium
  • Ni Nickel
  • Ag gold
  • platinum platinum
  • tantalum tantalum
  • Zn zinc
  • other metal materials can be used. These may be used alone, or among these, several metals may be used as an alloy. Alternatively, a film in which the metal single layer or alloy layer is laminated may be used.
  • a conductive metal oxide such as ITO (indium tin oxide, In—Sn—O, IndiumInTin Oxide) or aluminum zinc oxide (Al—Zn—O) may be used.
  • a conductive metal nitride such as titanium nitride (TiN) can be used.
  • a semiconductor that contains impurities and has many carriers (electrons and holes) and low resistivity may be used.
  • a stacked body of the above metal compound (metal oxide, metal nitride) or semiconductor and a metal (including an alloy) may be used.
  • the conductor layer for the gate electrode layer GE For the formation of the conductor layer for the gate electrode layer GE, a sputtering method, a vapor deposition method, a CVD (Chemical Vapor Deposition) method, or the like can be used. Further, the patterning of the conductor layer for the gate electrode layer GE can be performed by forming a photoresist film having a predetermined shape using a photolithography technique and then etching using the photoresist film as an etching mask. As this etching, dry etching or wet etching can be used.
  • the conductor layer in a region other than the predetermined shape is removed together with the photoresist film by a so-called lift-off method. Patterning may be performed.
  • a molybdenum (Mo) film having a thickness of about 70 nm is formed by a sputtering method, and patterned by reactive ion etching (RIE), whereby the gate electrode layer GE and the substrate SUB are formed on the substrate SUB.
  • RIE reactive ion etching
  • a gate insulating layer (gate insulating film, gate insulating film layer) that is an insulating layer for the gate insulating film so as to cover the gate electrode layer GE and the antenna layer ANT2a.
  • a silicon oxide (SiO x ) film is deposited by a CVD method or the like, for example, about 100 to 200 nm, for example, about 100 nm.
  • an aluminum oxide (AlO x ) film or another oxide film such as Y 2 O 3 , YSZ, or HfO 2 may be used.
  • inorganic insulating films such as silicon nitride (SiN x ) films and aluminum nitride (AlN) films, polyimide derivatives, benzocyclobutene derivatives, photoacryl derivatives, polystyrene derivatives, polyvinyl phenol derivatives, polyester derivatives
  • An organic insulating film such as a polycarbonate derivative, a polyester derivative, a polyvinyl acetate derivative, a polyurethane derivative, a polysulfone derivative, an acrylate resin, an acrylic resin, or an epoxy resin may be used, but the above oxide film is more preferably used. .
  • the gate insulating layer GI functions as a gate insulating film in the TFT formation region, but in the antenna formation region, an interlayer insulating film, specifically, an insulating layer between the conductive layers ANT1 and ANT2 of the coil antenna ANT (the above-mentioned interlayer insulating layer). Functions as a membrane IL). Therefore, here, the insulating layer (the interlayer insulating film IL) between the conductive layers ANT1 and ANT2 of the coil antenna ANT is formed by the same insulating layer as the gate insulating film (gate insulating layer GI) of the TFT. become.
  • an oxide semiconductor layer CH is formed as a semiconductor layer for the channel region on the gate insulating layer GI.
  • the oxide semiconductor layer CH for example, an indium gallium zinc oxide (In—Ga—Zn—O) film is deposited with a thickness of 5 nm or more by an RF sputtering method.
  • In—Ga—Zn—O indium gallium zinc oxide
  • the channel material material of the oxide semiconductor layer CH
  • the oxide semiconductor layer CH has an amorphous or polycrystalline structure.
  • a method for forming the oxide semiconductor layer CH in addition to the sputtering method, a CVD method, a PLD (Pulsed Laser Deposition) method, a coating method, a printing method, and the like can be used.
  • the channel material the material of the oxide semiconductor layer CH
  • a sputtering method or the like by controlling the oxygen partial pressure, either the conductivity or the semiconductor characteristics is revealed in the formed film. Can be controlled. That is, by increasing the oxygen partial pressure, the amount of oxygen in the film increases (thus, the amount of carrier electrons decreases), and a transition from conductivity to semiconductor characteristics occurs continuously.
  • the oxygen partial pressure When the oxygen partial pressure is decreased to increase the conductivity, it can be used as a material for the gate electrode layer GE described above and the source / drain electrode layer SD described later.
  • the metal oxide is indicated by listing each element contained, and the composition ratio is not specified, but for these composition ratios, for example, desired characteristics, for example, If it is a semiconductor film, it should just be a semiconductor characteristic, and if it is an electroconductive film, what is necessary is just the composition ratio which has electroconductivity.
  • FIG. 27 shows a stage where the oxide semiconductor layer CH is patterned.
  • the oxide semiconductor layer CH For example, after a photoresist film is formed on the oxide semiconductor layer CH, exposure and development (photolithography) are performed to leave only a photoresist film having a desired shape. Next, by using the photoresist film as an etching mask, the channel layer (oxide semiconductor layer) CH is wet-etched or dry-etched to leave the oxide semiconductor layer CH having a desired shape, thereby forming an oxide for the channel region. A semiconductor layer CH is formed.
  • the gate insulating layer GI is formed using the photoresist film as an etching mask.
  • a contact hole (not shown) having a desired shape is formed by wet etching or dry etching.
  • a source / drain electrode layer SD conductive layer (conductive film) is deposited by, for example, sputtering, and patterned into a predetermined shape to form a source / drain electrode layer. SD is formed.
  • Examples of the source / drain electrode material include molybdenum (Mo), chromium (Cr), tungsten (W), aluminum (Al), and copper (Cu).
  • Metal materials such as titanium (Ti), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), and zinc (Zn) can be used. These may be used alone, or among these, several metals may be used as an alloy. Alternatively, a film in which the metal single layer or alloy layer is laminated may be used.
  • a conductive metal oxide such as ITO (indium tin oxide, In—Sn—O, IndiumInTin Oxide) or aluminum zinc oxide (Al—Zn—O) may be used.
  • a conductive metal nitride such as titanium nitride (TiN) can be used.
  • a semiconductor that contains impurities and has many carriers (electrons and holes) and low resistivity may be used.
  • a stacked body of the above metal compound (metal oxide, metal nitride) or semiconductor and a metal (including an alloy) may be used.
  • the conductor layer (conductive film) for the source / drain electrode layer SD For the formation of the conductor layer (conductive film) for the source / drain electrode layer SD, an evaporation method, a CVD (chemical vapor deposition) method, or the like can be used in addition to the sputtering method.
  • the patterning of the conductor layer (conductive film) for the source / drain electrode layer SD is performed by forming a photoresist film having a predetermined shape by using a photolithography technique and then using the photoresist film as an etching mask. Can be performed. As this etching, dry etching or wet etching can be used.
  • the conductor layer in a region other than the predetermined shape is combined with the photoresist film.
  • Patterning may be performed by a so-called lift-off method of removing.
  • a molybdenum (Mo) film having a thickness of about 120 nm is formed by sputtering and patterned by reactive ion etching (RIE) to form the source / drain electrode layer SD.
  • RIE reactive ion etching
  • a field effect transistor is formed by the gate electrode layer GE, the source / drain electrode layer SD, the oxide semiconductor layer CH, and the gate insulating layer GI.
  • the oxide semiconductor layer CH located between the source / drain electrode layer SD for source and the source / drain electrode layer SD for drain and above the gate electrode layer GE is formed of a field effect transistor (TFT).
  • the gate insulating layer GI that functions as a channel region and is located between the channel region (oxide semiconductor layer CH) and the gate electrode layer GE functions as a gate insulating film of a field effect transistor (TFT).
  • a contact hole (corresponding to the contact hole CNT1 in FIG. 7 described above, not shown here) for connection between the antenna / wiring layer AW to be formed later and the antenna layer ANT2a already formed is formed.
  • the gate insulating layer GI is wet-etched or dry-etched using the photoresist film as an etching mask to form a contact hole (not shown) having a desired shape in the gate insulating layer GI.
  • an antenna / wiring layer AW is formed on the gate insulating layer GI.
  • an aluminum (Al) film is deposited on the substrate SUB with a thickness of 1 ⁇ m by using an electron beam evaporation method.
  • the material (electrode material) of the antenna / wiring layer AW here is aluminum (Al), molybdenum (Mo), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), titanium.
  • Metal materials such as (Ti), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), and zinc (Zn) can be used.
  • metals may be used alone, or among these, several metals may be used as an alloy.
  • a film in which the metal single layer or alloy layer is laminated may be used.
  • it has conductivity such as ITO (IndiumxTin Oxide: Indium Tin Oxide, In-Sn-O) and Aluminum Zinc Oxide (Al-Zn-O), and conductive metal oxides such as Titanium Nitride (TiN).
  • ITO IndiumxTin Oxide: Indium Tin Oxide, In-Sn-O
  • Al-Zn-O Aluminum Zinc Oxide
  • TiN Titanium Nitride
  • a laminated film of metal nitride and the above metal film can also be used.
  • the antenna / wiring layer AW can be formed by forming a conductor film (conductive film) for the antenna / wiring layer AW and patterning the conductor film. This patterning is performed by photolithography. After forming a photoresist film having a predetermined shape using a technique, etching can be performed using the photoresist film as an etching mask. As this etching, dry etching or wet etching can be used.
  • the conductor film in a region other than the predetermined shape is removed together with the photoresist film.
  • the patterning may be performed by a so-called lift-off method.
  • the antenna / wiring layer AW formed in the antenna formation region corresponds to the conductive layer (antenna layer) ANT1 of the coil antenna ANT. Further, the wiring of the IC part 11 is also formed by the antenna / wiring layer AW.
  • a protective film is formed as an insulating layer on the substrate SUB so as to cover the source / drain electrode layer SD, the antenna / wiring layer AW, and the oxide semiconductor layer CH.
  • (Protective layer, protective film layer) PA1 may be formed.
  • the protective film PA1 for example, a silicon oxide film (SiO x ) having a thickness of about 300 nm formed by a CVD method or the like can be used.
  • another oxide film such as an aluminum oxide (AlO x ) film may be used.
  • inorganic insulating films such as silicon nitride (SiN x ) films and aluminum nitride (AlN) films, polyimide derivatives, benzocyclobutene derivatives, photoacryl derivatives, polystyrene derivatives, polyvinyl phenol derivatives, polyester derivatives
  • An organic insulating film such as a polycarbonate derivative, a polyester derivative, a polyvinyl acetate derivative, a polyurethane derivative, a polysulfone derivative, an acrylate resin, an acrylic resin, or an epoxy resin may be used, but the above oxide film is more preferably used.
  • a sputtering method, a vapor deposition method, a coating method, or the like may be used as a method for forming the protective film PA1 in addition to the CVD method.
  • heat treatment at 200 ° C. to 450 ° C. can be performed for the purpose of improving the characteristics of the field effect transistor (TFT in this case).
  • the heat treatment temperature is desirably 350 ° C. or lower. Since this heat treatment is intended to improve the characteristics of the transistor (here TFT), the heat treatment can be performed at any time after the formation of the channel layer (corresponding to the oxide semiconductor layer CH) to obtain the same effect. it can.
  • the semiconductor device (antenna integrated semiconductor device) of this embodiment is substantially completed. Thereafter, the substrate SUB may be cut as necessary. In that case, an individualized semiconductor device (antenna integrated semiconductor device) is obtained. Also in the semiconductor device (antenna integrated semiconductor device) when separated, the state in which the coil antenna ANT and the IC part 11 are formed on the same substrate SUB is maintained.
  • the TFT formed in the TFT formation region (right side in FIG. 30) on the main surface of the substrate SUB corresponds to the transistor (field effect transistor) formed in the IC section 11.
  • the antenna layer ANT2a formed in the antenna formation region (left side of FIG. 30) on the main surface of the substrate SUB corresponds to the conductive layer (antenna layer) ANT2 of the coil antenna ANT and is formed in the antenna formation region.
  • the antenna / wiring layer AW thus formed corresponds to the conductive layer (antenna layer) ANT1 of the coil antenna ANT.
  • the conductive layer (antenna layer) ANT2 of the coil antenna ANT is formed by the antenna layer ANT2a described here, and the conductive layer (antenna layer) ANT1 of the coil antenna ANT is the antenna / wiring layer AW described here. It is formed by.
  • the antenna / wiring layer AW can form not only the conductive layer (antenna layer) ANT1 of the coil antenna ANT but also other wiring.
  • the TFT includes a gate electrode layer GE, a gate insulating layer GI, a channel region semiconductor layer (here, an oxide semiconductor layer CH), and source / drain electrode layers. SD.
  • the insulating layer (the interlayer insulating film IL) between the conductive layer ANT1 (here, the antenna / wiring layer AW) of the coil antenna ANT and the conductive layer ANT2 (here, the antenna layer ANT2a) is a gate insulating layer GI of the TFT. It is the same layer.
  • the gate insulating layer GI is designed in consideration of the transistor characteristics of the TFT, and its thickness is determined by the required transistor characteristics.
  • the thickness of the gate insulating layer GI is relatively thin (for example, about 200 nm or less), and the insulating layer between the conductive layers ANT1 and ANT2 of the coil antenna ANT (the interlayer insulating film IL) is the same as the gate insulating layer GI of the TFT.
  • the capacitance generated at the intersection (overlapping portion OVL) of the coil antenna tends to increase.
  • the structure of the overlapping portion OVL as described above for example, the first example of FIG. 8, the second example of FIG. 14, the third example of FIG. 17.
  • the area of the overlapping portion OVL can be sufficiently reduced, and the capacitance generated at the crossing portion (overlapping portion OVL) of the coil antenna can be suppressed.
  • the structure of the overlapping portion OVL as described above in this embodiment for example, the first example in FIG. 8, the second example in FIG. 14, the third example in FIG. 17, the fourth example in FIG. 22).
  • the insulating layer (the above-mentioned interlayer insulating film IL) between the conductive layers ANT1 and ANT2 of the coil antenna ANT is made the same layer as the gate insulating film (gate insulating layer GI) that tends to be thin, , Extremely effective.
  • the thickness of the insulating layer (the interlayer insulating film IL) interposed between the conductive layer ANT1 and the conductive layer ANT2 of the coil antenna ANT is thin at the intersection (overlapping portion OVL) of the coil antenna, the capacitance generated there Tends to grow.
  • the structure of the overlapping portion OVL of the present embodiment (for example, the first example of FIG. 8, the second example of FIG. 14, the third example of FIG. 17, the fourth example of FIG. 22) is applied. Otherwise, the parasitic capacitance at the intersection of the coil antennas increases, and the performance of a semiconductor device (for example, an IC tag) provided with the coil antennas decreases.
  • the structure of the overlapping portion OVL of the present embodiment (for example, the first example in FIG. 8, the second example in FIG. 14, the third example in FIG. 17, the fourth example in FIG. 22)
  • the thickness of the insulating layer (interlayer insulating film IL) interposed between the conductive layer ANT1 and the conductive layer ANT2 of the coil antenna ANT is thin at the intersection (overlapping portion OVL) of the coil antenna ANT, the effect is obtained. Is big.
  • the thickness of the insulating layer (the interlayer insulating film IL) interposed between the conductive layers ANT1 and ANT2 of the coil antenna ANT is 0.5 ⁇ m or less at the intersection (overlapping portion OVL) of the coil antenna ANT.
  • the structure of the overlapping portion OVL of this embodiment (for example, the first example of FIG. 8, the second example of FIG. 14, the third example of FIG. 17, the fourth example of FIG. 22) is applied.
  • the effect is extremely large. That is, when the thickness of the insulating layer (the interlayer insulating film IL) interposed between the conductive layer ANT1 and the conductive layer ANT2 of the coil antenna ANT is 0.5 ⁇ m or less, the first comparative example of FIG.
  • the structure of the overlapping portion OVL of the present embodiment (for example, the first example in FIG. 8, the second example in FIG. 14, the third example in FIG. 17, and the fourth example in FIG. 22) is applied.
  • the thickness of the insulating layer (the interlayer insulating film IL) between the conductive layers ANT1 and ANT2 of the coil antenna ANT is reduced, the characteristics (inductance and resistance) required for the coil antenna ANT can be satisfied.
  • the coil antenna ANT and the IC unit 11 are formed together (in the same manufacturing process) on the same substrate SUB, so that a high-performance antenna-integrated semiconductor device can be manufactured at low cost. It becomes possible to manufacture with.
  • the coil antenna ANT and the TFT are formed together (by the same manufacturing process) on the same substrate SUB using a thin film process.
  • the conductive layer ANT1 or the conductive layer ANT2 of the coil antenna ANT is formed of the same layer as the gate electrode layer GE or the source / drain electrode layer SD of the TFT because the number of manufacturing steps can be reduced. 25 to 30, the conductive layer ANT2 of the coil antenna ANT is formed of the same layer as the gate electrode layer GE of the TFT.
  • the conductive layer ANT2 of the coil antenna ANT is formed of the same layer as the source / drain electrode layer SD of the TFT.
  • the conductive layer ANT2 of the coil antenna ANT is formed of the same layer as the gate electrode layer GE of the TFT.
  • the conductive layer ANT2 of the coil antenna ANT is formed of the same layer as the source / drain electrode layer SD of the TFT, and the conductive layer ANT1 of the coil antenna ANT is connected to the gate electrode layer GE of the TFT. It is formed of the same layer. Accordingly, the coil antenna ANT and the TFT (TFT constituting the IC unit 11) can be formed together on the same substrate SUB while suppressing the number of manufacturing steps.
  • FIGS. 31 and 32 show the case where the structure of the first comparative example of FIG. 11 is applied to the intersection (overlapping portion OVL101) of the coil antenna (that is, the overlapping portions OVL of the conductive layers ANT101 and ANT102 of the coil antenna). Corresponds to the case where the width is not narrowed).
  • FIG. 33 and FIG. 34 show the case where the structure of the present embodiment (here, the third example of FIG. 17 described above) is applied to the crossing portion (overlapping portion OVL) of the coil antenna (that is, the coil at the overlapping portion OVL). This corresponds to a case where the width of the antenna conductive layers ANT1 and ANT2 is reduced).
  • the graphs of FIGS. 31 and 33 show the frequency characteristics of the resistance in the coil antenna.
  • the horizontal axis of the graph corresponds to the frequency
  • the vertical axis of the graph corresponds to the resistance of the coil antenna.
  • 32 and 34 show the frequency characteristics of the inductance in the coil antenna.
  • the horizontal axis of the graph corresponds to the frequency
  • the vertical axis of the graph corresponds to the inductance of the coil antenna.
  • FIGS. 31 and 32 show a case where the structure of the first comparative example of FIG. 11 is applied to the crossing portion (overlapping portion OVL101) of the coil antenna.
  • the line spacing (adjacent spacing of the coil pattern) is 0.5 mm
  • a rectangular shape of 35 mm ⁇ 50 mm is used.
  • a coil antenna having 7 turns (7 turns) was formed using a thin film process. Examples of the actual measurement results of the resistance and inductance of the coil antenna in this case are shown in FIGS.
  • the inductance of the coil antenna should change little with frequency, but due to the capacitance of the crossing portion (overlapping portion OVL101) of the coil antenna, the inductance of the coil antenna becomes small, and as shown in FIG. As the value increases, the inductance of the coil antenna decreases. This deteriorates the performance of the semiconductor device provided with the coil antenna. For example, when the inductance of the coil antenna is reduced, the voltage between the terminals LA and LB in FIG. 1 is reduced, which may deteriorate the operating characteristics of a semiconductor device (such as an IC tag) provided with the coil antenna. .
  • FIGS. 33 and 34 show a case where the structure of the present embodiment is applied to the crossing portion (overlapping portion OVL) of the coil antenna.
  • FIGS. 33 and 34 show examples of measurement results of resistance and inductance of the coil antenna.
  • the resistance of the coil antenna increases as the frequency increases.
  • the inductance of the coil antenna has a substantially constant value even when the frequency is changed.
  • the inductance of the coil antenna hardly decreases even when the frequency is increased.
  • the inductance shown in FIG. 34 has a substantially constant value at a high level.
  • the capacitance of the crossing portion (overlapping portion OVL) of the coil antenna can be suppressed, so that the inductance of the coil antenna can be increased, and the semiconductor device including the coil antenna Performance can be improved.
  • the inductance of the coil antenna increases, the voltage between the terminals LA and LB in FIG. 1 increases, so that the operating characteristics of a semiconductor device (such as an IC tag) provided with the coil antenna can be improved.
  • the structure of the intersection (overlapping portion OVL) of the coil antenna described with reference to the above drawings (for example, FIG. 8, FIG. 14, FIG. 17, FIG. 22) is adopted.
  • the increase in resistance of the coil antenna can be suppressed, the stability of the inductance of the coil antenna with respect to the frequency can be obtained, and a thin antenna-integrated semiconductor device can be provided at low cost.
  • 35 to 40 are cross-sectional views of a main part during the manufacturing process of the semiconductor device according to the second embodiment.
  • the present embodiment is different from the first embodiment in that the source / drain electrode layer SD of the TFT (thin film transistor) is used for the antenna layer ANT2a and the protective film PA1 of the TFT is formed in the present embodiment.
  • the antenna / wiring layer AW will be formed later. That is, the present embodiment uses the protective film PA1 as the interlayer insulating film IL between the conductive layer (antenna layer) ANT1 and the conductive layer (antenna layer) ANT2 of the coil antenna ANT.
  • This is different from the manufacturing process described in the first embodiment. Other points regarding materials, film formation, and processing are the same as those in the manufacturing process of the first embodiment. This will be specifically described below.
  • a conductive layer (conductive film) for the gate electrode layer GE is formed on the substrate SUB, and this conductive layer (conductive film) is formed.
  • a gate electrode layer GE is formed as shown in FIG.
  • the other steps are basically the same as the steps up to obtaining the structure of FIG. 25 of the first embodiment. The same.
  • a gate insulating layer GI that is an insulating layer for a gate insulating film is formed on the substrate SUB so as to cover the gate electrode layer GE, as in the first embodiment. .
  • an oxide semiconductor layer CH is formed and patterned as a semiconductor layer for the channel region on the gate insulating layer GI, as in the first embodiment. Then, in order to use a part of the source / drain electrode layer SD to be formed later as a wiring, a contact hole (not shown) for connection with the gate electrode layer GE that has already been formed is formed. This contact hole (not shown) is formed in a desired shape in the gate insulating layer GI by wet etching or dry etching of the gate insulating layer GI using the photoresist film as an etching mask.
  • a conductor layer (conductive film) for the source / drain electrode layer SD is formed on the substrate SUB, that is, on the gate insulating layer GI, and this conductor film is patterned.
  • the source / drain electrode layer SD and the antenna layer ANT2a are formed.
  • the formation method and patterning method of the conductor layer (conductive film) for the source / drain electrode layer SD are basically the same as those in the first embodiment, but only the source / drain electrode layer SD is used in this step.
  • the antenna layer ANT2a is also formed together, which is different from the first embodiment.
  • the source / drain electrode layer SD and the antenna layer ANT2a are formed in the same step by the same conductive layer (conductive film). Is done.
  • the material of the conductor layer (conductive film) for the source / drain electrode layer SD the material described in the first embodiment can be used.
  • the material for the source / drain electrode layer SD is used.
  • a molybdenum film with a thickness of 200 nm is used for the conductor layer (conductive film).
  • a film thickness of 0 is formed on the substrate SUB (here, on the gate insulating layer GI) so as to cover the source / drain electrode layer SD, the antenna layer ANT2a, and the oxide semiconductor layer CH.
  • a protective film PA1 having a thickness of about 05 to 0.5 ⁇ m is formed.
  • the material and forming method of the protective film PA1 are basically the same as those in the first embodiment.
  • the protective film PA1 functions as a protective film in the TFT formation region, but in the antenna formation region, an interlayer insulating film, specifically, an insulating layer between the conductive layers ANT1 and ANT2 of the coil antenna ANT (the interlayer insulating film IL described above). ).
  • the insulating layer (the interlayer insulating film IL) between the conductive layers ANT1 and ANT2 of the coil antenna ANT is formed of the same insulating layer as the protective film (PA1) of the TFT.
  • a contact hole (corresponding to the contact hole CNT1 in FIG. 7 described above, not shown here) for connection between the antenna / wiring layer AW to be formed later and the antenna layer ANT2a already formed is formed.
  • the protective film PA1 is wet-etched or dry-etched using the photoresist film as an etching mask to form a contact hole (not shown) having a desired shape in the protective film PA1.
  • contact holes (through holes) CNT2 exposing a part of the source / drain electrode layer SD are also formed, and antennas / wirings to be formed later are formed through the contact holes CNT2.
  • a part of the layer AW (a part to be a wiring) can be connected to the source / drain electrode layer SD.
  • an antenna / wiring layer AW is formed on the protective film PA1.
  • the antenna / wiring layer AW can be formed by forming a conductor film (conductive film) for the antenna / wiring layer AW and patterning the conductor film.
  • the film method and the patterning method are basically the same as those in the first embodiment.
  • the semiconductor device (antenna integrated semiconductor device) of this embodiment is substantially completed.
  • the TFT includes a gate electrode layer GE, a gate insulating layer GI, a channel region semiconductor layer (here, an oxide semiconductor layer CH), and source / drain electrode layers. It has SD and protective film PA1 which covers these.
  • the insulating layer (the interlayer insulating film IL) between the conductive layer ANT1 (here, the antenna / wiring layer AW) of the coil antenna ANT and the conductive layer ANT2 (here, the antenna layer ANT2a) is a TFT protective film PA1. It is the same layer.
  • the protective film PA1 is provided mainly for the protection of the TFT, and it is only necessary to secure a thickness necessary for the protection.
  • the thickness of the protective film PA1 tends to be thicker than that of the gate insulating layer GI, but the thickness is still relatively thin (for example, about 400 nm or less), and the insulating layer between the conductive layers ANT1 and ANT2 of the coil antenna ANT (above-mentioned
  • the interlayer insulating film IL is formed in the same layer as the protective film PA1 of the TFT, the capacitance generated at the intersection (overlapping portion OVL) of the coil antenna tends to increase.
  • the structure of the overlapping portion OVL as described above for example, the first example of FIG. 8, the second example of FIG. 14, the third example of FIG. 17.
  • the area of the overlapping portion OVL can be sufficiently reduced, and the capacitance generated at the crossing portion (overlapping portion OVL) of the coil antenna can be suppressed.
  • the structure of the overlapping portion OVL as described above in this embodiment for example, the first example in FIG. 8, the second example in FIG. 14, the third example in FIG. 17, the fourth example in FIG. 22).
  • the insulating layer (the interlayer insulating film IL) between the conductive layers ANT1 and ANT2 of the coil antenna ANT is made the same layer as the protective film (PA) of the TFT that tends to be thin, Great effect.
  • the coil antenna formed with the interlayer insulating film IL having a film thickness of 0.05 ⁇ m to 5 ⁇ m exhibited substantially the same antenna characteristics as the coil antenna manufactured in the first embodiment.
  • the RFID circuit manufactured in this embodiment normal wireless operation could be confirmed as in the first embodiment.
  • the conventional antenna structure corresponding to the first comparative example in FIG. 11 and the like
  • the interlayer insulating film IL is thinned. In the case of (less than 2 ⁇ m), it was confirmed that the inductance of the coil antenna decreased depending on the frequency, and it was found difficult to obtain good antenna characteristics.
  • the structure of the intersection (overlapping portion OVL) of the coil antenna described with reference to the above drawings (for example, FIG. 8, FIG. 14, FIG. 17, FIG. 22) is adopted.
  • the increase in resistance of the coil antenna can be suppressed, the stability of the inductance of the coil antenna with respect to the frequency can be obtained, and a thin antenna-integrated semiconductor device can be provided at low cost.
  • 41 and 42 are cross-sectional views of relevant parts in the manufacturing process of the semiconductor device of the third embodiment.
  • This embodiment is different from the first embodiment in that the antenna / wiring layer AW is formed after the formation of the protective film PA1 of the TFT in the present embodiment. That is, in the present embodiment, a plurality of insulating layers (the interlayer insulating film IL) are used as an insulating layer (the interlayer insulating film IL) between the conductive layer (antenna layer) ANT1 and the conductive layer (antenna layer) ANT2 of the coil antenna ANT. The point of using two or more insulating layers) is different from the manufacturing process described in the first embodiment.
  • the process is basically the same as that in the first embodiment. That is, also in the present embodiment, the gate electrode layer GE, the antenna layer ANT2a, the gate insulating layer GI, the channel layer CH, and the source / drain electrode layer SD are formed in the same manner as in the first embodiment described above. Get the structure. Similarly to the first embodiment, also in the present embodiment, the gate electrode layer GE and the antenna layer ANT2a are formed in the same step by the same conductive layer (conductive film).
  • the conductor film (conductive film formation) and the gate insulating layer GI for the gate electrode layer GE and the antenna layer ANT2a those described in the first embodiment can be used.
  • the gate electrode As the GE a molybdenum film having a thickness of 100 nm is used, and a gate insulating layer GI having a thickness of 0.02 to 0.5 ⁇ m is used.
  • a film thickness of about 0.05 to 0.5 ⁇ m is formed on the substrate SUB so as to cover the source / drain electrode layer SD and the oxide semiconductor layer CH.
  • a protective film PA1 is formed.
  • the material and forming method of the protective film PA1 are basically the same as those in the first embodiment.
  • the gate insulating layer GI and the protective film PA1 function as a gate insulating film and a protective film, respectively, in the TFT formation region, but in the antenna formation region, an interlayer insulating film, specifically, conductive layers ANT1, ANT2 of the coil antenna ANT. It functions as an insulating layer (interlayer insulating film IL).
  • the insulating layer (the interlayer insulating film IL) between the conductive layers ANT1 and ANT2 of the coil antenna ANT is the same layer as the gate insulating film (gate insulating layer GI) and the protective film (PA1) of the TFT. It will be formed by layers.
  • a contact hole (corresponding to the contact hole CNT1 in FIG. 7 described above, not shown here) for connection between the antenna / wiring layer AW to be formed later and the antenna layer ANT2a already formed is formed. Therefore, the protective film PA1 and the gate insulating layer GI are wet-etched or dry-etched using the photoresist film as an etching mask. Thereby, a contact hole (not shown) having a desired shape is formed in the laminated film of the protective film PA1 and the gate insulating layer GI.
  • a contact hole CNT2 exposing a part of the source / drain electrode layer SD is formed in the protective film PA1, and a part of the antenna / wiring layer AW (wiring and wiring) to be formed later is formed through the contact hole CNT2. Can be connected to the source / drain electrode layer SD.
  • an antenna / wiring layer AW is formed on the protective film PA1.
  • the antenna / wiring layer AW can be formed by forming a conductor film (conductive film) for the antenna / wiring layer AW and patterning the conductor film.
  • the film method and the patterning method are basically the same as those in the first embodiment.
  • the semiconductor device (antenna integrated semiconductor device) of this embodiment is substantially completed.
  • the interlayer insulating film IL is composed of two layers of a gate insulating layer GI and a protective film PA1.
  • the coil antenna formed with the interlayer insulating film IL having a film thickness of 0.07 ⁇ m to 5.5 ⁇ m exhibited substantially the same antenna characteristics as the coil antenna manufactured in the first embodiment.
  • normal wireless operation could be confirmed as in the first embodiment.
  • the interlayer insulating film IL is thinned. In the case of (less than 2 ⁇ m), it was confirmed that the inductance of the coil antenna decreased depending on the frequency, and it was found difficult to obtain good antenna characteristics.
  • the structure of the crossing portion (overlapping portion OVL) of the coil antenna described with reference to the above drawings (for example, FIG. 8, FIG. 14, FIG. 17, FIG. 22 etc.) is adopted.
  • an increase in resistance of the coil antenna can be suppressed, the stability of the inductance of the coil antenna with respect to the frequency can be obtained, and a thin antenna-integrated semiconductor device can be provided at low cost.
  • FIG. 43 is a fragmentary cross-sectional view of the semiconductor device of Fourth Embodiment during the manufacturing process thereof.
  • This embodiment is different from the first to third embodiments in the following points. That is, in the present embodiment, in the coil antenna ANT, the portion where the width of the coil antenna ANT is narrow at the intersection (overlapping portion OVL) (the conductive layer ANT1 in FIGS. 8, 14, 17 and 22 above). , The width of ANT2 is W1 and W3) (the thickness of one or both of the conductive layers ANT1 and ANT2) is thicker than the thickness of the other portion (the thickness of the coil antenna ANT). It has become. Other points regarding materials, film formation, and processing are the same as those in any of Embodiments 1 to 3 in this embodiment. This will be specifically described below.
  • the wiring layer AW is formed to obtain the structure shown in FIG.
  • the process up to the antenna / wiring layer AW formation process is basically the same as that of the third embodiment, and therefore the description thereof is omitted here.
  • the antenna / wiring layer AW which is the upper conductive layer of the conductive layers ANT1 and ANT2, at the intersection (overlapping portion OVL) of the coil antenna ANT.
  • a process of increasing the thickness of (thickening locally) is performed. This is because, after the antenna / wiring layer AW is formed, a conductive layer is locally formed (added or stacked) on the antenna / wiring layer AW at the intersection (the overlapping portion OVL) of the coil antenna ANT. ) And so on.
  • a conductive layer of about 5 ⁇ m can be formed by a printing method.
  • an additional conductive layer is formed on the antenna / wiring layer AW only at the intersection (the overlapping portion OVL) of the coil antenna ANT and in the vicinity thereof, and this additional conductive layer is also a part of the antenna / wiring layer AW. Function as. For this reason, the thickness of the antenna / wiring layer AW at the intersection (the overlapping portion OVL) of the coil antenna ANT and the vicinity thereof is thicker than the thickness of the antenna / wiring layer AW at other locations.
  • the semiconductor device (antenna integrated semiconductor device) of this embodiment is substantially completed.
  • the antenna / wiring layer AW is formed to obtain the structure shown in FIG. 29, and then the intersection of the coil antenna ANT (the overlapping portion OVL).
  • a conductive layer may be locally formed on the antenna / wiring layer AW by a printing method or the like.
  • the antenna / wiring layer AW is formed to obtain the structure shown in FIG. 40, and then the intersection of the coil antenna ANT (the overlapping portion OVL).
  • a conductive layer may be locally formed on the antenna / wiring layer AW by a printing method or the like.
  • the thickness of the overlapping portion OVL is thicker than the other portions. is doing. In the overlapping portion OVL, the resistance is likely to increase due to the narrow width. However, by making the thickness in the overlapping portion OVL thicker than other portions, the resistance in the overlapping portion OVL can be reduced, and the resistance of the coil antenna ANT is reduced. Can be achieved. Thereby, the performance of the semiconductor device including the coil antenna can be further improved.
  • the thickness of not only the overlap portion OVL but the entire coil antenna ANT is increased, the manufacturing time becomes longer, leading to a decrease in throughput and an increase in manufacturing cost.
  • the thickness is locally increased in the overlap portion OVL. By doing so, such a problem does not occur.
  • the coil antenna formed with the interlayer insulating film IL having a film thickness of 0.07 ⁇ m to 5.5 ⁇ m showed the same antenna characteristics as those of the coil antenna manufactured in the first embodiment. This was found to be due to a decrease in the resistance value of the antenna. This decrease in resistance value is obtained by increasing the film thickness of the antenna layer in the overlapping portion OVL.
  • normal wireless operation could be confirmed as in the first embodiment.
  • the conventional antenna structure (corresponding to the first comparative example in FIG. 11 and the like) that does not use the configuration of the intersection shown in FIG. 8, FIG. 14, FIG. 17 and FIG. Even when the resistance value was decreased by increasing the thickness of the layer, it was confirmed that the inductance of the coil antenna decreased depending on the frequency, and it was found difficult to obtain good antenna characteristics.
  • the structure of the crossing portion (overlapping portion OVL) of the coil antenna described with reference to the above drawings (for example, FIG. 8, FIG. 14, FIG. 17, FIG. 22 etc.) is adopted.
  • an increase in resistance of the coil antenna can be suppressed, the stability of the inductance of the coil antenna with respect to the frequency can be obtained, and a thin antenna-integrated semiconductor device can be provided at low cost.
  • 44 to 47 are fragmentary cross-sectional views of the semiconductor device according to the fifth embodiment during the manufacturing process thereof.
  • the manufacturing process applied when the TFT is a so-called bottom gate TFT has been described.
  • the present invention can also be applied to a top gate TFT.
  • a manufacturing process when applied to a top gate type TFT will be described.
  • the bottom gate type herein refers to a structure in which a gate electrode (here, the gate electrode layer GE) is formed below the channel layer (here, the oxide semiconductor layer CH).
  • a gate electrode here, the gate electrode layer GE
  • the gate electrode layer GE is formed above the channel layer (here, the oxide semiconductor layer CH).
  • a substrate SUB similar to that of the first embodiment is prepared, and then an oxide semiconductor layer CH is formed and patterned as a semiconductor layer for a channel region on the substrate SUB.
  • the material of the oxide semiconductor layer CH the material described in Embodiment 1 can be used.
  • the oxide semiconductor layer CH can be formed by sputtering, PLD method, CVD method, coating method, printing method, etc., and processing (patterning) can be performed by general photolithography technique and dry etching or wet etching. Can be performed in combination.
  • In—Ga—Zn—O may be formed to a thickness of about 5 to 100 nm by a sputtering method as the oxide semiconductor layer CH, but the present invention is not limited thereto.
  • a conductor layer (conductive film) for the source / drain electrode layer SD is formed on the substrate SUB so as to cover the oxide semiconductor layer CH, and this conductor film Are patterned to form the source / drain electrode layer SD and the antenna layer ANT2a.
  • the material, formation method, and patterning method of the conductor layer (conductive film) for the source / drain electrode layer SD are basically the same as those in the first embodiment, but in this step, the source / drain electrode layer SD is formed. Not only the antenna layer ANT2a but also the antenna layer ANT2a is formed together with the first embodiment. That is, in the present embodiment, the source / drain electrode layer SD and the antenna layer ANT2a (that is, the conductive layer ANT2 of the coil antenna ANT) are formed in the same step by the same conductive layer (conductive film). Is done.
  • the gate insulating layer GI which is an insulating layer for the gate insulating film, covers the antenna layer ANT2a, the source / drain electrode layer SD, and the oxide semiconductor layer CH on the substrate SUB.
  • the material of the gate insulating layer GI the material described in Embodiment Mode 1 can be used.
  • the gate insulating layer GI functions as a gate insulating film of the TFT, and the interlayer insulating film IL between the conductive layer (antenna layer) ANT1 and the conductive layer (antenna layer) ANT2 of the coil antenna ANT. It also becomes.
  • the gate insulating layer GI can be formed by a sputtering method, a PLD method, a CVD method, a coating method, a printing method, or the like, and the processing is performed by a combination of general photolithography technology and dry etching or wet etching. be able to.
  • the gate insulating layer GI functions as a gate insulating film in the TFT formation region, but in the antenna formation region, an interlayer insulating film, specifically, an insulating layer between the conductive layers ANT1 and ANT2 of the coil antenna ANT (the above-mentioned interlayer insulating layer). Functions as a membrane IL). Therefore, here, the insulating layer (the interlayer insulating film IL) between the conductive layers ANT1 and ANT2 of the coil antenna ANT is formed by the same insulating layer as the gate insulating film (gate insulating layer GI) of the TFT. become.
  • a contact hole (corresponding to the contact hole CNT1 in FIG. 7 described above, not shown here) for connection between the antenna / wiring layer AW to be formed later and the antenna layer ANT2a already formed is formed.
  • the gate insulating layer GI is wet-etched or dry-etched using the photoresist film as an etching mask to form a contact hole (not shown) having a desired shape in the gate insulating layer GI.
  • contact holes (through holes) CNT3 exposing a part of the source / drain electrode layer SD are also formed, and antennas / wirings to be formed later are formed through the contact holes CNT3.
  • a part of the layer AW (a part to be a wiring) can be connected to the source / drain electrode layer SD.
  • an antenna / wiring layer AW and a gate electrode layer (gate electrode) GE are formed on the gate insulating layer GI.
  • a common conductor layer (conductive film) for the antenna / wiring layer AW and the gate electrode layer (gate electrode) GE is patterned.
  • a layer (gate electrode) GE can be formed.
  • the antenna / wiring layer AW and the gate electrode layer (gate electrode) GE are formed in the same step by the same conductive layer (conductive film).
  • the conductive layer ANT1 and the gate electrode layer (gate electrode) GE of the coil antenna ANT are formed in the same process by the same conductive layer (conductive film).
  • the material of the antenna / wiring layer AW, the film forming method, and the patterning method can be basically the same as those in the first embodiment.
  • film formation can be performed by sputtering, PLD, vapor deposition, CVD, coating, printing, etc.
  • processing can be performed using general photolithography technology and dry etching or wet etching. This can be done by a combination of
  • the protective film PA1 (not shown here) is formed on the substrate SUB (that is, on the gate insulating layer GI) so as to cover the antenna / wiring layer AW and the gate electrode layer GE. May be.
  • the semiconductor device (antenna integrated semiconductor device) of this embodiment is substantially completed.
  • the coil antenna formed in the fifth embodiment showed almost the same antenna characteristics as the coil antenna manufactured in the first embodiment.
  • the RFID circuit manufactured in this embodiment normal wireless operation could be confirmed as in the first embodiment.
  • the structure of the crossing portion (overlapping portion OVL) of the coil antenna described with reference to the above drawings (for example, FIG. 8, FIG. 14, FIG. 17, FIG. 22 etc.) is adopted.
  • an increase in resistance of the coil antenna can be suppressed, the stability of the inductance of the coil antenna with respect to the frequency can be obtained, and a thin antenna-integrated semiconductor device can be provided at low cost.
  • the present invention is effective when applied to a semiconductor device and its manufacturing technology.

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  • Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
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Abstract

Dans un dispositif à semi-conducteur selon la présente invention, où une unité CI et une antenne à cadre qui est connectée à ladite unité CI sont formées sur le même substrat, l'antenne à cadre est constituée de couches conductrices (ANT1) et (ANT2) qui sont des couches mutuellement différentes. Un film isolant intermédiaire est intercalé entre les couches conductrices (ANT1) et (ANT2). Les couches conductrices (ANT1) et (ANT2) sont dotées de sections chevauchantes (OVL) qui se chevauchent par l'intermédiaire du film isolant intermédiaire dans la direction qui est orthogonale à la surface principale d'un substrat, la largeur des couches conductrices (ANT1) et (ANT2) au niveau des sections chevauchantes (OVL) étant inférieure à la largeur des autres sections.
PCT/JP2012/079835 2012-01-20 2012-11-16 Dispositif à semi-conducteur et son procédé de fabrication WO2013108477A1 (fr)

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JP2012010000A JP5819737B2 (ja) 2012-01-20 2012-01-20 半導体装置

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02137356A (ja) * 1988-11-18 1990-05-25 Nec Corp 半導体集積回路
JPH0410624A (ja) * 1990-04-27 1992-01-14 Hitachi Ltd 半導体集積回路
JPH051239U (ja) * 1991-06-25 1993-01-08 三洋電機株式会社 半導体集積回路
JP2006179871A (ja) * 2004-11-29 2006-07-06 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2006229211A (ja) * 2005-01-21 2006-08-31 Semiconductor Energy Lab Co Ltd 半導体装置
WO2009041119A1 (fr) * 2007-09-27 2009-04-02 Sharp Kabushiki Kaisha Dispositif d'antenne, substrat de dispositif d'affichage, unité d'affichage à cristaux liquides, système d'affichage, procédé de fabrication d'un dispositif d'antenne et procédé de fabrication d'un substrat de dispositif d'affichage
WO2009116177A1 (fr) * 2008-03-21 2009-09-24 株式会社島津製作所 Dispositif à matrice optique

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4149293B2 (ja) * 2003-03-18 2008-09-10 日立マクセル株式会社 コイルオンチップ及びコイルオンチップの製造方法
US8698697B2 (en) * 2007-06-12 2014-04-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP5578797B2 (ja) * 2009-03-13 2014-08-27 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02137356A (ja) * 1988-11-18 1990-05-25 Nec Corp 半導体集積回路
JPH0410624A (ja) * 1990-04-27 1992-01-14 Hitachi Ltd 半導体集積回路
JPH051239U (ja) * 1991-06-25 1993-01-08 三洋電機株式会社 半導体集積回路
JP2006179871A (ja) * 2004-11-29 2006-07-06 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2006229211A (ja) * 2005-01-21 2006-08-31 Semiconductor Energy Lab Co Ltd 半導体装置
WO2009041119A1 (fr) * 2007-09-27 2009-04-02 Sharp Kabushiki Kaisha Dispositif d'antenne, substrat de dispositif d'affichage, unité d'affichage à cristaux liquides, système d'affichage, procédé de fabrication d'un dispositif d'antenne et procédé de fabrication d'un substrat de dispositif d'affichage
WO2009116177A1 (fr) * 2008-03-21 2009-09-24 株式会社島津製作所 Dispositif à matrice optique

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