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WO2013181905A1 - Transistor, substrat à réseau et procédé de fabrication de celui-ci, panneau à cristaux liquides et dispositif d'affichage - Google Patents

Transistor, substrat à réseau et procédé de fabrication de celui-ci, panneau à cristaux liquides et dispositif d'affichage Download PDF

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Publication number
WO2013181905A1
WO2013181905A1 PCT/CN2012/085561 CN2012085561W WO2013181905A1 WO 2013181905 A1 WO2013181905 A1 WO 2013181905A1 CN 2012085561 W CN2012085561 W CN 2012085561W WO 2013181905 A1 WO2013181905 A1 WO 2013181905A1
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WO
WIPO (PCT)
Prior art keywords
layer
silicon oxynitride
thin film
film transistor
array substrate
Prior art date
Application number
PCT/CN2012/085561
Other languages
English (en)
Chinese (zh)
Inventor
谢振宇
张文余
徐少颖
李田生
阎长江
Original Assignee
北京京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 北京京东方光电科技有限公司 filed Critical 北京京东方光电科技有限公司
Publication of WO2013181905A1 publication Critical patent/WO2013181905A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • Embodiments of the present invention relate to an oxide thin film transistor (oxide TFT), an array substrate, and a method of fabricating the same, and to a liquid crystal panel and a display device prepared by using the oxide thin film transistor. Background technique
  • oxide thin film transistors usually include bottom gate type TFTs and top gate type TFTs, bottom gate type
  • the structure of the TFT is as shown in FIG. 1.
  • a gate electrode 2, a gate insulating layer 3, an oxide semiconductor layer 4, an etch barrier layer 5, a source/drain metal layer 6, and a passivation layer 7 are formed on the glass substrate 1, a gate electrode 2, a gate insulating layer 3, an oxide semiconductor layer 4, an etch barrier layer 5, a source/drain metal layer 6, and a passivation layer 7 are formed.
  • the gate 2 is formed at the bottom of the thin film transistor.
  • the structure of the top gate type TFT is as shown in FIG. 12, and a layer structure of an active/drain metal layer 6, an oxide semiconductor layer 4, a gate insulating layer 3, a gate electrode 2, and the like is formed on the glass substrate 1, wherein the gate electrode 2 is formed.
  • the characteristics of the oxide thin film transistor are affected by various factors such as the characteristics of the material of the gate insulating layer 3 and the etch barrier layer 5, and the like.
  • the semiconductor characteristics of the IGZO thin film further affect the stability of the oxide thin film transistor, for example, the drift value of the turn-on voltage becomes large.
  • an insulating layer having a low hydrogen content is usually used to reduce the influence of hydrogen ions on the oxide semiconductor layer, for example, an insulating layer formed of a material such as alumina or silicon oxide, but at the same time It also brings the drawbacks of complicated processes, and the etching of the silicon oxide film is difficult and the etching rate is low.
  • the present invention provides an oxide thin film transistor and a method of fabricating the same for improving the characteristics of an oxide thin film transistor and improving the stability of an oxide thin film transistor by a simple process.
  • the present invention includes an array substrate prepared by an oxide thin film transistor, a liquid crystal panel, and a display device.
  • An aspect of the present invention provides an oxide thin film transistor including an oxide semiconductor layer and a gate An insulating layer, the gate insulating layer comprising a silicon oxynitride layer of a silicon oxynitride material, the silicon oxynitride layer contacting the oxide semiconductor layer.
  • the above oxide thin film transistor may further include an etch barrier layer formed on the oxide semiconductor layer, the etch barrier layer including a silicon oxynitride material.
  • the silicon oxynitride material is formed by a silicon nitride material treated by an oxidation process.
  • an array substrate including a substrate and an oxide thin film transistor, the oxide thin film transistor including an oxide semiconductor layer and a gate insulating layer, the gate insulating layer including oxynitride of a silicon oxynitride material A silicon layer, the silicon oxynitride layer contacting the oxide semiconductor layer.
  • the oxide thin film transistor may further include an etch barrier layer formed on the oxide semiconductor layer, and the etch barrier layer includes a silicon oxynitride material.
  • the silicon oxynitride material may be formed by a silicon nitride material treated by an oxidation process.
  • a gate layer is formed on the substrate, and a gate insulating layer is covered on the substrate on which the gate layer is formed, and an oxide semiconductor layer, an etch barrier layer, and the gate insulating layer are formed on the gate insulating layer.
  • a source/drain electrode layer of the source electrode and the drain electrode, a passivation layer having a via hole formed on the source/drain electrode layer, and a pixel electrically connected to the drain electrode through the via hole is formed on the passivation layer electrode.
  • the silicon oxynitride layer and the etch stop layer of the array substrate of the present invention may each have a thickness of 300-1000 A; preferably, the silicon oxynitride layer and the etch stop layer have a thickness of 400 to 600 ⁇ , respectively.
  • the molar ratio of oxygen, silicon, and nitrogen in the silicon oxynitride material may be 1: 0.5-3: 0.5-4.
  • Still another aspect of the present invention provides a method of producing the above oxide thin film transistor, which comprises the steps of forming a silicon nitride layer of a silicon nitride material and then oxidizing part or all of the silicon nitride material to form a silicon oxynitride material.
  • oxygen ions are implanted into a silicon nitride material by an ion implantation apparatus, thereby oxidizing the silicon nitride material to form a silicon oxynitride material.
  • the silicon oxynitride layer can be formed by an oxidation process.
  • the oxidation process is performed by ionization using a dry etching apparatus or an ion implantation apparatus.
  • the oxidation process parameters such as power, gas pressure, and oxygen flow rate vary depending on the equipment used.
  • the power when using TFT-LCD 5G equipment (SE-1300T, dry etching equipment), the power can be For 1000W ⁇ 15000W, the air pressure can be 20mtorr ⁇ 500mtorr, the oxygen flow rate can be 100 sccm ⁇ 5000sccm, the inert gas can be He, Ar, etc., and the flow rate can be 500sccm ⁇ 3000sccm.
  • the ion implantation apparatus ionizes oxygen into oxygen ions and injects it onto the surface of the gate insulating layer or the surface of the etching barrier layer, and the power can be set to 1000 W to 10000 W.
  • the air pressure can be set to 20mtorr ⁇ 300mtorr, and the oxygen flow rate can be set to 50sccm ⁇ 3000sccm.
  • an annealing process is performed after oxidizing a silicon nitride layer to form a silicon oxynitride layer, and the formed silicon oxynitride layer is optimized.
  • the annealing process can be carried out at 200 ° C to 500 ° C for 0.5 to 1 hour.
  • Still another aspect of the present invention provides a liquid crystal panel including the above array substrate.
  • Yet another aspect of the present invention provides a display device including the above array substrate.
  • FIG. 1 is a schematic structural view of a bottom gate type oxide thin film transistor in the prior art
  • FIG. 2 is a schematic view showing an example of the structure of an oxide thin film transistor of the present invention.
  • Figure 3 is a schematic view showing the formation of a gate electrode on a glass substrate
  • Figure 4 is a schematic view showing the formation of a gate insulating layer on the gate
  • Figure 5 is a view showing a state in which a surface layer portion of a gate insulating layer is formed into a silicon oxynitride layer by an oxidation process
  • Figure 6 is a schematic view showing the deposition of an oxide semiconductor layer by magnetron sputtering
  • Figure 7 is a schematic view showing the deposition of an etch barrier layer
  • Figure 8 is a schematic view showing the formation of a source/drain metal layer
  • Figure 9 is a schematic view showing the etching barrier layer as a whole after forming a silicon oxynitride layer by an oxidation process
  • Figure 10 is a schematic view showing the formation of a passivation layer
  • Figure 11 is a schematic view showing the formation of via holes
  • Figure 12 is a schematic view showing a top gate type oxide thin film transistor in the prior art
  • Fig. 13 is a view showing another example of the structure of the oxide thin film transistor of the present invention. detailed description
  • an oxide thin film transistor includes an oxide semiconductor layer 4 and a gate insulating layer 3, and the gate insulating layer 3 includes a silicon oxynitride layer 9 of a silicon oxynitride material, and the silicon oxynitride layer 9 is in contact.
  • the oxide thin film transistor may be a bottom gate type TFT.
  • the oxide thin film transistor may have a gate electrode 2, a gate insulating layer 3, an oxide semiconductor layer 4, and a gate electrode sequentially formed on the substrate.
  • the oxide thin film transistor may sequentially form an active/drain metal layer 6, an oxide semiconductor layer 4, a gate insulating layer 3, and a gate electrode 2 on a glass substrate. Equal layer structure.
  • the bottom gate type oxide thin film transistor may further include an etch stop layer 10 formed on the oxide semiconductor layer 4, and the etch stop layer 10 is a silicon oxynitride material.
  • the silicon oxynitride material may be formed by processing a silicon nitride material through an oxidation process.
  • the present invention also relates to an array substrate including a substrate 1 and an oxide thin film transistor, the oxide thin film transistor including an oxide semiconductor layer 4 and a gate insulating layer 3, and the gate insulating layer 3 includes A silicon oxynitride layer 9 of a silicon oxynitride material, the silicon oxynitride layer 9 contacting the oxide semiconductor layer 4.
  • the oxide thin film transistor may further include an etch barrier layer 10 formed on the oxide semiconductor layer 4, and the etch barrier layer 10 may be a silicon oxynitride material.
  • the silicon oxynitride material may be formed by a silicon nitride material treated by an oxidation process.
  • the structure of the array substrate of the present invention may be, for example, forming a gate layer on the substrate 1, covering the gate insulating layer 3 on the substrate 1 on which the gate layer is formed, and then forming an oxide semiconductor on the gate insulating layer 3.
  • a bulk layer 4 an etch stop layer 10, and a source/drain electrode layer 6 having source and drain electrodes, a passivation layer 7 having via holes formed on the source/drain electrode layer 6, and a passivation layer 7
  • a pixel electrode 8 electrically connected to the drain electrode through the via hole is formed.
  • the thickness of the silicon oxynitride layer 9 and the etch stop layer 10 of the array substrate of the present invention may each be 300-1000 A.
  • the silicon oxynitride layer 9 and the etch stop layer 10 have a thickness of 400 to 600 ⁇ , respectively.
  • the molar ratio of oxygen, silicon and nitrogen in the silicon oxynitride material may be 1: 0.5-3: 0.5-4.
  • the present invention also relates to a method of fabricating the above oxide thin film transistor, the method comprising the steps of forming a silicon nitride layer of a silicon nitride material and then oxidizing the silicon nitride material to form a silicon oxynitride material.
  • the present invention also relates to a method of fabricating the above array substrate, the method comprising the steps of forming a silicon nitride layer of a silicon nitride material and then oxidizing the silicon nitride material to form a silicon oxynitride material.
  • oxygen ions are implanted into a silicon nitride material by an ion implantation apparatus to oxidize the silicon nitride material to form a silicon oxynitride material.
  • the silicon oxynitride material can be formed by an oxidation process.
  • the oxidation process is performed by ionization using a dry etching apparatus or an ion implantation apparatus.
  • the oxidation process parameters such as power, gas pressure, and oxygen flow rate vary depending on the equipment used. For example, when using TFT-LCD 5G equipment (SE-1300T, dry etching equipment), the power can be 1000W.
  • the gas pressure can be 20mtorr ⁇ 500mtorr
  • the oxygen flow rate can be lOOsccm ⁇ 5000sccm
  • the inert gas can be He, Ar, etc.
  • the flow rate can be 500sccm ⁇ 3000sccm.
  • the ion implantation apparatus When an ion implantation apparatus is used for the oxidation process, the ion implantation apparatus ionizes oxygen into oxygen ions and injects it into the surface of the gate insulating layer or etches the barrier layer.
  • the power can be set to 1000 W-10000 W, and the gas pressure can be set.
  • the oxygen flow rate can be set from 50sccm to 3000sccm.
  • an annealing process is performed after oxidizing the silicon nitride material to form a silicon oxynitride material to improve the properties of the formed silicon oxynitride material. For example, it can be placed at 200 ° C ⁇ 500 ° C for 0.5 ⁇ 1 hour for the annealing process.
  • the invention further relates to a liquid crystal panel comprising the above array substrate.
  • the present invention relates to a display device including the above array substrate.
  • the gate line and the gate electrode 2 may be a single layer film composed of a material selected from the group consisting of AlNd alloy, Al, Cu, Mo, MoW alloy, and Cr, or a composite composed of any two or more of the materials. membrane.
  • Step 2) As shown in FIG. 4, a gate insulating layer (ie, a silicon nitride layer) of silicon nitride having a silicon to nitrogen molar ratio of about 3:4 is prepared by plasma enhanced chemical vapor deposition. , the thickness is about 4000A.
  • Step 5) As shown in FIG. 7, plasma enhanced chemical vapor deposition is performed on the above oxide semiconductor layer 4 to form an etch barrier layer of a silicon nitride material having a silicon to nitrogen molar ratio of about 3:4 ( That is, the silicon nitride layer) 5 has a thickness of about 100A.
  • the source/drain metal layer 6 may be a single layer film composed of one material selected from the group consisting of AlNd, Al, Cu, Mo, MoW, and Cr, or may be composed of any two or more materials selected from the group consisting of Composite film.
  • Step 7) As shown in FIG. 9, the etching barrier layer 5 of the silicon nitride material is integrally formed as an etch stop layer 10 of a silicon oxynitride material by the same oxidation process as in the above step 3).
  • etch stop layer 10 Good performance a silicon oxynitride layer 10 having a thickness of about 2:1:2 in a silicon, oxygen, and nitrogen is formed.
  • Step 8) As shown in FIG. 10, a passivation layer 7 is prepared by plasma enhanced chemical vapor deposition, and a photoresist is applied, and a photoresist pattern of a via process is formed after exposure and development, and after dry etching The photoresist is stripped, as shown in Fig. 11, and via holes are formed.
  • Step 9) As shown in FIG. 2, the material of the pixel electrode 8 is deposited on the glass substrate on which the via hole is formed by magnetron sputtering, and the photoresist is coated, and the light of the pixel electrode layer is formed after exposure and development.
  • the photoresist pattern is formed, and after the wet etching, the photoresist is stripped to form the pixel electrode 8.
  • the oxide thin film transistor 1 shown in Fig. 2 is formed.
  • the oxide thin film transistor of Comparative Example 1 was formed by the same operation as in Example 1 except that the above steps 3) and 7) were not carried out.
  • the silicon oxynitride layer 9 and the silicon oxynitride layer 10 are not formed in the oxide thin film transistor.
  • the drift value of the oxide thin film transistor of the present invention is remarkably smaller than that of the conventional oxide thin film transistor, thereby improving the stability of the oxide thin film transistor.
  • the inventors believe that in the present invention, when the silicon nitride material is subjected to an oxidation process, oxygen is ionized into oxygen ions, and the generated oxygen ions are combined with hydrogen, silicon, and nitrogen in the silicon nitride material, thereby binding hydrogen. The movement of ions improves the characteristics of the oxide semiconductor layer 4, thereby improving the stability of the oxide thin film transistor.
  • the present invention is also applicable to other types of oxide thin film transistors other than the bottom gate type oxide thin film transistor, such as a top gate type oxide thin film transistor.
  • a top gate type oxide thin film transistor As shown in FIG. 13, it does not include an etch barrier layer, and the gate insulating layer 3 includes a silicon oxynitride layer 9 formed of a silicon oxynitride material, and the silicon oxynitride layer 9 contacts the oxide semiconductor layer 4.
  • the stability of the thus obtained top gate type oxide thin film transistor The same has been improved.
  • the manufacturing order of each part thereof needs to be adjusted accordingly.
  • the oxide thin film transistor and the method of fabricating the same according to the embodiments of the present invention can improve the characteristics of the oxide thin film transistor and improve the stability of the oxide thin film transistor.
  • dry etching equipment is used for oxidation treatment, the process can be simplified and the production cost can be reduced.

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  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

L'invention concerne un transistor, un substrat à réseau et un procédé de fabrication de celui-ci, un panneau à cristaux liquides, et un dispositif d'affichage. Le transistor est un transistor en couche mince à oxyde, et comprend une couche semi-conductrice d'oxyde (4) et une couche d'isolation de grille (3). La couche d'isolation de grille (3) comprend une couche d'oxynitrure de silicium (9) qui est faite d'un matériau en oxynitrure de silicium. La couche d'oxynitrure de silicium (9) adhère à la couche semi-conductrice d'oxyde (4). La présente invention peut améliorer de manière efficace les caractéristiques du transistor en couche mince à oxyde.
PCT/CN2012/085561 2012-06-06 2012-11-29 Transistor, substrat à réseau et procédé de fabrication de celui-ci, panneau à cristaux liquides et dispositif d'affichage WO2013181905A1 (fr)

Applications Claiming Priority (2)

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CN201210185116.8A CN102738243B (zh) 2012-06-06 2012-06-06 晶体管、阵列基板及其制造方法、液晶面板和显示装置
CN201210185116.8 2012-06-06

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CN102738243B (zh) * 2012-06-06 2016-07-06 北京京东方光电科技有限公司 晶体管、阵列基板及其制造方法、液晶面板和显示装置
CN103456745B (zh) * 2013-09-10 2016-09-07 北京京东方光电科技有限公司 一种阵列基板及其制备方法、显示装置
CN103744240A (zh) * 2013-12-27 2014-04-23 深圳市华星光电技术有限公司 阵列基板及用该阵列基板的液晶显示面板
CN104392928A (zh) * 2014-11-20 2015-03-04 深圳市华星光电技术有限公司 薄膜晶体管的制造方法
CN109244085A (zh) * 2018-09-27 2019-01-18 惠科股份有限公司 一种阵列基板及显示面板

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CN101572274A (zh) * 2009-05-26 2009-11-04 友达光电股份有限公司 一种具有刻蚀阻挡层的氧化物薄膜晶体管及其制备方法
CN101614896A (zh) * 2009-06-22 2009-12-30 友达光电股份有限公司 薄膜晶体管数组基板、显示面板、液晶显示装置及其制作方法
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CN101614896A (zh) * 2009-06-22 2009-12-30 友达光电股份有限公司 薄膜晶体管数组基板、显示面板、液晶显示装置及其制作方法
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