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WO2013033943A1 - 薄膜晶体管基板及其制作方法 - Google Patents

薄膜晶体管基板及其制作方法 Download PDF

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Publication number
WO2013033943A1
WO2013033943A1 PCT/CN2011/081118 CN2011081118W WO2013033943A1 WO 2013033943 A1 WO2013033943 A1 WO 2013033943A1 CN 2011081118 W CN2011081118 W CN 2011081118W WO 2013033943 A1 WO2013033943 A1 WO 2013033943A1
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metal layer
thin film
film transistor
transistor substrate
minutes
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PCT/CN2011/081118
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English (en)
French (fr)
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郑文达
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深圳市华星光电技术有限公司
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Priority to US13/377,542 priority Critical patent/US8492767B2/en
Publication of WO2013033943A1 publication Critical patent/WO2013033943A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a thin film transistor substrate and a method of fabricating the same.
  • liquid crystal display has the advantages of high image quality, small volume, low power consumption and low radiation.
  • liquid crystal display technology liquid crystal displays are widely used in various fields.
  • Most of the conventional liquid crystal displays are provided with a thin film transistor substrate, a color filter substrate, and a liquid crystal layer disposed between the two substrates.
  • the thin film transistor substrate includes a substrate body and two metal layers on the disposed substrate, and another layer such as an insulating layer is further disposed between the two metal layers.
  • the two metal layers provided on the thin film transistor substrate are generally formed by physical vapor deposition of a metal plating film.
  • the metal layer produced in this way has defects in the lattice interface.
  • the metal in the metal layer may be crystallized due to the increase of temperature due to the defect of the lattice interface of the metal layer.
  • the direction of the interface defect is convex, forming a metal hillock, and the metal hillock can even penetrate the insulating layer, thereby causing a short circuit between the two metal layers in the case of energization.
  • a main object of the present invention is to provide a thin film transistor substrate and a method of manufacturing the same, which prevent lattice interface defects of a metal layer in a thin film transistor substrate and prevent occurrence of a metal layer hillock phenomenon.
  • the invention provides a method for manufacturing a thin film transistor substrate, comprising:
  • the thin film transistor substrate is annealed to rearrange the lattice of the first metal layer to prevent grain boundary defects in the first metal layer.
  • the method further comprises:
  • a scan line is formed on the first metal layer.
  • the above method further comprises:
  • the thin film transistor substrate is annealed to rearrange the lattice of the second metal layer to prevent grain boundary defects in the second metal layer.
  • the annealing the thin film transistor substrate to realign the lattice of the second metal layer further comprises:
  • a data line is formed on the second metal layer.
  • the annealing operation on the thin film transistor substrate is specifically:
  • the thin film transistor substrate is placed in a heating environment, and the temperature rising environment is controlled to be heated from 25 ° C to 400 ° C to 600 ° C in 30 minutes to 60 minutes;
  • the temperature-increasing environment is controlled to cool to 25 ° C at a constant rate in 60 minutes to 80 minutes.
  • the time for controlling the temperature rising environment to be uniformly heated from 25 ° C to 400 ° C to 600 ° C is 45 minutes.
  • the isolation layer comprises an insulating layer and a semiconductor layer, the insulating layer is disposed on the first metal layer, and the semiconductor layer is disposed between the insulating layer and the second metal layer.
  • the present invention further provides a thin film transistor substrate provided with a first metal layer, which is annealed after the first metal layer is formed thereon, so that the lattice of the first metal layer is rearranged.
  • the first metal layer is formed with a scan line, and the annealing process operation is performed after the scan line is formed on the first metal layer.
  • the thin film transistor substrate further includes:
  • An isolation layer and a second metal layer are sequentially disposed on the first metal layer. After the isolation layer and the second metal layer are disposed, the thin film transistor substrate is annealed to rearrange the lattice of the second metal layer.
  • the second metal layer is formed with a data line, and the annealing treatment operation after the second metal layer is disposed is performed after the data line is formed on the second metal layer.
  • the annealing process is specifically:
  • the thin film transistor substrate is placed in a heating environment, and the temperature rising environment is controlled to be heated from 25 ° C to 400 ° C to 600 ° C in 30-60 minutes;
  • the controlled temperature rise environment is cooled to 25 ° C at a constant rate from 60 minutes to 80 minutes.
  • the temperature for controlling the temperature rising environment is uniformly increased from 25 ° C to 400 ° C to 600 ° C for 45 minutes.
  • the isolation layer comprises an insulating layer and a semiconductor layer, the insulating layer is disposed on the first metal layer, and the semiconductor layer is disposed between the insulating layer and the second metal layer.
  • the thin film transistor substrate After forming the first metal layer on the thin film transistor substrate, the thin film transistor substrate is sequentially annealed to rearrange the lattice of the first metal layer; effectively preventing the first metal layer from generating grain boundary defects, thereby effectively The occurrence of the first metal layer hillock phenomenon is prevented.
  • FIG. 1 is a flow chart showing a method of manufacturing a thin film transistor substrate of the present invention
  • FIG. 2 is a schematic view showing the structure of a thin film transistor substrate of the present invention.
  • the method for manufacturing the thin film transistor substrate specifically includes: after providing a first metal layer on the thin film transistor substrate, annealing the thin film transistor substrate to rearrange the lattice of the first metal layer to prevent the first metal layer from being generated Grain boundary defects.
  • the thin film transistor further includes a process of forming a scan line on the first metal layer before performing the annealing process.
  • the scanning line is formed by exposing the first metal layer to exposure.
  • the formation of the first metal layer on the thin film transistor substrate is generally formed by physical vapor deposition.
  • the first metal layer formed in this way often has lattice interface defects, and in the subsequent high-temperature process or in the high-temperature environment, it is easy to squeeze out the defects of the metal from the lattice interface due to excessive temperature.
  • the thin film transistor substrate is annealed to rearrange the lattice of the first metal layer, and after the lattice is rearranged, the lattice interface defects of the first metal layer can be largely eliminated. Thereby, it is possible to prevent or reduce the occurrence of hillock phenomenon in the portion where the first metal layer forms the scanning line.
  • the lattice of the first metal layer may be detected, and if there is no lattice interface defect, the process proceeds directly to the next process. If there is a lattice interface defect, the lattice interface defect is repaired and then proceeds to the next process.
  • the embodiment of the method for manufacturing a thin film transistor substrate further includes the following steps: after the isolation layer and the second metal layer are sequentially disposed on the first metal layer, the thin film transistor substrate is annealed to make the second metal The lattice of the layers is rearranged to prevent grain boundary defects in the second metal layer.
  • the annealing the thin film transistor substrate to realign the lattice of the second metal layer further includes the following process: forming data on the second metal layer line.
  • the formation of the data line is performed by exposure etching of the second metal layer.
  • the thin film transistor substrate is annealed to rearrange the lattice of the second metal layer, and after the lattice is rearranged, the lattice interface defect of the second metal layer can be largely eliminated. Thereby, the lattice quality of the portion where the second metal layer forms the data line is improved.
  • the thin film transistor substrate is annealed, and the lattice of the second metal layer can be detected. If there is no lattice interface defect, the process proceeds directly to the next process. If there is a lattice interface defect, the lattice interface defect is repaired and then proceeds to the next process.
  • FIG. 1 is a flow chart of an embodiment of a method for fabricating a thin film transistor substrate of the present invention.
  • the annealing operation of the thin film transistor substrate is as follows:
  • Step S101 the thin film transistor substrate is placed in a temperature rising environment, and the temperature rising environment is controlled to be uniformly heated from 25 ° C to 400 ° C to 600 ° C in 30 minutes - 60 minutes;
  • Step S102 maintaining 400 ° C -600 ° C for 40-60 minutes;
  • Step S103 controlling the temperature rising environment to uniformly cool to 25 ° C in 60 minutes - 80 minutes.
  • the method for manufacturing a thin film transistor substrate is characterized in that the temperature for controlling the temperature rising environment is raised from a constant temperature of 25 ° C to 400 ° C to 600 ° C for 45 minutes.
  • the higher the temperature after the temperature rise the better the lattice rearrangement effect of the metal layer.
  • the isolation layer includes an insulating layer and a semiconductor layer, the insulating layer is disposed on the first metal layer, and the semiconductor layer is disposed between the insulating layer and the second metal layer.
  • the first metal layer and the second metal layer both overcome the lattice interface defects, thereby effectively overcoming the cause.
  • a lattice interface defect in which a portion of the scan line on the first metal layer is extruded from a lattice interface defect, and a phenomenon in which the isolation layer is connected to the second metal layer is formed; thereby effectively preventing the power from being applied, The occurrence of a short circuit phenomenon between the first metal layer and the second metal layer.
  • FIG. 2 is a schematic structural view of a thin film transistor substrate 100 of the present invention.
  • the thin film transistor substrate 100 is provided with a first metal layer 110, which is annealed after the first metal layer is formed thereon, so that the lattice of the first metal layer is rearranged.
  • the first metal layer is formed with a scan line, and the annealing process is performed after the scan line is formed on the first metal layer.
  • the formation of the first metal layer 110 on the thin film transistor substrate 100 is generally formed by physical vapor deposition.
  • the first metal 110 layer formed in this way often has lattice interface defects, and in the subsequent high-temperature process or in the use of a high-temperature environment, it is easy to be extruded from the defects of the lattice interface due to excessive temperature. .
  • the thin film transistor substrate 100 is annealed to rearrange the lattice of the first metal layer 110, and after the lattice is rearranged, the crystal of the first metal layer 110 can be largely eliminated.
  • the interface is defective, so that the portion of the first metal layer 110 forming the scan line can be prevented or reduced to cause a hillock phenomenon.
  • the lattice of the first metal layer 110 may be detected, and if there is no lattice interface defect, the process proceeds directly to the next process. If there is a lattice interface defect, the lattice interface defect is repaired and then proceeds to the next process.
  • the method further includes: an isolation layer and a second metal layer 130 sequentially disposed on the first metal layer 110, the thin film transistor substrate 100 being in the isolation layer and the second After the metal layer 130 is disposed, the lattice of the second metal layer 130 is rearranged by annealing.
  • the second metal layer 130 is formed with a data line, and the annealing processing operation after the second metal layer 130 is disposed is performed after the data line is formed on the second metal layer 130. .
  • the thin film transistor substrate 100 is annealed to rearrange the lattice of the second metal layer 130, and after the lattice is rearranged, the crystal of the second metal layer 130 can be largely eliminated.
  • the interface is deficient, thereby improving the lattice quality of the portion of the second metal 130 layer forming the data line.
  • the thin film transistor substrate 100 is annealed, and the lattice of the second metal layer 130 may be detected. If there is no lattice interface defect, the film is directly entered. A process. If there is a lattice interface defect, the lattice interface defect is repaired and then proceeds to the next process.
  • the annealing process is specifically: placing the thin film transistor substrate 100 in a heating environment, and controlling the temperature rising environment to increase the temperature from 25 ° C to 400 ° C in 30-60 minutes. 600 ° C; maintain 400 ° C -600 ° C for 40-60 minutes; control the temperature rising environment to cool at 25 ° C in 60 minutes to 80 minutes.
  • the time for controlling the temperature rising environment to be uniformly heated from 25 ° C to 400 ° C to 600 ° C is 45 minutes.
  • the isolation layer includes an insulating layer 121 and a semiconductor layer 122.
  • the insulating layer 121 is disposed on the first metal layer 110, and the semiconductor layer 122 is disposed on the insulating layer 121. Between the second metal layers 130.
  • the first metal layer 110 and the second metal layer 130 are both overcome the lattice interface defects. Further effectively overcomes the lattice interface defect, the metal in the portion of the scan line on the first metal layer 110 is extruded from the lattice interface defect, and passes through the isolation layer, so that the first metal layer 110 and the second metal layer 130 The occurrence of the connected phenomenon; thereby effectively preventing the occurrence of a short circuit between the first metal layer 110 and the second metal layer 130 under energization.

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Abstract

提供一种薄膜晶体管基板及其制造方法，制造方法包括：在薄膜晶体管基板上设置第一金属层后，对该薄膜晶体管基板进行退火处理，使该第一金属层的晶格重新排列，防止第一金属层产生晶界缺陷。通过在薄膜晶体管基板形成第一金属层后，对该薄膜晶体管基板依次进行退火处理，使第一金属层的晶格重新排列；有效地防止了第一金属层产生晶界缺陷，从而有效地防止了第一金属层小丘现象的发生。

Description

薄膜晶体管基板及其制作方法
技术领域
本发明涉及液晶显示技术领域，尤其是涉及一种薄膜晶体管基板及其制作方法。
背景技术
目前，使用液晶显示器已成为一种潮流。液晶显示器具有高画质、所占体积小、功率消耗低辐射小等优点。随着液晶显示器技术的日益成熟，使得液晶显示器广泛应用到各个领域中。现有的液晶显示器大都设有薄膜晶体管基板、彩色滤光片基板以及设置于两基板之间的液晶层。其中，薄膜晶体管基板包括基板本体和设置的基板上的两层金属层，该两层金属层之间还设置有绝缘层等其他层。
其中，上述薄膜晶体管基板设置的两层金属层，一般通过物理气相沉积金属镀膜的方式形成。采用这种方式产生的金属层存在晶格界面的缺陷，薄膜晶体管基板在后续的高温制程中，因金属层的晶格界面的缺陷，金属层中的金属可能因温度的升高而向晶格界面缺陷的方向凸起，形成金属小丘，该金属小丘甚至可穿透绝缘层，从而导致在通电的情况下两金属层产生短路现象。
发明内容
本发明的主要目的在于提供一种薄膜晶体管基板及其制造方法，防止薄膜晶体管基板中金属层的晶格界面缺陷，防止金属层小丘现象的发生。
本发明提出一种薄膜晶体管基板的制造方法，包括：
在薄膜晶体管基板上设置第一金属层后，对该薄膜晶体管基板进行退火处理，使该第一金属层的晶格重新排列，防止第一金属层产生晶界缺陷。
优选地，所述对该薄膜晶体管基板进行退火处理之前还包括：
在第一金属层上形成扫描线。
优选地，上述方法还包括：
在所述第一金属层上依次设置隔离层和第二金属层后，对该薄膜晶体管基板进行退火处理，使该第二金属层的晶格重新排列，防止第二金属层产生晶界缺陷。
优选地，所述对该薄膜晶体管基板进行退火处理，使该第二金属层的晶格重新排列之前还包括：
在第二金属层上形成数据线。
优选地，所述对薄膜晶体管基板进行退火操作具体为：
将薄膜晶体管基板置于升温环境中，控制升温环境在30分钟-60分钟内由25℃匀速升温至400℃-600℃；
保持400℃-600℃40-60分钟；
控制升温环境在60分钟-80分钟内匀速降温至25℃。
优选地，控制升温环境由25℃匀速升温至400℃-600℃的时间为45分钟。
优选地，所述隔离层包括绝缘层和半导体层，绝缘层设置在第一金属层上，半导体层设置在绝缘层与第二金属层之间。
本发明另提出一种薄膜晶体管基板，设有第一金属层，所述薄膜晶体管基板在第一金属层成形于其上之后，经退火处理，使第一金属层的晶格被重新排列。
优选地，所述第一金属层形成有扫描线，所述退火处理操作在第一金属层上形成扫描线之后执行。
优选地，上述薄膜晶体管基板还包括：
依次设置在所述第一金属层上的隔离层和第二金属层，该薄膜晶体管基板在隔离层和第二金属层设置后，经退火处理，使第二金属层的晶格被重新排列。
优选地，所述第二金属层形成有数据线，所述在设置第二金属层后的退火处理操作，在第二金属层上形成数据线之后执行。
优选地，所述退火处理的工艺具体为：
将薄膜晶体管基板置于升温环境中，控制升温环境在30-60分钟内由25℃匀速升温至400℃-600℃；
保持400℃-600℃40-60分钟；
控制升温环境在60分钟至80分钟内匀速降温至25℃。
优选地，所述退火处理的工艺中，控制升温环境由25℃匀速升温至400℃-600℃的时间为45分钟。
优选地，所述隔离层包括绝缘层和半导体层，绝缘层设置在第一金属层上，半导体层设置在绝缘层与第二金属层之间。
本发明通过在薄膜晶体管基板形成第一金属层后，对该薄膜晶体管基板依次进行退火处理，使第一金属层的晶格重新排列；有效地防止了第一金属层产生晶界缺陷，从而有效地防止了第一金属层小丘现象的发生。
附图说明
图1是本发明的薄膜晶体管基板的制造方法流程图；
图2是本发明的薄膜晶体管基板的结构示意图。
本发明目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
提出本发明一种薄膜晶体管基板的制造方法一实施例。该薄膜晶体管基板的制造方法，具体包括：在薄膜晶体管基板上设置第一金属层后，对该薄膜晶体管基板进行退火处理，使该第一金属层的晶格重新排列，防止第一金属层产生晶界缺陷。
进一步地，上述薄膜晶体管基板的制造方法实施例中，所述对薄膜晶体管进行退火处理之前还包括如下处理：在第一金属层上形成扫描线。该扫描线的形成是第一金属层经过曝光蚀刻而成。
本发明中，在薄膜晶体管基板上形成第一金属层一般采用物理气相沉积的方式形成。采用这种方式形成的第一金属层常常会存在晶格界面缺陷，在后续的高温制程或在高温环境下使用的过程中，容易因温度过高金属从晶格界面存在缺陷处挤压出来。尤其是在第一金属层上形成的扫描线部分，容易形成凸起部，即产生小丘现象。通过本实施例在形成第一金属层，对薄膜晶体管基板进行退火操作，使第一金属层的晶格重新排列，晶格重新排列后，可以大大地消除第一金属层的晶格界面缺陷，从而可以防止或减少第一金属层形成扫描线的部分产生小丘现象。
另外，本实施例中，在对薄膜晶体管基板进行退火操作后，还可以对第一金属层的晶格进行检测，若不存在晶格界面缺陷，则直接进入下一制程。若存在晶格界面缺陷，则进行晶格界面缺陷修补，然后进入下一制程。
进一步地，上述薄膜晶体管基板的制造方法实施例还包括如下处理：在所述第一金属层上依次设置隔离层和第二金属层后，对该薄膜晶体管基板进行退火处理，使该第二金属层的晶格重新排列，防止第二金属层产生晶界缺陷。
进一步地，上薄膜晶体管基板的制造方法实施例中，所述对该薄膜晶体管基板进行退火处理，使该第二金属层的晶格重新排列之前还包括如下处理：在第二金属层上形成数据线。该数据线的形成是第二金属层经过曝光蚀刻而成。
本实施例中在形成第二金属层后，对薄膜晶体管基板进行退火操作，使第二金属层的晶格重新排列，晶格重新排列后，可以大大地消除第二金属层的晶格界面缺陷，从而达到改善第二金属层形成数据线的部分的晶格质量。
另外，本实施例中，对设置第二金属层后薄膜晶体管基板进行退火操作后，还可以对第二金属层的晶格进行检测，若不存在晶格界面缺陷，则直接进入下一制程。若存在晶格界面缺陷，则进行晶格界面缺陷修补，然后进入下一制程。
进一步地，参见图1，图1是本发明薄膜晶体管基板的制造方法实施例中的一流程图。上述薄膜晶体管基板的制造方法实施例中，所述对薄膜晶体管基板进行退火操作具体如下：
步骤S101、将薄膜晶体管基板置于升温环境中，控制升温环境在30分钟-60分钟内由25℃匀速升温至400℃-600℃；
步骤S102、保持400℃-600℃40-60分钟；
步骤S103、控制升温环境在60分钟-80分钟内匀速降温至25℃。
进一步地，所述薄膜晶体管基板的制造方法，其特征在于，控制升温环境由25℃匀速升温至400℃-600℃的时间为45分钟。
本实施例中，退火过程中，升温后的温度越高金属层的晶格重排效果越好。
进一步地，上述薄膜晶体管基板的制造方法实施例中，所述隔离层包括绝缘层和半导体层，绝缘层设置在第一金属层上，半导体层设置在绝缘层与第二金属层之间。
本实施例中，由于在形成第一金属层和形成第二金属层后都对薄膜晶体管进行退火操作，使第一金属层和第二金属层都克服晶格界面缺陷，进而有效地克服了因晶格界面缺陷，第一金属层上扫描线的部分中金属从晶格界面缺陷处挤出，并穿过隔离层与第二金属层相连现象的发生；从而有效地防止了在通电情况下，第一金属层与第二金属层短路现象的发生。
参见图2，图2是本发明的薄膜晶体管基板100的结构示意图。薄膜晶体管基100设有第一金属层110，所述薄膜晶体管基板在第一金属层成形于其上之后，经退火处理，使第一金属层的晶格被重新排列。
进一步地，上述薄膜晶体管基板实施例中，所述第一金属层形成有扫描线，所述退火处理操作在第一金属层上形成扫描线之后执行。
本发明中，在薄膜晶体管基板100上形成第一金属层110一般采用物理气相沉积的方式形成。采用这种方式形成的第一金属110层常常会存在晶格界面缺陷，在后续的高温制程或在高温环境下的使用过程中，容易因温度过高金属从晶格界面存在缺陷处挤压出来。尤其是在第一金属层110上形成的扫描线部分，容易形成凸起部，即产生小丘现象。通过本实施例在形成第一金属层110，对薄膜晶体管基板100进行退火操作，使第一金属层110的晶格重新排列，晶格重新排列后，可以大大地消除第一金属层110的晶格界面缺陷，从而可以防止或减少第一金属层110形成扫描线的部分产生小丘现象。
另外，本实施例中，在对薄膜晶体管基板100进行退火操作后，还可以对第一金属层110的晶格进行检测，若不存在晶格界面缺陷，则直接进入下一制程。若存在晶格界面缺陷，则进行晶格界面缺陷修补，然后进入下一制程。
进一步地，参见图2，上述薄膜晶体管基板实施例中，还包括：依次设置在所述第一金属层110上的隔离层和第二金属层130，该薄膜晶体管基板100在隔离层和第二金属层130设置后，经退火处理，使第二金属层130的晶格被重新排列。
进一步地，上述薄膜晶体管基板100实施例，所述第二金属层130形成有数据线，所述在设置第二金属层130后的退火处理操作，在第二金属层130上形成数据线之后执行。
本实施例中在形成第二金属层130后，对薄膜晶体管基板100进行退火，使第二金属层130的晶格重新排列，晶格重新排列后，可以大大地消除第二金属层130的晶格界面缺陷，从而达到改善第二金属130层形成数据线的部分的晶格质量。
另外，本实施例中，对设置第二金属层130后薄膜晶体管基板100进行退火操作后，还可以对第二金属层130的晶格进行检测，若不存在晶格界面缺陷，则直接进入下一制程。若存在晶格界面缺陷，则进行晶格界面缺陷修补，然后进入下一制程。
进一步地，上述薄膜晶体管基板100实施例中，所述退火处理的工艺具体为：将薄膜晶体管基板100置于升温环境中，控制升温环境在30-60分钟内由25℃匀速升温至400℃-600℃；保持400℃-600℃40-60分钟；控制升温环境在60分钟至80分钟内匀速降温至25℃。
进一步地，上述薄膜晶体管基板100实施例，所述退火处理的工艺中，控制升温环境由25℃匀速升温至400℃-600℃的时间为45分钟。
进一步地，参见图2，上述薄膜晶体管基板100实施例中，所述隔离层包括绝缘层121和半导体层122，绝缘层121设置在第一金属层110上，半导体层122设置在绝缘层121与第二金属层130之间。
本实施例中，由于在形成第一金属层110和形成第二金属层130后都对薄膜晶体管基板100进行退火操作，使第一金属层110和第二金属层130都克服晶格界面缺陷，进而有效地克服了因晶格界面缺陷，第一金属层110上扫描线的部分中金属从晶格界面缺陷处挤出，并穿过隔离层，使第一金属层110与第二金属层130相连现象的发生；从而有效地防止了在通电情况下，第一金属层110与第二金属层130短路现象的发生。
应当理解的是，以上仅为本发明的优选实施例，不能因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (18)

  1. 一种薄膜晶体管基板的制造方法，其特征在于，包括：
    在薄膜晶体管基板上设置第一金属层后，对该薄膜晶体管基板进行退火处理，使该第一金属层的晶格重新排列，防止第一金属层产生晶界缺陷。
  2. 根据权利要求1所述的薄膜晶体管基板的制造方法，其特征在于，所述对该薄膜晶体管基板进行退火处理之前还包括：
    在第一金属层上形成扫描线。
  3. 根据权利要求2所述的薄膜晶体管基板的制造方法，其特征在于，所述对薄膜晶体管基板进行退火操作具体为：
    将薄膜晶体管基板置于升温环境中，控制升温环境在30分钟-60分钟内由25℃匀速升温至400℃-600℃；
    保持400℃-600℃40-60分钟；
    控制升温环境在60分钟-80分钟内匀速降温至25℃。
  4. 根据权利要求3所述的薄膜晶体管基板的制造方法，其特征在于，控制升温环境由25℃匀速升温至400℃-600℃的时间为45分钟。
  5. 根据权利要求1所述的薄膜晶体管基板的制造方法，其特征在于，还包括：
    在所述第一金属层上依次设置隔离层和第二金属层后，对该薄膜晶体管基板进行退火处理，使该第二金属层的晶格重新排列，防止第二金属层产生晶界缺陷。
  6. 根据权利要求5所述的薄膜晶体管基板的制造方法，其特征在于，所述对该薄膜晶体管基板进行退火处理，使该第二金属层的晶格重新排列之前还包括：
    在第二金属层上形成数据线。
  7. 根据权利要求6所述的薄膜晶体管基板的制造方法，其特征在于，在所述第一金属层上依次设置隔离层和第二金属层后，对薄膜晶体管基板进行退火操作具体为：
    将薄膜晶体管基板置于升温环境中，控制升温环境在30分钟-60分钟内由25℃匀速升温至400℃-600℃；
    保持400℃-600℃40-60分钟；
    控制升温环境在60分钟-80分钟内匀速降温至25℃。
  8. 根据权利要求7所述的薄膜晶体管基板的制造方法，其特征在于，控制升温环境由25℃匀速升温至400℃-600℃的时间为45分钟。
  9. 根据权利要求5所述的薄膜晶体管基板的制造方法，其特征在于，所述隔离层包括绝缘层和半导体层，绝缘层设置在第一金属层上，半导体层设置在绝缘层与第二金属层之间。
  10. 一种薄膜晶体管基板，设有第一金属层，其特征在于，所述薄膜晶体管基板在第一金属层成形于其上之后，经退火处理，使第一金属层的晶格被重新排列。
  11. 根据权利要求10所述的薄膜晶体管基板，其特征在于，所述第一金属层形成有扫描线，所述退火处理操作在第一金属层上形成扫描线之后执行。
  12. 根据权利要求11所述的薄膜晶体管基板，其特征在于，所述退火处理的工艺具体为：
    将薄膜晶体管基板置于升温环境中，控制升温环境在30-60分钟内由25℃匀速升温至400℃-600℃；
    保持400℃-600℃40-60分钟；
    控制升温环境在60分钟至80分钟内匀速降温至25℃。
  13. 根据权利要求12所述的薄膜晶体管基板，其特征在于，
    所述退火处理的工艺中，控制升温环境由25℃匀速升温至400℃-600℃的时间为45分钟。
  14. 根据权利要求10所述的薄膜晶体管基板，其特征在于，还包括：
    依次设置在所述第一金属层上的隔离层和第二金属层，该薄膜晶体管基板在隔离层和第二金属层设置后，经退火处理，使第二金属层的晶格被重新排列。
  15. 根据权利要求14所述的薄膜晶体管基板，其特征在于，所述第二金属层形成有数据线，所述在设置第二金属层后的退火处理操作，在第二金属层上形成数据线之后执行。
  16. 根据权利要求15所述的薄膜晶体管基板，其特征在于，所述在设置第二金属层后的退火处理工艺具体为：
    将薄膜晶体管基板置于升温环境中，控制升温环境在30-60分钟内由25℃匀速升温至400℃-600℃；
    保持400℃-600℃40-60分钟；
    控制升温环境在60分钟至80分钟内匀速降温至25℃。
  17. 据权利要求16所述的薄膜晶体管基板，其特征在于， 所述退火处理的工艺中，控制升温环境由25℃匀速升温至400℃-600℃的时间为45分钟。
  18. 根据权利要求14所述的薄膜晶体管基板，其特征在于， 所述隔离层包括绝缘层和半导体层，绝缘层设置在第一金属层上，半导体层设置在绝缘层与第二金属层之间。
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