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WO2013031130A1 - Dispositif de traitement d'informations, son procédé de contrôle d'accès et circuit intégré - Google Patents

Dispositif de traitement d'informations, son procédé de contrôle d'accès et circuit intégré Download PDF

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Publication number
WO2013031130A1
WO2013031130A1 PCT/JP2012/005211 JP2012005211W WO2013031130A1 WO 2013031130 A1 WO2013031130 A1 WO 2013031130A1 JP 2012005211 W JP2012005211 W JP 2012005211W WO 2013031130 A1 WO2013031130 A1 WO 2013031130A1
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WO
WIPO (PCT)
Prior art keywords
attribute
access
processor
switching
permission
Prior art date
Application number
PCT/JP2012/005211
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English (en)
Japanese (ja)
Inventor
章郎 古賀
隆晃 今仲
貴司 大山
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パナソニック株式会社
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Publication of WO2013031130A1 publication Critical patent/WO2013031130A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/62—Protecting access to data via a platform, e.g. using keys or access control rules
    • G06F21/6218—Protecting access to data via a platform, e.g. using keys or access control rules to a system of files or objects, e.g. local or distributed file system or database

Definitions

  • the present invention relates to an information processing apparatus, and more particularly to a technique for controlling access to a device from a processor and peripheral circuits.
  • Such an information processing apparatus includes a management table for managing a memory address area accessible for each process, and an attribute register for storing attribute information indicating a process currently being executed by the processor.
  • a management table for managing a memory address area accessible for each process
  • an attribute register for storing attribute information indicating a process currently being executed by the processor.
  • peripheral circuits In order to reduce the processing load of the processor, a part of the processing is shared with peripheral circuits.
  • This peripheral circuit does not store information for identifying the process from which the process to be executed in response to a request from the processor is performed due to restrictions such as storage capacity. Therefore, when the peripheral circuit needs to access the memory device in the course of processing, the peripheral circuit refers to the value of the attribute register and receives a request as processing related to the process currently being executed by the processor. Assuming access to memory devices.
  • the process that requests the peripheral circuit to execute the process and the processor that is executed when the peripheral circuit actually accesses the device are executed.
  • the process may be different. For example, this is a case where the processor switches processes during processing in the peripheral circuit and the value of the attribute register is rewritten.
  • the peripheral circuit leads to the result that the access to the memory device that should be handled as the process of the process before switching is handled as the process of the process after switching. Then, an undesired operation in which access to the address is denied occurs.
  • An object of the present invention is to provide an information processing apparatus that suppresses the occurrence.
  • an information processing apparatus including an access target device accessed from a processor and a peripheral circuit, and switches and executes a plurality of internal processes having different attributes.
  • a processor that generates an access command including an attribute value for identifying the attribute and access content instruction information, and an attribute indicating an attribute of an internal process being executed by the processor
  • An attribute storage unit for storing information and an instruction to perform processing including access to the access target device are received from the processor, and when accessing the access target device, the attribute storage unit
  • a peripheral circuit that refers to the attribute information and generates an access command including an attribute value and access content instruction information;
  • An access that receives an access command generated by each of the processor and the peripheral circuit and performs access suppression control for the access target device according to the correspondence between the attribute indicated by the attribute value of the access command and the information of the access content instruction
  • the peripheral circuit causes the access control unit to output an access command that is not output related
  • the timing for switching the attribute related to the access control to the memory device is controlled, and the occurrence of an undesired operation when the peripheral circuit accesses the memory device is suppressed. Can do.
  • Functional block diagram of information processing apparatus 1 according to Embodiment 1 Data structure example of access command
  • Flow chart showing operation of access control processing in access control unit The figure which shows the flow of access from the peripheral circuit 20 of the information processing apparatus 1 to the device 30
  • Functional block diagram of the information processing apparatus 2 according to the second embodiment The flowchart which shows the operation
  • Embodiment 1 Hereinafter, an information processing apparatus 1 according to an embodiment of the present invention will be described.
  • FIG. 1 is a diagram illustrating a configuration of the information processing apparatus 1.
  • the information processing apparatus 1 includes a processor 10, a peripheral circuit 20, a device 30, and an access control apparatus 40.
  • the information processing apparatus 1 has a function of switching and operating two virtual machines as needed. Different OSs (Operating Systems) operate on the respective virtual machines, and the OS 1 operates on one virtual machine and the other virtual machine. In the above, OS2 operates. In this case, the attribute means information for identifying the virtual machine, that is, information for identifying “OS1” and “OS2”.
  • the access control unit prevents each OS process from affecting other OS processes.
  • the access range of the device 30 (for example, a memory device) is limited for each OS in which 44 is different, and whether access is permitted is determined. That is, in the access control unit 44, the address range permitted for access by the OS1 process is different from the address range permitted for access by the OS2 process.
  • the peripheral circuit 20 performs the processing requested by the processor 10 in order to reduce the processing load on the processor 10.
  • the peripheral circuit 20 is a circuit that performs general-purpose data processing. Whether the request received from the processor 10 is a request for processing executed by the OS 1 or a request for processing executed by the OS 2 due to restrictions on storage capacity or the like. Do not keep the information inside. For this reason, the access control device 40 includes an attribute storage unit 42, stores information for identifying whether the processor is operating in OS1 or OS2, and the peripheral circuit 20 is connected to the device 30 (for example, a memory device). When access is required, the information stored in the attribute storage unit 42 is referred to, and an access command including the attribute and the access destination address (for example, a Read command, a Write command, etc. for the access destination address) is generated. The device 30 is accessed as a process executed with the attribute indicated by the attribute storage unit 42.
  • the peripheral circuit 20 has not completed access to the device 30 generated in the process of executing the processing requested by the processor 10 while operating on the OS1.
  • the peripheral circuit 20 when the processor 10 rewrites the attribute value in the attribute storage unit 42 from OS1 to OS2, the peripheral circuit 20 generates an access command including OS2 that is the attribute value after switching, and accesses the device 30. Will do. For this reason, the access control unit 44 may be denied access by the access command generated by the peripheral circuit 20 after the attribute value is switched.
  • the processor 10 stops a request for a new process to the peripheral circuit 20 at the time of attribute switching, and sends a request for permission of attribute switching to the attribute switching control unit 41. Do.
  • the process in which the processor 10 switches from the OS1 process to the OS2 process and rewrites the attribute value in the attribute storage unit 42 is referred to as “attribute switching”.
  • the attribute switching control unit 41 controls the peripheral circuit 20, causes the access control unit 44 to output an access command related to the processing that the peripheral circuit 20 has already received from the processor 10, and if there is no access command output from the peripheral circuit 20.
  • the processor 10 is notified of permission of attribute switching.
  • the processor 10 switches the attribute after obtaining permission to switch the attribute.
  • the attribute switching control unit 41 permits the attribute switching by the processor 10 in accordance with the output status of the access command output from the peripheral circuit 20, so that the access from the peripheral circuit 20 to the device 30 is appropriate. It is possible to prevent the processing from being stopped.
  • processor 10 reads and executes a program stored in the memory.
  • the processor 10 has a function of generating an access command for the device 30 as necessary in the course of program execution, and outputting the generated access command to access the device 30.
  • the access command will be described later.
  • the processor 10 has a function of making a request for processing execution to the peripheral circuit 20 as necessary in the course of program execution.
  • the processor 10 has a function of executing processing by switching between OS1 and OS2.
  • the processor 10 stops the request for the peripheral circuit 20 to execute a new process and the access to the device 30, makes an attribute switching permission request to the attribute switching control unit 41,
  • the attribute value of the attribute storage unit 42 is rewritten.
  • the peripheral circuit 20 is a circuit that receives a processing execution request from the processor 10 and executes the processing.
  • the peripheral circuit 20 is, for example, a DSP (Digital Signal Processor), a DMA (Direct Memory Access) controller, an encryption / decryption circuit, or the like.
  • the peripheral circuit 20 When the peripheral circuit 20 needs to access the device 30 in the process execution process, the peripheral circuit 20 refers to the attribute value in the attribute storage unit 42, generates an access command including the attribute value, and outputs the access command, thereby outputting the access command. It has a function to access.
  • the peripheral circuit 20 includes a buffer 300.
  • the buffer 300 has a function of storing an address of an access destination for generating an access command generated in the process in which the peripheral circuit 20 receives a request from the processor 10.
  • processing waiting data data at the address stored in the buffer 300 in a state where the information indicating the attribute is not stored and is not completed as an access command
  • processing waiting data data at the address stored in the buffer 300 in a state where the information indicating the attribute is not stored and is not completed as an access command
  • processing wait access command The access command before being output to is called a “processing wait access command”.
  • the peripheral circuit 20 has a function of outputting the number of processing-waiting data stored in the buffer 300 to the state acquisition unit 43.
  • the device 30 is a device accessed from the processor 10 and the peripheral circuit 20 by an access command.
  • the device 30 is, for example, a memory device (for example, a DRAM (Dynamic Random Access Memory)).
  • the access command is received by an access control unit 44 described later, and the access control unit 44 In order to protect against unauthorized memory access, whether access to the device 30 is permitted or not is determined. Only when access is permitted by the access control unit 44, the processor 10 and the peripheral circuit 20 can read and write to the device 30.
  • FIG. 2 shows a configuration example of a data portion related to access permission determination in the access command access control unit 44.
  • the access command is further added with information for distinguishing a command such as a Read instruction or a Write instruction for the device 30, information indicating data to be written in the case of the Write instruction, and the like.
  • the access command includes an attribute 101 and an address 102.
  • the attribute 101 is an item for storing information indicating an attribute being executed by the information processing apparatus, and the peripheral circuit 20 sets an attribute value in the attribute 101 with reference to the attribute value in the attribute storage unit 42.
  • the address 102 is an item for storing an access destination address for the device 30.
  • the access control device 40 includes an attribute switching control unit 41, an attribute storage unit 42, a state acquisition unit 43, and an access control unit 44.
  • the access control device 40 is an integrated circuit (for example, LSI (Large Scale Integration)).
  • the functions of the attribute switching control unit 41, the state acquisition unit 43, and the access control unit 44 are realized by executing a program stored in the integrated circuit, which is the access control device 40, by a processor inside the integrated circuit.
  • the attribute switching control unit 41 receives an attribute switching permission request from the processor 10, and gives an access command to the peripheral circuit 20 to access the device 30 generated during the process currently being executed in the peripheral circuit 20. And has a function of outputting an access command not yet output to the access control unit 44.
  • the attribute switching control unit 41 has a function of determining whether or not to allow attribute switching based on the information acquired by the state acquisition unit 43 and outputting attribute switching permission to the processor 10 when the determination is positive. Have.
  • the attribute storage unit 42 is a storage element (for example, an attribute storage register) that stores an attribute value that is referred to when the peripheral circuit 20 generates an access command for accessing the device 30.
  • the attribute value in the attribute storage unit 42 is information for identifying an attribute, and is changed by the processor 10 when the processor 10 switches processing.
  • the attribute value is an OS identifier for specifying the OS.
  • the state acquisition unit 43 has a function of acquiring the number of data waiting for processing stored in the buffer 300 of the peripheral circuit 20 from the peripheral circuit 20.
  • the access control unit 44 receives the access command output from the processor 10 and the peripheral circuit 20, refers to the access control rule 200 stored therein, and based on the attribute 101 included in the access command and the address 102, the device 30 has a function of determining whether access to the address 30 is permitted or not, and performing control for suppressing access to the device 30.
  • FIG. 3 is a diagram showing a configuration and example contents of the access control rule 200.
  • the access control rule 200 is a table in which an attribute 201, a start address 202, and an end address 203 are recorded in association with each other.
  • the attribute 201 is an item for storing information for identifying the attribute of the information processing apparatus 1.
  • the start address 202 is an item for storing the start address of the address range of the device 30 that is permitted to be accessed.
  • the end address 203 is an item for storing the end address of the address range of the device 30 that is permitted to access. Access to addresses outside the range indicated by the start address 202 and the end address 203 is denied.
  • the processor 10 of the information processing apparatus 1 switches between the process A in the OS 1 and the process B in the OS 2, executes the process A in the OS 1, and performs device A to the peripheral circuit 20 during the execution of the process A.
  • a request is made to execute process A ′ that requires access to 30.
  • the peripheral circuit 20 that has received the request executes the process A ′.
  • the peripheral circuit 20 issues sequential access commands to the access control unit 44 during the process A ′.
  • the processing result in the processing A ′ in the peripheral circuit 20 is used in the processor 10 as follows, for example.
  • the peripheral circuit 20 writes the processing result in the processing A ′ into a specific address area of the device 30, and the processor 10 reads out the data written in the specific address area and uses it in the processing A.
  • the processor 10 When the information processing apparatus 1 receives an instruction to switch to the process B executed by the OS 2 from the user during the execution of such a process, the processor 10 interrupts the execution of the process A and executes the process B. Process to switch to.
  • the processor 10 When switching to the execution of the process B, the processor 10 first makes an attribute switching permission request to the attribute switching control unit 41. When the attribute switching is permitted from the attribute switching control unit 41, the processor 10 switches to the execution of the process B, and rewrites the attribute in the attribute storage unit 42 from OS1 to OS2 information.
  • FIG. 4 is a flowchart showing an operation of attribute switching control processing by the attribute switching control unit 41.
  • the attribute switching control unit 41 receives an attribute switching permission request from the processor 10 (step S10). Note that, after making an attribute switching permission request to the attribute switching control unit 41, the processor 10 interrupts the processing and enters a standby state until the attribute switching control unit 41 permits the attribute switching.
  • the attribute switching control unit 41 generates an access command for the peripheral circuit 20 from the processing-waiting data related to the processing that has already been executed in response to the request from the processor 10, and outputs the access command to the access control unit 44. That is, the peripheral circuit 20 is requested to complete the output of the processing waiting access command (step S11).
  • the peripheral circuit 20 sequentially outputs processing-waiting access commands according to the processing capabilities of the access control unit 44 and the device 30.
  • the state acquisition unit 43 acquires the number of data waiting for processing in the peripheral circuit 20 (step S12). Specifically, for example, when there is an instruction to output an access command from the attribute switching control unit 41, the peripheral circuit 20 stores processing waiting data in the buffer 300, and the state acquisition unit 43 waits for processing in the buffer 300. Count the number of data.
  • the attribute switching control unit 41 confirms the number of processing-waiting data acquired by the state acquisition unit 43 (step S13). If the number of data waiting for processing is not 0 (step S13: NO), the processing from step S12 is repeated.
  • step S13 when the number of data waiting to be processed is 0 (step S13: YES), the attribute switching control unit 41 outputs information for permitting attribute switching to the processor 10 (step S14).
  • the processor 10 that has received the information that permits the attribute switching from the attribute switching control unit 41 switches the process and rewrites the attribute value in the attribute storage unit 42.
  • FIG. 5 is a flowchart showing the operation of access suppression control processing by the access control unit 44.
  • the access control unit 44 receives the access command 100 output from the processor 10 and the peripheral circuit 20 (step S20).
  • the access control unit 44 extracts the attribute value described in the attribute 101 included in the access command 100 (step S21), and similarly extracts the value of the address described in the address 102 (step S22). ).
  • the access control unit 44 refers to the access control rule 200 stored therein, and the attribute whose address value extracted in step S22 is within the address range indicated by the start address 202 and the end address 203 of the access control rule.
  • a value is acquired (step S23). For example, if the address extracted from the access command 100 is 0x0000A000, this address is in the address range of 0x00000000 to 0x00FFFFFF, so the access control unit 44 uses the corresponding attribute according to the access control rule shown in FIG. The attribute value “OS1” is acquired.
  • the access control unit 44 compares the attribute value acquired from the access command 100 in step S21 with the attribute value acquired in step S23 (step S24). When the attribute values match (step S24: YES), the access control unit 44 sends the address of the device 30 indicated by the address value acquired in step S22 to the processor 10 and the peripheral circuit 20 that output the access command. Is permitted (step S25).
  • step S24 if the attribute values do not match (step S24: NO), the access control unit 44 provides the processor 10 and the peripheral circuit 20 that output the access command to the device 30 indicated by the address value acquired in step S22. Access to the address is denied (step S26).
  • FIG. 6 is a diagram illustrating an example of a flow of access from the peripheral circuit 20 to the device 30 in the information processing apparatus 1.
  • the peripheral circuit 20 receives a processing request from the processor 10 and accesses the device 30 in the course of the processing.
  • the access destination address of the device 30 is sent to the buffer 300, and the access control unit 44 and the device 30 are accessed.
  • the access commands are sequentially generated based on the addresses stored in the buffer 300 in accordance with the processing capability of the received data and sent to the access control unit 44.
  • a series of access destination addresses 1000 are accumulated in the buffer in the course of processing requested by the processor 10 whose attribute is operating in OS1.
  • Processor 10 makes an attribute switching permission request to attribute switching control unit 41 at time T1.
  • the three output commands 1001 to 1003 are output to the access control unit 44, and the remaining two addresses remain stored in the buffer 300.
  • Access commands 1004 to 1005 corresponding to this address are not output to the access control unit 44.
  • the attribute switching control unit 41 does not permit the attribute switching to the processor 10, so the attribute maintains the state of OS1.
  • the attribute switching control unit 41 permits the processor 10 to switch attributes. As described above, the attribute switching is performed not at time T1 but at time T2 when the access to be processed in the case of the attribute OS1 is completed.
  • FIG. 7 is a diagram illustrating an example of a flow of access from the peripheral circuit 20 to the device 30 when the attribute switching control unit 41 does not perform attribute switching control.
  • the access destination address for the device 30 is temporarily stored in the buffer 300, and the peripheral circuit 20 waits for the processing stored in the buffer 300. Access commands are sequentially generated from the data, and the generated access commands are output to the control unit 44.
  • the peripheral circuit 20 Assuming that the processor 10 switches the attribute from OS1 to OS2 at time T1 ′, in the example of FIG. 7, the peripheral circuit 20 generates access commands 1001 to 1003 by time T1 ′ and sends them to the access control unit 44. Output is complete. However, the two processing-waiting data stored in the buffer 300 (data indicating addresses 0x000001100 and 0x000001150 in the figure) are not generated as access commands by the time T1 'but are accumulated in the buffer 300. The peripheral circuit 20 generates an access command after the time T ⁇ b> 1 ′ and outputs it to the access control unit 44 for the two processing-waiting data. That is, access commands 1004b and 1005b in which “OS2” is written as attribute values in the attribute 101 of the access command are generated and output.
  • the access control apparatus that has received the access command 1004b refers to the access control rule 200 and, based on the address “0x000001100” included in the access command 1004b, as an attribute value of an attribute permitted to access the address “0x000001100” Obtain “OS1”. Since the acquired attribute value “OS1” is different from the attribute value “OS2” of the attribute included in the access command 1004b, access to the address “0x000001100” is denied. Similarly, the access command 1005b is also denied access to the address specified by the address “0x0001150”.
  • the peripheral circuit 20 executes the process before the processor 10 outputs the access command for accessing the device 30 that is generated in the course of the processing requested by the processor 10 while the processor 10 is executing OS1.
  • OS operating OS
  • OS2 access to an address to which access should be permitted is denied. That is, the peripheral circuit 20 cannot properly access the device 30.
  • the attribute switching control unit 41 does not permit the processor 10 to switch attributes unless there is no processing waiting data in the peripheral circuit 20. Before switching the attribute, the output of the access command from the peripheral circuit 20 to the device 30 related to the process before the switching is completed, and inappropriate access from the peripheral circuit 20 to the device 30 can be suppressed.
  • Second Embodiment> ⁇ 2-1. Overview>
  • the processor 10 when switching the attribute from the OS 1 to the OS 2, the processor 10 stops the process execution in the OS 1 to quickly switch the attribute, and sends the attribute to the attribute switching control unit 41. Make a switch permission request.
  • the processor 10 cannot be used until the attribute switching permission is obtained after the attribute switching permission request is made. That is, if the time period from when the attribute switching permission request is made until the attribute switching permission is obtained (hereinafter referred to as “waiting time”) is long, the utilization efficiency of the processor 10 is degraded.
  • the switching permission unit 45 permits output to the processor 10 when the number of data waiting for processing in the peripheral circuit 20 is equal to or less than a predetermined number.
  • the processor 10b makes the attribute switching permission request after the number of data waiting to be processed becomes equal to or less than the predetermined number, the time from the attribute switching permission request to the attribute switching can be shortened. Even if the processor 10b requests output permission, the processor 10b continues to perform the processing in the OS 1 before switching until the attribute switching request is made. Therefore, it is possible to suppress a decrease in utilization efficiency of the processor 10b.
  • FIG. 8 is a diagram illustrating a configuration of the information processing apparatus 2.
  • the information processing device 2 has the same basic configuration as the information processing device 1, but differs from the information processing device 1 in that the access control device further includes a switching permission unit 45.
  • the access control device provided with the switching permission unit 45 in the access control device 40 is referred to as an access control device 40b.
  • a processor 10b in which the function of the processor 10 is expanded is provided.
  • the processor 10 b has a function of outputting an output permission request to the switching permission unit 45 and receiving an output permission from the switching permission unit 45 before making an attribute switching permission request to the attribute switching control unit 41.
  • Peripheral circuit 20 and device 30 have the same configuration as in the first embodiment.
  • the access control device 40b is an integrated circuit.
  • the configuration other than the switching permission unit 45 of the access control device 40b is basically the same as that of the access control device 40. However, instead of the state acquisition unit 43, a state acquisition unit 43b in which the function of the state acquisition unit 43 is expanded is provided.
  • the state acquisition unit 43b has a function of outputting the number of processing-waiting data received from the peripheral circuit 20 to the switching permission unit 45.
  • the switching permission unit 45 receives an output permission request from the processor 10, determines whether or not to permit output based on the number of processing-waiting data obtained from the state acquisition unit 43 b, and sends the determination result to the processor 10. Has a function to reply.
  • the switching permission unit 45 has a function of preliminarily storing a threshold value used for determination of permission / prohibition of output permission in comparison with the number of processing-waiting data acquired from the state acquisition unit 43b.
  • the threshold value is determined based on the processing capability of the peripheral circuit 20, the access control unit 44, and the device 30, after the processor 10 b obtains output permission from the switching permission unit 45, and sends an attribute switching permission request to the attribute switching control unit 41.
  • This is determined based on the maximum number N of processing-waiting access commands that can be processed by the access control unit 44 during the shortest time required to complete the processing to be performed.
  • the threshold value is set to the same level as N
  • the processor 10b obtains output permission from the switching permission unit 45 and makes an attribute switching permission request to the attribute switching control unit 41
  • the processing waiting access command is The processor 10b can switch attributes in a short standby time.
  • the functions of the state acquisition unit 43b and the switching permission unit 45 are realized by a processor in the integrated circuit executing a program stored in the integrated circuit that is the access control device 40b.
  • the processor 10b makes a request for output permission to the switching permission unit 45, and the switching permission unit 45 transmits to the processor 10b. Then, a switching permission process for determining whether or not to permit output is performed.
  • the processor 10b After obtaining the output permission from the switching permission unit 45, the processor 10b performs processing from START (A) shown in FIG.
  • FIG. 9 is a flowchart showing the operation of the switching permission process in the switching permission unit 45.
  • the switching permission unit 45 receives an output permission request from the processor 10 (step S30).
  • the switching permission unit 45 acquires the number of data waiting for processing of the peripheral circuit 20 from the state acquisition unit 43b (step S31).
  • a specific acquisition method is the same as the method in step S13 of FIG.
  • the switching permission unit 45 compares the number of processing-waiting data acquired from the state acquisition unit 43b with a threshold value stored in advance in an internal memory (step S32). If the number of data waiting for processing is larger than the threshold (step S32: NO), the processing is repeated from step S31. On the other hand, when the number of data waiting for processing is equal to or less than the threshold (step S32: YES), the processor 10b is permitted to output (step S33).
  • the processor 10b continues the processing in the OS 1 even when an output permission request is sent to the switching permission unit 45, and receives the output permission from the switching permission unit 45 as an interrupt to the processor 10b.
  • the processor 10b continues the processing of START (A) in FIG.
  • the switching permission unit 45 switches the attribute according to the number of data waiting for processing in the peripheral circuit 20.
  • the timing of making the request can be adjusted.
  • the processor 10b performs an attribute switching process when the number of data waiting to be processed is equal to or less than a predetermined number, thereby making an attribute switching permission request to the attribute switching control unit 41 and then performing attribute switching. Since the time until permission is allowed can be shortened, processing can be performed efficiently.
  • the processing mode is either the first mode in which output permission is requested from the switching permission unit 45b or the second mode in which output permission is not requested from the switching permission unit 45b.
  • the information processing device 3 provided with the mode control unit 46 for determining whether or not the access control device 40c is provided will be described. Note that the process for determining which of the first and second processing modes is called “mode determination process”.
  • the example of the information processing apparatus 2 that suppresses the decrease in the utilization efficiency of the processor 10b by requesting attribute switching at the timing when the number of commands waiting to be processed becomes a predetermined number or less is shown.
  • the peripheral circuit 20 is not a process in which a large amount of processing-waiting data is not generated, for example, a process that is performed while frequently referring to the data of the device 30, but the data of the device 30 is read at the beginning of the process.
  • a dedicated circuit that performs processing performed inside 20 there is little need to request output permission to the switching permission unit 45b. This is because in such a case, it is unlikely that the processing state in the peripheral circuit 20 when the processor 10b attempts to switch the attribute is a state in which the number of commands waiting for processing exceeds a predetermined number. .
  • attribute switching processing is performed in the case where an attribute switching permission request is made to the attribute switching control unit 41 without making an output permission request to the switching permission unit 45, so that an output permission request is not made to the switching permission unit 45. This is because it is considered that there are many cases where this can be performed smoothly.
  • the information processing device 3 allows the user to set in advance in the mode storage unit 47 whether the processing mode is the first mode or the second mode according to the processing to be executed by the information processing device 3, and the processor
  • the mode determination unit 46 determines which processing mode is present based on the setting content of the mode storage unit 47. By doing in this way, it is possible to perform the processing for the attribute switching request in an appropriate processing mode according to the processing executed by the processor. Further, when operating in the second mode, the access control device 40c can stop the function of the switching permission unit 45b and reduce power consumption.
  • FIG. 10 is a diagram illustrating a configuration of the information processing apparatus 3.
  • the information processing device 3 has basically the same configuration as the information processing device 2, but differs from the information processing device 2 in that the access control device further includes a mode determination unit 46 and a mode storage unit 47.
  • the access control device obtained by adding the mode determination unit 46 and the mode storage unit 47 to the access control device 40b is defined as an access control device 40c.
  • processor 10b instead of the processor 10b, a processor 10c having an expanded function of the processor 10b is provided.
  • the processor 10c Before making the attribute switching permission request to the attribute switching control unit 41, the processor 10c makes a request for output permission to the mode determination unit 46 instead of the switching permission unit 45, and in the case of the first mode, the switching permission unit. In the case of the second mode, a function of receiving an output permission from the mode determination unit 46 via the mode determination unit 46 from 45b is provided.
  • the peripheral circuit 20 and the device 30 have the same configuration as in the second embodiment.
  • the access control device 40c includes a mode determination unit 46 and a mode storage unit 47 in addition to the configuration of the access control device 40b.
  • the access control device 40c is an integrated circuit.
  • the configuration other than the mode determination unit 46 and the mode storage unit 47 is basically the same as that of the access control device 40b.
  • a switching permission unit 45b obtained by expanding the function of the switching permission unit 45 is provided.
  • the switching permission unit 45b has a function of receiving an output permission request from the processor 10c when the mode determination unit 46 determines the first mode.
  • the mode determination unit 46 determines whether the processing mode is the first mode or the second mode based on information stored in a mode storage unit 47 described later. A function to determine is provided. When it is determined that the mode is the first mode, the output permission request received from the processor 10c is output to the switching permission unit 45b. When it is determined that the mode is the second mode, the processor 10c is permitted to output the function. Is provided.
  • the function of the mode determination unit 46 is realized by a processor stored in the integrated circuit serving as the access control device 40c being executed by a processor inside the integrated circuit.
  • the mode storage unit 47 is a non-volatile memory, and when the processor 10c switches from the process executed by the OS1 to the process executed by the OS2, the first mode in which an output permission request is made to the switching permission unit 45b, and the output A function of storing mode information indicating which processing mode is in the second mode in which no permission request is made to the switching permission unit 45b is provided.
  • the mode information is set by inputting a setting command using, for example, an input device such as a keyboard provided in the information processing apparatus before the user causes the information processing apparatus 3 to execute processing.
  • the information indicating in which processing mode the operation is specifically, for example, is 1-bit information. In the case of “0”, the first mode is selected. In the case of “1”, the second mode is selected. To express.
  • the determination unit 46 determines whether the processing mode of the access control device 40 c is the first mode or the second mode. Judgment is made.
  • the processing mode is the first mode
  • the access control device 40c performs the same processing as that described in the second embodiment, and in the second mode, performs the same processing as that described in the first embodiment. .
  • FIG. 11 is a flowchart showing the operation of the mode determination process in the access control device 40c.
  • the mode determination unit 46 receives an output permission request from the processor 10c (step S40).
  • the mode determination unit 46 reads the value of information indicating the processing mode stored in the mode storage unit (step S41).
  • the mode determination unit 46 determines whether the mode is the first mode or the second mode (step S42). Specifically, if the read value is “0”, the first mode is determined, and if not, the second mode is determined.
  • step S42 determines whether the mode is not the first mode (step S42: NO)
  • the mode determination unit 46 permits the output to the processor 10c, and the processor 10c performs the processing of START (A) in FIG. Do.
  • step S42 determines whether the first mode is determined in step S42 (step S42: YES). If the first mode is determined in step S42 (step S42: YES), the mode determination unit 46 outputs an output permission request to the switching permission unit 45b (step S43).
  • the switching permission unit 45b acquires the number of data waiting for processing of the peripheral circuit 20 from the state acquisition unit 43b (step S44).
  • a specific acquisition method is the same as the method in step S13 of FIG.
  • the switching permission unit 45b compares the number of processing-waiting data acquired from the state acquisition unit 43b with a threshold value stored in advance in an internal memory (step S45). If the number of data waiting for processing is larger than the threshold (step S45: NO), the processing is repeated from step S44. On the other hand, when the number of data waiting to be processed is equal to or smaller than the threshold (step S45: YES), permission information for outputting an attribute switching permission request to the attribute switching control unit 41 is output to the processor 10c (step S46).
  • the information processing apparatus 3 is in the first mode in which the output permission request is made to the switching permission unit 45b before the processor 10c switches the attribute, or the attribute is not requested.
  • the mode determination unit determines whether the second mode in which an attribute switching permission request is made to the switching control unit 41. For this reason, for example, when processing that does not generate a large amount of processing-waiting data is performed, the processing in the switching permission unit 45b can be omitted by setting the second mode in advance. Further, when performing processing that generates a lot of processing-waiting data, the standby time in the attribute switching process of the processor 10c can be shortened by setting the first mode. ⁇ 4.
  • the illustrated information processing apparatus can be modified as follows, and the present invention is limited to the information processing apparatus as described in the above embodiment.
  • the processor 10 executes processing by switching between two OSs, and the information indicating the attribute is information for identifying the OS.
  • the attribute indicating the processing of the processor 10 may not be information for identifying the OS. Any information may be used as long as it can identify the attribute when the access area to the device 30 is restricted for each of the plurality of attributes.
  • the switching permission unit 45 permits the attribute switching permission request to be sent to the attribute switching control unit until the number of data waiting to be processed becomes a predetermined number or less. However, after a certain period of time has elapsed since the processor 10b made a request for permission to output to the switching permission unit 45, it may be permitted even if the number of data waiting for processing does not fall below a predetermined number. .
  • the switching permission unit 45 in this case has a timer inside, and this timer measures an elapsed time after receiving an output permission request from the processor 10.
  • the attribute switching permission request is changed to the attribute switching. This is done for the control unit.
  • the processor 10b requests output permission in order to switch from the process executed by the OS 1 to the process executed by the OS 2, it is required that the attribute can be quickly switched.
  • the processor 10b in the state in which the processing in OS1 is being executed, the number of data waiting for processing in the peripheral circuit 20 does not become a predetermined number or less, so the processor 10b can obtain the output permission. Therefore, there is a possibility that the attribute switching permission request cannot be made to the attribute switching control unit 41 quickly.
  • the number of data waiting to be processed in the peripheral circuit 20 does not become a predetermined number or less after a predetermined time has elapsed since the processor 10b made a request for output permission to the switching permission unit 45.
  • the processor 10b can make an attribute switching permission request to the attribute switching control unit 41 by permitting output to the processor 10b.
  • FIG. 12 shows a flowchart of processing in which the switching permission unit 45 performs output permission to the processor 10b after a predetermined time has elapsed.
  • step S50, step S51, and step S53 in the figure are the same as those in step S30, step S31, and step S33 in FIG.
  • the switching permission unit 45 performs the process of step S53 when the number of data waiting to be processed is equal to or less than the predetermined number (step S52: YES).
  • step S52 when the number of data waiting to be processed is not less than or equal to the predetermined number (step S52: NO), the switching permission unit 45 compares the elapsed time with a predetermined time, and elapses over a predetermined time. It is determined whether or not (step S54). If NO in step S54, the processing from step S51 is repeated.
  • step S54 the switching permission unit 45 permits the processor 10 to make an attribute switching permission request to the attribute switching control unit 41 (step S53).
  • the processor 10b can obtain the output permission from the switching permission unit 45b after a predetermined time has elapsed since the request for permission to output even when the data waiting for processing does not become a predetermined number or less. Therefore, an attribute switching permission request can be made to the attribute switching control unit 41.
  • the number of data waiting to be processed may be permitted even if it does not become a predetermined number or less.
  • the switching permission unit 45b in this case has a timer therein, and the elapsed time since receiving a permission request to the attribute switching control unit 41 from the processor 10 for the attribute switching permission request. Measure time.
  • FIG. 13 shows a flowchart of processing for permitting output to the processor 10c after a predetermined time has elapsed when the operation state of the information processing apparatus 3 is in the first mode.
  • steps S60 to S63 and steps S64 to S66 in FIG. 11 are the same as the processes in steps S40 to S43 and steps S44 to S46 in FIG.
  • step S65 the switching permission unit 45b compares the elapsed time with a predetermined time, and determines whether or not a predetermined time or more has elapsed (step S67). If NO in step S67, the processing from step S64 is repeated.
  • step S67 the switching permission unit 45b performs the process of step S66.
  • the processor 10c does not wait for a predetermined number of processing waits until the output of the output is requested for a certain period of time. Since the output permission can be obtained from the switching permission unit 45b after the lapse, the attribute switching permission request can be made to the attribute switching control unit 41. (3) In the information processing apparatuses 1 to 3 of the embodiment, one peripheral circuit has been described, but there may be a plurality of peripheral circuits.
  • the state acquisition unit acquires the number of data waiting for processing in all the peripheral circuits, and the attribute switching control unit When the processing waiting data of all the peripheral circuits becomes 0, the processor may be allowed to switch the attribute.
  • the number of processing waiting data acquired by the switching permission unit in the second and third embodiments is the sum of the processing waiting data in all the peripheral circuits, and this sum is equal to or less than a predetermined number. In such a case, output permission may be performed.
  • the attribute switching control unit 41 that has received the attribute switching permission request from the processor outputs all the access commands generated from the processing waiting data stored in the buffer 300 of the peripheral circuit 20. The attribute switching is permitted when the processing-waiting data becomes 0, but it is not limited to outputting all access commands.
  • the attribute switching control unit 41 causes the peripheral circuit 20 to stop processing and stops the output of the access command. May be permitted.
  • the peripheral circuit 20 outputs to the processor 10 information on how far the processing-waiting data stored in the buffer 300 has been processed, and the processing interrupted when the processor 10 switches to processing executed by the OS 1 again. May be resumed from the continuation.
  • the attribute switching control unit 41 permits the attribute switching to the processor, the processor switches the process, and updates the attribute value in the attribute storage unit 42.
  • the attribute switching procedure is not limited to this.
  • the attribute switching control unit 41 updates the attribute value in the attribute storage unit 42 and notifies the processor that the update has been completed, it is only necessary that the attribute can be switched when there is no processing waiting data.
  • the processor may switch processing.
  • the state acquisition unit 43 acquires the number of data waiting for processing from the peripheral circuit 20, but the state acquisition unit 43 acquires only the number of access commands. Absent. Since it is only necessary to acquire that there is no processing waiting data, for example, information regarding whether or not there is processing waiting data may be obtained.
  • the peripheral circuit 20 outputs information indicating that there is no processing waiting data to the state acquisition unit 43, and when the state acquisition unit 43 receives information indicating that there is no processing waiting data, the peripheral circuit 20 sends an attribute to the processor 10. Allow switching.
  • the buffer circuit 300 may not be provided in the peripheral circuit 20.
  • the peripheral circuit 20 may output information indicating that there is no processing waiting data to the state acquisition unit 43 when the processing being executed is completed.
  • a control program for causing the access control apparatus to execute each process described in the embodiment is recorded on a recording medium. Or can be distributed and distributed via various communication channels.
  • a recording medium includes an IC card, a hard disk, an optical disk, a flexible disk, a ROM, a flash memory, and the like.
  • the distributed and distributed control program is used by being stored in a memory or the like that can be read by a processor different from the processors 10, 10b, and 10c in the device, and the access control device executes the control program.
  • Each function shown in the embodiment is realized.
  • All or some of the constituent elements of the attribute switching control unit, the state acquisition unit, the access control unit, and the switching permission unit of the access control device described in the embodiment are realized by an integrated circuit of one chip or a plurality of chips. May be.
  • some or all of the functions of these components may be realized by a computer program, or in any other form. (9) You may combine said embodiment and said modification suitably suitably. ⁇ 4.
  • An information processing apparatus is an information processing apparatus including an access target device accessed from a processor and a peripheral circuit, and executes a plurality of internal processes with different attributes by switching between the access processing devices.
  • a processor When accessing a target device, a processor that generates an access command including an attribute value for identifying the attribute and access content instruction information, and attribute information indicating an attribute of an internal process being executed by the processor
  • An attribute storage unit for storing and an instruction to perform processing including access to the access target device from the processor, and when accessing the access target device, the attribute of the attribute storage unit
  • a peripheral circuit that references the information and generates an access command including an attribute value and access content instruction information;
  • An access control unit that receives an access command generated by each peripheral circuit and performs access suppression control on the access target device according to a correspondence relationship between the attribute indicated by the attribute value of the access command and the access content instruction information
  • the peripheral circuit When the attribute switching permission request from the processor is received, the peripheral circuit is caused to output an access command that is not output related to the processing received from the processor to the access control unit, and the output of the access command is
  • An attribute switching control unit that permits the processor to switch attributes when the processing is completed, and when the processor switches internal processing, the processor makes
  • the processor when switching the attribute, the processor makes an attribute switching permission request to the attribute switching control unit, and the attribute switching control unit outputs an access command to access the device with the attribute before switching from the peripheral circuit. Until the process is completed, the processor is not allowed to switch attributes. Then, the processor switches the attribute after receiving the attribute switching permission.
  • the attribute switching control unit includes a state acquisition unit that repeatedly acquires the number of processing-waiting access commands that are not output from the peripheral circuit to the access control unit, and the process acquired by the state acquisition unit When the number of waiting access commands is 0, it may be determined that the output of the access commands is completed.
  • the status acquisition unit repeatedly acquires the number of processing-waiting data that has not been output to the access control unit, and when the number of access commands becomes 0, the attribute switching control unit outputs the access command. Judge that completed.
  • the processor can switch the attribute when there is no access command output from the peripheral circuit, and can suppress undesired access when accessing the access target device from the peripheral circuit. .
  • a request for permission to make the attribute switching permission request to the attribute switching control unit is received from the processor, and the number of processing waiting access commands is equal to or less than a predetermined number.
  • a switching permission unit that allows the processor to perform the attribute switching permission request to the attribute switching control unit, and the processor sends the attribute switching permission request to the attribute switching control unit. In the case where a request for permission to be performed is sent to the switching permission unit, when the permission to perform the attribute switching permission request is obtained from the switching permission unit, the attribute switching permission request is sent to the attribute switching control. It may be performed on the part.
  • the processor before making an attribute switching permission request to the attribute switching control unit, requests the switching permission unit to make an attribute switching permission request to the attribute switching control unit.
  • the switching permission unit permits the processor to make an attribute switching permission request to the attribute switching control unit when the number of data to be processed is equal to or less than a predetermined number.
  • the processor can make an attribute switching permission request to the attribute switching control unit after the number of data waiting to be processed becomes equal to or less than a predetermined number, so that the attribute switching control unit obtains permission for attribute switching.
  • the waiting time can be shortened, and a decrease in processing efficiency can be suppressed.
  • the switching permission unit counts the number of access commands waiting for processing. Even if the value does not fall below the predetermined number, the processor may be permitted to make the attribute switching permission request to the attribute switching control unit.
  • the switching permission unit even if the number of data waiting to be processed does not become the predetermined number or less after a predetermined time has elapsed since the request for permission to perform the attribute switching permission request has been received.
  • the processor is permitted to make an attribute switching permission request to the attribute switching control unit.
  • the processor can perform the attribute switching process after a certain period of time has elapsed since the request for permission to perform the attribute switching permission request.
  • the processor does not request the switching permission unit for permission to perform the attribute switching permission request to the switching permission unit, and does not request the switching permission unit to permit the attribute switching permission request.
  • a mode storage unit that stores information on which mode is the second mode, and whether the processing mode of the device is the first mode or the second mode is stored in the mode storage unit.
  • a mode determination unit for determining based on information, and when the mode determination unit determines that the mode is the first mode when switching the internal process, the processor performs an attribute switching permission request When the request for permission is made to the switching permission unit and the second mode is determined, the request for permission to perform the attribute switching permission request is not sent to the switching permission unit, and the attribute switching permission request is sent to the switching permission unit.
  • Genus It may perform relative to the switching control unit.
  • the mode determination unit is in the first mode that requests the switching permission unit to permit the attribute switching permission request, or in the second mode that does not request permission of the attribute switching permission request from the switching permission unit. Determine if there is.
  • the access control device switches between the first mode and the second mode according to the determination of the mode determination unit.
  • the processing mode can be switched between the case of a dedicated circuit that performs processing that does not generate a lot of processing-waiting data and the case of a dedicated circuit that performs processing that generates a lot of processing-waiting data. It can be processed in an appropriate processing mode.
  • the access target device is a memory device
  • the access content instruction information included in the access command may be information including information indicating a memory address of an access destination to the memory device. Good.
  • the access command accesses the memory device by specifying the address to be accessed.
  • the access control unit can determine whether or not to permit access to the specified address included in the access command.
  • an information processing apparatus including a processor, a peripheral circuit, and an access target device, it is useful for realizing access to a specific area of the access target device according to the operating state of the processor operating with a plurality of attributes (OS, process, etc.). .

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Abstract

Selon la présente invention, un processeur (10) effectue une requête de permission de commutation d'attribut pour une unité de commande de commutation d'attribut (41) lors d'une commutation de traitement interne. L'unité de commande de commutation d'attribut (41) qui a reçu la requête de permission de commutation d'attribut amène un circuit périphérique (20) à délivrer une instruction d'accès, qui est relative à un traitement reçu en provenance du processeur (10), à une unité de contrôle d'accès (44) de telle sorte qu'à l'achèvement de la délivrance de l'instruction d'accès, la commutation d'attribut est permise pour le processeur (10). Le processeur (10) est caractérisé en ce que, si une permission pour la commutation d'attribut est acquise en provenance de l'unité de commande de commutation d'attribut (41), un traitement interne est commuté et des informations d'attribut dans une unité de stockage d'attribut (42) sont mises à jour.
PCT/JP2012/005211 2011-09-01 2012-08-20 Dispositif de traitement d'informations, son procédé de contrôle d'accès et circuit intégré WO2013031130A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160119140A (ko) * 2014-02-10 2016-10-12 에이알엠 리미티드 타겟 메모리 어드레스에 대응한 메모리 속성 유닛의 영역을 식별하는 영역식별 연산

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7627649B2 (ja) 2021-12-08 2025-02-06 ルネサスエレクトロニクス株式会社 半導体装置及びハードウェア仮想化方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002163239A (ja) * 2000-11-22 2002-06-07 Toshiba Corp マルチプロセッサシステムおよびその制御方法
JP2002268942A (ja) * 2001-03-13 2002-09-20 Toshiba Corp マルチバンクアクセス制御装置及びマルチバンクアクセス制御方法
JP2004252761A (ja) * 2003-02-20 2004-09-09 Ntt Data Corp マルチオペレーティングシステム制御方法、およびその方法をコンピュータに実行させるプログラム、ならびにマルチオペレーティングシステム制御装置
JP2008052714A (ja) * 2006-07-25 2008-03-06 Ntt Docomo Inc 複数オペレーティングシステム切替制御装置及びコンピュータシステム
JP2009530715A (ja) * 2006-03-16 2009-08-27 株式会社エヌ・ティ・ティ・ドコモ セキュアなオペレーティングシステムのスイッチング
JP2010152527A (ja) * 2008-12-24 2010-07-08 Sony Computer Entertainment Inc ユーザレベルｄｍａとメモリアクセス管理を提供する方法と装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002163239A (ja) * 2000-11-22 2002-06-07 Toshiba Corp マルチプロセッサシステムおよびその制御方法
JP2002268942A (ja) * 2001-03-13 2002-09-20 Toshiba Corp マルチバンクアクセス制御装置及びマルチバンクアクセス制御方法
JP2004252761A (ja) * 2003-02-20 2004-09-09 Ntt Data Corp マルチオペレーティングシステム制御方法、およびその方法をコンピュータに実行させるプログラム、ならびにマルチオペレーティングシステム制御装置
JP2009530715A (ja) * 2006-03-16 2009-08-27 株式会社エヌ・ティ・ティ・ドコモ セキュアなオペレーティングシステムのスイッチング
JP2008052714A (ja) * 2006-07-25 2008-03-06 Ntt Docomo Inc 複数オペレーティングシステム切替制御装置及びコンピュータシステム
JP2010152527A (ja) * 2008-12-24 2010-07-08 Sony Computer Entertainment Inc ユーザレベルｄｍａとメモリアクセス管理を提供する方法と装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160119140A (ko) * 2014-02-10 2016-10-12 에이알엠 리미티드 타겟 메모리 어드레스에 대응한 메모리 속성 유닛의 영역을 식별하는 영역식별 연산
JP2017505492A (ja) * 2014-02-10 2017-02-16 エイアールエム リミテッド 目標メモリ・アドレスに対応するメモリ属性ユニットの領域を特定するための領域特定演算
KR102383900B1 (ko) 2014-02-10 2022-04-07 에이알엠 리미티드 타겟 메모리 어드레스에 대응한 메모리 속성 유닛의 영역을 식별하는 영역식별 연산

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