+

WO2013018636A1 - Dispositif d'affichage et procédé d'attaque associé - Google Patents

Dispositif d'affichage et procédé d'attaque associé Download PDF

Info

Publication number
WO2013018636A1
WO2013018636A1 PCT/JP2012/068918 JP2012068918W WO2013018636A1 WO 2013018636 A1 WO2013018636 A1 WO 2013018636A1 JP 2012068918 W JP2012068918 W JP 2012068918W WO 2013018636 A1 WO2013018636 A1 WO 2013018636A1
Authority
WO
WIPO (PCT)
Prior art keywords
pixel electrode
electrode
potential
pixel
period
Prior art date
Application number
PCT/JP2012/068918
Other languages
English (en)
Japanese (ja)
Inventor
耕平 田中
豪 鎌田
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Publication of WO2013018636A1 publication Critical patent/WO2013018636A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G02F1/134354—Subdivided pixels, e.g. for grey scale or redundancy the sub-pixels being capacitively coupled
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling

Definitions

  • the present invention relates to a display device, and more particularly to a display device having a configuration in which one pixel is divided into a plurality of sub-pixels in order to improve viewing angle characteristics and a driving method thereof.
  • an active matrix liquid crystal display device including a thin film transistor (TFT) as a switching element is known.
  • the display portion of the active matrix liquid crystal display device includes a plurality of source bus lines (video signal lines), a plurality of gate bus lines (scanning signal lines), the plurality of source bus lines, and a plurality of gates.
  • a plurality of pixel forming portions provided corresponding to the intersections with the bus lines are included. These pixel forming portions are arranged in a matrix to constitute a pixel array.
  • FIG. 30 is a circuit diagram showing a configuration of a pixel forming portion of a conventional general active matrix type liquid crystal display device.
  • the pixel forming portion includes a thin film transistor T91 having a gate electrode connected to a gate bus line GL passing through a corresponding intersection and a source electrode connected to a source bus line SL passing through the intersection.
  • the pixel electrode 92 connected to the drain electrode of the thin film transistor T91, the common electrode (counter electrode) COM and the auxiliary capacitance electrode CS provided in common to the plurality of pixel forming portions, the pixel electrode 92, and the common electrode
  • a liquid crystal capacitor Clc formed by COM and an auxiliary capacitor Cstg formed by the pixel electrode 92 and the auxiliary capacitor electrode CS are included.
  • a pixel capacitor is formed by the liquid crystal capacitor Clc and the auxiliary capacitor Cstg.
  • the auxiliary capacitor Cstg is not necessarily provided.
  • FIG. 31 is a circuit diagram showing a configuration example of a pixel formation portion in a conventional liquid crystal display device having a multi-pixel structure. As shown in FIG.
  • the pixel forming portion PIX9 is configured by two subpixel portions (a first subpixel portion PIX9a and a second subpixel portion PIX9b). Both sub-pixel portions (PIX9a, PIX9b) include transistors (T92, T93), pixel electrodes (E91, E92), liquid crystal capacitors (ClcA, ClcB), and storage capacitors (CstA, CstB) as common components. I have.
  • the second sub-pixel portion PIX9b further includes a transistor T94 having a gate electrode connected to the scanning signal line GLi + 1 and a source electrode connected to the pixel electrode E92, and a capacitor connected to the drain electrode of the transistor T94.
  • An electrode E93, and a buffer capacitor Cdown formed by a capacitor electrode E93 and a common electrode (auxiliary capacitor electrode) COM902 are provided.
  • the scanning signal line GLi when the scanning signal line GLi is selected, the potential of the pixel electrode E91 in the first subpixel unit PIX9a is equal to the potential of the pixel electrode E92 in the second subpixel unit PIX9b.
  • the transistor T94 is turned on.
  • charges move between the pixel electrode E92 and the capacitor electrode E93, and the potential of the pixel electrode E92 varies.
  • the pixel electrode E91 and the pixel electrode E92 have different potentials
  • the first subpixel unit PIX9a and the second subpixel unit PIX9b have different luminance.
  • the pixel forming portion is configured as shown in FIG. 32, and the thin film transistor T95 and the thin film transistor T96 are made to have different sizes, so that the charging capability between the thin film transistor T95 and the thin film transistor T96 is obtained.
  • An invention of a liquid crystal display device in which the luminance of two subpixels is made different from each other by providing a difference is disclosed.
  • Japanese Patent Application Laid-Open No. 2009-109600 discloses a liquid crystal display device that can reduce the amplitude of a video signal by amplifying the pixel electrode potential.
  • the pixel forming portion is configured as shown in FIG. 33 and the following driving is performed.
  • an on-level potential is applied to the line indicated by reference numeral 9 while an off-level potential is applied to the gate bus line GL.
  • the thin film transistors T902 and T903 are turned on.
  • the video signal potential (the potential of the source bus line SL) is applied to the node 991
  • the potential of the common electrode COM is applied to the node 992.
  • an on-level potential is applied to the gate bus line GL while an off-level potential is applied to the line indicated by reference numeral 9. Accordingly, the thin film transistor T901 is turned on. As a result, a video signal potential is applied to the node 992. That is, the potential of the node 992 rises from the common electrode potential to the video signal potential. At this time, since the node 991 is in a floating state, the potential of the node 991 increases via the capacitor C91 as the potential of the node 992 increases. As described above, a larger voltage is applied between the pixel electrode and the common electrode.
  • a common electrode potential is applied to the node 992 (see FIG. 33) during the first half of one horizontal scanning period. That is, precharge using the common electrode potential is performed. Therefore, the pixel electrode potential is amplified according to the difference between the video signal potential and the common electrode potential.
  • the common electrode potential cannot be set freely, the difference between the video signal potential and the common electrode potential cannot be sufficiently increased, and the degree of amplification of the pixel electrode potential is not sufficient.
  • the invention disclosed in Japanese Unexamined Patent Publication No. 2009-109600 is applied to a liquid crystal display device having a multi-pixel structure. I can't. Further, since three thin film transistors are provided in one pixel formation portion, the aperture ratio is reduced.
  • the amplitude of the video signal cannot be reduced so as to reduce the power consumption for the following reason.
  • positive writing when the transistor T94 is turned on, positive charge moves from the storage capacitor CstB to the buffer capacitor Cdown.
  • the potential of the pixel electrode E92 in the second subpixel unit PIX9b is lower than the potential of the pixel electrode E91 in the first subpixel unit PIX9a.
  • negative polarity writing when the transistor T94 is turned on, positive charges move from the buffer capacitor Cdown to the storage capacitor CstB.
  • the potential of the pixel electrode E92 in the second subpixel portion PIX9b is higher than the potential of the pixel electrode E91 in the first subpixel portion PIX9a.
  • the liquid crystal applied voltage in the second sub-pixel unit PIX9b is smaller than the liquid crystal applied voltage in the first sub-pixel unit PIX9a in both the frame where the positive polarity writing is performed and the frame where the negative polarity writing is performed.
  • a difference voltage between the video signal potential and the common electrode potential is applied to the liquid crystal.
  • a voltage smaller than the difference voltage between the video signal potential and the common electrode potential is applied to the liquid crystal.
  • an object of the present invention is to realize low power consumption by reducing the amplitude of a video signal in a liquid crystal display device in which one pixel is divided into a plurality of sub-pixels.
  • a plurality of video signal lines there are a plurality of video signal lines, a plurality of first scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines, and the plurality of first signals.
  • An active matrix display having a plurality of pixel formation portions arranged in a matrix corresponding to intersections with one scanning signal line and a common electrode provided in common to the plurality of pixel formation portions.
  • a device A second scanning signal line provided to correspond to the first scanning signal line on a one-to-one basis; Each pixel forming part A first pixel electrode and a second pixel electrode to which a potential corresponding to an image to be displayed is to be respectively applied; A first display capacitor formed by the first pixel electrode and the common electrode; A second display capacitor formed by the second pixel electrode and the common electrode; A first switching element having a control terminal connected to the first scanning signal line, a first conduction terminal connected to the video signal line, and a second conduction terminal connected to the first pixel electrode; A control terminal is connected to the second scanning signal line, a first conduction terminal is connected to the video signal line, and a second switching element having a second conduction terminal connected to the second pixel electrode is electrically connected to the second switching element. And a first coupling capacitor formed between one pixel electrode and the second pixel electrode.
  • One frame period which is a period during which one screen is displayed, is a period for changing the potentials of the first pixel electrode and the second pixel electrode in accordance with the image to be displayed, and is a first charging period.
  • a selection period including the second charging period and a non-selection period that is a period other than the selection period
  • the corresponding first scanning signal line is supplied with a potential for turning on the first switching element during the first charging period, and the first switching element is turned off during a period other than the first charging period. Is given a potential to The corresponding second scanning signal line is given a potential for turning on the second switching element during the second charging period, and the second switching element is turned off during a period other than the second charging period. It is characterized in that a potential is applied.
  • a first transparent electrode including a portion functioning as the first pixel electrode and a portion functioning as the second pixel electrode, and a second transparent electrode electrically connected to the portion functioning as the first pixel electrode.
  • the first coupling capacitor is formed by a portion functioning as the second pixel electrode in the first transparent electrode and the second transparent electrode.
  • Each pixel forming part A first auxiliary capacitor electrically formed between the first pixel electrode and the first auxiliary capacitor line; It further includes a second auxiliary capacitor electrically formed between the second pixel electrode and the second auxiliary capacitor line.
  • a first transparent electrode including a portion that functions as the first pixel electrode and a portion that functions as the second pixel electrode; and a first electrode portion that is electrically connected to the portion that functions as the first pixel electrode.
  • the second transparent electrode further includes a second electrode portion functioning as the first auxiliary capacitance wiring and a third electrode portion functioning as the second auxiliary capacitance wiring, The portion functioning as the first pixel electrode and the portion functioning as the second pixel electrode are electrically separated,
  • the first coupling capacitance is formed by a portion functioning as the second pixel electrode of the first transparent electrode and the first electrode portion of the second transparent electrode,
  • the first auxiliary capacitance is formed by a portion functioning as the first pixel electrode of the first transparent electrode and the second electrode portion of the second transparent electrode,
  • the second auxiliary capacitor is formed by a portion functioning as the second pixel electrode in the first transparent electrode and the third electrode portion in the second transparent electrode.
  • a sixth aspect of the present invention is the fourth aspect of the present invention, Changes in the potential generated in the first pixel electrode when switching from the first charging period to the second charging period and when switching from the second charging period to the non-selection period, and from the second charging period to the non-selection period.
  • the capacitance value of the first auxiliary capacitor and the capacitance value of the second auxiliary capacitor are set so that the change in potential generated in the second pixel electrode when switching to the same is made. To do.
  • Each pixel forming part A first parasitic capacitance formed between the first pixel electrode and the first scanning signal line; A second parasitic capacitance formed between the second pixel electrode and the second scanning signal line; Changes in the potential generated in the first pixel electrode when switching from the first charging period to the second charging period and when switching from the second charging period to the non-selection period, and from the second charging period to the non-selection period.
  • the capacitance value of the first parasitic capacitance and the capacitance value of the second parasitic capacitance are set so that a change in potential generated in the second pixel electrode when switching to the same is made. To do.
  • Each pixel forming part A first auxiliary capacitor electrically formed between the first pixel electrode and the first auxiliary capacitor line; A second storage capacitor electrically formed between the second pixel electrode and the second storage capacitor line; A first parasitic capacitance formed between the first pixel electrode and the first scanning signal line; A second parasitic capacitance formed between the second pixel electrode and the second scanning signal line; Changes in the potential generated in the first pixel electrode when switching from the first charging period to the second charging period and when switching from the second charging period to the non-selection period, and from the second charging period to the non-selection period.
  • Each pixel forming part A third pixel electrode to be supplied with a potential corresponding to an image to be displayed; A third display capacitor formed by the third pixel electrode and the common electrode; A third switching element having a control terminal connected to the first scanning signal line, a first conduction terminal connected to the video signal line, and a second conduction terminal connected to the third pixel electrode; A second coupling capacitor electrically formed between the third pixel electrode and the second pixel electrode; The capacitance value of the first coupling capacitor and the capacitance value of the second coupling capacitor are set to different values.
  • a first transparent electrode including a portion functioning as the first pixel electrode, a portion functioning as the second pixel electrode, and a portion functioning as the third pixel electrode, and a portion functioning as the second pixel electrode electrically It further comprises a two-layer transparent electrode consisting of connected second transparent electrodes, The portion functioning as the first pixel electrode, the portion functioning as the second pixel electrode, and the portion functioning as the third pixel electrode are electrically separated from each other,
  • the first coupling capacitor is formed by the portion of the first transparent electrode that functions as the first pixel electrode and the second transparent electrode,
  • the second coupling capacitance is formed by a portion functioning as the third pixel electrode in the first transparent electrode and the second transparent electrode.
  • An eleventh aspect of the present invention is the second aspect of the present invention,
  • Each pixel forming part A third pixel electrode to be supplied with a potential corresponding to an image to be displayed;
  • a third display capacitor formed by the third pixel electrode and the common electrode;
  • a third switching element having a control terminal connected to the first scanning signal line, a first conduction terminal connected to the video signal line, and a second conduction terminal connected to the third pixel electrode;
  • the first coupling capacitor is connected in series and includes a second coupling capacitor electrically formed between the first pixel electrode and the second pixel electrode.
  • a twelfth aspect of the present invention is the eleventh aspect of the present invention,
  • a first transparent electrode including a portion functioning as the first pixel electrode, a portion functioning as the second pixel electrode, and a portion functioning as the third pixel electrode, and a portion functioning as the first pixel electrode electrically It further comprises a two-layer transparent electrode consisting of connected second transparent electrodes, The portion functioning as the first pixel electrode, the portion functioning as the second pixel electrode, and the portion functioning as the third pixel electrode are electrically separated from each other,
  • the first coupling capacitance is formed by a portion functioning as the second pixel electrode in the first transparent electrode and the second transparent electrode,
  • the second coupling capacitance is formed by a portion functioning as the third pixel electrode in the first transparent electrode and the second transparent electrode.
  • a period for changing the potentials of the first pixel electrode and the second pixel electrode in accordance with the image to be displayed in one frame period which is a period during which one screen is displayed is a selection period.
  • a potential applied to the first scanning signal line to turn on the first switching element is defined as a first on-potential, and the second switching element is turned on to turn on the second switching element.
  • a potential applied to the scanning signal line is defined as a second on potential
  • a period in which the first on potential is applied to the first scanning signal line in each selection period is defined as a first on period
  • the second on potential is applied to the second scanning signal line in each selection period
  • the first on potential is different from the second on potential.
  • a drive mode control unit for switching between two drive modes including the first drive mode and the second drive mode When focusing on an arbitrary pixel formation part, One frame period, which is a period during which one screen is displayed, is a period for changing the potentials of the first pixel electrode and the second pixel electrode in accordance with the image to be displayed, and is a first charging period. And a selection period including the second charging period and a non-selection period that is a period other than the selection period, When the first drive mode is selected, The corresponding first scanning signal line is supplied with a potential for turning on the first switching element during the first charging period, and the first switching element is turned off during a period other than the first charging period.
  • the corresponding second scanning signal line is given a potential for turning on the second switching element during the second charging period, and the second switching element is turned off during a period other than the second charging period. Is given a potential to When the second drive mode is selected, The corresponding first scanning signal line is given a potential for turning on the first switching element during the selection period, and given a potential for turning off the first switching element during the non-selection period. , The corresponding second scanning signal line is given a potential for turning on the second switching element during the selection period, and given a potential for turning off the second switching element during the non-selection period. It is characterized by that.
  • the plurality of pixel forming portions includes a plurality of color pixel forming portions, Among the plurality of color pixel formation portions, at least one color pixel formation portion has a capacitance value of the first coupling capacitance different from that of the other color pixel formation portions.
  • a plurality of video signal lines, a plurality of first scanning signal lines intersecting with the plurality of video signal lines, and a potential corresponding to an image to be displayed should be given, respectively.
  • a plurality of pixel forming portions each having a first pixel electrode and a second pixel electrode and arranged in a matrix corresponding to intersections of the plurality of video signal lines and the plurality of first scanning signal lines;
  • a driving method of an active matrix display device having a common electrode provided in common to the plurality of pixel formation portions, Regarding each pixel formation part, A pixel electrode potential changing step for changing the potential of the first pixel electrode and the second pixel electrode in accordance with the image to be displayed every frame period, which is a period during which one screen is displayed;
  • the display device includes a second scanning signal line provided to correspond to the first scanning signal line on a one-to-one basis, Each pixel forming
  • each pixel forming portion includes a first pixel electrode and a second pixel electrode, and a first switching element and a second pixel provided corresponding to the first pixel electrode.
  • the second switching elements provided corresponding to the electrodes are connected to different scanning signal lines. For this reason, the video signal potential can be applied to the first pixel electrode and the second pixel electrode at different timings.
  • a capacitor first coupling capacitor
  • the selection period for changing the potentials of the first pixel electrode and the second pixel electrode according to the display image includes a first charging period and a second charging period.
  • the potential of the first pixel electrode is made equal to the video signal potential
  • the potential of the second pixel electrode is made equal to the video signal potential.
  • a capacitor first coupling capacitor
  • the potential of the first pixel electrode is amplified with a change in the potential of the second pixel electrode.
  • the potential of the second pixel electrode becomes equal to the video signal potential
  • the potential of the first pixel electrode becomes higher than the video signal potential (when positive writing is performed). For this reason, even if the amplitude of the video signal is made smaller than before, it is possible to apply the same potential to the first pixel electrode as before. Thereby, in a display device having a multi-pixel structure, low power consumption can be realized by reducing the amplitude of the video signal. Moreover, since it is a comparatively simple structure, it can be applied to not only large panels but also medium and small panels relatively easily.
  • the aperture ratio can be improved and the aperture ratio is affected.
  • the first coupling capacitance can be set without any problem.
  • pixels that perform relatively bright display hereinafter referred to as “bright display” and relatively dark display (hereinafter referred to as “dark display”).
  • a supplementary capacitor is provided for each of the pixels in which the operation is performed (see FIG. 11). For this reason, by adjusting the capacitance value of the auxiliary capacitor in both pixels, it is possible to generate a bias in the applied voltage to the pixel capacitor between the positive and negative polarities in both the bright display pixel and the dark display pixel. It becomes possible to suppress.
  • the aperture ratio is improved.
  • the first coupling capacitance, the first auxiliary capacitance, and the second auxiliary capacitance can be set without affecting the aperture ratio.
  • the magnitude of the feedthrough voltage in the pixel for bright display is equal to the magnitude of the feedthrough voltage in the pixel for dark display. For this reason, the occurrence of bias in the applied voltage to the pixel capacitance between the positive and negative polarities is suppressed in both the bright display pixel and the dark display pixel, and the occurrence of image sticking to the screen is suppressed.
  • each of the bright display pixel and the dark display pixel is provided with the parasitic capacitance formed between the pixel electrode and the scanning signal line. (See FIG. 14).
  • the capacitance values of the parasitic capacitances are set so that the magnitude of the feedthrough voltage in the bright display pixel is equal to the magnitude of the feedthrough voltage in the dark display pixel. For this reason, the occurrence of bias in the applied voltage to the pixel capacitance between the positive and negative polarities is suppressed in both the bright display pixel and the dark display pixel, and the occurrence of image sticking to the screen is suppressed.
  • the parasitic capacitance formed between the auxiliary capacitance and the pixel electrode-scanning signal line in each of the bright display pixel and the dark display pixel. are provided (see FIG. 17).
  • the capacitance values of these capacitors are set such that the magnitude of the feedthrough voltage in the bright display pixel is equal to the magnitude of the feedthrough voltage in the dark display pixel. For this reason, the occurrence of bias in the applied voltage to the pixel capacitance between the positive and negative polarities is suppressed in both the bright display pixel and the dark display pixel, and the occurrence of image sticking to the screen is suppressed.
  • each pixel forming portion includes a first pixel electrode, a second pixel electrode, and a third pixel electrode, and the potential of these pixel electrodes is changed in accordance with the display image.
  • the selection period includes a first charging period and a second charging period. In the first charging period, the potential of the first pixel electrode and the potential of the third pixel electrode are made equal to the video signal potential, and in the second charging period, the potential of the second pixel electrode is made equal to the video signal potential.
  • capacitances are formed between the first pixel electrode and the second pixel electrode, and between the third pixel electrode and the second pixel electrode, and the second During the charging period, the first pixel electrode and the third pixel electrode are in a floating state. For this reason, in the second charging period, the potential of the first pixel electrode and the potential of the third pixel electrode are amplified in accordance with the change in the potential of the second pixel electrode. Thus, at the end of the selection period, the potential of the second pixel electrode becomes equal to the video signal potential, and (when positive writing is performed) the potential of the first pixel electrode and the potential of the third pixel electrode are It becomes higher than the video signal potential.
  • the capacitance value of the first coupling capacitor and the capacitance value of the second coupling capacitor are set to different values. Accordingly, at the end of the selection period, the potential of the first pixel electrode, the potential of the second pixel electrode, and the potential of the third pixel electrode are different from each other. As described above, it is possible to improve the viewing angle characteristics with higher accuracy while reducing the power consumption as compared with the prior art.
  • the aperture ratio can be improved, and The first coupling capacitance and the second coupling capacitance can be set without affecting the aperture ratio.
  • the eleventh aspect of the present invention similarly to the ninth aspect of the present invention, it is possible to improve the viewing angle characteristics with higher accuracy while reducing the power consumption as compared with the prior art.
  • the aperture ratio can be improved, and The first coupling capacitance and the second coupling capacitance can be set without affecting the aperture ratio.
  • the display quality is reduced due to insufficient charging.
  • the viewing angle characteristics can be improved while suppressing.
  • an effect of improving the viewing angle characteristic can be obtained by appropriately switching the driving mode, and the deterioration of display quality due to insufficient charging at the time of high-speed driving is suppressed. An effect is also obtained.
  • the degree of amplification of the potential of the first pixel electrode in the second charging period can be different for each color. This makes it possible to adjust the viewing angle characteristics more finely.
  • the same effect as that of the first aspect of the present invention can be achieved in the display device driving method.
  • FIG. 2 is an equivalent circuit diagram illustrating a configuration of a pixel formation portion (a portion for forming one pixel) in the active matrix liquid crystal display device according to the first embodiment of the present invention.
  • the said 1st Embodiment it is a block diagram which shows the whole structure of a liquid crystal display device. It is a figure which shows the layout of the pixel formation part vicinity in the said 1st Embodiment.
  • FIG. 6 is a diagram for describing a layout in the vicinity of a pixel formation portion in the first embodiment. It is a signal waveform diagram for demonstrating the drive method in the said 1st Embodiment.
  • FIG. 8 is a sectional view taken along line AA in FIG. 7. It is a signal waveform diagram for demonstrating the view of the 2nd Embodiment of this invention.
  • FIG. 5 is an equivalent circuit diagram illustrating a configuration of a pixel formation unit in the second embodiment.
  • FIG. 10 is an equivalent circuit diagram illustrating a configuration of a pixel formation unit in a second modification of the second embodiment. It is a figure which shows the layout of the pixel formation part vicinity in the 2nd modification of the said 2nd Embodiment. It is a figure which shows another example of the layout of the pixel formation part vicinity in the 2nd modification of the said 2nd Embodiment. It is an equivalent circuit diagram which shows another example of a structure of the pixel formation part in the 2nd modification of the said 2nd Embodiment.
  • the term “amplification” is used to mean that the difference between the pixel electrode potential and the common electrode potential is increased.
  • FIG. 2 is a block diagram showing the overall configuration of the active matrix liquid crystal display device according to the first embodiment of the present invention.
  • the liquid crystal display device includes a display unit 100, a display control circuit 200, a gate driver 300, and a source driver 400.
  • the display unit 100 is provided corresponding to a plurality of source bus lines SL, a plurality of gate bus lines GL, and intersections of the plurality of source bus lines SL and the plurality of gate bus lines GL. And a plurality of pixel formation portions. A detailed description of the configuration of the pixel formation portion will be given later.
  • the display control circuit 200 receives image data DAT and a timing signal group TG such as a horizontal synchronization signal and a vertical synchronization signal sent from the outside, and receives a digital video signal DV and a gate start pulse signal for controlling the operation of the gate driver 300.
  • GSP and gate clock signal GCK, and source start pulse signal SSP, source clock signal SCK, and latch strobe signal LS for controlling the operation of source driver 400 are output.
  • the gate driver 300 receives the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit 200, and applies a scanning signal to each gate bus line GL.
  • the source driver 400 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 200, and applies a driving video signal to each source bus line SL. .
  • the scanning signal is applied to each gate bus line GL and the driving video signal is applied to each source bus line SL, whereby an image based on the image data DAT sent from the outside is displayed on the display unit 100. Is displayed.
  • FIG. 1 is an equivalent circuit diagram illustrating a configuration of a pixel formation portion (a portion for forming one pixel) in the present embodiment.
  • the pixel forming portion includes two thin film transistors T1 and T2 and three capacitors Clc1, Clc2, and Ctr.
  • two gate bus lines GL1 and GL2 and one source bus line SL are provided as wirings passing through the pixel formation portion.
  • the gate bus line GL1 is referred to as a “first gate bus line”
  • the gate bus line GL2 is referred to as a “second gate bus line”.
  • the capacitance Clc1, the capacitance Clc2, and the capacitance Ctr their capacitance values are also indicated by the same symbols “Clc1”, “Clc2”, and “Ctr”, respectively.
  • the pixel formation portion shown in FIG. 1 forms a pixel having a multi-pixel structure. That is, one pixel is divided into a plurality of subpixels (here, two subpixels).
  • the capacitor Clc1 is a capacitor provided in the pixel for bright display
  • the capacitor Clc2 is a capacitor provided in the pixel for dark display.
  • the capacitors Clc1 and Clc2 are so-called liquid crystal capacitors.
  • the connection relationship between the components in the pixel forming section is as follows.
  • the gate electrode is connected to the first gate bus line GL1
  • the source electrode is connected to the source bus line SL
  • the drain electrode is connected to one end of the capacitor Clc1 and one end of the capacitor Ctr.
  • the gate electrode is connected to the second gate bus line GL2
  • the source electrode is connected to the source bus line SL
  • the drain electrode is connected to the other end of the capacitor Ctr and one end of the capacitor Clc2.
  • One end of the capacitor Clc1 is connected to the drain electrode of the thin film transistor T1 and one end of the capacitor Ctr, and the other end of the capacitor Clc1 is connected to the common electrode COM.
  • One end of the capacitor Clc2 is connected to the drain electrode of the thin film transistor T2 and the other end of the capacitor Ctr, and the other end of the capacitor Clc2 is connected to the common electrode COM.
  • One end of the capacitor Ctr is connected to the drain electrode of the thin film transistor T1 and one end of the capacitor Clc1
  • the other end of the capacitor Ctr is connected to the drain electrode of the thin film transistor T2 and one end of the capacitor Clc2.
  • the pixel electrode 1011 for bright display exists at one end of the capacitor Clc1. That is, the capacitor Clc1 is formed by the pixel electrode 1011 for bright display and the common electrode COM.
  • a pixel electrode 1012 for dark display exists at one end of the capacitor Clc2. That is, the capacitor Clc2 is formed by the pixel electrode 1012 for dark display and the common electrode COM.
  • the other end of the capacitor Ctr has a capacitor (a pixel of the bright display pixel electrode 1011 between the pixel electrode 1011 for bright display or an electrode electrically connected to the pixel electrode 1011 for bright display.
  • an electrode hereinafter referred to as “amplifying electrode” 102 for forming a capacitor for amplifying the potential.
  • the potential of the amplification electrode 102 is equal to the potential of the pixel electrode 1012 for dark display.
  • the potential of the pixel electrode 1011 for bright display is represented by the symbol Vpix1
  • the potential of the pixel electrode 1012 for dark display is represented by the symbol Vpix2.
  • the first display capacitor is realized by the capacitor Clc1
  • the second display capacitor is realized by the capacitor Clc2
  • the first coupling capacitor is realized by the capacitor Ctr.
  • the first switching element is realized by the thin film transistor T1
  • the second switching element is realized by the thin film transistor T2
  • the first pixel electrode is realized by the pixel electrode 1011 for bright display
  • the second switching element is realized by the pixel electrode 1012 for dark display.
  • a pixel electrode is realized.
  • the gate electrode corresponds to the control terminal
  • the source electrode corresponds to the first conduction terminal
  • the drain electrode corresponds to the second conduction terminal.
  • FIG. 3 is a diagram showing a layout in the vicinity of the pixel formation portion for realizing the circuit configuration shown in FIG.
  • the gate metal forming the first gate bus line GL1 and the gate metal forming the second gate bus line GL2 are arranged in parallel to each other.
  • the gate metal and the source metal forming the source bus line SL are disposed so as to be orthogonal to each other.
  • the area other than the area where the first gate bus line GL1 and the second gate bus line GL2 are disposed is used for bright display.
  • the transparent electrode 111 that functions as the pixel electrode 1011 and the transparent electrode 112 that functions as the pixel electrode 1012 for dark display are formed.
  • the area ratio between the transparent electrode 111 and the transparent electrode 112 is not particularly limited. Further, the electrode 12 functioning as the amplification electrode 102 described above is formed by gate metal between two adjacent source bus lines SL as shown in FIG. In the present embodiment, the transparent electrode 111 and the transparent electrode 112 are formed in the same layer.
  • the drain electrode of the thin film transistor T1 and the transparent electrode 111 are electrically connected by the source metal SE1 and the contact CT1.
  • the drain electrode of the thin film transistor T2 and the electrode 12 are electrically connected by the source metal SE2 and the contact CT2.
  • the drain electrode of the thin film transistor T2 and the transparent electrode 112 are electrically connected by the source metal SE2 and the contact CT3.
  • the source metal SE1 and the electrode 12 form a capacitor Ctr.
  • the positions of the transparent electrode 111, the transparent electrode 112, the electrode 12, the source metal SE1, the source metal SE2, and the contacts CT1 to CT3 in FIG. 3 are shown on the equivalent circuit diagram shown in FIG. 1, as shown in FIG. It becomes.
  • FIG. 5 is a signal waveform diagram for explaining the operation of the pixel formation portion in the selection period (a period for writing to the capacitance Clc1 and the capacitance Clc2 in accordance with an image to be displayed in each pixel formation portion).
  • the symbol Vdata represents the video signal potential (the potential of the source bus line SL)
  • the symbol Vcom represents the common electrode potential.
  • the length of the selection period typically corresponds to the length of one horizontal scanning period in a conventional liquid crystal display device.
  • the selection period includes a first half period (hereinafter referred to as “first charging period”) Ta and a second half period (hereinafter referred to as “second charging period”) Tb.
  • first charging period a first half period
  • second charging period a second half period
  • one frame period includes a selection period including the first charging period Ta and the second charging period Tb and a non-selection period that is a period other than the selection period.
  • the length of the first charging period Ta and the length of the second charging Tb are not necessarily equal.
  • an odd frame a frame in which positive polarity writing is performed (here, an odd frame is referred to as an odd frame). Will be described.
  • the first gate bus line GL1 is turned on (see FIG. 5) while the second gate bus line GL2 is supplied with the off-level (low level in the example shown in FIG. 5) potential.
  • a high level potential is applied.
  • the thin film transistor T1 is turned on and the thin film transistor T2 is turned off.
  • the video signal potential Vdata is applied to the pixel electrode 1011 (transparent electrode 111) for bright display.
  • the video signal potential Vdata is a potential determined according to the display image.
  • an on-level potential is applied to the second gate bus line GL2 while an off-level potential is applied to the first gate bus line GL1.
  • the thin film transistor T1 is turned off and the thin film transistor T2 is turned on.
  • the video signal potential Vdata is applied to the dark display pixel electrode 1012 (transparent electrode 112).
  • the pixel electrode potential Vpix2 rises from a negative potential to a positive potential with respect to the common electrode potential Vcom.
  • the pixel electrode 1011 for bright display is in a floating state, the pixel electrode potential Vpix1 rises via the capacitor Ctr as the pixel electrode potential Vpix2 rises.
  • the value of the pixel electrode potential Vpix1 at the end of the second charging period Tb that is, at the end of the selection period. Is represented by the following equation (1).
  • Cpix1 is represented by the following equation (2)
  • Cpix2 is represented by the following equation (3).
  • Cpix1 Clc1 + CP1
  • Cpix2 Clc2 + CP2 (3)
  • CP1 represents the capacitance value of the parasitic capacitance in the pixel for bright display
  • CP2 represents the capacitance value of the parasitic capacitance in the pixel for dark display.
  • the potential of the second gate bus line GL2 changes from the on level to the off level.
  • voltage fluctuations ⁇ Vg1, ⁇ Vg2 called “feedthrough voltage”, “pull-in voltage”, etc. occur in the pixel electrode potentials Vpix1, Vpix2.
  • the value of the pixel electrode potential Vpix1 becomes a value represented by the following equation (4), and the value of the pixel electrode potential Vpix2 becomes “Vdata ⁇ Vg2”.
  • the pixel electrode potential Vpix1 is maintained at the value expressed by the above equation (4) and the pixel electrode potential Vpix2 is maintained during the period from the occurrence of the voltage variation to the writing of the next frame after the selection period ends. It is maintained at “Vdata ⁇ Vg2” (however, fluctuations in potential due to leakage current or the like are ignored).
  • the capacitor Clc1 and the capacitor Clc2 are sequentially charged during one horizontal scanning period, so that a thin film transistor in the pixel formation portion has high mobility. It is preferable to do.
  • a thin film transistor including an oxide semiconductor is preferably used. As a result, even if driving at a relatively high frame rate is performed, a reduction in display quality due to insufficient charging is suppressed.
  • the pixel electrode potential changing step is realized by the operation in the selection period
  • the pixel electrode potential maintaining step is realized by the operation in the non-selection period.
  • the first step is realized by the operation of the first charging period Ta
  • the second step is realized by the operation of the second charging period Tb.
  • the selection period for charging the pixel capacitor includes the first charging period Ta and the second charging period Tb.
  • the pixel electrode potential Vpix1 is made equal to the video signal potential Vdata
  • the pixel electrode potential Vpix2 is made equal to the video signal potential Vdata.
  • a capacitor Ctr is formed between the pixel electrode 1011 for bright display and the pixel electrode 1012 for dark display, and the pixel electrode 1011 for bright display is in a floating state during the second charging period Tb. It has become. Therefore, in the second charging period Tb, the pixel electrode potential Vpix1 is amplified with the change of the pixel electrode potential Vpix2.
  • the pixel electrode potential Vpix2 becomes equal to the video signal potential Vdata, and (when positive writing is performed), the pixel electrode potential Vpix1 becomes higher than the video signal potential Vdata.
  • the pixel electrode potential for dark display is lower than the video signal potential at the end of the selection period, and the pixel electrode potential for bright display becomes the video signal potential. It was equal.
  • the liquid crystal display device according to the present embodiment when the amplitude of the video signal is the same, the pixel electrode voltage for bright display (the difference between the pixel electrode potential Vpix2 and the common electrode potential Vcom) is The liquid crystal display device in this embodiment is larger.
  • FIG. 6 is a diagram showing the relationship between the difference between the video signal potential and the common electrode potential and the transmittance.
  • the characteristic representing the relationship between the liquid crystal applied voltage and the transmittance in the liquid crystal display device is referred to as “VT characteristic”. Therefore, the characteristic representing the relationship shown in FIG. 6 is referred to as “pseudo VT characteristic” for convenience.
  • a thin solid line denoted by reference numeral 71 represents a pseudo VT characteristic in a pixel for dark display.
  • the pixel electrode potential Vpix1 is amplified during the second charging period Tb. .
  • a pseudo-VT characteristic represented by, for example, a thick solid line indicated by reference numeral 72 is obtained in the bright display pixel.
  • the pixel electrode voltage for bright display at the end of the selection period is larger than that of the conventional liquid crystal display device, and an image necessary for obtaining an arbitrary transmittance is obtained.
  • the amplitude of the signal is smaller in the bright display pixel than in the dark display pixel.
  • the amplitude of the video signal can be made smaller than before, it is possible to perform the same image display as before.
  • the amplitude of the video signal can be made smaller than before, the power consumption is reduced more than before.
  • the multi-pixel structure was mainly used in large panels for televisions.
  • the configuration according to this embodiment is a simple configuration as can be understood from FIGS. It can be applied relatively easily to medium and small panels.
  • FIG. 7 is a diagram showing a layout in the vicinity of the pixel formation portion in the modification of the first embodiment.
  • the transparent electrode has one layer (see FIG. 3), but in the present modification, the transparent electrode has two layers.
  • the pixel electrode 1011 for bright display functions in a portion other than the region where the first gate bus line GL1 and the second gate bus line GL2 are disposed in the region between two adjacent source bus lines SL.
  • the upper transparent electrode 121a and the upper transparent electrode 121b functioning as the pixel electrode 1012 for dark display being provided, the upper transparent electrode 121a and the upper transparent electrode
  • the lower transparent electrode 122 is provided so as to have a portion overlapping the electrode 121b in the vertical direction.
  • a capacitor Ctr is formed by the upper transparent electrode 121b and the lower transparent electrode 122.
  • the first transparent electrode is realized by the upper transparent electrodes 121a and 121b
  • the second transparent electrode is realized by the lower transparent electrode 122.
  • the upper transparent electrode 121a and the upper transparent electrode 121b are electrically separated.
  • the drain electrode of the thin film transistor T1 and the upper transparent electrode 121a are electrically connected by the source metal SE3 and the contact CT4.
  • the drain electrode of the thin film transistor T2 and the upper transparent electrode 121b are electrically connected by the source metal SE4 and the contact CT5.
  • the source metal SE3 and the lower transparent electrode 122 are electrically connected by a contact CT4.
  • FIG. 8 is a cross-sectional view taken along line AA in FIG.
  • the upper transparent electrodes 121a and 121b are arranged closer to the common electrode COM than the lower transparent electrode 122.
  • a capacitor Clc1 is formed by the upper transparent electrode 121a and the common electrode COM
  • a capacitor Clc2 is formed by the upper transparent electrode 121b and the common electrode COM.
  • the upper layer transparent electrode 121b and the lower layer transparent electrode 122 form a capacitor Ctr. Note that the upper transparent electrode 121a, the lower transparent electrode 122, and the source metal SE3 are electrically connected to each other by the contact CT4.
  • the capacitor Ctr is formed by two transparent layers of electrodes (upper transparent electrode and lower transparent electrode). For this reason, compared with the said 1st Embodiment (refer FIG. 3), an aperture ratio can be enlarged and a capacity
  • the liquid crystal applied voltage when writing is performed is different from the liquid crystal applied voltage when negative writing is performed. For example, when the pixel electrode potentials Vpix1 and Vpix2 change as shown in FIG.
  • the pixel for bright display is subjected to positive polarity writing.
  • the liquid crystal application voltage when negative polarity writing is performed is larger than the liquid crystal application voltage.
  • the liquid crystal applied voltage is biased with positive and negative polarities, and as a result, the reliability of the liquid crystal is lowered (for example, image sticking occurs on the screen).
  • ⁇ Vg1 and ⁇ Vg2 depends on the difference between the on-level potential and off-level potential applied to the gate bus line, the pixel electrode (or an electrode electrically connected to the pixel electrode, etc.) and other electrodes, etc. Depends on the size of the capacitance formed. Therefore, in this embodiment, an auxiliary capacitor is provided in parallel with the liquid crystal capacitor, and the capacitance value of the auxiliary capacitor is adjusted so that the magnitude of ⁇ Vg1 and the magnitude of ⁇ Vg2 are as equal as possible.
  • FIG. 10 is a block diagram showing the overall configuration of an active matrix liquid crystal display device according to the second embodiment of the present invention.
  • This liquid crystal display device is provided with an auxiliary capacitance wiring driver 500 in addition to the components in the first embodiment shown in FIG.
  • a plurality of auxiliary capacitance lines CSL are formed in addition to the plurality of gate bus lines GL and the plurality of source bus lines SL.
  • the auxiliary capacitance line driver 500 controls the potential of the auxiliary capacitance line CSL based on the auxiliary capacitance line control signal SCS output from the display control circuit 200.
  • Other components operate in the same manner as in the first embodiment.
  • the driving method is the same as that in the first embodiment.
  • FIG. 11 is an equivalent circuit diagram illustrating a configuration of the pixel formation portion in the present embodiment.
  • a wiring that passes through the pixel forming portion in addition to the first gate bus line GL1, the second gate bus line GL2, and the source bus line SL, a bright display pixel and a dark display pixel are connected.
  • Auxiliary capacitance lines CSL1 and CSL2 are provided so as to correspond to each.
  • the pixel formation portion includes an electrode 1031 electrically connected to the pixel electrode 1011 for bright display, and a pixel electrode 1012 for dark display and an electrical connection to the pixel electrode 1012 for dark display. And an electrode 1032 connected to each other.
  • the storage capacitor Ccs1 is formed by the storage capacitor line CSL1 and the electrode 1031
  • the storage capacitor Ccs2 is formed by the storage capacitor line CSL2 and the electrode 1032.
  • the auxiliary capacitance line CSL1 is referred to as “first auxiliary capacitance line”
  • the auxiliary capacitance line CSL2 is referred to as “second auxiliary capacitance line”.
  • the description is based on the premise that two auxiliary capacitor lines are provided as the lines passing through each pixel formation portion, but the auxiliary capacitor line and the auxiliary capacitor Ccs2 for forming the auxiliary capacitor Ccs1 are formed.
  • the auxiliary capacitance wiring for this may be the same wiring.
  • the first auxiliary capacitor is realized by the auxiliary capacitor Ccs1
  • the second auxiliary capacitor is realized by the auxiliary capacitor Ccs2.
  • Layout> 12 is a diagram showing a layout in the vicinity of the pixel formation portion for realizing the circuit configuration shown in FIG. Only differences from the first embodiment (see FIG. 3) will be described.
  • the first auxiliary capacitance line CSL1 is disposed so as to overlap the transparent electrode 111 in the vertical direction and to extend in parallel with the first gate bus line GL1.
  • the second auxiliary capacitance line CSL2 is disposed so as to overlap the transparent electrode 112 in the vertical direction and to extend in parallel with the second gate bus line GL2.
  • the storage capacitor Ccs1 is formed by the source metal SE1 connected to the drain electrode of the thin film transistor T1 and the first storage capacitor line CSL1, and the source metal SE2 connected to the drain electrode of the thin film transistor T2 and the second auxiliary capacitor Ccs1.
  • a storage capacitor Ccs2 is formed by the capacitor wiring CSL2. That is, the source metal SE1 functions as the electrode 1031 and the source metal SE2 functions as the electrode 1032.
  • each of the bright display pixel and the dark display pixel is provided with an auxiliary capacitor, and the magnitude of the voltage variation ⁇ Vg1 in the bright display pixel and the voltage variation ⁇ Vg2 in the dark display pixel.
  • the capacitance values of the auxiliary capacitors in both the pixels are adjusted so that the size of each pixel becomes as equal as possible.
  • the occurrence of a bias in the liquid crystal applied voltage between the positive and negative polarities is suppressed in both the dark display pixel and the bright display pixel, and the reliability of the liquid crystal is reduced (such as the occurrence of image sticking to the screen). It is suppressed.
  • FIG. 13 is a diagram showing a layout in the vicinity of the pixel formation portion in the first modification of the second embodiment.
  • the transparent electrode has two layers as in the modification of the first embodiment. That is, the region between the two adjacent source bus lines SL functions as a bright display pixel electrode 1011 in a portion other than the region where the first gate bus line GL1 and the second gate bus line GL2 are disposed.
  • a lower transparent electrode is provided in addition to the upper transparent electrode 121a and the upper transparent electrode 121b functioning as the pixel electrode 1012 for dark display.
  • the upper transparent electrodes 121a and 121b have the same shape as that of the modified example of the first embodiment (see FIG. 7).
  • the upper transparent electrode 121a and the upper transparent electrode 121b are electrically separated.
  • the lower transparent electrode is divided into a portion denoted by reference numeral 122a, a portion denoted by reference numeral 122b, and a portion denoted by reference numeral 122c in FIG.
  • the lower transparent electrode 122a functions in the same way as the modification of the first embodiment, the lower transparent electrode 122b functions as the first auxiliary capacitance line CSL1, and the lower transparent electrode 122c functions as the second auxiliary capacitance line CSL2.
  • the upper transparent electrode 121a and the lower transparent electrode 122a are electrically connected by a contact CT4.
  • the first transparent electrode is realized by the upper transparent electrodes 121a and 121b
  • the second transparent electrode is realized by the lower transparent electrodes 122a, 122b, and 122c.
  • the first electrode portion is realized by the lower transparent electrode 122a
  • the second electrode portion is realized by the lower transparent electrode 122b
  • the third electrode portion is realized by the lower transparent electrode 122c.
  • the auxiliary capacitor Ccs1 is formed by the upper transparent electrode 121a and the lower transparent electrode 122b (first auxiliary capacitor line CSL1) connected to the drain electrode of the thin film transistor T1, and is connected to the drain electrode of the thin film transistor T2.
  • the auxiliary capacitance Ccs2 is formed by the upper transparent electrode 121b and the lower transparent electrode 122c (second auxiliary capacitance line CSL2).
  • a capacitor Ctr is formed by the upper transparent electrode 121b and the lower transparent electrode 122a.
  • the auxiliary capacitance Ccs1 is formed by the upper transparent electrode 121a and the lower transparent electrode 122b which are two transparent electrodes, and the upper transparent electrode 121b and the lower transparent electrode 122c which are two transparent electrodes.
  • an auxiliary capacitor Ccs2 is formed. For this reason, the fall of the aperture ratio by providing an auxiliary capacity
  • FIG. 14 is an equivalent circuit diagram showing a configuration of the pixel formation portion in the second modification of the second embodiment.
  • the auxiliary capacitor is provided in parallel with the liquid crystal capacitor. However, in this modification, it is formed between the pixel electrode and the gate bus line. Adjustments are made to the size of the parasitic capacitance. More specifically, the size of ⁇ Vg1 is adjusted based on the size of the parasitic capacitance Cgd1 formed between the pixel electrode 1011 for bright display and the first gate bus line GL1, and the pixel electrode 1012-second gate for dark display is adjusted.
  • the magnitude of ⁇ Vg2 is adjusted based on the magnitude of the parasitic capacitance Cgd2 formed between the bus lines GL2.
  • the first parasitic capacitance is realized by the parasitic capacitance Cgd1
  • the second parasitic capacitance is realized by the parasitic capacitance Cgd2.
  • FIG. 15 is a diagram showing a layout in the vicinity of the pixel formation portion for realizing the circuit configuration shown in FIG.
  • the source metal SE1 and the first gate bus line for electrically connecting the transparent electrode 111 functioning as the pixel electrode 1011 for bright display and the drain electrode of the thin film transistor T1.
  • a parasitic capacitance Cgd1 is formed by GL1.
  • the size of the portion where the source metal SE1 and the first gate bus line GL1 overlap and the size of the portion where the source metal SE2 and the second gate bus line GL2 overlap are adjusted.
  • the magnitudes (capacitance values) of the parasitic capacitances Cgd1 and Cgd2 are adjusted so that the magnitude of ⁇ Vg1 and the magnitude of ⁇ Vg2 are as equal as possible.
  • a parasitic capacitance Cgd1 is formed by the gate bus line GL1, and a source metal SE4 and a second gate bus for electrically connecting the upper transparent electrode 121b functioning as the pixel electrode 1012 for dark display and the drain electrode of the thin film transistor T2 are connected.
  • the parasitic capacitance Cgd2 is formed by the line GL2, and the size of the portion 63 where the source metal SE3 and the first gate bus line GL1 overlap and the size of the portion 64 where the source metal SE4 and the second gate bus line GL2 overlap are adjusted. (See FIG. 16).
  • the configuration of the pixel forming portion the configuration of the present modification (see FIG. 14) and the configuration of the second embodiment (see FIG. 11) may be combined. That is, as shown in FIG. 17, the components for adjusting the magnitudes of ⁇ Vg1 and ⁇ Vg2 are formed between the auxiliary capacitances Ccs1 and Ccs2 formed between the pixel electrode and the auxiliary capacitance line and between the pixel electrode and the gate bus line. Parasitic capacitances Cgd1 and Cgd2 may be provided.
  • FIG. 18 is an equivalent circuit diagram showing a configuration of a pixel formation portion of an active matrix liquid crystal display device according to the third embodiment of the present invention.
  • the pixel forming portion is provided with one thin film transistor T3 and two capacitors Clc3 and Ctra in addition to the components in the first embodiment shown in FIG.
  • the overall configuration is the same as that of the first embodiment, and a description thereof will be omitted (FIG. 2).
  • the gate electrode is connected to the first gate bus line GL1
  • the source electrode is connected to the source bus line SL
  • the drain electrode is connected to one end of the capacitor Clc3 and one end of the capacitor Ctra.
  • One end of the capacitor Clc3 is connected to the drain electrode of the thin film transistor T3 and one end of the capacitor Ctra, and the other end of the capacitor Clc3 is connected to the common electrode COM.
  • One end of the capacitor Ctra is connected to the drain electrode of the thin film transistor T3 and one end of the capacitor Clc3, and the other end of the capacitor Ctra is connected to the drain electrode of the thin film transistor T2, one end of the capacitor Clc2, and the other end of the capacitor Ctr.
  • the capacitance value of the capacitor Ctr and the capacitance value of the capacitor Ctra are set to different values.
  • the pixel electrode 1013 for intermediate display display of intermediate brightness between bright display and dark display
  • the capacitor Clc3 is formed by the intermediate display pixel electrode 1013 and the common electrode COM.
  • the other end of the capacitor Ctra is connected to the capacitor (the intermediate display pixel electrode 1013) between the intermediate display pixel electrode 1013 or an electrode electrically connected to the intermediate display pixel electrode 1013.
  • the potential of the amplification electrode 104 is equal to the potential of the pixel electrode 1012 for dark display.
  • the potential of the pixel electrode 1013 for intermediate display is denoted by reference numeral Vpix3.
  • one end of the capacitor Ctr is electrically connected to the pixel electrode 1012 for dark display or electrically connected to the pixel electrode 1012 for dark display.
  • a third display capacitor is realized by the capacitor Clc3
  • a second coupling capacitor is realized by the capacitor Ctra
  • a third switching element is realized by the thin film transistor T3
  • an intermediate display is provided.
  • a third pixel electrode is realized by the pixel electrode 1013.
  • FIG. 19 is a diagram showing a layout in the vicinity of the pixel formation portion for realizing the circuit configuration shown in FIG.
  • the gate metal forming the two first gate bus lines GL1 and the gate metal forming the second gate bus line GL2 are arranged in parallel to each other.
  • the gate metal and the source metal forming the source bus line SL are disposed so as to be orthogonal to each other.
  • the area other than the area where the first gate bus line GL1 and the second gate bus line GL2 are disposed is used for bright display.
  • the transparent electrode 131 that functions as the pixel electrode 1011, the transparent electrode 132 that functions as the pixel electrode 1012 for dark display, and the transparent electrode 133 that functions as the pixel electrode 1013 for intermediate display are formed. Further, an electrode 15 functioning as the amplification electrode 103 and an electrode 14 functioning as the amplification electrode 104 are formed between two adjacent source bus lines SL by gate metal as shown in FIG. In the present embodiment, the transparent electrode 131, the transparent electrode 132, and the transparent electrode 133 are formed in the same layer.
  • the drain electrode of the thin film transistor T1 and the electrode 15 are electrically connected by the source metal SE7 and the contact CT9.
  • the drain electrode of the thin film transistor T1 and the transparent electrode 131 are electrically connected by the source metal SE7 and the contact CT10.
  • the drain electrode of the thin film transistor T2 and the electrode 14 are electrically connected by the source metal SE6 and the contact CT7.
  • the drain electrode of the thin film transistor T2 and the transparent electrode 132 are electrically connected by the source metal SE6 and the contact CT8.
  • the drain electrode of the thin film transistor T3 and the transparent electrode 133 are electrically connected by the source metal SE5 and the contact CT6.
  • the source metal SE6 and the electrode 15 form a capacitor Ctr
  • the source metal SE5 and the electrode 14 form a capacitor Ctra.
  • the selection period includes a first charging period Ta and a second charging period Tb.
  • the first gate bus line GL1 is turned on (see FIG. 20) while the second gate bus line GL2 is supplied with the off-level (low level in the example shown in FIG. 20) potential.
  • a high level potential is applied.
  • the thin film transistors T1 and T3 are turned on and the thin film transistor T2 is turned off.
  • the video signal potential Vdata is applied to the pixel electrode 1011 (transparent electrode 131) for bright display and the pixel electrode 1013 (transparent electrode 133) for intermediate display.
  • the second charging period Tb an on-level potential is applied to the second gate bus line GL2 while an off-level potential is applied to the first gate bus line GL1.
  • the thin film transistors T1 and T3 are turned off and the thin film transistor T2 is turned on.
  • the video signal potential Vdata is applied to the dark display pixel electrode 1012 (transparent electrode 132).
  • the pixel electrode potential Vpix2 rises from a negative potential to a positive potential with respect to the common electrode potential Vcom.
  • the pixel electrode 1011 (transparent electrode 131) for bright display is in a floating state
  • the pixel electrode potential Vpix1 rises via the capacitor Ctr as the pixel electrode potential Vpix2 rises.
  • the intermediate display pixel electrode 1013 (transparent electrode 133) is also in a floating state, the pixel electrode potential Vpix3 rises via the capacitor Ctra as the pixel electrode potential Vpix2 rises.
  • the capacitance value of the capacitor Ctr and the capacitance value of the capacitor Ctra are set to different values. For this reason, the magnitude of the change in the pixel electrode potential Vpix1 and the magnitude of the change in the pixel electrode potential Vpix3 are different in the second charging period Tb.
  • the selection period for charging the pixel capacitor includes the first charging period Ta and the second charging period Tb.
  • the first charging period Ta the pixel electrode potential Vpix1 and the pixel electrode potential Vpix3 are made equal to the video signal potential Vdata
  • the second charging period Tb the pixel electrode potential Vpix2 is made equal to the video signal potential Vdata.
  • a capacitor is formed between the pixel electrode 1011 for bright display and the pixel electrode 1012 for dark display, and between the pixel electrode 1013 for intermediate display and the pixel electrode 1012 for dark display, and
  • the second charging period Tb the pixel electrode 1011 for bright display and the pixel electrode 1013 for intermediate display are in a floating state.
  • the pixel electrode potential Vpix1 and the pixel electrode potential Vpix3 are amplified with the change of the pixel electrode potential Vpix2.
  • the pixel electrode potential Vpix2 becomes equal to the video signal potential Vdata (when positive writing is performed)
  • the pixel electrode potential Vpix1 and the pixel electrode potential Vpix3 are higher than the video signal potential Vdata.
  • the capacitance Ctr between the pixel electrode 1012 for bright display and the pixel electrode 1012 for dark display is different from the capacitance Ctra between the pixel electrode 1012 for intermediate display and the pixel electrode 1012 for dark display. .
  • the pixel electrode potential Vpix1 and the pixel electrode potential Vpix3 have different values (Vpix1> Vpix3 in the example shown in FIG. 20). Accordingly, at the end of the selection period, the pixel electrode potential Vpix1, the pixel electrode potential Vpix2, and the pixel electrode potential Vpix3 have different values. As a result, different voltages are applied to the liquid crystal in the bright display pixel, the intermediate display pixel, and the dark display pixel. Similarly to the first embodiment, even when the amplitude of the video signal is made smaller than that of the conventional image display, the same image display as the conventional image can be performed. As described above, it is possible to improve the viewing angle characteristics with higher accuracy while reducing the power consumption as compared with the prior art.
  • FIG. 21 is a diagram showing a layout in the vicinity of the pixel formation portion in the modification of the third embodiment.
  • the transparent electrode has one layer (see FIG. 19), but in the present modification, the transparent electrode has two layers.
  • the pixel electrode 1011 for bright display functions in a portion other than the region where the first gate bus line GL1 and the second gate bus line GL2 are disposed in the region between two adjacent source bus lines SL.
  • the upper transparent electrode 141 functioning as the pixel electrode 1012 for dark display, and the upper transparent electrode 143 functioning as the pixel electrode 1013 for intermediate display, the upper transparent electrode 141 is provided.
  • the lower transparent electrode 144 is provided so as to have a portion that overlaps with each other in the vertical direction.
  • the first transparent electrode is realized by the upper transparent electrodes 141, 142, and 143
  • the second transparent electrode is realized by the lower transparent electrode 144.
  • the upper transparent electrodes 141, 142, and 143 are electrically separated from each other.
  • the drain electrode of the thin film transistor T1 and the upper transparent electrode 141 are electrically connected by the source metal SE10 and the contact CT13.
  • the drain electrode of the thin film transistor T2 and the upper transparent electrode 142 are electrically connected by the source metal SE9 and the contact CT12.
  • the upper transparent electrode 142 and the lower transparent electrode 144 are connected by the contact CT12.
  • the drain electrode of the thin film transistor T3 and the upper transparent electrode 143 are electrically connected by the source metal SE8 and the contact CT11.
  • the upper transparent electrode 141 and the lower transparent electrode 144 form a capacitor Ctr
  • the upper transparent electrode 143 and the lower transparent electrode 144 form a capacitor Ctra.
  • the capacitors Ctr and Ctra are formed by two transparent electrodes. For this reason, the effect similar to the said 3rd Embodiment can be acquired, suppressing the fall of an aperture ratio.
  • FIG. 22 is an equivalent circuit diagram showing a configuration of a pixel formation portion of an active matrix liquid crystal display device according to the fourth embodiment of the present invention.
  • the pixel formation portion is provided with one thin film transistor T3 and two capacitors Clc3 and Ctrb in addition to the components in the first embodiment shown in FIG.
  • the overall configuration is the same as that of the first embodiment, and a description thereof will be omitted (FIG. 2).
  • the gate electrode is connected to the first gate bus line GL1
  • the source electrode is connected to the source bus line SL
  • the drain electrode is connected to one end of the capacitor Clc3 and one end of the capacitor Ctrb.
  • One end of the capacitor Clc3 is connected to the drain electrode of the thin film transistor T3 and one end of the capacitor Ctrb, and the other end of the capacitor Clc3 is connected to the common electrode COM.
  • One end of the capacitor Ctrb is connected to the drain electrode of the thin film transistor T3 and one end of the capacitor Clc3, and the other end of the capacitor Ctrb is connected to the drain electrode of the thin film transistor T1, one end of the capacitor Clc1, and one end of the capacitor Ctr.
  • the capacitor Ctr and the capacitor Ctrb are connected in series.
  • the pixel electrode 1013 for intermediate display (display of intermediate brightness between bright display and dark display) is present at one end of the capacitor Clc3. That is, the capacitor Clc3 is formed by the intermediate display pixel electrode 1013 and the common electrode COM.
  • the other end of the capacitor Ctrb has a capacitor (the intermediate display pixel electrode 1013) between the intermediate display pixel electrode 1013 or an electrode electrically connected to the intermediate display pixel electrode 1013.
  • FIG. 23 is a diagram showing a layout in the vicinity of the pixel formation portion for realizing the circuit configuration shown in FIG.
  • the gate metal forming each of the two first gate bus lines GL1 and the gate metal forming the second gate bus line GL2 are arranged in parallel to each other.
  • the gate metal and the source metal forming the source bus line SL are disposed so as to be orthogonal to each other.
  • the area other than the area where the first gate bus line GL1 and the second gate bus line GL2 are disposed is used for bright display.
  • the transparent electrode 151 that functions as the pixel electrode 1011, the transparent electrode 152 that functions as the pixel electrode 1012 for dark display, and the transparent electrode 153 that functions as the pixel electrode 1013 for intermediate display are formed. Further, the electrode 17 functioning as the amplification electrode 102 and the electrode 16 functioning as the amplification electrode 105 are formed between the two adjacent source bus lines SL by gate metal as shown in FIG. In the present embodiment, the transparent electrode 151, the transparent electrode 152, and the transparent electrode 153 are formed in the same layer.
  • the drain electrode of the thin film transistor T1 and the electrode 16 are electrically connected by the source metal SE12 and the contact CT15.
  • the drain electrode of the thin film transistor T1 and the transparent electrode 151 are electrically connected by the source metal SE12 and the contact CT16.
  • the drain electrode of the thin film transistor T2 and the electrode 17 are electrically connected by the source metal SE13 and the contact CT17.
  • the drain electrode of the thin film transistor T2 and the transparent electrode 152 are electrically connected by the source metal SE13 and the contact CT18.
  • the drain electrode of the thin film transistor T3 and the transparent electrode 153 are electrically connected by the source metal SE11 and the contact CT14.
  • the source metal SE12 and the electrode 17 form a capacitor Ctr
  • the source metal SE11 and the electrode 16 form a capacitor Ctrb.
  • the driving method is the same as that in the third embodiment (see FIG. 20). However, in the present embodiment, the pixel electrode potential Vpix1 and the pixel electrode potential Vpix3 have different values at the end of the selection period for a reason different from that in the third embodiment. This will be described below.
  • a capacitor Ctr exists between the pixel electrode 1012 for dark display and the pixel electrode 1011 for bright display. On the other hand, between the pixel electrode 1012 for dark display and the pixel electrode 1013 for intermediate display, the capacitor Ctr and the capacitor Ctrb are connected in series.
  • the capacitance values thereof are also denoted by the same symbols “Ctr” and “Ctrb”, respectively.
  • the capacitance value between the pixel electrode 1012 for dark display and the pixel electrode 1011 for bright display becomes Ctr.
  • the combined capacitance value between the pixel electrode 1012 for dark display and the pixel electrode 1013 for intermediate display is Cx.
  • the combined capacitance value Cx is expressed by the following equation (6).
  • Cx Ctr ⁇ Ctrb / (Ctr + Ctrb) (6)
  • FIG. 24 is a diagram showing a layout in the vicinity of the pixel formation portion in the modification of the fourth embodiment.
  • the transparent electrode has one layer (see FIG. 23), but in the present modification, the transparent electrode has two layers.
  • the pixel electrode 1011 for bright display functions in a portion other than the region where the first gate bus line GL1 and the second gate bus line GL2 are disposed in the region between two adjacent source bus lines SL.
  • the upper transparent electrode 161 functioning as the pixel electrode 1012 for dark display, and the upper transparent electrode 163 functioning as the pixel electrode 1013 for intermediate display, the upper transparent electrode 161 is provided.
  • the first transparent electrode is realized by the upper transparent electrodes 161, 162, and 163, and the second transparent electrode is realized by the lower transparent electrode 164.
  • the upper transparent electrodes 161, 162, and 163 are electrically separated from each other.
  • the drain electrode of the thin film transistor T1 and the upper transparent electrode 161 are electrically connected by the source metal SE15 and the contact CT20. Further, the upper transparent electrode 161 and the lower transparent electrode 164 are connected by the contact CT20.
  • the drain electrode of the thin film transistor T2 and the upper transparent electrode 162 are electrically connected by the source metal SE16 and the contact CT21.
  • the drain electrode of the thin film transistor T3 and the upper transparent electrode 163 are electrically connected by the source metal SE14 and the contact CT19.
  • the upper transparent electrode 162 and the lower transparent electrode 164 form a capacitor Ctr
  • the upper transparent electrode 163 and the lower transparent electrode 164 form a capacitor Ctrb.
  • the capacitors Ctr and Ctrb are formed by two transparent electrodes. For this reason, it is possible to improve the viewing angle characteristics with higher accuracy while suppressing the decrease in the aperture ratio and reducing the power consumption as compared with the related art.
  • FIG. 25 is a signal waveform diagram for describing a driving method in the present embodiment.
  • the length of the selection period typically corresponds to the length of one horizontal scanning period in a conventional liquid crystal display device.
  • an on-level potential is applied only to the first gate bus line GL1 during a period Tp during which an on-level potential is applied to both the first gate bus line GL1 and the second gate bus line GL2.
  • Period Tq In the period Tp, the thin film transistor T1 is turned on and the thin film transistor T2 is turned on.
  • the pixel electrode potential Vpix2 rises to a potential lower than the pixel electrode potential Vpix1 by capacitive coupling between the pixel electrode 1012 for bright display and the pixel electrode 1012 for dark display by the capacitor Ctr (see FIG. 1).
  • a potential difference is generated between the source bus line SL and the pixel electrode 1012 for dark display, and charging is performed via the thin film transistor T2 in the pixel for dark display.
  • the thin film transistor T1 is turned on and the thin film transistor T2 is turned off. As a result, only the pixels for bright display are charged, and the pixel electrode potential Vpix1 rises to the video signal potential Vdata.
  • the period during which the on-level potential is applied is shorter in the second gate bus line GL2 than in the first gate bus line GL1.
  • the gate-on voltage VGH2 for the second gate bus line GL2 is lower than the gate-on voltage VGH1 for the first gate bus line GL1.
  • the charging capability of the thin film transistor T2 is lower than the charging capability of the thin film transistor T1. Therefore, the difference between the pixel electrode potential Vpix1 and the pixel electrode potential Vpix2 caused by the capacitive coupling does not become zero during the selection period. In this manner, voltages having different magnitudes are applied to the liquid crystal between the dark display pixel and the bright display pixel.
  • the first on-period is realized by a period (a period corresponding to one horizontal scanning period) that is a combination of the period Tp and the period Tq, and the second on-period is realized by the period Tp.
  • a first on-potential is realized by VGH1
  • a second on-potential is realized by VGH2.
  • the pixel electrode potential Vpix1 is equal to the video signal potential Vdata, and the pixel electrode potential Vpix2 is lower than the pixel electrode potential Vpix1. Therefore, unlike the first to fourth embodiments, the effect of reducing the power consumption by reducing the amplitude of the video signal cannot be obtained. However, since the charging time of a length corresponding to one horizontal scanning period is obtained for the bright display pixel, the charging load is reduced as compared with the first to fourth embodiments. Therefore, even if high-speed driving is performed, deterioration in display quality due to insufficient charging is suppressed. As described above, it is possible to improve both viewing angle characteristics and drive speed.
  • the pixel formation portion is configured as shown in FIG. 32, and the thin film transistors T95 and T96 have different sizes.
  • the thin film transistors T95 and T96 have different sizes.
  • a thin film transistor using an oxide semiconductor such as IGZO in the channel portion since the mobility is high, the size of the thin film transistor is generally reduced at the initial stage of design. Therefore, considering the processing accuracy in the manufacturing process, it is difficult to make the size of one thin film transistor smaller than the size of the other thin film transistor.
  • the gate-on voltage VGH1 for the first gate bus line GL1 and the gate-on voltage VGH2 for the second gate bus line GL2 are set to different values, and the gate-on period for the first gate bus line GL1.
  • the present invention is not limited to this, although the gate-on periods for the second gate bus line GL2 are different from each other.
  • the first gate bus line GL1 and the second gate bus line GL2 have the same gate-on period, and the gate-on voltage VGH1 and the second gate bus line GL2 for the first gate bus line GL1. Even if the gate-on voltage VGH2 is set to a different value, the same effect as in the fifth embodiment can be obtained.
  • the gate-on voltage value of the first gate bus line GL1 and the second gate bus line GL2 are the same, and the gate-on period of the first gate bus line GL1 and the second gate bus line GL2 Even if the gate-on period is different from each other, the same effect as in the fifth embodiment can be obtained.
  • FIG. 28 is a block diagram showing the overall configuration of an active matrix liquid crystal display device according to the sixth embodiment of the present invention.
  • a drive mode control unit 210 is provided in the display control circuit 200.
  • the liquid crystal display device according to the present embodiment is provided with two drive modes, a first drive mode and a second drive mode.
  • the two drive modes are switched by the drive mode control unit 210 according to the type of display image. For example, switching between the first drive mode and the second drive mode is performed depending on whether the display is a moving image display or a still image display. Since the pixel structure and the layout in the vicinity of the pixel formation portion are the same as those in the first embodiment, description thereof will be omitted (see FIGS. 1 and 3).
  • the liquid crystal display device is driven in the same manner as in the first embodiment (see FIG. 5). That is, the selection period is constituted by the first charging period Ta and the second charging period Tb, the pixel electrode potential Vpix1 is made equal to the video signal potential Vdata in the first charging period Ta, and the pixel electrode in the second charging period Tb.
  • the potential Vpix2 is set equal to the video signal potential Vdata.
  • the liquid crystal display device is driven as follows (see FIGS. 1 and 29).
  • an on-level (high level in the example shown in FIG. 29) potential is applied to both the first gate bus line GL1 and the second gate bus line GL.
  • the thin film transistor T1 is turned on and the thin film transistor T2 is turned on.
  • the video signal potential Vdata is applied to both the pixel electrode 1011 for bright display and the pixel electrode 1012 for dark display. That is, at the end of the selection period, the pixel electrode potential Vpix1 and the pixel electrode potential Vpix2 are equal.
  • the length of the selection period corresponds to the length of one horizontal scanning period in the conventional liquid crystal display device.
  • the potential of the first gate bus line GL1 and the potential of the second gate bus line GL change from the on level to the off level.
  • the above-described voltage fluctuation occurs in the same manner in the pixel electrode 1011 for bright display and the pixel electrode 1012 for dark display. Therefore, there is no difference in pixel electrode potential between the bright display pixel and the dark display pixel.
  • the second drive mode is selected, the effect of improving the viewing angle characteristics by adopting the multi-pixel structure cannot be obtained.
  • the liquid crystal display device can be driven in two drive modes.
  • the first drive mode the effect of improving the viewing angle characteristics can be obtained as described above.
  • the second drive mode the effect of improving the viewing angle characteristics cannot be obtained.
  • a charging time having a length corresponding to one horizontal scanning period is obtained in both the bright display pixel and the dark display pixel. Therefore, when high speed driving is required, driving in the second driving mode can suppress deterioration in display quality due to insufficient charging.
  • the second drive mode may be selected.
  • the effect of improving the viewing angle characteristics can be obtained by appropriately switching the drive mode, and the effect of suppressing the deterioration of display quality due to insufficient charging during high-speed driving. Can also be obtained.
  • the pixel electrode potential Vpix2 does not rise to the video signal potential Vdata during the selection period (see FIG. 25).
  • both the pixel electrode potential Vpix1 and the pixel electrode potential Vpix2 are equal to the video signal potential Vdata.
  • a general color liquid crystal display device includes three pixels for R (red) color, G (green) color, and B (blue) color. For a bright display in the second charging period Tb.
  • the amplification amount of the pixel electrode potential Vpix1 and the pixel electrode potential Vpix3 for intermediate display can be adjusted for each color. This makes it possible to adjust the viewing angle characteristics more finely.
  • the capacitance value of the capacitance Ctr is set to a different value for each color.
  • the value of the pixel electrode potential Vpix1 at the start of the second charging period Tb is the value of the video signal potential Vdata regardless of the capacitance value of the capacitor Ctr, and the pixel at the end of the second charging period Tb. Since the value of the electrode potential Vpix1 is expressed by the above formulas (1) to (3), it can be understood that the amount of amplification of the pixel electrode potential Vpix1 in the second charging period Tb is different if the capacitance value of the capacitor Ctr is different. For example, in the case of a three-color liquid crystal display device, the capacitance value of the capacitor Ctr may be different from the other two colors for only one color.
  • the liquid crystal display device has been described as an example.
  • the present invention is not limited to this, and the present invention can be applied to display devices other than the liquid crystal display device. it can.
  • the present invention is useful in that the display device having a large panel can reduce the power consumption by reducing the amplitude of the video signal.
  • the present invention can also be applied to a display device having a small panel. it can.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

Dans un dispositif d'affichage à cristaux liquides de la présente invention, ledit dispositif d'affichage à cristaux liquides présente une configuration telle qu'un pixel est divisé en une pluralité de sous-pixels, la consommation d'énergie étant réduite du fait de la réduction de l'amplitude de signaux vidéo. Dans chacune des sections de formation de pixels, un condensateur (Ctr) est disposé entre une électrode de pixels (1011) destinée à un affichage clair et une électrode de pixels (1012) destinée à un affichage foncé. Une période de sélection est constituée d'une première période de charge et d'une seconde période de charge. Pendant la première période de charge, le potentiel d'une ligne de bus de source (SL) est appliqué à l'électrode de pixels (1011) destinée à un affichage clair. Pendant la seconde période de charge, le potentiel de la ligne de bus de source (SL) est appliqué à l'électrode de pixels (1012) destinée à l'affichage clair tandis que l'électrode de pixels (1011) destinée à l'affichage clair se trouve dans un état flottant.
PCT/JP2012/068918 2011-08-03 2012-07-26 Dispositif d'affichage et procédé d'attaque associé WO2013018636A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011169855 2011-08-03
JP2011-169855 2011-08-03

Publications (1)

Publication Number Publication Date
WO2013018636A1 true WO2013018636A1 (fr) 2013-02-07

Family

ID=47629161

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/068918 WO2013018636A1 (fr) 2011-08-03 2012-07-26 Dispositif d'affichage et procédé d'attaque associé

Country Status (1)

Country Link
WO (1) WO2013018636A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04348324A (ja) * 1990-07-23 1992-12-03 Hosiden Corp 液晶表示素子
JP2006139288A (ja) * 2004-11-12 2006-06-01 Samsung Electronics Co Ltd 表示装置及びその駆動方法
JP2008129607A (ja) * 2006-11-23 2008-06-05 Samsung Electronics Co Ltd 表示パネル
WO2009107271A1 (fr) * 2008-02-27 2009-09-03 シャープ株式会社 Substrat de matrice active, écran à cristaux liquides, dispositif d'affichage à cristaux liquides, unité d'affichage à cristaux liquides et téléviseur
WO2009130826A1 (fr) * 2008-04-25 2009-10-29 シャープ株式会社 Dispositif d'affichage à cristaux liquides et récepteur de télévision

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04348324A (ja) * 1990-07-23 1992-12-03 Hosiden Corp 液晶表示素子
JP2006139288A (ja) * 2004-11-12 2006-06-01 Samsung Electronics Co Ltd 表示装置及びその駆動方法
JP2008129607A (ja) * 2006-11-23 2008-06-05 Samsung Electronics Co Ltd 表示パネル
WO2009107271A1 (fr) * 2008-02-27 2009-09-03 シャープ株式会社 Substrat de matrice active, écran à cristaux liquides, dispositif d'affichage à cristaux liquides, unité d'affichage à cristaux liquides et téléviseur
WO2009130826A1 (fr) * 2008-04-25 2009-10-29 シャープ株式会社 Dispositif d'affichage à cristaux liquides et récepteur de télévision

Similar Documents

Publication Publication Date Title
US9715861B2 (en) Display device having unit pixel defined by even number of adjacent sub-pixels
US8928568B2 (en) Sub-pixel voltage control using coupling capacitors
US9411206B2 (en) Liquid crystal display
JP4790798B2 (ja) アクティブマトリクス型液晶表示装置及びその駆動方法
US8373633B2 (en) Multi-domain vertical alignment liquid crystal display with charge sharing
US9928791B2 (en) Display apparatus and method of driving with pixels alternatively connected to adjacent gate lines
WO2012111476A1 (fr) Dispositif d'affichage et procédé d'entraînement
CN102231256B (zh) 显示子像素电路及使用其的平面显示面板
US20070273677A1 (en) Driving device and display apparatus having the same
KR101906182B1 (ko) 표시장치
US20080067512A1 (en) Array substrate and display apparatus having the same
KR20070059340A (ko) 액정 표시 장치
JPWO2007102382A1 (ja) アクティブマトリクス基板、表示装置及びテレビジョン受像機
US10209580B2 (en) Liquid crystal display device
US20150221273A1 (en) Liquid crystal display device and method for driving the same
TWI518670B (zh) 顯示面板及其驅動方法
US8068085B2 (en) Electro-optical device, method of driving electro-optical device, and electronic apparatus
WO2012111475A1 (fr) Dispositif d'affichage et procédé d'entraînement
KR20120090888A (ko) 액정 표시 장치
KR20140095926A (ko) 액정표시장치
WO2013069559A1 (fr) Dispositif d'affichage et son procédé de commande
WO2013018636A1 (fr) Dispositif d'affichage et procédé d'attaque associé
KR102160121B1 (ko) 표시장치
CN101174043A (zh) 液晶显示装置
WO2013100086A1 (fr) Dispositif d'affichage à cristaux liquides

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12819574

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12819574

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载