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WO2013011705A1 - Procédé de traitement d'un substrat pour éléments semi-conducteurs - Google Patents

Procédé de traitement d'un substrat pour éléments semi-conducteurs Download PDF

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Publication number
WO2013011705A1
WO2013011705A1 PCT/JP2012/051899 JP2012051899W WO2013011705A1 WO 2013011705 A1 WO2013011705 A1 WO 2013011705A1 JP 2012051899 W JP2012051899 W JP 2012051899W WO 2013011705 A1 WO2013011705 A1 WO 2013011705A1
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Prior art keywords
substrate
processing
processing method
blast processing
blast
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Application number
PCT/JP2012/051899
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English (en)
Inventor
Kouichi Inoue
Norihito Shibuya
Original Assignee
Sintokogio, Ltd.
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Filing date
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Application filed by Sintokogio, Ltd. filed Critical Sintokogio, Ltd.
Priority to JP2013532763A priority Critical patent/JP5716834B2/ja
Priority to KR1020137029494A priority patent/KR101883520B1/ko
Priority to CN201280013566.7A priority patent/CN103430281B/zh
Publication of WO2013011705A1 publication Critical patent/WO2013011705A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S2304/00—Special growth methods for semiconductor lasers
    • H01S2304/04—MOCVD or MOVPE
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/0213—Sapphire, quartz or diamond based substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • H01S5/323—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • H01S5/32308—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm
    • H01S5/32341—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm blue laser based on GaN or GaP
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
    • H10H20/01335—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials

Definitions

  • the present invention relates to a processing method of a substrate for semiconductor elements.
  • a light-emitting layer made of a GaN-based compound semiconductor is formed by epitaxial crystal growth on a mirror-finished main surface of a substrate formed of a material such as sapphire, and then electrodes are formed on the epitaxially grown wafer.
  • the epitaxial growth (EPI growth) process includes steps, such as a step of forming a film on a substrate while heating the substrate, and a step of cooling the substrate to normal temperature after the film-forming step.
  • Patent Literature 1 discloses a technique to correct the warp. In this method, a large-sized press apparatus capable of applying pressure of 4.9x10 4 Pa to 4.9 10 6 Pa is used.
  • Patent Literature 1 Japanese Patent Laid-Open Publication No. 2003-128499
  • Patent Literature 1 In the method described in Patent Literature 1, a press mechanism needs to be provided in an MOCVD apparatus for epitaxial growth. Further, according to a market trend toward mass production, the size of the substrate used in the manufacturing process tends to be further increased from the two-inch size to the four-inch size in future.
  • a processing method of a substrate for semiconductor elements is a processing method of a substrate for semiconductor elements, for applying blast processing to a substrate having a first surface and a second surface opposite to the first surface, and is featured by including a step of applying the blast processing to the second surface opposite to the first surface on which a compound semiconductor film is formed or the compound semiconductor film is to be formed.
  • Figure 1 is a flow chart of an example according to an embodiment of the present invention.
  • Figure 2 is a schematic view showing a measuring method according to the embodiment.
  • Figure 3 is a schematic view showing an evaluation method according to the embodiment.
  • Figure 4 is a schematic view showing a trajectory of relative movement of a blast iiozzle and a substrate at the time when blast processing according to the embodiment is performed.
  • Figure 5 is a schematic view showing a principle for correcting distortion of a wafer by the blast processing according to the embodiment.
  • Figure 6 is a flow chart showing a method according to another embodiment.
  • Figure 7 is a flow chart showing a method according to still another embodiment.
  • a method according to an embodiment of the present invention is a warp correction method using blast processing which is applied to a substrate made of a material, such as sapphire, at the time when light-emitting diode (LED) elements, and the like, are manufactured.
  • a warp is corrected by using blast processing which is applied to a substrate for semiconductor elements at the time when LED elements or LD elements are manufactured.
  • this method may include: a step of making a substrate; a step of performing a step of forming a compound semiconductor film on the substrate; a step of applying blast processing to the surface of the substrate, the surface being opposite to the mirror surface on which the compound semiconductor film is formed; and a step of forming LED electrodes or LD electrodes on the surface being opposite to the surface subjected to the blast processing and then cutting the substrate into LED elements or LD elements.
  • the LED element means, for example, an InGaN-based high luminance LED.
  • the other LED elements there are an AlGaNlnP-based high luminance LED, a GaP-based high luminance LED, a GaAs-based high luminance LED, and the like.
  • the LED means a light-emitting diode which emits light at the time when electricity is supplied thereto and which is used for large area illumination, and the like.
  • the LD means a laser diode which emits laser light at the time when electricity is thereto and which is used as a light source for communication and an optical disk.
  • the substrate means a substrate which is made by slicing an ingot of a single-crystal of sapphire, SiC, GaAS, GaP, GaAlAs, or the like, and which can be subjected to epitaxial growth.
  • This substrate is, for example, a substrate for semiconductor elements and has a first surface and a second surface opposite to the first surface.
  • a compound semiconductor film is formed on the first surface.
  • the second surface may have a surface roughness larger than the surface roughness of the first surface.
  • the both surfaces of the substrate may be polished.
  • the blast processing means processing in which a workpiece is processed in such a manner that a mixture of abrasive grains and compressed air is ejected as a solid-air two-phase flow by using a rectangular nozzle or a round nozzle, and that the grains of the solid-air two-phase flow are made to collide with the workpiece.
  • the workpiece was processed while being scanned (scan processing method).
  • the mirror surface of the sapphire substrate means a surface having surface roughness of about 1 to 5 A Ra.
  • the GaN-based compound semiconductor film means a film which is formed on the mirror surface side of the substrate by using a gas phase growth method or a liquid phase growth method.
  • Forming an LED electrode or an LD electrode means forming a transparent electrode, a pad electrode, a protective film, and the like, on the compound semiconductor film formed on the substrate. For example, a GaN-based compound semiconductor film is formed.
  • the element means an LED chip or an LED chip.
  • Cutting means cutting the substrate into chips having a standard size by using a method using a laser, a blade, or a blast, or the like.
  • Figure 1 shows a flow chart of a warp correction method using blast processing which is applied to a substrate at the time of manufacturing LED elements or LD elements.
  • the processing method includes: a step (S10) of making a substrate; a step (SI 2) of performing a step of forming a compound semiconductor film on the substrate; a step (SI 4) of applying blast processing to the surface opposite to the mirror surface on which the compound semiconductor film is formed; and a step (SI 6) of forming LED electrodes or LD electrodes on the surface being opposite to the surface which the blast processing is applied, and then cutting the substrate into LED elements or LD elements.
  • a step (S10) of making a substrate a step (SI 2) of performing a step of forming a compound semiconductor film on the substrate; a step (SI 4) of applying blast processing to the surface opposite to the mirror surface on which the compound semiconductor film is formed; and a step (SI 6) of forming LED electrodes or LD electrodes on the surface being opposite to the surface which the blast processing
  • a substrate is made (S10).
  • a substrate which is made of sapphire and which has a size of 4 inches and a thickness of 0.65 mm, is made.
  • a film is formed on the substrate (S12).
  • a GaN-based compound semiconductor film is formed.
  • a blast processing step is performed (S14).
  • the blast processing is performed, for example, under the following conditions (Table 1) in order to apply the blast processing to the entire surface of the substrate, the entire surface being opposite to the surface on which the GaN-based compound semiconductor film is formed.
  • the conditions shown in Table 1 represent, as an example, a case where a rectangular nozzle having a nozzle size of 15 mm x 4.8 mm is used. However, a round nozzle having a nozzle diameter of q>8 mm, or the like, may also be used. Further, the conditions shown in Table 1 represent, as an example, a case where the blast processing is applied to the entire surface of a sapphire substrate by using a scan processing method. Thereby, stress is applied to the entire wafer, so that the warp of the wafer is corrected. Note that, when the uniformity of surface roughness of the surface subjected to the blast processing is not needed, the blast processing needs not necessarily be applied to the entire wafer surface. For example, stress may also be applied by performing the ejection at a fixed portion, such as the center portion of the sapphire substrate.
  • a blasting machine for example, MICROBLASTER MB-1 (manufactured by Sintokogio, Ltd.) can be adopted.
  • a suction type flat nozzle that is a rectangular nozzle can be adopted as the nozzle for the blast processing.
  • the surface roughness (arithmetic average roughness Ra) of the surface subjected to the blast processing may be in a range of, for example, 0.01 to 5.0 um Ra, whereby, the warp can be corrected without significantly changing the surface roughness before and after the blast processing. Further, it may be more preferred that the surface roughness of the surface subjected to the blast processing is in a range of 0.5 to 5.0 ⁇ Ra. In order to obtain the surface roughness in the range of 0.5 to 5.0 um Ra, the blast processing may be performed, for example, under the blasting conditions shown in Table 2.
  • the abrasive is the material included the abrasive micro grain sizes of JIS (Japanese Industrial Standards) R6001.
  • the blasting conditions shown in Table 2 are examples.
  • the warp amount of the sapphire substrate is changed according to the size and thickness of the sapphire substrate and further according to the conditions under which the GaN-based compound semiconductor film is formed. For this reason, each of the blasting conditions may be arbitrarily changed according to the warp amount of the sapphire substrate to be corrected.
  • abrasive for example, an example, in which alumina abrasive grains expressed by a chemical formula of A1 2 0 3 are used as the abrasive, is shown in Table 2.
  • any material may be used as long as the material can give stress to the substrate.
  • the hardness of the material may also be suitably selected as long as the material having the selected hardness can apply give to the substrate.
  • the size of the abrasive preferably has an average particle diameter of 25 to 70 um.
  • the surface of the substrate is roughened.
  • the average particle diameter of the abrasive is less than 25 um, there is a possibility that, even when the ejection pressure is increased, since the collision energy of the grains applied to the substrate is insufficient, the warp of the substrate cannot be corrected to a desired curvature radius.
  • the ejection speed is determined by the kind of abrasive, the ejection pressure, the ejection amount, and the like.
  • the ejection pressure may be set in a range of 0.2 MPa to 0.4 MPa. In the case where the ejection pressure is more than 0.4 MPa, since the processing energy becomes excessive, breakage and cracks may occur in the substrate. In the case where the ejection pressure is less than 0.2 MPa, since stress applied to the substrate becomes small, the processing time required to correct the warp of the substrate may be increased. Further, the ejection amount may be set in a range of 100 g/min to 400 g/min.
  • the coverage is an indicator similar to the density of material ejected to the substrate, and is influenced by the kind of abrasive, the ejection amount, the ejection time, the nozzle traverse speed, the nozzle feed pitch, the ejection angle, and the like.
  • the abrasive may have an average particle diameter in a range of 25 um to 70 um.
  • the ejection pressure may be set in a range of 0.2 MPa to 0.5 MPa, and more preferably set in a range of 0.2 MPa to 0.4 MPa.
  • the ejection amount may be set in a range of 100 g/min to 400 g/min, and more preferably set in a range of 200 g/min to 400 g/min.
  • the blast processing can be performed at a high speed of about 20 seconds for one scan by using the above-described blasting machine.
  • both the sliced surfaces of the sapphire substrate may also be polished.
  • the surface roughness of the polished surfaces is, for example, as follows (Table 3).
  • the surface roughness in the table is as an example, and the surface roughness before the film formation can be changed according to the condition of the polishing step after the substrate is made by the slicing step, and according to the condition at the time when the GaN-based compound semiconductor film is formed.
  • the front and back surfaces of the substrate may have a difference in the surface roughness after the substrate is formed by the slicing step and is polished by the polishing step. This is because a surface subjected to mirror polishing is necessary to form a uniform and thin film at the time of epitaxial growth.
  • the back surface is subjected to a step referred to as BGP (Back Grinding Polish) to reduce the thickness of the substrate to about 0.1 mm, and hence the back surface of the substrate need not be polished to a mirror surface at the time of the polishing step after the substrate is made by the slicing step.
  • BGP Back Grinding Polish
  • a warp of the substrate can be corrected without giving damage to the mirror surface of the substrate which surface is subjected to epitaxial growth.
  • a difference in the surface roughness between the surface and the back surface of the substrate is provided beforehand, an advantage is obtained that a warp of the substrate can be corrected without giving damage to the mirror surface of the substrate which surface is subjected to epitaxial growth.
  • a surface roughness meter SURFCOM HOOD manufactured by Tokyo Seimitsu Co., Ltd.
  • An example of a measurement range is shown in Figure 2.
  • FIG 3 is a schematic view showing an evaluation method.
  • the warp amount Ah is a difference between a maximum height and a minimum height on the surface of the sapphire substrate.
  • the warp amount Ah is represented by a plus value when the surface is convex, while the warp amount Ah is represented by a minus value when the surface is concave.
  • the curvature radius R can be converted from the warp amount Ah.
  • the relationship between the curvature radius R and the warp amount Ah is shown in Figure 3. Note that the apparatus and method for measuring the surface roughness is not limited to those described above.
  • FIG. 4 is a schematic view showing a trajectory of relative movement between the blast nozzle and the substrate at the time of the blast processing according to the present invention.
  • a method may also be adopted in which the side of the suction jig for fixing the sapphire substrate is scanned, and in which the nozzle is fixed.
  • the blast processing may also be performed by performing the scanning operation in such a manner that the nozzle is moved along one axis while the suction jig is moved in the direction orthogonal to the moving direction of the nozzle.
  • any scanning means can be used only as long as the scan processing is applied to the sapphire wafer by moving the wafer and the nozzle relative to each other.
  • FIG. 5 is a schematic view showing a principle for correcting distortion of a wafer by the blast processing according to the embodiment. Note that, in the following, a case where the blast processing is applied after the formation of a GaN-based compound semiconductor film is described.
  • an abrasive F is ejected from a nozzle N to a sapphire wafer W which is warped due to the formation of a film of GaN-based compound semiconductor G
  • the warp of the sapphire wafer W warped due to the formation of the film of GaN-based compound semiconductor G is corrected in the state where the GaN-based compound semiconductor Gf is held on the sapphire wafer Wf.
  • Table 4 shows an example of measurement results when the abrasive, the ejection amount, the ejection pressure, and the warp amount after EPI step are changed.
  • Substrate 1 WA#600 200 0.3 83 32 36.8
  • alumina abrasive grains (White Alundum)
  • WA#240 to WA #600 manufactured by Sintokogio, Ltd.
  • alumina abrasive grains having an average particle diameter of 25 um to 70 ⁇ were used.
  • the abrasive is the material included the abrasive micro grain sizes of JIS (Japanese Industrial Standards) R6001.
  • an ejection pressure of 0.3 MPa to 0.5 MPa was used.
  • the warp amount in an area of 97 mm x 97 mm of a 4-inch ( ⁇ mm) substrate (wafer) W after the EPI step was varied in a range of 83 um to 210 um. However, after the blast processing, the warp amount was corrected to 40 um or less (35 um to 20 um). Note that the curvature radius converted from the warp amount was 30 m or more. Further, in the case where the inch size of the wafer is increased in future, the warp amount of a wafer as a whole may become 40 um or more.
  • the warp amount is acceptable as long as, when the warp amount is converted to a warp amount of the 4-inch ( ⁇ mm) wafer, the converted warp amount is 40 um or less. In this range of the warp amount, there is an advantage that, in the subsequent process, the yield in laser processing for cutting the substrate into chips is improved.
  • the processing is shifted to the electrode forming step (SI 6).
  • the electrode forming step a transparent electrode, a pad electrode, a protective film, and the like, are formed on the compound semiconductor film formed on the wafer.
  • the processing is shifted to the element cutting step (SI 8).
  • the element cutting step the substrate is cut into chips having a standard size.
  • the warp caused at the time of the formation of the GaN-based compound semiconductor film can be corrected by performing the blast processing after the formation of the GaN-based compound semiconductor film.
  • the embodiment described above shows an example of the processing method according to the present invention.
  • the processing method according to the present invention is not limited to the processing method according to the above-described embodiment.
  • the blast processing is performed before the formation of the compound semiconductor film, it is also possible to correct a warp caused at the time of the formation of the GaN-based compound semiconductor film.
  • the flow chart of this example is shown in Figure 6.
  • the flow chart shown in Figure 6 is substantially the same as the flow chart shown in Figure 1, and the processing of each of S20, S26 and S28 corresponds to the processing of each of S10, S16 and SI 8. That is, in Figure 6, the film forming step (S24) is performed after the blast processing step (S22).
  • the blast processing is performed before the formation of the GaN-based compound semiconductor film
  • the phenomenon, in which the mirror surface side of the substrate is warped into a convex shape at the time of the formation of the GaN-based compound semiconductor film can be offset by forming beforehand the mirror surface side of the substrate in a concave shape.
  • film formation variation may occur depending on the way of heating by a heat source at the time of the formation of the GaN-based compound semiconductor film. Therefore, it is preferred that the blast processing is performed after the formation of the
  • GaN-based compound semiconductor film GaN-based compound semiconductor film.
  • the manufacturing process in which LED elements or LD elements are manufactured, is designed such that the blast processing is performed before or after the GaN-based compound semiconductor film is formed on the substrate.
  • the curvature radius of a warp of the substrate caused at the time of the formation of the GaN-based compound semiconductor film can be increased to 30 m or more.
  • FIG. 7 shows an example of the processing method in which the washing step is added.
  • the flow chart shown in Figure 7 is substantially the same as the flow chart shown in Figure 1, and the processing of S30 corresponds to the processing of S10 in Figure 1. Further, the processing of S36 to S40 corresponds to the processing of S12 to S16 in Figure 1, and the processing of S46 corresponds to the processing of S 18 in Figure 1. That is, the polishing process (S32 and S42) and the washing process (S34 and S44) are included in Figure 7.
  • the blast processing is performed while the surface roughness is measured, and that the measured result is fed back to the blast processing.
  • the measurement of the surface roughness need not be necessarily performed for all the substrates. When the processing conditions are determined, the measurement of the surface roughness is unnecessary in the ordinary step.
  • a warp of a substrate can be corrected at the time of manufacturing LED elements and LD elements, whereby in the subsequent process for cutting the substrate into respective elements by using a laser, it is possible to eliminate cutting failure due to focusing failure that is caused when the substrate is warped.
  • the blast processing is applied, by changing the blast processing conditions, to the surface opposite to the surface on which a GaN-based compound semiconductor film is formed.
  • the blasted surface of the substrate can be processed to have any surface roughness.
  • the light diffusion property can be improved in correspondence with the wavelength of light emitted from the LED or the LD.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

La présente invention vise à fournir un procédé de traitement d'un substrat pour éléments semi-conducteurs, destiné à appliquer un traitement de soufflage à un substrat ayant une première surface et une seconde surface opposée à la première surface. Le procédé de traitement comprend une étape d'application d'un traitement de soufflage à la seconde surface opposée à la première surface, sur laquelle un film semi-conducteur de composé est formé ou est à former.
PCT/JP2012/051899 2011-07-21 2012-01-23 Procédé de traitement d'un substrat pour éléments semi-conducteurs WO2013011705A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2013532763A JP5716834B2 (ja) 2011-07-21 2012-01-23 半導体素子用基板の処理方法
KR1020137029494A KR101883520B1 (ko) 2011-07-21 2012-01-23 반도체 소자용 기판의 처리 방법
CN201280013566.7A CN103430281B (zh) 2011-07-21 2012-01-23 用于半导体元件的基板的处理方法

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JP2011160113 2011-07-21
JP2011-160113 2011-07-21

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WO2013011705A1 true WO2013011705A1 (fr) 2013-01-24

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KR (1) KR101883520B1 (fr)
CN (1) CN103430281B (fr)
TW (1) TWI545623B (fr)
WO (1) WO2013011705A1 (fr)

Cited By (1)

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US9947571B2 (en) 2014-11-14 2018-04-17 Kabushiki Kaisha Toshiba Processing apparatus, nozzle, and dicing apparatus

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103909475A (zh) * 2014-04-02 2014-07-09 天通控股股份有限公司 一种大尺寸蓝宝石衬底片背面粗糙度的干式加工方法
JP2016134433A (ja) * 2015-01-16 2016-07-25 株式会社東芝 ダイシング装置
CN105810578B (zh) * 2016-03-18 2019-01-18 成都海威华芯科技有限公司 化合物半导体基材的表面处理方法及外延结构
CN109015394A (zh) * 2018-08-10 2018-12-18 天通控股股份有限公司 一种大尺寸钽酸锂衬底片背面粗糙度的干式加工方法
CN112740551B (zh) * 2018-09-25 2025-01-24 京瓷株式会社 复合基板、压电元件以及复合基板的制造方法
JP7259773B2 (ja) * 2020-01-14 2023-04-18 新東工業株式会社 ブラスト加工装置及びブラスト加工方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4820650A (en) * 1986-11-14 1989-04-11 Mitsubishi Denki Kabushiki Kaisha Introducing lattice defect with ice particles in semiconductor wafer
EP0525455A2 (fr) * 1991-07-19 1993-02-03 Shin-Etsu Handotai Company Limited Piégeage extrinsèque pour un substrat semi-conducteur
EP1139424A2 (fr) * 2000-03-31 2001-10-04 Sharp Kabushiki Kaisha Dispositif semi-conducteur et procéde de fabrication associée
JP2003300800A (ja) * 1998-09-30 2003-10-21 Nec Corp Ｉｉｉ族元素窒化物半導体ウェーハの製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63124534A (ja) * 1986-11-14 1988-05-28 Mitsubishi Electric Corp 半導体装置におけるゲツタリング方法
JPH07114207B2 (ja) * 1991-07-19 1995-12-06 信越半導体株式会社 半導体基板及びその製造方法
JP2001344710A (ja) * 2000-06-05 2001-12-14 Tdk Corp ウエハの平面度制御方法及び薄膜磁気ヘッドの製造方法
JP2003128499A (ja) 2001-10-18 2003-05-08 Hitachi Cable Ltd 窒化物結晶基板の製造方法及び窒化物結晶基板
JP2004165226A (ja) 2002-11-08 2004-06-10 Toyoda Gosei Co Ltd Ｉｉｉ族窒化物系化合物半導体発光素子の製造方法
JP4232605B2 (ja) * 2003-10-30 2009-03-04 住友電気工業株式会社 窒化物半導体基板の製造方法と窒化物半導体基板
KR100894064B1 (ko) * 2007-09-03 2009-04-21 삼성에스디아이 주식회사 전자 방출 촉진 물질-함유 ＭｇＯ 보호막, 이의 제조 방법및 상기 보호막을 구비한 플라즈마 디스플레이 패널
JP4965479B2 (ja) * 2008-02-15 2012-07-04 株式会社アルバック スパッタリングターゲットの製造方法及びスパッタリングターゲットの洗浄方法
JP2010205888A (ja) * 2009-03-03 2010-09-16 Toppan Printing Co Ltd 半導体装置
JP2011222608A (ja) * 2010-04-06 2011-11-04 Okamoto Machine Tool Works Ltd 半導体基板の薄肉研削方法およびそれに用いる半導体基板の薄肉研削加工装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4820650A (en) * 1986-11-14 1989-04-11 Mitsubishi Denki Kabushiki Kaisha Introducing lattice defect with ice particles in semiconductor wafer
EP0525455A2 (fr) * 1991-07-19 1993-02-03 Shin-Etsu Handotai Company Limited Piégeage extrinsèque pour un substrat semi-conducteur
JP2003300800A (ja) * 1998-09-30 2003-10-21 Nec Corp Ｉｉｉ族元素窒化物半導体ウェーハの製造方法
EP1139424A2 (fr) * 2000-03-31 2001-10-04 Sharp Kabushiki Kaisha Dispositif semi-conducteur et procéde de fabrication associée

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
DUBOTZKY A ET AL: "Evaluation of alternative preparation methods for failure analysis at modern chip- and package technologies", PROCEEDINGS OF INTERNATIONAL SYMPOSIUM FOR TESTING AND FAILURE ANALYSIS 11-15 NOV. 2001 SANTA CLARA, CA, USA, 1 January 2001 (2001-01-01), ISTFA 2001. Proceedings of the 27th International Symposium for Testing and Failure Analysis ASM Int. Materials Park, OH, USA, pages 83 - 86, XP002675679, ISBN: 0-87170-746-2 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9947571B2 (en) 2014-11-14 2018-04-17 Kabushiki Kaisha Toshiba Processing apparatus, nozzle, and dicing apparatus

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