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WO2013065569A1 - Élément d'imagerie à semi-conducteurs, procédé de fabrication d'un élément d'imagerie à semi-conducteurs, et dispositif électronique - Google Patents

Élément d'imagerie à semi-conducteurs, procédé de fabrication d'un élément d'imagerie à semi-conducteurs, et dispositif électronique Download PDF

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Publication number
WO2013065569A1
WO2013065569A1 PCT/JP2012/077580 JP2012077580W WO2013065569A1 WO 2013065569 A1 WO2013065569 A1 WO 2013065569A1 JP 2012077580 W JP2012077580 W JP 2012077580W WO 2013065569 A1 WO2013065569 A1 WO 2013065569A1
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Prior art keywords
semiconductor substrate
solid
state imaging
light shielding
imaging device
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PCT/JP2012/077580
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English (en)
Japanese (ja)
Inventor
秀晃 富樫
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ソニー株式会社
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Publication of WO2013065569A1 publication Critical patent/WO2013065569A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
    • H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
    • H10F30/21—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation
    • H10F30/22—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes
    • H10F30/221—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier being a PN homojunction
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/199—Back-illuminated image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/805—Coatings
    • H10F39/8057—Optical shielding

Definitions

  • the present technology relates to a solid-state imaging device, a manufacturing method of the solid-state imaging device, and an electronic device.
  • the present invention relates to a solid-state imaging device having a global shutter function, a manufacturing method of the solid-state imaging device, and an electronic apparatus.
  • a CMOS (Complementary Metal Oxide Semiconductor) image sensor generally accumulates a photoelectrically converted charge in a photodiode from the time a signal is output. Since the signals of the CMOS image sensor are read by sequentially scanning the photodiode array, the accumulation period is shifted for each photodiode. For this reason, when a fast-moving subject is imaged with a CMOS image sensor, the image is distorted.
  • CMOS Complementary Metal Oxide Semiconductor
  • CMOS image sensor there is a global shutter structure in which an analog memory is formed in a pixel as one method for realizing the simultaneous charge accumulation.
  • the global shutter structure includes an analog memory for each photodiode. By simultaneously transferring charges from the photodiode to the analog memory in the entire image pickup device array, simultaneous charge accumulation can be realized.
  • this analog memory needs to be covered with a light shielding layer so that new signal charges are not generated by photoelectric conversion.
  • One method for realizing high sensitivity in a CMOS image sensor is a backside illumination type structure.
  • the back-illuminated CIS light is incident from the back side of the semiconductor substrate that is not affected by the wiring on the pixel and the pixel transistor, so that the opening of the photodiode can be maximized. For this reason, the amount of light incident on the photodiode is increased, and the sensitivity is improved as compared with the surface-illuminated imaging device.
  • a global shutter structure is formed in the backside illuminated CMOS image sensor to achieve high sensitivity.
  • backside illumination CIS having a global shutter structure. This is because, when the global shutter structure is formed in the back-illuminated CIS, it is very difficult to sufficiently shield the analog memory from light incident from the back side, particularly light incident from an oblique direction. If the light shielding is performed effectively, the opening is inevitably narrowed and the sensitivity is lowered, so that the advantages of the back-illuminated CIS cannot be utilized.
  • Patent Document 1 In order to realize a global shutter structure in the back-illuminated CIS, a structure in which a light shielding layer is formed in a semiconductor substrate has been proposed (for example, see Patent Document 1).
  • a photodiode (PD) is formed in a semiconductor substrate
  • a light shielding film is formed on the semiconductor substrate.
  • a semiconductor layer is formed by epitaxial growth on the surface of the semiconductor substrate on which the light shielding film is formed, and various transistors including analog memory are formed in the epitaxial growth layer.
  • the present technology provides a solid-state imaging device having a global shutter function and capable of suppressing white spots and dark current, a manufacturing method of the solid-state imaging device, and an electronic apparatus.
  • the solid-state imaging device of the present technology includes a semiconductor substrate, a photodiode formed on the semiconductor substrate, and a floating diffusion region to which signal charges accumulated in the photodiode are transferred. Further, the semiconductor substrate includes a horizontal light shielding portion parallel to the semiconductor substrate surface covering the floating diffusion region and a light shielding layer including a vertical light shielding portion perpendicular to the semiconductor substrate surface. Moreover, the electronic device of this technique is provided with the said solid-state image sensor and the signal processing circuit which processes the output signal of a solid-state image sensor.
  • the method for manufacturing a solid-state imaging device of the present technology includes a step of forming a photodiode on a semiconductor substrate and a step of forming a floating diffusion region to which signal charges accumulated in the photodiode are transferred on the semiconductor substrate. Then, a step of forming a cavity for forming a horizontal light-shielding portion parallel to the semiconductor substrate surface and a vertical light-shielding portion perpendicular to the semiconductor substrate surface in the semiconductor substrate, and filling the cavity with a light-shielding material Forming a layer.
  • the light shielding layer is formed in the floating diffusion region where the signal charge is held.
  • a cavity is formed in the semiconductor substrate, and the light shielding layer is formed by embedding the cavity. For this reason, a light shielding layer is formed in the semiconductor substrate.
  • the light-shielding layer is not embedded by an epitaxial growth layer or the like, a charge transfer path output from the photodiode is formed in the semiconductor substrate. Therefore, no dark current is generated due to crystal defects such as an epitaxial growth layer.
  • a white spot and dark current can be suppressed, and a solid-state imaging device having a global shutter function, a method for manufacturing the solid-state imaging device, and an electronic apparatus can be provided.
  • FIG. 4 is a cross-sectional view taken along line AA of the pixel portion of the solid-state imaging device shown in FIG. A and B are diagrams showing the configuration of the light shielding layer.
  • A is a top view which shows the structure by the side of the surface of the pixel part of the solid-state image sensor of the modification of 4th Embodiment.
  • B is a cross-sectional view taken along line AA of the pixel portion of the solid-state imaging device shown in A of FIG.
  • A is a top view which shows the structure by the side of the surface of the pixel part of the solid-state image sensor of the modification of 4th Embodiment.
  • B is a cross-sectional view taken along line AA of the pixel portion of the solid-state imaging device shown in A of FIG. It is sectional drawing which shows the structure of the pixel part of the solid-state image sensor of 5th Embodiment.
  • a to C are manufacturing process diagrams illustrating a first embodiment of a method for manufacturing a solid-state imaging device.
  • D to F are manufacturing process diagrams illustrating a first embodiment of a method for manufacturing a solid-state imaging device.
  • GI are manufacturing process diagrams showing a first embodiment of a method for manufacturing a solid-state imaging device.
  • J to L are manufacturing process diagrams illustrating a first embodiment of a method for manufacturing a solid-state imaging device.
  • FIGS. 8A to 8C are manufacturing process diagrams illustrating a modification of the first embodiment of the method for manufacturing a solid-state imaging device.
  • DF are manufacturing process diagrams showing a modification of the first embodiment of the manufacturing method of the solid-state imaging device.
  • FIGS. 9A to 9C are manufacturing process diagrams illustrating a second embodiment of a method for manufacturing a solid-state imaging device.
  • FIGS. DF are manufacturing process diagrams illustrating a second embodiment of a method for manufacturing a solid-state imaging device.
  • GI are manufacturing process diagrams showing a second embodiment of a method for manufacturing a solid-state imaging device. It is a figure which shows the structure of an electronic device.
  • FIG. 1 shows a schematic configuration diagram of a three-dimensional MOS (Metal Oxide Semiconductor) type solid-state image pickup device as an example of a back-illuminated solid-state image pickup device.
  • a solid-state imaging device 10 illustrated in FIG. 1 includes a sensor substrate 11 on which photoelectric conversion units are arranged and a circuit substrate 21 that is bonded to the sensor substrate 11 in a stacked state.
  • the sensor substrate 11 includes a pixel region 14 in which one surface is a light receiving surface A and a plurality of pixels 13 including a photoelectric conversion unit are two-dimensionally arranged with respect to the light receiving surface A.
  • a plurality of pixel drive lines 15 are wired in the row direction
  • a plurality of vertical signal lines 16 are wired in the column direction
  • one pixel 13 includes one pixel drive line 15 and one pixel drive line 15. They are arranged in a state of being connected to the vertical signal line 16.
  • Each of these pixels 13 is provided with a photoelectric conversion unit, a charge storage unit, and a pixel circuit composed of a plurality of transistors (so-called MOS transistors) and a capacitor element.
  • MOS transistors a plurality of transistors
  • a part of the pixel circuit is provided on the surface side opposite to the light receiving surface A.
  • a part of the pixel circuit may be shared by a plurality of pixels.
  • the sensor substrate 11 includes a peripheral region 17 outside the pixel region 14.
  • a wiring 18 including an electrode pad is provided in the peripheral region 17.
  • the wiring 18 is connected to the pixel drive line 15 and the vertical signal line 16 provided on the sensor substrate 11 and the pixel circuit, and further to the drive circuit provided on the circuit board 21 as necessary.
  • the circuit board 21 has a vertical drive circuit 22, a column signal processing circuit 23, a horizontal drive circuit 24, and a system control circuit for driving each pixel 13 provided on the sensor board 11 on one side facing the sensor board 11 side. 25 etc. are provided. These drive circuits are connected to the wiring 18 on the sensor substrate 11 side. Note that the pixel circuit provided on the front surface side of the sensor substrate 11 is also a part of the drive circuit.
  • FIG. 2 shows a cross-sectional view of a main part constituting one pixel of the solid-state imaging device of the present embodiment.
  • a photodiode (PD) 32 is formed from a light incident surface (back surface of the substrate) 31 ⁇ / b> A of the semiconductor substrate 31.
  • the solid-state imaging device 30 includes a first transistor (Tr1) and a second transistor (Tr2) on the side opposite to the light incident surface (base surface) 31B.
  • the first transistor Tr1 includes a PD 32, a first gate electrode 34 formed through the gate insulating film 33, and a first floating diffusion region 35 for accumulating signal charges transferred from the PD 32.
  • the second transistor Tr2 includes a second gate electrode 36 formed via the gate insulating film 33, a first floating diffusion region 35 shared with the first transistor Tr1, and a second floating diffusion region 37.
  • the PD 32 includes a first conductivity type (p-type) semiconductor region 32A and a second conductivity type (n-type) semiconductor region 32B from the back surface 31A side in a region formed in the first conductivity type of the semiconductor substrate 31.
  • the p-type semiconductor region 32A is formed on the surface of the semiconductor substrate 31 on the back surface 31A side.
  • the n-type semiconductor region 32B is formed in contact with the p-type semiconductor region 32A, and a part thereof is continuously formed up to the surface 31B side of the semiconductor substrate 31.
  • a vertical gate of the first gate electrode 34 is formed through a gate insulating film 33 in a region protruding to the surface 31B side of the n-type semiconductor region 32B.
  • the vertical gate of the first gate electrode 34 is formed by filling a trench formed from the surface 31 ⁇ / b> B side of the semiconductor substrate 31.
  • Tr1 a potential (potential) immediately below the first gate electrode 34 is changed by applying a positive voltage to the first gate electrode 34 at the time of reading. Then, the signal charge accumulated in the PD 32 passes through a region around the vertical gate of the first gate electrode 34 and is transferred to the first floating diffusion region 35. In Tr2, a positive voltage is applied to the second gate electrode 36, whereby the potential (potential) immediately below the second gate electrode 36 changes. Then, the signal charge accumulated in the first floating diffusion region 35 passes under the second gate electrode 36 and is transferred to the second floating diffusion region 37.
  • signal charges are read from the PD 32 to the first floating diffusion region 35 simultaneously in all the pixels in the imaging region.
  • the photodiode array is sequentially scanned, and signal charges are transferred from the first floating diffusion region 35 to the second floating diffusion region 37.
  • the first floating diffusion region 35 functions as an analog memory (storage unit) until it is transferred to the second floating diffusion region 37.
  • the second floating diffusion region 37 functions as a charge detection unit (floating diffusion FD) for signal charges transferred from the first floating diffusion region 35.
  • the signal charge transferred from the PD 32 is held in the analog memory, so that the global shutter function is given to the solid-state imaging device 30.
  • the solid-state imaging device 30 includes a light shielding layer 38 that covers the light incident surface side of the first floating diffusion region 35 so that a new signal charge due to photoelectric conversion is not generated in the analog memory that holds the signal charge.
  • the light shielding layer 38 includes a horizontal light shielding portion 38A that extends in a direction parallel to the main surface of the semiconductor substrate 31, and a vertical light shielding portion 38B that extends in a direction perpendicular to the main surface of the semiconductor substrate 31.
  • the horizontal light shielding portion 38 ⁇ / b> A is embedded in the semiconductor substrate 31.
  • the vertical light shielding portion 38B is formed from the back surface 31A side of the semiconductor substrate 31 to a depth connecting to the horizontal light shielding portion 38A.
  • the horizontal light shielding portion 38A needs to be provided in the semiconductor substrate 31 at a position that covers at least the first floating diffusion region 35 and does not allow incident light to enter the analog memory.
  • the horizontal light shielding portion 38A has a length of a flat portion in a direction orthogonal to the vertical light shielding portion 38B of 5 ⁇ m or less.
  • the aspect ratio of the vertical light shielding part 38B and the horizontal light shielding part 38A is preferably 0.5 or less.
  • the light shielding layer 38 moves the horizontal light shielding portion 38A as close as possible to the first floating diffusion region 35 so that light that has entered the periphery and side surfaces of the horizontal light shielding portion 38A does not easily enter the first floating diffusion region 35. It is preferable to form.
  • a PD 32 can be formed in a region from the back surface 31A of the semiconductor substrate 31 to the horizontal light shielding portion 38A.
  • a first conductivity type (p-type) semiconductor region 39 is formed around the light shielding layer 38.
  • the PD 32 and the light shielding layer 38 are separated by the p-type semiconductor region 39.
  • the light shielding layer 38 is a material generally used as an insulating material in a semiconductor device such as SiO 2 or Si 3 N 4 , a metal material such as aluminum, tungsten, titanium, cobalt, hafnium, and tantalum, or It is made of a light shielding material selected from organic materials such as graphite and resist materials.
  • a metal material such as aluminum, tungsten, titanium, cobalt, hafnium, and tantalum
  • It is made of a light shielding material selected from organic materials such as graphite and resist materials.
  • the insulating layer is an oxide insulating film such as hafnium, aluminum, tantalum, titanium, or lanthanum, and other insulating films having a negative fixed charge can also be used.
  • the vertical light shielding portion 38B is formed of a conductive material, a wiring or the like (not shown) is connected to the light shielding layer. Then, it is electrically connected to an external circuit, and the light shielding layer 38 is configured to be able to apply a voltage.
  • a conductive layer is embedded in a semiconductor substrate, unnecessary charges are generated from the interface between the semiconductor layer and the conductive layer due to charging of the conductive layer.
  • charge transfer can be assisted by applying a positive voltage optimized to the light shielding layer 38 during charge transfer from the PD 32 to the first floating diffusion region 35.
  • FIG. 3 shows a positional relationship in the plane of the PD 32, Tr1, Tr2, and the light shielding layer 38 in the solid-state imaging device 30 described above.
  • 3A is a plan view showing the surface 31B side of the solid-state imaging device 30.
  • FIG. 3B is a plan view showing the back side of the solid-state imaging device 30.
  • FIG. 4 is a cross-sectional view of the solid-state imaging device shown in FIG.
  • FIG. 3A and 3B show an area corresponding to 8 pixels of the solid-state imaging device 30.
  • the first gate electrode 34, the PD 32, and the first floating diffusion region (analog memory) 35 corresponding to the PD 32, which constitute the Tr 1, are formed.
  • the second floating diffusion region (charge detection unit) 37 constituting the Tr2 is formed in common with the adjacent four pixels.
  • the horizontal light-shielding portion 38A is formed at a position that covers the first floating diffusion regions 35 of the four adjacent pixels. As described above, the horizontal light shielding portion 38A can be formed in common in adjacent pixels. At this time, in the solid-state imaging device 30 having the configuration shown in FIG. 3, the four pixels sharing the second floating diffusion region 37 and the four pixels having the horizontal light-shielding portion 38A formed in common are the pixel positions. Are different. In the configuration shown in FIG. 4, the pixels at positions shifted by one row are supplied and shared. Note that the pixel sharing the second floating diffusion region 37 and the pixel having the horizontal light shielding portion 38A formed in common may be at the same position.
  • the vertical light-shielding portion 38B is formed in a region where a photodiode is not formed, for example, a region between adjacent pixels. For this reason, the formation of the light shielding layer 38 does not affect the PD formation region of the solid-state imaging device 30 and does not limit the size of the opening. For this reason, there is no deterioration of the sensitivity characteristic of the solid-state imaging device 30.
  • the vertical light-shielding portion 38B is continuously formed in the direction along the side in contact with the adjacent pixel between the adjacent four pixels.
  • the vertical light shielding part 38B is formed from the back surface 31A side of the semiconductor substrate 31 to the depth of the horizontal light shielding part 38A.
  • the light shielding layer 38 functions as a pixel separation unit. For this reason, the PD 32 of each pixel is separated by the vertical light shielding portion 38B, and color mixing and blooming between adjacent pixels can be suppressed.
  • the configuration of the light shielding layer is as long as it includes a horizontal light shielding portion configured to shield the analog memory and a vertical light shielding portion connected to the horizontal light shielding portion from one main surface side of the semiconductor substrate. It is good also as another structure not only the structure of description in (4).
  • the end of the horizontal light-shielding portion can be bent to the analog memory side.
  • light that circulates from the horizontal direction with respect to the light shielding layer 38 can be blocked by the end portion of the horizontal light shielding portion, and therefore has higher light shielding performance than the light shielding layer 38 having the configuration shown in FIGS.
  • the vertical light shielding part 38B may be configured to penetrate the horizontal light shielding part.
  • the shape of the horizontal light-shielding portion 38A is a substantially square shape with corners cut off, but it may be constituted by other polygons, circles, etc., for example. Further, it is sufficient that the analog memory can be shielded, and it is not necessary to shield the charge detection unit. However, by forming the horizontal light shielding unit 38A widely under the PD 32, more effects as a reflector can be obtained. Furthermore, the vertical light-shielding portion 38B only needs to be formed between the pixels, and the shape is not limited to the lattice configuration shown in FIG. 3, but may be configured in a polygonal shape, a circular shape, or the like in accordance with the shape of the PD. Good.
  • a vertical or light-shielding portion 38B is configured by forming circular or polygonal vias from the back surface 31A of the semiconductor substrate 31 to the horizontal light-shielding portion 38A between the pixels. Also good.
  • one first floating diffusion region 35 serving as an analog memory is formed for one PD 32.
  • a plurality of analog memories may be formed for one PD 32.
  • a plurality of floating scattering regions may be stacked in the vertical direction.
  • a plurality of transfer gate electrodes from the PD 32 to the analog memory can be provided.
  • these analog memories can be selected and used according to the operation mode of the solid-state imaging device 30. Further, signal charges may be transferred between analog memories.
  • the analog memory in the back-illuminated solid-state imaging device, can be effectively shielded by forming the light shielding layers in the horizontal direction and the vertical direction inside the semiconductor substrate. .
  • a solid-state imaging device having a global shutter structure with a large photodiode aperture and high sensitivity can be configured.
  • the light shielding layer can be connected to an external device so that a voltage can be applied. For this reason, it is possible to prevent the dark current generated near the interface between the semiconductor substrate and the light shielding layer from entering the photodiode or the analog memory. Therefore, it is possible to reduce the dark current of the solid-state image sensor.
  • FIG. 6 shows a cross-sectional view of a main part constituting one pixel of the solid-state imaging device of the second embodiment.
  • a first photodiode (PD) 42 and a second photodiode (PD) 43 are formed from the light incident surface (substrate back surface) 41 ⁇ / b> A side of the semiconductor substrate 41.
  • the solid-state imaging device 40 includes a photoelectric conversion film 44 on the incident surface of the semiconductor substrate 41.
  • the solid-state imaging device 40 has a configuration in which two photodiodes 42 and 43 are stacked in a direction (longitudinal direction) perpendicular to the main surface of the semiconductor substrate surface, and further includes a photoelectric conversion film 44.
  • the short wavelength component of the received light is photoelectrically converted by the PD 42
  • the long wavelength component is photoelectrically converted by the PD 43
  • the intermediate wavelength component is photoelectrically converted by the photoelectric conversion film 44. it can.
  • the PD 42 is formed in contact with the p-type semiconductor region and the first conductivity-type (p-type) semiconductor region formed on the surface of the back surface 41A in the region formed in the first conductivity type of the semiconductor substrate 41.
  • the PD 43 includes a first conductivity type (p-type) semiconductor region and a second conductivity type (n-type) semiconductor region formed below (above the drawing) the PD 42. A part of the n-type semiconductor region of the PD 43 is continuously formed up to the surface 41 ⁇ / b> B side of the semiconductor substrate 41.
  • the photoelectric conversion film 44 is provided between the transparent electrode 54 provided on the light incident surface side and the transparent electrode 55 provided on the semiconductor substrate 41 side on the light incident surface side of the semiconductor substrate 41. Yes.
  • the transparent electrode 54 is connected via an electrode 57 to a second conductivity type (n-type) semiconductor region 56 formed continuously from the front surface 41B side to the back surface 41A side of the semiconductor substrate 41.
  • the n-type semiconductor region 56 is connected to an external device on the surface 41 ⁇ / b> B of the semiconductor substrate 41.
  • the transparent electrode 55 is connected to the second conductivity type (n-type) semiconductor region 59 through the electrode 58.
  • the signal charges generated in the photoelectric conversion film 44 are output from the transparent electrode 55 to the n-type semiconductor region 59.
  • the n-type semiconductor region 59 becomes a charge storage region for signal charges photoelectrically converted by the photoelectric conversion film 44.
  • the solid-state imaging device 40 includes first to sixth transistors (Tr1 to 6) for charge transfer on the surface opposite to the light incident surface (substrate surface) 31B.
  • the first transistor Tr1 and the second transistor Tr2 are transistors that transfer signal charges photoelectrically converted by the PD.
  • the third transistor Tr3 and the fourth transistor Tr4 transfer the charge photoelectrically converted by the PD 43.
  • the fifth transistor Tr5 and the sixth transistor Tr6 transfer the signal charge photoelectrically converted by the photoelectric conversion film 44.
  • the first transistor Tr1 includes a first PD 42, a vertical first gate electrode 45 formed through a gate insulating film 46, and a first floating diffusion region 47 that accumulates signal charges transferred from the first PD 42. Become.
  • the first gate electrode 45 is formed up to a position where the end of the vertical gate contacts the n-type semiconductor region of the first PD 42.
  • the second transistor Tr2 includes a second gate electrode 48 formed via the gate insulating film 46, a first floating diffusion region 47 shared with the first transistor Tr1, and a second floating diffusion region 49.
  • Tr1 a potential (potential) around the first gate electrode 45 formed to the deep part of the semiconductor substrate 41 is changed by applying a positive voltage to the first gate electrode 45 at the time of reading. Then, the signal charge accumulated in the PD 42 on the front surface 41 ⁇ / b> A side of the semiconductor substrate 41 passes through a region around the vertical gate of the first gate electrode 45 and is transferred to the first floating diffusion region 47.
  • Tr 2 a positive voltage is applied to the second gate electrode 48, thereby changing the potential (potential) immediately below the second gate electrode 48. Then, the signal charge accumulated in the first floating diffusion region 47 passes under the second gate electrode 48 and is transferred to the second floating diffusion region 49.
  • the signal charge accumulated in the first floating diffusion region 47 functions as an analog memory until it is transferred to the second floating diffusion region 49.
  • the second floating diffusion region 49 functions as a charge detection unit (floating diffusion FD) for signal charges transferred from the first floating diffusion region 47.
  • floating diffusion FD charge detection unit
  • the third transistor Tr3 includes a third gate electrode 50 formed through the gate insulating film 46, a second PD 43, and a third floating diffusion region 51 for accumulating signal charges transferred from the second PD 43.
  • the fourth transistor Tr4 includes a fourth gate electrode 52 formed through the gate insulating film 46, a third floating diffusion region 51 shared with the third transistor Tr3, and a fourth floating diffusion region 53. Also in Tr3 and Tr4, the signal charge transferred from the PD 43 is held in the third floating diffusion region 51 (analog memory) when simultaneously reading out the signal charge in all the pixels in the imaging region.
  • the fourth floating diffusion region 53 functions as a charge detection unit (floating diffusion FD) for signal charges transferred from the third floating diffusion region 51.
  • Tr5 is transferred from the fifth gate electrode 60 formed through the gate insulating film 46, the n-type semiconductor region 59 in which the signal charges photoelectrically converted by the photoelectric conversion film 44 are accumulated, and the n-type semiconductor region 59. And a fifth floating diffusion region 61 for storing the signal charges.
  • the sixth transistor Tr6 includes a sixth gate electrode 62 formed through the gate insulating film 46, a fifth floating diffusion region 61 shared with the third transistor Tr5, and a sixth floating diffusion region 63. Also in Tr5 and Tr6, when signal charges are read simultaneously in all the pixels in the imaging region, the signal charges photoelectrically converted by the photoelectric conversion film 44 accumulated in the n-type semiconductor region 59 are in the fifth floating diffusion region. 61 (analog memory).
  • the sixth floating diffusion region 63 functions as a charge detection unit (floating diffusion FD) for signal charges transferred from the fifth floating diffusion region 61.
  • the first floating diffusion region 47 functioning as an analog memory includes a first light shielding layer 64 that covers the light incident surface side of the first floating diffusion region 47 so that a new signal charge is not generated by photoelectric conversion.
  • the first light shielding layer 64 includes a horizontal light shielding portion 64A that extends in a direction parallel to the main surface of the semiconductor substrate 41, and a vertical light shielding portion 64B that extends in a direction perpendicular to the main surface of the semiconductor substrate surface.
  • the horizontal light shielding portion 64 ⁇ / b> A is embedded in the semiconductor substrate 41 so as to cover the first floating diffusion region 47.
  • the vertical light shielding portion 64B is formed from the back surface 41A side of the semiconductor substrate 41 to a depth connecting to the horizontal light shielding portion 64A.
  • the third floating diffusion region 51 and the fifth floating diffusion region 61 functioning as an analog memory are respectively provided with a second light shielding layer 65 and a third light shielding layer 66.
  • the second light shielding layer 65 includes a horizontal light shielding portion 65A that extends in a direction parallel to the main surface of the semiconductor substrate 41, and a vertical light shielding portion 65B that extends in a direction perpendicular to the main surface of the semiconductor substrate 41.
  • the horizontal light shielding portion 65A is formed in a range that covers the third floating diffusion region 51 so that light does not enter the analog memory.
  • the third light shielding layer 66 includes a horizontal light shielding portion 66A that extends in a direction parallel to the main surface of the semiconductor substrate 41, and a vertical light shielding portion 66B that extends in a direction perpendicular to the main surface of the semiconductor substrate 41.
  • the horizontal light shielding portion 66A is formed in a range that covers the fifth floating diffusion region 61 so that light does not enter the analog memory.
  • a light-shielding layer that effectively shields the analog memory can be formed. Furthermore, a light shielding layer can also be formed in a solid-state imaging device having a photoelectric conversion film in combination with a photodiode. With this configuration, a solid-state imaging device having a global shutter structure with a large photodiode aperture and high sensitivity can be configured.
  • a solid-state imaging device having a global shutter function in which a plurality of photodiodes and photoelectric conversion films are installed at different positions in the depth direction within a single pixel in response to the wavelength dependence of the light absorption coefficient of light. Can be configured.
  • FIG. 7 shows a cross-sectional view of a main part constituting one pixel of the solid-state imaging device of the third embodiment.
  • the solid-state image sensor 70 of the third embodiment shown in FIG. 7 differs from the solid-state image sensor of the first embodiment described above only in the configuration of the transistors, and the configuration other than the transistors is the same as that of the solid-state image sensor of the first embodiment. It is.
  • a solid-state imaging device 70 shown in FIG. 7 includes an analog memory and a charge detection unit, to which a separate floating diffusion region is applied in the solid-state imaging device of the first embodiment described above, configured as one floating diffusion region. Yes.
  • a photodiode (PD) 72 is formed on the surface of the semiconductor substrate 71 on the light incident surface (substrate back surface) 71A side.
  • the solid-state imaging device 70 includes a transfer transistor Tr1 on the surface opposite to the light incident surface (substrate surface) 71B side.
  • the transfer transistor Tr1 includes a vertical gate electrode 74 formed through a gate insulating film 73, the PD 72, and a floating diffusion region 75 for accumulating signal charges transferred from the PD 72.
  • the PD 72 includes a first conductivity type (p-type) semiconductor region 72A and a second conductivity type (n-type) semiconductor region 72B from the back surface 71A side in a region formed in the first conductivity type of the semiconductor substrate 71.
  • the p-type semiconductor region 72A is formed on the surface of the semiconductor substrate 71 on the back surface 71A side.
  • the n-type semiconductor region 72B is formed in contact with the p-type semiconductor region 72A, and a part thereof is continuously formed up to the surface 71B side of the semiconductor substrate 71.
  • a vertical gate of the gate electrode 74 is formed through a gate insulating film 73 in a region protruding to the surface 71B side of the n-type semiconductor region 72B.
  • the vertical gate of the gate electrode 74 is formed by filling a trench formed from the surface 71 ⁇ / b> B side of the semiconductor substrate 71.
  • Tr1 a positive voltage is applied to the gate electrode 74 at the time of reading, and the potential (potential) immediately below the gate electrode 74 changes. Then, the signal charge accumulated in the PD 72 passes through a region around the vertical gate of the gate electrode 74 and is transferred to the floating diffusion region 75.
  • the floating diffusion region 75 functions as an analog memory until the accumulated signal charge is output.
  • the floating diffusion region 75 functions as a charge detection unit for accumulated signal charges.
  • the solid-state imaging device 70 includes a light shielding layer 76 that covers the light incident surface side of the floating diffusion region 75 so that a new signal charge is not generated by photoelectric conversion in the floating diffusion region 75 that functions as an analog memory.
  • the light shielding layer 76 includes a horizontal light shielding portion 76A extending in a direction parallel to the main surface of the semiconductor substrate 71 and a vertical light shielding portion 76B extending in a direction perpendicular to the main surface of the semiconductor substrate 71.
  • the horizontal light-shielding portion 76 ⁇ / b> A is embedded in the semiconductor substrate 71 in a range that covers the floating diffusion region 75.
  • the vertical light shielding portion 76B is formed from the back surface 71A side of the semiconductor substrate 71 to a depth connecting to the horizontal light shielding portion 76A.
  • the horizontal light-shielding portion 76A covers at least the floating diffusion region 75 in the semiconductor substrate 71 and is formed at a position where incident light does not enter the analog memory.
  • a first conductivity type (p-type) semiconductor region 77 is formed around the light shielding layer 76.
  • the PD 72 and the light shielding layer 76 are separated by the p-type semiconductor region 77.
  • the solid-state imaging device 70 having the above-described configuration, signal charges of the PD 72 are read out simultaneously for all the pixels in the imaging region.
  • the signal charge from the PD 72 is temporarily held in the floating diffusion region 75 and then output from the floating diffusion region 75.
  • the global shutter function can be provided to the solid-state imaging device 70.
  • the FD needs to be formed for each PD in the configuration of the third embodiment. For this reason, it cannot be set as the structure which shares FD with a some pixel like the solid-state image sensor of 1st Embodiment.
  • the analog memory has a functionally large floating diffusion region because the capacitance can be increased.
  • the smaller floating diffusion region is advantageous in terms of conversion efficiency and variation. Therefore, in the solid-state imaging device, the configuration of the floating diffusion region is appropriately selected in consideration of the characteristics of the global shutter and the area of the transistor formation region.
  • FIG. 8 shows a cross-sectional view of a main part constituting one pixel of the solid-state imaging device of the fourth embodiment.
  • the solid-state imaging device 80 of the fourth embodiment shown in FIG. 8 differs from the solid-state imaging device of the third embodiment described above only in the configuration of the light shielding layer, and the configuration other than the light shielding layer is the solid-state imaging device of the third embodiment. It is the same.
  • the solid-state image sensor 80 shown in FIG. 8 forms the configuration of the vertical light-shielding part formed from the back surface side to the horizontal light-shielding part in the solid-state image sensor of the third embodiment described above from the front surface side to the position exceeding the horizontal light-shielding part. ing.
  • a photodiode (PD) 82 is formed on the surface of the semiconductor substrate 81 on the light incident surface (substrate back surface) 81A side.
  • the solid-state imaging device 80 includes a transfer transistor (Tr1) on the surface opposite to the light incident surface (substrate surface) 81B.
  • the transfer transistor Tr1 includes a vertical gate electrode 84 formed through a gate insulating film 83, and the floating diffusion region 85 that accumulates the signal charges transferred from the PD 82 and PD 82.
  • the PD 82 includes a first conductivity type (p-type) semiconductor region 82A and a second conductivity type (n-type) semiconductor region 82B from the back surface 81A side in a region formed in the first conductivity type of the semiconductor substrate 81. .
  • the p-type semiconductor region 82A is formed on the surface of the semiconductor substrate 81 on the back surface 81A side.
  • the n-type semiconductor region 82B is formed in contact with the p-type semiconductor region 82A, and a part thereof is continuously formed up to the surface 81B side of the semiconductor substrate 81.
  • a vertical gate of the gate electrode 84 is formed through a gate insulating film 83 in a region protruding to the surface 81B side of the n-type semiconductor region 82B.
  • the vertical gate of the gate electrode 84 is formed by filling a trench formed from the surface 81 ⁇ / b> B side of the semiconductor substrate 81.
  • Tr1 a positive voltage is applied to the gate electrode 84 at the time of reading, and the potential (potential) immediately below the gate electrode 84 changes. Then, the signal charge accumulated in the PD 82 passes through the region around the vertical gate of the gate electrode 84 and is transferred to the floating diffusion region 85.
  • the floating diffusion region 85 functions as an analog memory until the accumulated signal charge is output.
  • the floating diffusion region 85 functions as a charge detection unit for accumulated signal charges.
  • a light shielding layer 86 that covers the light incident surface side of the floating diffusion region 85 is provided so that a new signal charge is not generated by photoelectric conversion in the floating diffusion region 85 that functions as an analog memory.
  • an insulating layer 87 provided between the light shielding layer 86 and the semiconductor substrate 81 is provided continuously from the surface 81 ⁇ / b> B side of the semiconductor substrate 81.
  • a first conductivity type (p-type) semiconductor region 88 is formed around the light shielding layer 86. The PD 82 and the light shielding layer 86 are separated by the p-type semiconductor region 88.
  • the light shielding layer 86 includes a horizontal light shielding portion 86A extending in a direction parallel to the main surface of the semiconductor substrate 81, and a vertical light shielding portion 86B extending in a direction perpendicular to the main surface of the semiconductor substrate 81.
  • the horizontal light shielding portion 86 ⁇ / b> A is embedded in the semiconductor substrate 81 in a range that covers the floating diffusion region 85.
  • the horizontal light-shielding portion 86A covers at least the floating diffusion region 85 in the semiconductor substrate 81 and is formed at a position where incident light does not enter the analog memory.
  • the vertical light-shielding portion 86B has an end exposed on the surface on the surface 81B side of the semiconductor substrate 81, and is formed through the horizontal light-shielding portion 86A to the vicinity of the back surface 81A of the semiconductor substrate 81. Further, the vertical light-shielding portion 86B is formed up to between the PDs 82 of adjacent pixels. For this reason, by making it the shape which protruded in the back surface side, a vertical light-shielding part is formed between adjacent PD, and the vertical light-shielding part 86B between pixels functions as pixel separation.
  • the light shielding layer 86 is formed from the surface 81B side of the semiconductor substrate 81. Even when the light shielding layer 86 is formed from the surface 31B side, a solid-state imaging device having a global shutter function can be configured by shielding the floating diffusion region 85 functioning as an analog memory from incident light.
  • [Modification] 9 and 10 show the positional relationship in the plane of the photodiode, the transistor, and the light shielding layer in the solid-state imaging device having a structure in which the light shielding layer is formed from the surface side.
  • the vertical light shielding portion is formed from the surface of the base to the horizontal light shielding portion.
  • the gate electrode is formed only from a planar gate. Accordingly, the configuration of the solid-state imaging device shown in FIG. 9 corresponds to the configuration in which the light shielding layer is formed from the substrate surface side in the solid-state imaging device having the configuration shown in FIG.
  • the analog memory and the charge detection unit are configured from one floating diffusion region, and a light shielding layer is further provided. This corresponds to the configuration formed from the substrate surface side.
  • [Modification 1] 9A is a plan view showing the surface 91B side of the solid-state imaging device 90.
  • FIG. 9B is a cross-sectional view taken along line AA of the solid-state imaging device 90 shown in FIG. 9A.
  • a and B in FIG. 9 indicate areas for four pixels of the solid-state imaging device 90.
  • Each pixel includes a photodiode (PD) 92 formed on the back surface 91A side of the semiconductor substrate 91, a first transistor (Tr1) and a second transistor (Tr2) formed on the surface 91B side of the semiconductor substrate 91. It is composed of
  • the PD 92 is formed on and in contact with the first conductivity type (p-type) semiconductor region 92A formed on the surface of the semiconductor substrate 91 on the back surface 91A side, and a part of the PD 92 is on the surface 91B side of the semiconductor substrate 91. And a second conductivity type (n-type) semiconductor region 92B extending to the end.
  • a first gate electrode 94 and a second gate electrode 96 are formed on the surface 91 ⁇ / b> B side of the semiconductor substrate 91 via an insulating layer 93.
  • the Tr1 includes a first gate electrode 94, a PD 92, and a first floating diffusion region (analog memory) 95 corresponding to the PD 92.
  • the Tr2 includes a second gate electrode 96, a first floating diffusion region 95, and a second floating diffusion region (charge detection unit) 97.
  • the second floating diffusion region 97 is formed in common with two adjacent pixels.
  • the solid-state imaging device 90 includes a light shielding layer 98 that covers the light incident surface side of the first floating diffusion region 95.
  • the light shielding layer 98 includes a horizontal light shielding portion 98A that extends in a direction parallel to the main surface of the semiconductor substrate 91, and a vertical light shielding portion 98B that extends in a direction perpendicular to the main surface of the semiconductor substrate 91.
  • the horizontal light shielding portion 98A is formed at a position that covers the first floating diffusion regions 95 of adjacent four pixels. As described above, the horizontal light shielding portion 98A can be formed in common in adjacent pixels.
  • the vertical light shielding portion 98B is formed in a region where no photodiode is formed, for example, a region between adjacent pixels.
  • [Modification 2] 10A is a plan view showing the surface 101B side of the solid-state imaging device 100.
  • FIG. 10B is a cross-sectional view taken along line AA of the solid-state imaging device 100 shown in FIG. 10A and 10B show regions for four pixels of the solid-state imaging device 100.
  • FIG. Each pixel includes a photodiode (PD) 102 formed on the back surface 101A side of the semiconductor substrate 101 and a transistor (Tr1) formed on the front surface 101B side of the semiconductor substrate 101.
  • PD photodiode
  • Tr1 transistor
  • the PD 102 is formed in contact with the first conductive type (p-type) semiconductor region 102A formed on the back surface 101A side surface of the semiconductor substrate 101 and the p-type semiconductor region 102A, and a part thereof is on the front surface 101B side of the semiconductor substrate 101. And a second conductivity type (n-type) semiconductor region 102B extending to the end.
  • a gate electrode 104 is formed on the surface 101B side of the semiconductor substrate 101 with an insulating layer 103 interposed therebetween. Tr1 includes a gate electrode 104, a PD 102, and a floating diffusion region 105 corresponding to the PD 102. Further, as shown in FIGS.
  • the solid-state imaging device 100 includes a light shielding layer 106 that covers the light incident surface side of the floating diffusion region 105.
  • the light shielding layer 106 includes a horizontal light shielding portion 106A that extends in a direction parallel to the main surface of the semiconductor substrate 101, and a vertical light shielding portion 106B that extends in a direction perpendicular to the main surface of the semiconductor substrate 101.
  • the horizontal light-shielding portion 106A is formed at a position that covers the floating diffusion region 105 of four adjacent pixels. As described above, the horizontal light shielding portion 106A can be formed in common in adjacent pixels.
  • the vertical light shielding portion 106B is formed in a region where no photodiode is formed, for example, a region between adjacent pixels.
  • the configuration excluding the light shielding layer is the same as in the above-described first embodiment, second embodiment, and third embodiment.
  • a configuration similar to that of the solid-state imaging device can be applied.
  • FIG. 11 is a cross-sectional view of a main part constituting one pixel of the solid-state imaging device of the fifth embodiment.
  • a solid-state imaging device 110 shown in FIG. 11 is an example in which a light shielding layer is formed on a CCD image sensor (Charge Coupled Device Image Sensor).
  • a photodiode (PD) 112 is formed on the surface of the semiconductor substrate 111 on the light incident surface (substrate back surface) 111A side.
  • the solid-state imaging device 110 includes a transistor (Tr1) on the surface opposite to the light incident surface (substrate surface) 111B.
  • the transistor Tr1 includes a gate electrode 114, the PD 112, and a transfer unit 115 that transfers signal charges from the PD 112.
  • the PD 112 includes a first conductivity type (p-type) semiconductor region 112A and a second conductivity type (n-type) semiconductor region 112B from the back surface 111A side in the region formed in the first conductivity type of the semiconductor substrate 31. .
  • the p-type semiconductor region 112A is formed on the surface of the semiconductor substrate 111 on the back surface 111A side.
  • the n-type semiconductor region 112B is formed in contact with the p-type semiconductor region 112A, and a part thereof is continuously formed up to the surface 111B side of the semiconductor substrate 111.
  • a vertical gate of the gate electrode 114 is formed through a gate insulating film 113 along a region protruding to the surface 111B side of the n-type semiconductor region 112B.
  • the transfer unit 115 includes a second conductive type (n-type) semiconductor region 115A formed on the surface 111B side of the semiconductor substrate 111, and a first conductive type semiconductor region (pwell) formed deeper than the n-type semiconductor region 115A. ) 115B.
  • a light-shielding film that also serves as the gate electrode 114 is formed on the surface 111B side.
  • the PD 112 is provided on the back surface 111A side of the semiconductor substrate 111, and light is incident from the back surface 111A side. Therefore, it is necessary to have a configuration in which the transfer unit 115 is shielded so that new signal charges are not generated by photoelectric conversion with respect to light incident from the back surface 111A side.
  • the solid-state imaging device 110 illustrated in FIG. 11 includes a light shielding layer 116 that covers the surface 111 ⁇ / b> A side of the transfer unit 115.
  • the light shielding layer 116 includes a horizontal light shielding portion 116A extending in a direction parallel to the main surface of the semiconductor substrate 111 and a vertical light shielding portion 116B extending in a direction perpendicular to the main surface of the semiconductor substrate 111.
  • the light shielding layer 116 is covered with a first conductivity type (p-type) semiconductor region 117.
  • the horizontal light shielding portion 116A is embedded in the semiconductor substrate 111.
  • the vertical light shielding part 116B is formed from the surface 111B side of the semiconductor substrate 111 to a depth connecting to the horizontal light shielding part 116A.
  • the horizontal light shielding part 116A needs to be provided in the semiconductor substrate 111 at a position that covers at least the transfer part 115 and does not allow incident light to enter the analog memory.
  • a CCD image sensor having a configuration in which light enters from the back side of the semiconductor substrate can be configured.
  • a CCD image sensor is configured to perform a global shutter operation.
  • the analog memory can be shielded against incident light from the back surface side, so that a back-illuminated CCD image sensor can be realized.
  • the above-mentioned light shielding layer is formed from the surface side, you may provide the light shielding layer formed from the back surface side like the above-mentioned 1st Embodiment.
  • the first conductivity type (p-type) impurity and the second conductivity type (from the surface 31B side of the semiconductor substrate 31 on which the oxide layer 121 is formed to a predetermined depth)
  • An n-type impurity is ion-implanted.
  • a p-type semiconductor region 32A and an n-type semiconductor region 32B constituting the photodiode (PD) 32 are formed.
  • a p-type semiconductor region 39 that covers the periphery of the light shielding layer is formed.
  • the semiconductor substrate 31 for example, an SOI (Silicon on Insulator) substrate or the like is used.
  • annealing is performed.
  • the ion implantation region is designed in consideration of the diffusion caused by annealing.
  • the ion implantation may be performed in a plurality of times.
  • oxygen ions are implanted into a predetermined position of the semiconductor substrate 31.
  • an annealing process is performed to form the buried oxide layer 122.
  • the buried oxide layer 122 is formed so as to spread in a direction parallel to the main surface of the semiconductor substrate 31 at a position where the horizontal light shielding portion of the light shielding layer is provided.
  • the buried oxide layer 122 is formed using a known Partial SIMOX (Separation-by-Implanted-Oxgen) technique.
  • an n-type impurity is implanted into a predetermined position on the surface 31B of the semiconductor substrate 31 to form a first floating diffusion region 35 and a second floating diffusion region 37.
  • the first transistor Tr1 and the second transistor Tr2 are formed.
  • n-type impurities are ion-implanted from the surface 31B of the semiconductor substrate 31 to a depth contacting the n-type semiconductor region 32B of the PD 32.
  • a trench for forming a vertical gate is formed in the ion implanted region.
  • a gate electrode material is deposited on the surface 31B of the semiconductor substrate 31 so as to fill the trench.
  • the first gate electrode 34 and the second gate electrode 36 are formed by etching the gate electrode material into a predetermined gate electrode pattern.
  • a desired plug or the like is formed on the first transistor Tr1 and the second transistor Tr2.
  • a support substrate (not shown) or another semiconductor substrate is joined to the surface 31B side of the semiconductor substrate 31 and turned upside down. . Then, the semiconductor substrate 31 is separated from the oxide layer 121, and the back surface 31A side is exposed.
  • a hard mask 124 is formed on the back surface 31 ⁇ / b> A of the semiconductor substrate 31.
  • the hard mask 124 is formed of a material having resistance when the buried oxide layer 122 is removed in a later process.
  • a photoresist layer 125 is formed on the hard mask 124. Then, patterning is performed on the photoresist layer 125 to open a region for forming the vertical light shielding portion of the light shielding layer. Further, the hard mask 124 and the semiconductor substrate 31 are etched from the opening formed in the photoresist layer 125 to form a trench 126. For the etching of the semiconductor substrate 31, for example, reactive ion etching (RIE), Deep RIE, or the like is used. The depth at which the trench 126 is formed is within the range of the region where the buried oxide layer 122 is formed. In addition, trenches 126 that are in contact with the same buried oxide layer 122 may be formed at a plurality of locations on the semiconductor substrate 31.
  • RIE reactive ion etching
  • Deep RIE Deep RIE
  • the buried oxide layer 122 is removed from the formed trench 126 to form a cavity 127.
  • the cavity 127 is configured to communicate with the back surface 31 ⁇ / b> A side of the semiconductor substrate 31 through the trench 126. For this reason, a region serving as a light shielding layer is formed in the semiconductor substrate 31 by the trench 126 and the cavity 127.
  • the buried oxide layer 122 is removed by, for example, wet etching or dry etching.
  • a light shielding material is embedded in the trench 126 and the cavity 127 to form a light shielding material layer 128 on the semiconductor substrate 31.
  • the light shielding material layer 128 is formed using the above-described material.
  • the light shielding material layer 128 is formed using a CVD method or the like for a material such as metal, for example.
  • inorganic and organic materials are formed using a coating method or the like.
  • an insulating layer (not shown) may be formed on the inner surfaces of the trench 126 and the cavity 127 before forming the light shielding material layer 128.
  • the insulating layer is formed by using an ALD (atomic layer deposition) method or the like, using the material of the insulating layer that covers the light shielding layer.
  • the light shielding material layer 128 on the hard mask 124 is removed to form the light shielding layer 38.
  • the cavity 127 described above serves as the horizontal light shielding portion 38A
  • the trench 126 serves as the vertical light shielding portion 38B.
  • an insulating layer 129 is formed by using an HDP-CVD method or the like. The insulating layer 129 is formed with a thickness equal to or less than the above-described hard mask 124. Therefore, after the insulating layer 129 is formed, the upper end of the vertical light shielding portion 38B is exposed from the insulating layer 129.
  • the light shielding layer 38 is electrically connected to an external device by connecting a wiring 130 or the like to the upper end of the vertical light shielding portion 38B. Thereafter, an optical member such as a color filter (not shown) is formed on the photodiode PD32, and the on-chip lens 131 is formed.
  • an optical member such as a color filter (not shown) is formed on the photodiode PD32, and the on-chip lens 131 is formed.
  • the manufacturing method it is not necessary to perform formation of a semiconductor layer by epitaxial growth, bonding of a semiconductor substrate, or the like when forming a light shielding layer and a transistor, unlike the conventional manufacturing method. And since the charge transfer path for signal charges is formed in the semiconductor substrate in the same way as a normal solid-state imaging device, white spots and dark current are generated due to crystal defects generated on the epitaxial growth layer and the bonded surface of the substrate. Can be suppressed. Further, when the buried oxide layer 122 is formed using the SIMOX technique, oxygen ions are implanted, and then an annealing process is performed at a high temperature (for example, 1000 ° C. or higher). By this annealing treatment, crystal defects in the semiconductor substrate, particularly in regions such as PD 42 doped with impurities, are reduced. For this reason, the white spot and dark current of a solid-state image sensor are improved.
  • a high temperature for example, 1000 ° C. or higher
  • a via 132 extending from the surface to a predetermined depth is formed on the entire surface of the region where the horizontal light shielding portion of the light shielding layer is formed.
  • a plurality of vias 132 are formed in an array on the surface 31 ⁇ / b> B of the semiconductor substrate 31.
  • the diameter, depth, number of vias 132 and the interval between the vias 132 are optimally designed according to the position and size of the light shielding layer to be formed.
  • the semiconductor substrate 31 on which the above-described via 132 is formed is annealed in a hydrogen atmosphere.
  • the annealing process is performed for 3 minutes under the conditions of 1100 ° C. and 300 Torr, for example.
  • Si on the surface of the semiconductor substrate 31 migrates and a cavity 133 is formed as shown in FIG. *
  • the first conductivity type (p-type) impurity and the second conductivity type (n-type) impurity are ion-implanted from the surface 31 ⁇ / b> B side of the semiconductor substrate 31.
  • a p-type semiconductor region 32A and an n-type semiconductor region 32B constituting the photodiode (PD) 32 are formed by ion implantation. Further, a p-type semiconductor region 39 that covers the periphery of the light shielding layer is formed. Further, a first floating diffusion region 35 and a second floating diffusion region 37 are formed.
  • n-type impurities are ion-implanted from the surface 31B of the semiconductor substrate 31 to a depth in contact with the n-type semiconductor region 32B of the PD 32.
  • the first gate electrode 34 and the second gate electrode 36 are formed by filling the trench formed in the ion-implanted region.
  • the PD 32, the first transistor Tr1, and the second transistor Tr2 are formed.
  • a hard mask 124 and a photoresist layer 125 are formed on the back surface 31 ⁇ / b> A of the semiconductor substrate 31. Then, as shown in FIG. 17F, the photoresist layer 125, the hard mask 124, and the semiconductor substrate 31 are etched to form a trench 126.
  • Si on nothing.
  • the process up to the step H shown in FIG. 14 of the manufacturing method of the first embodiment described above can be performed. Subsequent steps are the same as those in the manufacturing method of the first embodiment described above, and thus description thereof is omitted.
  • the solid-state imaging device manufactured by this method also has effects such as suppression of white spots and dark current, as in the solid-state imaging device formed by the manufacturing method of the first embodiment described above.
  • a p-type semiconductor region 82A and an n-type semiconductor region 82B constituting the photodiode (PD) 82 are formed. Further, a p-type semiconductor region 88 that covers the periphery of the light shielding layer is formed.
  • a silicon wafer or an SOI (Silicon-on-Insulator) substrate is used as the semiconductor substrate 81.
  • oxygen ions are implanted into a predetermined position of the semiconductor substrate 81.
  • a buried oxide layer 135 is formed by performing + annealing after ion implantation.
  • the buried oxide layer 135 is formed so as to spread in a direction parallel to the main surface of the semiconductor substrate 81 at a position where the horizontal light shielding portion of the light shielding layer is provided.
  • an n-type impurity is implanted into a predetermined position on the surface 81 ⁇ / b> B of the semiconductor substrate 81 to form a floating diffusion region 85.
  • the transistor Tr1 is formed.
  • n-type impurities are ion-implanted from the surface 81B of the semiconductor substrate 81 to a depth in contact with the n-type semiconductor region 82B of the PD 82. Then, a trench for forming a vertical gate is formed in the ion implanted region. Then, a gate electrode material is deposited on the surface 81B of the semiconductor substrate 81 so as to fill the trench. After planarizing the surface of the gate electrode material, the gate electrode material is etched into a predetermined gate electrode pattern to form the gate electrode 84. Through the above steps, the PD 82 and the transistor Tr1 are formed.
  • an interlayer insulating layer 136 is formed on the surface 81B of the semiconductor substrate 81.
  • the interlayer insulating layer 136 is formed of a material having resistance when the buried oxide layer 135 is removed in a later process. For example, when hydrofluoric acid (HF) is used to remove the buried oxide layer 135, a material having resistance to HF such as SiN is used for the interlayer insulating layer 136.
  • HF hydrofluoric acid
  • a photoresist layer 137 is formed on the interlayer insulating layer 136. Then, patterning is performed on the photoresist layer 137 to open a region where the vertical light shielding portion of the light shielding layer is formed. Further, the trench 138 is formed by etching the interlayer insulating layer 136 and the semiconductor substrate 81 from the opening formed in the photoresist layer 137. For the etching of the semiconductor substrate 81, Deep RIE or the like is used. The trench 138 is formed through the region where the buried oxide layer 135 is formed to the back surface 81 ⁇ / b> A side from the buried oxide layer 135. In addition, trenches 138 that are in contact with the same buried oxide layer 135 may be formed at a plurality of locations of the semiconductor substrate 81.
  • the buried oxide layer 135 is removed from the formed trench 138 to form a cavity 139.
  • the cavity 139 communicates with the interlayer insulating layer 136 on the surface 81 ⁇ / b> B of the semiconductor substrate 81 through the trench 138. Therefore, a region serving as a light shielding layer is formed in the semiconductor substrate 81 from the trench 138 and the cavity 139.
  • a light shielding material is embedded in the trench 138 and the cavity 139 to form a light shielding material layer 140 on the semiconductor substrate 81.
  • the light shielding material layer 140 is formed using the above-described material.
  • the light shielding material layer 140 is formed using a CVD method or the like for a material such as a metal, for example.
  • inorganic and organic materials are formed using a coating method or the like.
  • an insulating layer (not shown) may be formed on the inner surfaces of the trench 138 and the cavity 139 before forming the light shielding material layer 140.
  • the insulating layer is formed by using an ALD (atomic layer deposition) method or the like, using the material of the insulating layer that covers the light shielding layer.
  • the light shielding material layer 140 on the interlayer insulating layer 136 is removed to form a light shielding layer 86.
  • the hollow portion 139 described above becomes the horizontal light shielding portion 86A
  • the trench 138 becomes the vertical light shielding portion 86B.
  • the solid-state imaging device of the fourth embodiment described above can be manufactured.
  • a solid-state imaging device having a configuration in which a light shielding layer is formed from the surface side of the semiconductor substrate can also be manufactured using the above-mentioned Partial SIMOX technology. Further, by applying the modification of the manufacturing method of the first embodiment described above to the manufacturing method of the second embodiment, the above-described Si on nothing.
  • the cavity can also be formed using technology.
  • FIG. 21 illustrates a schematic configuration when a solid-state imaging device is applied to a camera capable of capturing a still image or a moving image as an example of an electronic device.
  • the camera 150 in this example includes a solid-state image sensor 151, an optical system 152 that guides incident light to the light receiving sensor unit of the solid-state image sensor 151, a shutter device 153 provided between the solid-state image sensor 151 and the optical system 152, and a solid-state image sensor 151. And a drive circuit 154 for driving the image sensor 151. Furthermore, the camera 150 includes a signal processing circuit 155 that processes an output signal of the solid-state image sensor 151.
  • the solid-state image sensor 151 described in the first to fifth embodiments can be applied to the solid-state image sensor 151.
  • the optical system (optical lens) 152 forms image light (incident light) from a subject on an imaging surface (not shown) of the solid-state imaging device 151. Thereby, signal charges are accumulated in the solid-state imaging device 151 for a certain period.
  • the optical system 152 may be configured by an optical lens group including a plurality of optical lenses.
  • the shutter device 153 controls the light irradiation period and the light shielding period of the incident light to the solid-state imaging device 151.
  • the drive circuit 154 supplies a drive signal to the solid-state image sensor 151 and the shutter device 153.
  • the drive circuit 154 controls the signal output operation to the signal processing circuit 155 of the solid-state image sensor 151 and the shutter operation of the shutter device 153 by the supplied drive signal. That is, in this example, a signal transfer operation from the solid-state imaging device 151 to the signal processing circuit 155 is performed by a drive signal (timing signal) supplied from the drive circuit 154.
  • the signal processing circuit 155 performs various types of signal processing on the signal transferred from the solid-state image sensor 151.
  • the signal (video signal) that has been subjected to various signal processing is stored in a storage medium (not shown) such as a memory, or is output to a monitor (not shown).
  • the present invention is applied to an image sensor in which unit pixels that detect signal charges corresponding to the amount of visible light as physical quantities are arranged in a matrix has been described as an example.
  • the above-described solid-state imaging device is not limited to application to an image sensor, and can be applied to all column-type solid-state imaging devices in which column circuits are arranged for each pixel column of the pixel array unit. .
  • the solid-state imaging device described above is not limited to application to a solid-state imaging device that senses the distribution of the amount of incident light of visible light and captures it as an image, but uses the distribution of the incident amount of infrared rays, X-rays, or particles as an image.
  • the present invention can be applied to a solid-state imaging device for imaging.
  • the present invention can be applied to all solid-state imaging devices (physical quantity distribution detection devices) such as a fingerprint detection sensor that senses other physical quantity distributions such as pressure and capacitance and captures images as images.
  • the above-described solid-state imaging device is not limited to a solid-state imaging device that sequentially scans each unit pixel of the pixel array unit in units of rows and reads a pixel signal from each unit pixel.
  • the present invention can also be applied to an XY address type solid-state imaging device that selects an arbitrary pixel in pixel units and reads a signal from the selected pixel in pixel units.
  • the solid-state imaging device may be formed as a single chip, or may be in a module-like form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. Good.
  • the present invention can also be applied to a solid-state imaging device using holes as signal charges.
  • the first conductivity type is p-type and the second conductivity type is n-type
  • the first conductivity type is n-type and the second conductivity type is p-type.
  • the voltage applied to each pixel transistor replaces the positive voltage with a negative voltage and the negative voltage with a positive voltage.
  • this indication can also take the following structures.
  • a solid-state imaging device comprising: a horizontal light shielding portion and a light shielding layer comprising a vertical light shielding portion perpendicular to the semiconductor substrate surface.
  • the step of forming the cavity includes a step of forming a buried oxide layer in the semiconductor substrate, a step of forming a trench reaching the buried oxide layer, and etching the buried oxide layer.
  • the manufacturing method of the solid-state image sensor as described in (7) which consists of the process of forming the cavity parallel to the said semiconductor substrate surface.
  • the step of forming the cavity includes a step of forming a plurality of vias in the semiconductor substrate, and annealing the semiconductor substrate to form a cavity parallel to the semiconductor substrate surface in the semiconductor substrate.
  • a process for producing a solid-state imaging device according to (7) comprising the steps of: (10) An electronic apparatus comprising the solid-state imaging device according to any one of (1) to (6) and a signal processing circuit that processes an output signal of the solid-state imaging device.

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  • Solid State Image Pick-Up Elements (AREA)

Abstract

La présente invention se rapporte à un élément d'imagerie à semi-conducteurs, à un procédé de fabrication de l'élément d'imagerie à semi-conducteurs et à un dispositif électronique de telle sorte que l'élément d'imagerie à semi-conducteurs soit pourvu d'une fonction d'obturateur globale et puisse supprimer les points blancs et le courant noir. La présente invention comprend un substrat semi-conducteur (31), une photodiode (32) formée sur le substrat semi-conducteur (31) et une région de diffusion flottante (35) où est transférée une charge de signal qui est accumulée sur la photodiode (32). En outre, un élément d'imagerie à semi-conducteurs est configuré de sorte à être pourvu d'une couche de protection (32) dans le substrat semi-conducteur (31), la couche de protection comprenant une partie plate de protection contre la lumière (32A) qui est parallèle à la surface du substrat semi-conducteur (31) qui recouvre la région de diffusion flottante (35), ainsi qu'une partie de protection perpendiculaire (32B) qui est perpendiculaire à la surface du substrat semi-conducteur.
PCT/JP2012/077580 2011-11-04 2012-10-25 Élément d'imagerie à semi-conducteurs, procédé de fabrication d'un élément d'imagerie à semi-conducteurs, et dispositif électronique WO2013065569A1 (fr)

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