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WO2013065465A1 - Dispositif de communication et procédé de fonctionnement d'un dispositif de communication - Google Patents

Dispositif de communication et procédé de fonctionnement d'un dispositif de communication Download PDF

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Publication number
WO2013065465A1
WO2013065465A1 PCT/JP2012/076265 JP2012076265W WO2013065465A1 WO 2013065465 A1 WO2013065465 A1 WO 2013065465A1 JP 2012076265 W JP2012076265 W JP 2012076265W WO 2013065465 A1 WO2013065465 A1 WO 2013065465A1
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WO
WIPO (PCT)
Prior art keywords
output
storage unit
data
bit
transmission data
Prior art date
Application number
PCT/JP2012/076265
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English (en)
Japanese (ja)
Inventor
寒達 陳
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株式会社メガチップス
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Filing date
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Application filed by 株式会社メガチップス filed Critical 株式会社メガチップス
Publication of WO2013065465A1 publication Critical patent/WO2013065465A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/08—Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes

Definitions

  • the present invention relates to communication technology.
  • encoding for adding error correction information to the transmission data is performed, and the encoded transmission data is transmitted.
  • the receiving device that has received the encoded transmission data can acquire the original transmission data by decoding the reception data.
  • interleaving that rearranges the bit string of the data after repetition can be considered.
  • a communication unit having a function of performing interleaving after repetition such as a storage unit for storing data after repetition that has been repeatedly copied, is required to realize the function. This increases the number of parts.
  • an object of the present invention is to provide a technique capable of reducing the number of parts of a communication device while giving the communication device a function equivalent to a function of performing interleaving after repetition.
  • a first aspect of the communication device is a storage unit that stores transmission data, output control means that controls output of the transmission data stored in the storage unit, and data output from the storage unit Transmitting means for modulating and transmitting the data, and the output control means outputs each bit data included in the transmission data a predetermined number of times for each bit data by changing the output order.
  • a second aspect of the communication apparatus is the first aspect, wherein the output control means stores an address indicating a storage destination of output target bit data in the storage unit as an output start address.
  • the storage unit outputs the bit data stored in the output start address according to the input of the output start address, and sequentially outputs other bit data included in the transmission data.
  • the output control means outputs the output start address to the storage unit a predetermined number of times while changing the output start address.
  • the 3rd aspect of the communication apparatus which concerns on this invention is the said 1st aspect, Comprising:
  • the storage unit outputs bit data stored in each address according to the input of each address, and the output control means changes the output order of the addresses while changing the output order. The predetermined number of times is output for each address.
  • the 4th aspect of the communication apparatus which concerns on this invention is the said 1st aspect, Comprising:
  • the said output control means is the shift number at the time of carrying out bit shift of the bit sequence regarding the said transmission data memorize
  • the storage unit performs a cyclic shift process of shifting the bit string in a certain direction in accordance with the input of the shift number, and filling the bit string overflowed by the shift into an empty part, The storage unit sequentially outputs the bit string after the cyclic shift processing from one end, and the output control unit outputs the shift number to the storage unit the predetermined number of times while changing the shift number.
  • a communication device is the communication device according to any one of the first to fourth embodiments, wherein the input data is subjected to error correction encoding, and the code Interleaving means for performing an interleaving process on the data output from the converting means, and the transmission data stored in the storage unit is the data after the interleaving process.
  • the operation method of the communication apparatus includes: a) a step of outputting each bit data included in the transmission data stored in the storage unit a predetermined number of times for each bit data by changing the output order; b) the storage And modulating and transmitting data output from the unit.
  • the present invention it is possible to reduce the size of the communication device while giving the communication device a function equivalent to the function of performing interleaving after repetition.
  • FIG. 1 is a configuration diagram of a communication system 1 according to the present embodiment.
  • the communication system 1 includes a first communication device 10 and a second communication device 20.
  • the first communication device 10 and the second communication device 20 in the communication system 1 are configured to be able to communicate with each other by wired communication.
  • the transmission line 30 that electrically connects the first communication device 10 and the second communication device 20 may be a normal communication line or a power line.
  • PLC power line communication
  • wired communication between the communication devices 10 and 20 is performed using an OFDM (Orthogonal Frequency Frequency Division Multiplexing) signal obtained by combining a plurality of subcarriers orthogonal to each other on the frequency axis. Then, the OFDM signal is transmitted in packet units divided by a certain time unit.
  • OFDM Orthogonal Frequency Frequency Division Multiplexing
  • FIG. 2 is a diagram illustrating a configuration of the transmission device 10 according to the present embodiment.
  • the transmission device 10 includes a scrambler 111, an encoding unit 112, an interleave unit (interleaver) 113, an output control unit 131, a primary modulation unit 114, an input signal configuration unit 115, an IFFT (inverse high speed).
  • a Fourier transform unit 116, a parallel / serial conversion unit (parallel / serial conversion unit) 117, a GI addition unit 118, a preamble generation unit 119, a packet configuration unit 120, and a transmission unit 121 are provided.
  • the scrambler 111 performs a scramble process that agitates and rearranges the input transmission data.
  • the transmission data that has been scrambled by the scrambler 111 is input to the encoding unit 112.
  • a bit string of transmission data output from the encoding unit 112 is input to the interleaving unit 113.
  • the interleaving unit 113 performs bit interleaving for rearranging the bit string of the transmission data so that errors in the transmission data output from the encoding unit 112 are not biased.
  • the output control unit 131 has a function of controlling the output of the interleave unit 113. Details of the output control by the output control unit 131 will be described later. Transmission data output from the interleaving unit 113 is input to the primary modulation unit 114.
  • transmission data is mapped (correlated) to subcarriers for each symbol according to a predetermined modulation scheme (for example, QPSK, 16QAM).
  • a predetermined modulation scheme for example, QPSK, 16QAM.
  • the symbol (Symbol) here is a unit of transmission data, which is determined by each modulation scheme and is carried on a carrier wave (subcarrier).
  • a data symbol or a complex symbol is used.
  • symbol For example, in QPSK, transmission data that can be transmitted in one symbol (one data symbol) is 2 bits.
  • Input signal configuration section 115 is configured by a buffer or the like, and converts data symbols input from primary modulation section 114 into a predetermined number of parallel data in order to disperse data signals including transmission data on subcarriers. have.
  • the IFFT unit 116 performs inverse fast Fourier transform on the parallel data input from the input signal configuration unit 115 to convert the frequency domain data into time domain data.
  • the frequency domain data input from the input signal configuration unit 115 is amplitude and phase data for each subcarrier, and the IFFT unit 116 calculates time data for one OFDM symbol from the amplitude phase data for each subcarrier. Will be generated.
  • the parallel-serial conversion unit 117 has a function of converting parallel data input from the IFFT unit 116 into serial data.
  • the serial data output from the parallel-serial conversion unit 117 is input to the GI adding unit 118 as a baseband (baseband) OFDM signal (baseband OFDM signal).
  • the GI addition unit 118 performs a guard interval (GI) addition process on the baseband OFDM signal input from the parallel-serial conversion unit 117 and outputs the baseband OFDM signal to which the GI has been added to the packet configuration unit 120. .
  • GI guard interval
  • the preamble generation unit 119 has a function of generating and outputting a preamble signal for use in various synchronization processes such as frame synchronization and frequency synchronization performed on the reception side.
  • the packet configuration unit 120 adds a preamble signal to the OFDM signal output from the GI addition unit 118 to generate a signal in units of packets (also referred to as a “packet signal”).
  • the transmission unit 121 performs DA conversion processing that converts the digital packet signal generated by the packet configuration unit 120 into an analog packet signal, and outputs the packet signal after the DA conversion processing as a communication signal.
  • the communication signal output from the transmission unit 121 is transmitted to the reception device 20 via the transmission path 30.
  • the transmission apparatus 10 generates a packet signal and transmits the packet signal as a communication signal.
  • FIG. 3 is a diagram illustrating an example of processing performed on transmission data before primary modulation.
  • transmission data before being input to primary modulation section 114 is subjected to encoding for error correction in encoding section 112 (see FIG. 2).
  • encoding section 112 In order to reliably transmit data to the receiving side, it is preferable to improve the robustness of transmission data against interference.
  • transmission data D1 having a data length of 8 bits is output from the encoding unit 112
  • the interleaving unit 113 performs interleaving on the transmission data D1.
  • Transmission data D2 is generated.
  • the error part ER is included in the transmission data D1
  • the bias of the error part ER is corrected by the interleaving.
  • the transmission data D3 after repetition includes four transmission data D1.
  • the redundancy can be increased compared to the case where transmission data D1 before repetition is transmitted, and therefore there is a possibility that the transmission data D1 can be demodulated on the receiving side. Get higher.
  • the ratio of the maximum power to the average power (PAPR: Peak Average Power Ratio) in the OFDM signal may be increased.
  • PAPR Peak Average Power Ratio
  • a transmission apparatus that transmits an OFDM signal is designed so that the signal is not distorted by widening the dynamic range (maximum and minimum ranges of signal amplitude) of an amplifier that amplifies the transmission signal. For this reason, when the PAPR of the transmission signal increases, it becomes difficult to design an amplifier.
  • the transmission data D3 after repetition is vulnerable to burst errors that occur continuously, there is a possibility that data redundancy will not be sufficiently exhibited. Therefore, when the transmission data D3 after repetition is used as it is to generate an OFDM signal in the time domain and the OFDM signal is transmitted, the bit error rate (BER: Bit: Error Rate) of the demodulated data on the receiving side becomes worse than the theoretical value.
  • BER Bit: Error Rate
  • the transmission data D3 after repetition is data having periodicity generated by simply copying the transmission data D1 a plurality of times.
  • the transmission data D3 after repetition is further interleaved to generate transmission data D4 having no periodicity, and an OFDM signal is transmitted using the transmission data D4. Is preferably generated.
  • the transmission apparatus 10 of this embodiment controls the output of the interleaving unit 113 to perform primary modulation on data having the same properties as the transmission data D4 obtained by repetition and interleaving on the transmission data D2. Input to the unit 114.
  • FIG. 4 is a diagram for explaining the data output operation from the interleave unit 113.
  • transmission data D1 having a data length of 8 bits is output from the encoding unit 112, but the transmission data D1 has other data lengths. You may do it.
  • the 8-bit transmission data D1 output from the encoding unit 112 is subjected to interleaving in the interleaving unit 113.
  • the transmission data D2 generated by the interleaving is temporarily stored in the storage unit 132 in the interleaving unit 113.
  • the output control unit 131 outputs the bit unit data (also referred to as “bit data”) included in the transmission data D2 in the storage unit 132 so that the output order is changed a predetermined number of times (for example, four times) for each bit data. Control the output.
  • bit unit data also referred to as “bit data”
  • the output control unit 131 generates an address indicating a storage destination of data to be output, and outputs the address to the storage unit 132 as an output start address (also referred to as “read start address”).
  • the storage unit 132 outputs the bit data stored at the output start address, and sequentially outputs the bit data stored at other addresses according to a predetermined output rule. .
  • the storage unit 132 when the address AD0 is input as the output start address, the storage unit 132 outputs the bit data stored in the output start address AD0 and increments the address (output target address) by one.
  • the bit data stored at each address is sequentially output. That is, when the output start address AD0 is input, the storage unit 132 executes the output operation PE1, and the bit data b 0 , bit data b 1 , bit data b 2 , bit data b 3 , bit data b 4 , bit Data b 5 , bit data b 6 , and bit data b 7 are sequentially output in this order.
  • the output control unit 131 generates an output start address different from the previously output output start address AD0 and outputs it to the storage unit 132.
  • the output control unit 131 outputs an output start address AD6 different from the output start address AD0 to the storage unit 132.
  • the storage unit 132 outputs the bit data b 6 stored in the output start address AD6, increments the output target address by 1, and outputs the bit data b7.
  • the storage unit 132 resets the output target address and moves the output target address to the top address.
  • the output of the bit data is restarted from the head address, and the output target address is incremented by 1 until the output of all the bit data included in the transmission data D2 is completed, and stored in each incremented output target address.
  • the bit data is output sequentially.
  • bit data b 6 , bit data b 7 , bit data b 0 , bit data b 1 , bit data b 2 , bit Data b 3 , bit data b 4 , and bit data b 5 are sequentially output in this order.
  • the output control unit 131 generates an output start address that is different from the output start address AD6 output previously, and outputs the output start address to the storage unit 132.
  • the output control unit 131 outputs an output start address AD5 different from the output start address AD6 to the storage unit 132.
  • the storage unit 132 outputs the bit data b 5 stored in the output start address AD5, increments the output target address by 1, and outputs bit data b 6 and b 7 respectively.
  • the storage unit 132 resets the output target address and moves the output target address to the top address.
  • the output of the bit data is restarted from the head address, and the output target address is incremented by 1 until the output of all the bit data included in the transmission data D2 is completed, and stored in each incremented output target address.
  • the bit data is output sequentially.
  • bit data b 5 , bit data b 6 , bit data b 7 , bit data b 0 , bit data b 1 , bit Data b 2 , bit data b 3 , and bit data b 4 are sequentially output in this order.
  • the output control unit 131 generates an output start address different from the previously output output start address AD5 and outputs it to the storage unit 132.
  • the output control unit 131 outputs an output start address AD2 different from the output start address AD5 to the storage unit 132.
  • the storage unit 132 outputs the bit data b 2 stored in the output start address AD2, increments the output target address by 1, sequentially bit data stored in the incremented each address Output to.
  • the storage unit 132 resets the output target address and moves the output target address to the top address.
  • the output of the bit data is restarted from the head address, and the output target address is incremented by 1 until the output of all the bit data included in the transmission data D2 is completed, and stored in each incremented output target address.
  • the bit data is output sequentially.
  • bit data b 2 , bit data b 3 , bit data b 4 , bit data b 5 , bit data b 6 , bit Data b 7 , bit data b 0 , and bit data b 1 are sequentially output in this order.
  • the storage unit 132 when the output start addresses AD0, AD6, AD5, and AD2 are input to the storage unit 132 four times from the output control unit 131, all the bit data included in the transmission data D2 is received from the storage unit 132. Will be output four times. That is, the storage unit 132 outputs substantially four transmission data D2, and the output data D11 output from the storage unit 132 (in other words, from the interleave unit 113) is four times the transmission data D2. Corresponds to the data obtained (repeated three times).
  • the output control unit 131 changes the output start address for output, the output order of the bit data output by each output operation PE1, PE2, PE3, PE4 is different. As a result, the bit data in the output data D11 are arranged in a disordered manner as if they were interleaved.
  • the output control unit 131 controls the output of the interleaving unit 113 to thereby convert the data D11 having the same properties as data obtained by subjecting the transmission data D2 to repetition and interleaving to the primary modulation unit 114. To input.
  • the output control unit 131 outputs the output start address four times and the transmission data D2 is repeated three times (repetition number) is exemplified.
  • the transmission data D2 is repeated only once.
  • the output start address can be freely set by changing the number of outputs. For example, when the repeat count of the transmission data D2 is set to 1, the output count of the output start address by the output control unit 131 is set to 2 times. That is, the output count of the output start address by the output control unit 131 (corresponding to “predetermined number” in this specification) is set according to the number of repetitions of the transmission data D2.
  • the transmission device 10 includes the storage unit 132 that stores the transmission data D2, the output control unit 131 that controls the output of the transmission data D2 stored in the storage unit 132, and the storage unit 132. Transmitting means for modulating and transmitting the data output from. Then, the output control unit 131 outputs each bit data included in the transmission data D2 stored in the storage unit 132 a predetermined number of times for each bit data by changing the output order.
  • data D11 having the same properties as transmission data D4 obtained by subjecting transmission data D2 to repetition and interleaving can be input to primary modulation section 114. Therefore, the number of parts of the transmission apparatus 10 can be reduced as compared with a case where a function for actually performing repetition on the transmission data D2 and a function for actually interleaving data after repetition are newly provided. It becomes possible. In particular, in the transmission device 10 of the present embodiment, it is not necessary to provide a buffer for performing interleaving after repetition.
  • the interleaving after repetition will increase the processing time required for interleaving.
  • normal interleaving is not actually performed, so that the processing time required for interleaving can be shortened.
  • the receiving apparatus 20 has information about the output order of each bit data controlled by the output control unit 131 as known information in advance. For this reason, the receiving device 20 can acquire the transmission data by decoding the reception data.
  • the output control unit 131 inputs the output start address to the storage unit 132.
  • the present invention is not limited to this.
  • the output control unit 131 sequentially inputs one address at a time indicating the storage destination of the bit data to be output to the storage unit 132, and the storage unit 132 receives the bit according to the input address. It is good also as an aspect which outputs data.
  • the output control unit 131 sequentially outputs the addresses AD0 to AD7 to the storage unit 132, and the storage unit 132 changes each of the addresses AD0 to AD7 according to the inputs of the addresses AD0 to AD7.
  • Bit data b 0 to b 7 are sequentially output.
  • the output control unit 131 sequentially outputs to the addresses AD6, AD7, AD0 to AD5 storage unit 132, and the storage unit 132 responds to the inputs of the addresses AD6, AD7, AD0 to AD5.
  • the bit data b 6 , b 7 , b 0 to b 5 are sequentially output.
  • the output control unit 131 outputs each address indicating the storage destination of each bit data included in the transmission data a predetermined number of times for each address while changing the output order.
  • the data output operation from the interleave unit 113 may be a mode in which the bit data is output while shifting the bit string of the transmission data D2 and performing a cyclic shift to fill the vacant bit string in the vacant part. Good.
  • the output control unit 131 outputs the shift number when the bit string of the transmission data D2 is bit-shifted to the storage unit 132.
  • the output control unit 131 outputs, to the storage unit 132, the shift number “0” when performing the first output for each bit data included in the transmission data D2.
  • the storage unit 132 outputs bit data in order from the left end of the data stored in the storage unit 132 (in this case, bit data b 0 ) without performing a shift. To do.
  • the output control unit 131 outputs the shift number “2” when performing the second output for each bit data to the storage unit 132.
  • the storage unit 132 shifts the bit string of the data stored in the storage unit 132 to the left by 2 bits according to the input shift number “2”, and the bit string overflowed by the shift (bit data b 6 , b 7 ) Perform a cyclic shift process to fill the empty part, and store the data after the cyclic shift process in the storage unit 132. Then, the storage unit 132, the left end of the stored data (in this case, bit data b 6) outputs the bit data in order from.
  • the output control unit 131 outputs the shift number “1” when performing the third output for each bit data to the storage unit 132.
  • the storage unit 132 shifts the bit string of the data stored in the storage unit 132 to the left by 1 bit in accordance with the input shift number “1”, and the bit string (bit data b 5 ) overflowed by the shift is stored. Performs a cyclic shift process to fill in empty areas. Then, the storage unit 132, the left end of the data after cyclic shift processing (in this case, bit data b 5) outputs the bit data in order from.
  • the output control unit 131 outputs to the storage unit 132 the shift number “3” when performing the fourth output for each bit data.
  • the storage unit 132 shifts the bit string of the data stored in the storage unit 132 to the left by 3 bits according to the input shift number “3”, and the bit string overflowed by the shift (bit data b 2 , b 3 and b 4 ) are cyclically shifted to fill the empty part. Then, the storage unit 132, the left end of the data after cyclic shift processing (in this case, bit data b 2) and outputs the bit data in order from.
  • the output control unit 131 when the bit data is output while performing the cyclic shift, the output control unit 131 outputs the shift number to the storage unit 132 a predetermined number of times while changing the shift number.
  • the transmission device 10 and the reception device 20 in the communication system 1 are exemplified to be configured to be communicable by wired communication, but the present invention is not limited to this. Specifically, the transmission device 10 and the reception device 20 may be configured to be communicable by wireless communication.
  • storage part 132 was set as the aspect which exists in the interleave part 113, it is not limited to this, It is good also as an aspect provided inside the transmitter 10 and outside the interleave part 113. .
  • the output control unit 131 performs data output control on the storage unit 132.
  • Communication System 10 Communication Device (Transmitter) 20 Communication device (receiving device) 30 transmission path 112 encoding unit 113 interleaving unit 114 primary modulation unit 131 output control unit 132 storage unit

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

L'invention concerne un dispositif de communication (10) qui comporte les éléments suivants : une unité de stockage qui stocke des données de transmission; une unité de commande d'émission (131) qui commande l'émission des données de transmission stockées dans l'unité de stockage; et un moyen de transmission qui module et transmet des données émises à partir de l'unité de stockage. L'unité de commande d'émission (131) change l'ordre d'émission de données binaires dans les données de transmission stockées dans l'unité de stockage et a chaque donnée binaire émise un nombre de fois prescrit.
PCT/JP2012/076265 2011-11-04 2012-10-11 Dispositif de communication et procédé de fonctionnement d'un dispositif de communication WO2013065465A1 (fr)

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JP2011241934A JP2013098886A (ja) 2011-11-04 2011-11-04 通信装置および通信装置の動作方法
JP2011-241934 2011-11-04

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11298338A (ja) * 1998-04-07 1999-10-29 Sony Corp 送信装置及び送信方法
JP2003198386A (ja) * 2001-12-25 2003-07-11 Sony Corp インターリーブ装置及びインターリーブ方法、符号化装置及び符号化方法、並びに復号装置及び復号方法
JP2008199405A (ja) * 2007-02-14 2008-08-28 Matsushita Electric Ind Co Ltd 無線送信装置および無線送信方法
JP2008211752A (ja) * 2007-01-31 2008-09-11 Toshiba Corp 無線通信システム
JP2009033696A (ja) * 2006-11-02 2009-02-12 Panasonic Corp 送信方法、送信装置及び受信方法
WO2009066451A1 (fr) * 2007-11-21 2009-05-28 Panasonic Corporation Dispositif de communication sans fil, procédé de communication sans fil et système de communication sans fil

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0730523A (ja) * 1993-06-25 1995-01-31 Matsushita Electric Works Ltd データ通信方法
JP2003163960A (ja) * 2001-11-22 2003-06-06 Matsushita Electric Ind Co Ltd 無線通信システム及びデータ伝送方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11298338A (ja) * 1998-04-07 1999-10-29 Sony Corp 送信装置及び送信方法
JP2003198386A (ja) * 2001-12-25 2003-07-11 Sony Corp インターリーブ装置及びインターリーブ方法、符号化装置及び符号化方法、並びに復号装置及び復号方法
JP2009033696A (ja) * 2006-11-02 2009-02-12 Panasonic Corp 送信方法、送信装置及び受信方法
JP2008211752A (ja) * 2007-01-31 2008-09-11 Toshiba Corp 無線通信システム
JP2008199405A (ja) * 2007-02-14 2008-08-28 Matsushita Electric Ind Co Ltd 無線送信装置および無線送信方法
WO2009066451A1 (fr) * 2007-11-21 2009-05-28 Panasonic Corporation Dispositif de communication sans fil, procédé de communication sans fil et système de communication sans fil

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