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WO2013046579A1 - Dispositif de prise de vue à semi-conducteurs, son procédé de pilotage et dispositif de prise de vue - Google Patents

Dispositif de prise de vue à semi-conducteurs, son procédé de pilotage et dispositif de prise de vue Download PDF

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Publication number
WO2013046579A1
WO2013046579A1 PCT/JP2012/005824 JP2012005824W WO2013046579A1 WO 2013046579 A1 WO2013046579 A1 WO 2013046579A1 JP 2012005824 W JP2012005824 W JP 2012005824W WO 2013046579 A1 WO2013046579 A1 WO 2013046579A1
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Prior art keywords
signal
sample
imaging device
solid
pixel
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PCT/JP2012/005824
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English (en)
Japanese (ja)
Inventor
中川　琢磨
雅史 村上
洋士 久保
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パナソニック株式会社
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/618—Noise processing, e.g. detecting, correcting, reducing or removing noise for random or high-frequency noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present invention relates to a solid-state imaging device, a driving method thereof, and an imaging device including the solid-state imaging device, and more particularly, to a solid-state imaging device including a column circuit provided for each column.
  • MOS Metal Oxide Semiconductor
  • FIG. 23 is a block diagram showing a conventional solid-state imaging device disclosed in Patent Document 1. As shown in FIG.
  • the output circuits 6A and 6B described in the figure are provided on both sides of the vertical signal line 2 and have the same circuit configuration.
  • Each of the output circuits 6A and 6B reads and outputs the same pixel signal from the pixel 1A included in the pixel array unit 1.
  • the output circuits 6A and 6B include a CDS (correct double sampling) circuit that removes a variation component generated for each pixel column by taking the difference between the reset level and the signal level of each pixel.
  • Each of the output circuits 6A and 6B includes a clamp capacitor 61, a clamp switch 62, a sample hold switch 63, a sample hold capacitor 64, and an output selection switch 66.
  • the solid-state imaging device shown in FIG. 23 is provided in the subsequent stage of the output circuits 6A and 6B, selects a pixel signal for each pixel column, and outputs the selected pixel signal to the horizontal signal line 7. And 5B, and an output amplifier section 65.
  • the conventional technique needs to have the same output circuit on both sides of the vertical signal line, which leads to an increase in circuit scale.
  • the present invention has been made in view of the above problems, and provides a solid-state imaging device that reduces random noise without deteriorating imaging characteristics and without increasing the circuit scale, a driving method thereof, and an imaging device The purpose is to do.
  • a solid-state imaging device includes a plurality of pixel cells each having a light receiving element that generates a pixel signal corresponding to a light reception intensity and arranged in a matrix, A plurality of vertical signal lines that are arranged for each column and that output the pixel signals generated in a plurality of pixel cells arranged in the corresponding column; and a plurality of column circuits provided for each column, Each of the column circuits includes an analog signal processing circuit that generates a first signal by performing analog signal processing on the pixel signal of the vertical signal line arranged in the corresponding column, and for holding the first signal.
  • the first and second sample and hold capacitors, the first sample and hold switch for controlling the holding of the first signal in the first sample and hold capacitor according to the first control signal, and the first control signal are independent of each other.
  • an output selection circuit for outputting a first mixed signal obtained by mixing a part or all of the existing signal.
  • the solid-state imaging device holds the signal that has passed through the same analog signal processing circuit in the two sample hold capacitors.
  • the solid-state imaging device does not need to include two analog signal processing circuits as in the prior art, variations in gain or the like due to variations in these analog signal processing circuits can be suppressed.
  • the said solid-state imaging device can suppress the noise of a vertical line, it can suppress the deterioration of an imaging characteristic.
  • the solid-state imaging device can suppress an increase in circuit scale by using the same analog signal processing circuit.
  • the solid-state imaging device mixes two signals held in two sample hold capacitors. Thereby, the solid-state imaging device can reduce random noise.
  • the solid-state imaging device according to one embodiment of the present invention can reduce random noise without deteriorating imaging characteristics and without increasing the circuit scale.
  • the solid-state imaging device may hold the first signal corresponding to the pixel signal generated in the same pixel cell in the same period in the first and second sample and hold capacitors.
  • the solid-state imaging device may hold the first signal at different timings in time series to the first and second sample hold capacitors.
  • the solid-state imaging device can hold noise components that are uncorrelated with each other in time series. Therefore, the solid-state imaging device can reduce random noise by mixing the noise components.
  • the output selection circuit includes a first output selection switch connected to a subsequent stage of the first sample and hold capacitor, and a second output selection switch connected to a subsequent stage of the second sample and hold capacitor.
  • the imaging apparatus simultaneously turns on the first and second output selection switches, thereby causing the signal held in the first sample hold capacitor and the signal held in the second sample hold capacitor to May be mixed.
  • one of the source and the drain of the first and second output selection switches may be formed by a common diffusion region.
  • the analog signal processing circuit may include a CDS circuit for performing correlated double sampling processing.
  • the analog signal processing circuit may include an amplifier circuit that amplifies the pixel signal of the corresponding vertical signal line.
  • the solid-state imaging device can reduce the influence of noise generated at a later stage than the analog signal processing circuit, the effect of reducing random noise can be further increased.
  • the solid-state imaging device has the same timing for the first mode and the second sample and hold capacitor, and the first mode for holding the first signal at different timings in time series and the first and second sample and hold capacitors. And a second mode for holding the first signal.
  • the solid-state imaging device can switch between the first mode that prioritizes the reduction of random noise and the second mode that prioritizes the reading speed according to the imaging mode and the like.
  • the imaging device which concerns on 1 aspect of this invention is an imaging device provided with the said solid-state imaging device, Comprising: Each of these column circuits is further 3rd and 4th for hold
  • the output selection circuit further includes a signal held in the third sample and hold capacitor and the It is used to output a second mixed signal obtained by mixing a part or all of the signal held in the fourth sample-and-hold capacitor, and the image pickup device outputs the first mixed signal.
  • An analog-digital converter that converts the first mixed signal into a second digital signal, and a mixing unit that mixes the first digital signal and the second digital signal. .
  • the imaging device can further enhance the effect of reducing random noise by further mixing the signals converted into digital data.
  • the solid-state imaging device driving method includes a plurality of pixel cells each having a light-receiving element that generates a pixel signal corresponding to the received light intensity and arranged in a matrix.
  • the first and second sample and hold capacitors correspond to the pixel signal generated in the same period in the same pixel cell and generated by the same analog signal processing circuit at different timings.
  • a step of mixing the signal held in the first sample hold capacitor and the signal held in the second sample hold capacitor is a plurality of pixel cells each having a light-receiving element that generates a pixel signal corresponding to the received light intensity and arranged in a matrix.
  • the first and second sample and hold capacitors correspond to the pixel signal generated in the same period in the same pixel cell and generated by the same analog signal processing circuit at different timings.
  • a step of mixing the signal held in the first sample hold capacitor and the signal held in the second sample hold capacitor are examples of mixing the signal held in the first sample hold capacitor and the signal held in the second sample hold capacitor.
  • the driving method of the solid-state imaging device holds the signal that has passed through the same analog signal processing circuit in the two sample hold capacitors.
  • the driving method does not need to include two analog signal processing circuits as in the prior art, so that variations in gain and the like due to variations in these analog signal processing circuits can be suppressed.
  • the driving method can suppress a vertical noise, it can suppress the deterioration of an imaging characteristic.
  • the driving method can suppress an increase in circuit scale by using the same analog signal processing circuit.
  • the driving method mixes two signals held in two sample and hold capacitors. Thereby, the driving method can reduce random noise.
  • the solid-state imaging device driving method according to an embodiment of the present invention can reduce random noise without deteriorating imaging characteristics and without increasing the circuit scale.
  • the present invention can be realized not only as such a solid-state imaging device, but also as a driving method or a control method of a solid-state imaging device using characteristic means included in the solid-state imaging device as a step. It can also be realized as a program that causes a computer to execute typical steps. Needless to say, such a program can be distributed via a non-transitory computer-readable recording medium such as a CD-ROM and a transmission medium such as the Internet.
  • the present invention can be realized as a semiconductor integrated circuit (LSI) that realizes part or all of the functions of such a solid-state imaging device, or can be realized as an imaging device including such a solid-state imaging device.
  • LSI semiconductor integrated circuit
  • the present invention can provide a solid-state imaging device, a driving method thereof, and an imaging device that reduce random noise without deteriorating imaging characteristics and without increasing the circuit scale.
  • FIG. 1 is a block diagram showing the configuration of the solid-state imaging device according to Embodiment 1 of the present invention.
  • FIG. 2 is a circuit diagram showing an example of a pixel cell and a current source circuit according to Embodiment 1 of the present invention.
  • FIG. 3 is a circuit diagram showing another example of the pixel cell according to Embodiment 1 of the present invention.
  • FIG. 4 is a circuit diagram showing an example of the column circuit according to the first embodiment of the present invention.
  • FIG. 5 is a circuit diagram showing an example of the column selection circuit and its peripheral circuits according to Embodiment 1 of the present invention.
  • FIG. 6 is a timing chart of the column selection circuit according to the first embodiment of the present invention.
  • FIG. 1 is a block diagram showing the configuration of the solid-state imaging device according to Embodiment 1 of the present invention.
  • FIG. 2 is a circuit diagram showing an example of a pixel cell and a current source circuit according to Embodiment 1 of the present invention.
  • FIG. 7 is an example of a timing chart of the pixel cell and the column signal processing circuit according to Embodiment 1 of the present invention.
  • FIG. 8 is an example of a timing chart of the pixel cell and the column signal processing circuit according to Embodiment 1 of the present invention.
  • FIG. 9 is an example of a timing chart of the pixel cell and the column signal processing circuit according to Embodiment 1 of the present invention.
  • FIG. 10 is a diagram showing a layout of the output selection switch according to the first embodiment of the present invention.
  • FIG. 11 is a block diagram illustrating a configuration of a solid-state imaging device according to a modification of the first embodiment of the present invention.
  • FIG. 12 is a block diagram showing a configuration of the solid-state imaging apparatus according to Embodiment 2 of the present invention.
  • FIG. 13 is a circuit diagram showing an example of a column circuit according to the second embodiment of the present invention.
  • FIG. 14 is a circuit diagram showing an example of an inverting amplifier according to Embodiment 2 of the present invention.
  • FIG. 15 is an example of a timing chart of the pixel cell, the column amplifier circuit, and the column signal processing circuit according to Embodiment 2 of the present invention.
  • FIG. 16 is a block diagram showing a configuration of an imaging apparatus according to Embodiment 3 of the present invention.
  • FIG. 17 is a circuit diagram showing an example of a column circuit according to Embodiment 3 of the present invention.
  • FIG. 18 is a circuit diagram showing an example of the column selection circuit and its peripheral circuit according to Embodiment 3 of the present invention.
  • FIG. 19 is a timing chart of the column selection circuit according to the third embodiment of the present invention.
  • FIG. 20 is an example of a timing chart of the pixel cell and the column signal processing circuit according to Embodiment 3 of the present invention.
  • FIG. 21 is a block diagram showing a configuration of a modified example of the imaging apparatus according to Embodiment 3 of the present invention.
  • FIG. 22 is a block diagram showing a configuration of an imaging apparatus according to Embodiment 4 of the present invention.
  • FIG. 23 is a circuit diagram showing a configuration of a conventional solid-state imaging device.
  • Embodiment 1 The solid-state imaging device according to Embodiment 1 of the present invention holds signals that have passed through the same analog signal processing circuit in two sample-and-hold capacitors. Thereby, since the solid-state imaging device does not need to include two analog signal processing circuits as in the prior art, variations in gain or the like due to variations in these analog signal processing circuits can be suppressed. Thereby, since the noise of a vertical line can be suppressed, the deterioration of imaging characteristics can be suppressed. Furthermore, an increase in circuit scale can be suppressed. In addition, the solid-state imaging device mixes two signals held in two sample hold capacitors. Thereby, the solid-state imaging device can reduce random noise.
  • FIG. 1 is a diagram showing an overall configuration of a solid-state imaging device 100 according to Embodiment 1 of the present invention.
  • a solid-state imaging device 100 illustrated in FIG. 1 includes a pixel array 103 in which a plurality of pixel cells (unit cells) 102 serving as repeating units are arranged in an array, a row selection circuit 104, a plurality of vertical signal lines 105, and a current source.
  • a circuit 106, a column signal processing circuit 107, a column selection circuit 108, an output amplifier 109, and a timing control unit 114 are provided.
  • the plurality of pixel cells 102 are arranged in a matrix.
  • Each pixel cell 102 has a light receiving element (photodiode 201: see FIG. 2) that generates a pixel signal corresponding to the received light intensity.
  • the pixel cell 102 has a function of amplifying a pixel signal generated by photoelectric conversion by the photodiode 201 and outputting the amplified pixel signal to the vertical signal line 105.
  • the configuration of the pixel cell 102 will be described in detail later.
  • a plurality of vertical signal lines 105 are provided for each column. To each vertical signal line 105, a pixel signal generated in the plurality of pixel cells 102 arranged in the corresponding column is output. Further, the vertical signal line 105 has a function of transferring the pixel signal output from the pixel cell 102 to the current source circuit 106.
  • the current source circuit 106 includes a current source transistor 207 (see FIG. 2).
  • the current source transistor 207 forms a source follower circuit for amplifying the pixel signal generated in each pixel cell 102 of the pixel array 103 for each column.
  • the row selection circuit 104 has a function of controlling the reset operation, charge accumulation operation, and readout operation of the pixel cell 102 in units of rows.
  • the column signal processing circuit 107 includes a column circuit 115 provided for each column.
  • Each column circuit 115 includes a plurality of sample and hold capacitors that hold pixel signals.
  • the column circuit 115 includes a CDS (correct double sampling) circuit that removes a variation component for each pixel column by taking a difference between the reset level and the signal level of each pixel.
  • the column circuit 115 has a configuration for reducing random noise, and the configuration and function thereof will be described in detail later.
  • the column selection circuit 108 has a function of sequentially selecting the pixel signals of each column from the pixel signals for one row held in the column signal processing circuit 107 and reading the selected pixel signals to the output amplifier 109.
  • the timing control unit 114 controls the row selection circuit 104, the current source circuit 106, the column signal processing circuit 107, and the column selection circuit 108.
  • FIG. 2 is a circuit diagram showing an example of the configuration of the pixel cell 102.
  • the pixel cell 102 shown in FIG. 2 includes four transistors.
  • the pixel cell 102 includes at least one photodiode (PD) 201 that is a light receiving element that generates a signal charge corresponding to the amount of received light by photoelectric conversion. Further, the pixel cell 102 includes a floating diffusion (FD) 206 that converts the signal charge generated by the PD 201 into a signal voltage, a transfer transistor 202 that transfers the signal charge generated by the photodiode 201 to the FD 206, and a signal of the FD 206.
  • FD floating diffusion
  • An amplifying transistor 203 that amplifies the voltage, a reset transistor 204 for resetting the signal voltage of the FD 206, and a selection transistor 205 that selects a pixel for each pixel row and outputs a pixel signal to the vertical signal line 105 are provided. .
  • the transfer pulse signal ⁇ TRAN, the selection pulse signal ⁇ SEL, and the reset pulse signal ⁇ RST are supplied from the row selection circuit 104 to the transfer transistor 202, the selection transistor 205, and the reset transistor 204. Thereby, the charge accumulation operation, the read operation, and the reset operation are controlled.
  • This reduced voltage is amplified by a source follower circuit including an amplification transistor 203 of the pixel cell 102 and a current source transistor 207 provided in the current source circuit 106 for each vertical signal line 105. Further, the row selection circuit 104 applies the selection pulse signal ⁇ SEL to the selection transistor 205, whereby the pixel signal is output to the vertical signal line 105 for each pixel column.
  • the reset pulse signal ⁇ RST, the transfer pulse signal ⁇ TRAN, and the selection pulse signal ⁇ SEL are supplied to each pixel cell 102 from the row selection circuit 104 illustrated in FIG.
  • the pixel cell 102A shown in FIG. 3 can be used as the pixel cell 102 of the solid-state imaging device according to the present embodiment instead of the configuration shown in FIG.
  • a pixel cell 102A illustrated in FIG. 3 includes an amplification transistor 213, a reset transistor 214, a selection transistor 215 (address transistor), a photoelectric conversion element (photoelectric conversion film) 211, and a wiring that connects them.
  • the pixel cell 102A generates a pixel signal corresponding to incident light.
  • the photoelectric conversion element 211 converts incident light into signal charges.
  • the floating diffusion 216 is connected to the photoelectric conversion element 211 and accumulates signal charges generated by the photoelectric conversion element 211.
  • the photoelectric conversion element 211 (floating diffusion 216) is connected to the gate of the amplification transistor 213, and the power supply wiring 221 extending in the vertical direction is connected to one of the source and the drain.
  • a reset signal line 222 extending in the horizontal direction is connected to the gate of the reset transistor 214, a reset voltage line 223 extending in the vertical direction is connected to one of the source and the drain, and the other of the source and the drain is connected to the other.
  • a photoelectric conversion element 211 (floating diffusion 216) is connected.
  • An address signal line 224 extending in the horizontal direction is connected to the gate of the selection transistor 215, a vertical signal line 105 extending in the vertical direction is connected to one of the source and the drain, and an amplification transistor 213 is connected to the other of the source and the drain. The other of the source and drain is connected.
  • FIG. 4 is a circuit diagram showing an example of the configuration of the column circuit 115 according to the present embodiment.
  • the column circuit 115 is a circuit provided for each column included in the column signal processing circuit 107.
  • the column circuit 115 includes a CDS circuit 116 and a sample hold circuit 117.
  • the CDS circuit 116 is a circuit for performing CDS processing.
  • the CDS circuit 116 is an analog signal processing circuit that generates a first signal by performing analog signal processing on the pixel signal of the corresponding vertical signal line 105.
  • the CDS circuit 116 includes a clamp capacitor 301 and a clamp switch 304.
  • the sample hold circuit 117 samples and holds the pixel signal (first signal) that has passed through the CDS circuit 116.
  • the sample and hold circuit 117 includes sample and hold capacitors 302 and 303 for holding the first signal, sample and hold switches 306 and 307, and output selection switches 308 and 309.
  • a pixel reset signal Vrst and a pixel signal Vpix amplified by a source follower circuit including the amplification transistor 203 and the current source transistor 207 of the pixel cell 102 are sequentially input to the clamp capacitor 301.
  • the clamp switch 304 is controlled by a clamp control signal ⁇ CLIP.
  • the clamp control signal ⁇ CLIP is set to the H level.
  • the terminal voltage 305 on the opposite side (output side) of the clamp capacitor 301 from the vertical signal line 105 is set to the voltage VCLIP.
  • the clamp control signal ⁇ CLIP is set to the low level (hereinafter referred to as L level)
  • the terminal voltage 305 of the clamp capacitor 301 is clamped to the voltage VCLIP.
  • the pixel signal Vpix is output to the vertical signal line 105
  • the voltage of the vertical signal line 105 varies from the time when the pixel reset signal Vrst is output.
  • the terminal voltage 305 on the output side of the clamp capacitor 301 varies from the voltage VCLIP.
  • the column circuit 115 is provided with two sample hold capacitors 302 and 303 and two sample hold switches 306 and 307 for one clamp capacitor 301.
  • Sample hold switches 306 and 307 are independently controlled by sample hold control signals ⁇ SH1 and ⁇ SH2.
  • the sample hold switch 306 controls the holding of the first signal in the sample hold capacitor 302.
  • the sample hold switch 307 controls the holding of the first signal in the sample hold capacitor 303.
  • the terminal voltage 305 on the output side of the clamp capacitor 301 varies according to the pixel signal Vpix.
  • the sample hold control signals ⁇ SH1 and ⁇ SH2 are set to the L level, the signal charge amounts held in the sample hold capacitors 302 and 303 are determined.
  • the output selection switches 308 and 309 are output selection circuits for outputting a first mixed signal obtained by mixing some or all of the two signals held in the sample hold capacitors 303 and 304.
  • the output selection switch 308 is provided after the sample hold capacitor 302.
  • the output selection switch 309 is provided at the subsequent stage of the sample hold capacitor 303.
  • the solid-state imaging device 100 mixes the two signals held in the sample hold capacitors 302 and 303 by turning on the output selection switches 308 and 309 at the same time, and outputs the mixed signals to the horizontal signal line 111.
  • the output selection switches 308 and 309 are controlled by an output control signal ⁇ HSW.
  • the output control signal ⁇ HSW By setting the output control signal ⁇ HSW to the H level, the signals held in the sample hold capacitors 302 and 303 are mixed and output to the horizontal signal line 111.
  • the same pixel signal can be held in two different sample and hold capacitors 302 and 303. Further, by simultaneously turning on the output selection switches 308 and 309, the signals held in the sample hold capacitors 302 and 303 can be mixed and read out to the horizontal signal line 111.
  • the same pixel signal is a pixel signal generated in the same pixel cell 102 in the same period. More specifically, the same pixel signal is a pixel signal corresponding to a signal charge generated in the same pixel cell 102 in the same period. As will be described later, the timing at which the same pixel signal is held in the sample-and-hold capacitors 302 and 303 may be different or the same.
  • FIG. 5 is a diagram showing an example of the column selection circuit 108 for controlling the output control signal ⁇ HSW and its peripheral configuration.
  • FIG. 6 is a diagram illustrating an example of timing when the output control signal ⁇ HSW is controlled for each pixel column from the column selection circuit 108.
  • the signals held in two different sample hold capacitors 302 and 303 provided for each pixel column are mixed by setting the output control signal ⁇ HSW to the H level.
  • the data are sequentially read out to the horizontal signal line 111.
  • the signal read to the horizontal signal line 111 is amplified by the output amplifier 109, and the amplified signal is sequentially output to the outside of the solid-state imaging device 100.
  • the column signal processing circuit 107 in this embodiment includes two sets of sample hold capacitors and sample hold switches for holding the same pixel signal, but may include two or more sets. As the number of sets of sample hold capacitors and sample hold switches increases, the number of times that uncorrelated noise can be held in time series increases, and the effect of reducing random noise increases. On the other hand, since there are restrictions on the pixel pitch width, an arrangement of several sets is preferable.
  • FIG. 7 is a diagram illustrating an example of the timing of each control signal when the same pixel signal is held in two different sample hold capacitors 302 and 303 at different timings.
  • the transfer pulse signal ⁇ TRAN is at L level
  • the transfer transistor 202 is in an off state
  • the reset pulse signal ⁇ RST is at L level
  • the reset transistor 204 is in an off state.
  • the reset state of the voltage Vfd is maintained.
  • the selection pulse signal ⁇ SEL is at the H level
  • the selection transistor 205 is in the on state.
  • the amplification transistor 203 and the current source transistor 207 constitute a source follower circuit. Therefore, when the threshold voltage of the amplification transistor 203 is VTH1, the voltage Vsf of the vertical signal line 105 is as shown in (Expression 1).
  • the voltage Vsf is input to the clamp capacitor 301 of the column signal processing circuit 107 as a pixel reset signal.
  • V ⁇ is omitted here.
  • Vsf Vfdrst ⁇ VTH1 (Formula 1)
  • the clamp control signal ⁇ CLIP and the sample hold control signals ⁇ SH1 and ⁇ SH2 are each at the H level, the terminal voltage 305 on the output side of the clamp capacitor 301, the voltage Vsh1 of the sample hold capacitor 302, and the sample hold capacitor 303 The voltage Vsh2 is set to the voltage VCLIP.
  • Vfd Vfdrst ⁇ Vfdsig (Formula 2)
  • Vsf Vfdrst ⁇ Vfdsig ⁇ VTH1 (Formula 3)
  • the differential signal Vfdsig includes a signal component Vsig and a noise component Vn, and can be expressed as (Equation 4).
  • the noise component Vn here indicates a random noise component having irregular fluctuation in a time series.
  • Vfdsig Vsig + Vn (Formula 4)
  • the signal charge is held in the sample and hold capacitor 302 by setting the sample and hold control signal ⁇ SH1 to the L level.
  • the voltage Vsh1 of the sample-and-hold capacitor 302 is expressed by (Equation 6) from the charge conservation law.
  • Vn1 represents the noise component Vn at timing t5.
  • Vsh1 VCLIP ⁇ ⁇ x / (x + 2) ⁇ Vsig + x / (x + 2) ⁇ Vn1 ⁇ (Formula 6)
  • the signal held in the sample hold capacitor 302 includes a signal component of x / (x + 2) ⁇ Vsig and a noise component of x / (x + 2) ⁇ Vn1.
  • the signal charge is held in the sample hold capacitor 303 by setting the sample hold control signal ⁇ SH2 to the L level. Since the sample hold control signal ⁇ SH1 is already at the L level at the timing t6, the voltage Vsh2 of the sample hold capacitor 303 is expressed by (Equation 7) from the charge conservation law.
  • Vn2 represents the noise component Vn at timing t6.
  • Vsh2 VCLIP ⁇ [x / (x + 2) ⁇ Vsig + x / (x + 1) ⁇ Vn2-x / ⁇ (x + 1) (x + 2) ⁇ ⁇ Vn1] (Expression 7)
  • the signal held in the sample hold capacitor 303 includes a signal component of x / (x + 2) ⁇ Vsig and a noise component of x / (x + 1) ⁇ Vn2 ⁇ x / ⁇ (x + 1) (x + 2) ⁇ ⁇ Vn1.
  • Vsig_sh1 x / (x + 2) ⁇ Vsig + x / (x + 2) ⁇ Vn1 (Equation 8)
  • Vsig_sh2 x / (x + 2) ⁇ Vsig + x / (x + 1) ⁇ Vn2-x / ⁇ (x + 1) (x + 2) ⁇ ⁇ Vn1 (Equation 9)
  • the signals Vsig_sh1 and Vsig_sh2 held in the two sample hold capacitors 302 and 303 provided for each pixel column are obtained by setting the output control signal ⁇ HSW to the H level. Are mixed and then sequentially read out to the horizontal signal line 111.
  • the signal read out to the horizontal signal line 111 can be expressed as (Expression 10) from (Expression 8) and (Expression 9).
  • Vsig_sh1 + Vsig_sh2 2x / (x + 2) ⁇ Vsig + x / (x + 1) ⁇ Vn2 + x 2 / ⁇ (x + 1) (x + 2) ⁇ ⁇ Vn1 (Equation 10)
  • the SNR Signal Noise Ratio
  • SNR Signal Noise Ratio
  • FIG. 8 is a diagram illustrating an example of the timing of each control signal when the same pixel signal is held in two different sample hold capacitors 302 and 303 at the same timing.
  • the difference from FIG. 7 is that the sample hold control signals ⁇ SH1 and ⁇ SH2 are simultaneously set to the L level at the timing t5.
  • the same noise component is held in the sample hold capacitors 302 and 303 at the timing t5. Therefore, the signals Vsig_sh1 and Vsig_sh2 are as shown in (Equation 14).
  • Vsig_sh1 + Vsig_sh2 2x / (x + 2) ⁇ Vsig + 2x / (x + 2) ⁇ Vn (Expression 15)
  • each control signal supplied to the pixel cell 102 and the column signal processing circuit 107 may be as shown in FIG. Also in this case, since the same pixel signal can be held in the sample hold capacitors 302 and 303 at different timings, random noise can be reduced similarly to the timing shown in FIG.
  • the difference between the timing shown in FIG. 9 and the timing shown in FIG. 7 is that when the sample hold control signal ⁇ SH1 is at the H level, as shown at timings t4 ′ to t5 ′, the sample hold control signal ⁇ SH2 is set at the L level. As in t6 ′ to t7 ′, when the sample hold control signal ⁇ SH1 is at the L level, the sample hold control signal ⁇ SH2 is at the H level.
  • the signal charge is held in the sample hold capacitor 302 by setting the sample hold control signal ⁇ SH1 to the L level.
  • the sample hold control signal ⁇ SH2 is at the L level, and the signal Vsig_sh1 is expressed by (Equation 19) from the law of conservation of charge.
  • Vsig_sh1 x / (x + 1) ⁇ Vsig + x / (x + 2) ⁇ Vn1 (Equation 19)
  • the signal hold is held in the sample hold capacitor 303 by setting the sample hold control signal ⁇ SH2 to the L level.
  • the sample hold control signal ⁇ SH1 is at the H level, and the signal Vsig_sh2 is expressed by (Equation 20) from the law of conservation of charge.
  • Vsig_sh2 ⁇ x / (x + 1) ⁇ 2 ⁇ Vsig ⁇ x / (x + 1) 2 ⁇ Vn1 + x / (x + 1) ⁇ Vn2 (Equation 20)
  • the signal mixed in the horizontal signal line 111 is as shown in (Expression 21).
  • Vsig_sh1 + Vsig_sh2 ⁇ x (2x + 1) / (x + 1) 2 ⁇ ⁇ Vsig + ⁇ x / (x + 1) ⁇ 2 ⁇ Vn1 + x / (x + 1) ⁇ Vn2 (Equation 21)
  • the signal component S_diff2 and the noise component N_diff2 can be expressed as (Equation 22) and (Equation 23), respectively, from (Equation 21).
  • the column signal processing circuit 107 holds the uncorrelated noise components included in the same pixel signal in time series, and reduces the random noise by mixing the held signals. can do.
  • each control signal supplied to the pixel cell 102 and the column signal processing circuit 107 is the timing shown in FIGS. 7 and 9 as long as the uncorrelated noise components can be held in different sample hold capacitors in time series. It is not limited to what is shown.
  • the column signal processing circuit 107 since the column signal processing circuit 107 according to the present embodiment reads the same pixel signal using the same clamp capacitor, it is possible to reduce the capacitance variation compared to the conventional technique. Thereby, the solid-state imaging device 100 according to the present embodiment can effectively reduce random noise without generating vertical line noise.
  • the column signal processing circuit 107 since the column signal processing circuit 107 according to the present embodiment does not need to include a plurality of clamp capacitors in order to read out the same pixel signal, the circuit scale can be reduced as compared with the prior art.
  • the output selection switches 308 and 309 may be finger type transistors in which one of the source terminal and the drain terminal is formed by a common diffusion region as shown in FIG. By doing so, the terminal region for mixing signals can be made common, so that the effect of reducing the circuit scale can be further enhanced.
  • the output selection switches 308 and 309 are connected to the horizontal signal line 111 .
  • the output selection switches 308 and 309 are A / D converted for each column. It is good also as a structure connected to column ADC (Analog Digital Converter) which performs. Even with such a configuration, an equivalent random noise reduction effect can be obtained.
  • FIG. 11 is a block diagram illustrating a configuration of a solid-state imaging device 600 including a column ADC.
  • a solid-state imaging device 600 illustrated in FIG. 11 includes a column ADC 118 instead of the column selection circuit 108 in the configuration of the solid-state imaging device 100 illustrated in FIG.
  • the column ADC is arranged at the subsequent stage of the column signal processing circuit 107 and performs A / D conversion for each column. Specifically, as described above, the same pixel signal is mixed in the output selection switches 308 and 309 of the column circuit 115 provided for each column included in the column signal processing circuit 107.
  • the column ADC 118 has a function of converting pixel signals obtained by mixing into digital data for each column.
  • the solid-state imaging device 600 can convert the same pixel signal mixed in the column signal processing circuit 107 into digital data in parallel for each column, thereby improving the reading speed and random noise. Can be reduced.
  • the pixel cell 102 includes four transistors. However, the pixel cell 102 may not include the selection transistor 205.
  • the pixel cell 102 has a so-called 1-pixel 1-cell structure having one PD 201, transfer transistor 202, FD 206, reset transistor 204, and amplification transistor 203.
  • the pixel cell 102 includes a plurality of PDs 201, and may have a so-called multi-pixel 1-cell structure in which any one or all of the FD 206, the reset transistor 204, and the amplification transistor 203 are shared in the unit cell.
  • the solid-state imaging device 100 may be a so-called front-illuminated image sensor (front-illuminated solid-state imaging device) or a so-called back-illuminated image sensor (back-illuminated solid-state imaging device). ).
  • the PD 201 is formed on the surface of the semiconductor substrate, that is, on the same side as the surface on which the gate terminal and the wiring of the transistor are formed.
  • the PD 201 is formed on the back surface side of the semiconductor substrate, that is, on the back surface side with respect to the surface on which the transistor gate terminals and wirings are formed.
  • each transistor included in the solid-state imaging device 100 according to the present embodiment is not limited to the conductivity type described in the present embodiment.
  • a transistor having a reverse conductivity type may be used as long as it has the function and effect of each transistor described in this embodiment.
  • the solid-state imaging device 100 corresponds to the pixel signal generated in the same period in the same pixel cell, and the first signal generated by the same analog signal processing circuit at different timings.
  • the first and second sample hold capacitors are held.
  • the solid-state imaging device 100 mixes the signal held in the first sample hold capacitor and the signal held in the second sample hold capacitor.
  • the solid-state imaging device 100 can reduce random noise without deteriorating imaging characteristics due to vertical noise or the like and without causing an increase in circuit scale.
  • the solid-state imaging device 100 can realize an improvement in image quality.
  • Embodiment 2 a solid-state imaging device according to Embodiment 2 of the present invention will be described in detail with reference to the drawings. In the following description, the description will focus on the differences from the first embodiment of the present invention.
  • FIG. 12 is a diagram showing an overall configuration of a solid-state imaging device 200 according to the second embodiment of the present invention.
  • a solid-state imaging device 200 illustrated in FIG. 12 includes a column amplifier circuit 110 disposed between the current source circuit 106 and the column signal processing circuit 107 in addition to the configuration of the solid-state imaging device 100 illustrated in FIG. Other configurations are the same as those of the solid-state imaging device 100.
  • the column amplifier circuit 110 has a function of further amplifying the pixel signal of each column amplified by the source follower circuit including the amplification transistor 203 and the current source transistor 207.
  • the column signal processing circuit 107 holds uncorrelated noise components included in the same pixel signal in time series, and mixes the held signals to reduce random noise.
  • a column amplifier circuit 110 is provided in front of the column signal processing circuit 107. Then, the column amplifier circuit 110 amplifies the pixel signal (both signal component and noise component) of the vertical signal line 105, so that the influence of noise generated in the subsequent stage from the column amplifier circuit 110 can be reduced. Thereby, the random noise reduction effect in the column signal processing circuit 107 can be further enhanced.
  • FIG. 13 is a circuit diagram showing an example of the configuration of the column circuit 115A according to the present embodiment.
  • the column circuit 115A includes a column amplifier 110A, a CDS circuit 116, and a sample hold circuit 117.
  • the column amplifier 110 ⁇ / b> A is a circuit for one column included in the column amplifier circuit 110.
  • the CDS circuit 116 and the sample hold circuit 117 are circuits for one column included in the column signal processing circuit 107, and have the same configuration as shown in FIG.
  • the column amplifier 110A and the CDS circuit 116 correspond to an analog signal processing circuit that generates a first signal by performing analog signal processing on the pixel signal of the corresponding vertical signal line 105.
  • the column amplifier 110A includes an amplifier input capacitor 401, amplifier feedback capacitors 402 and 405, an amplifier reset switch 403, an inverting amplifier 404, and an amplifier gain changeover switch 406.
  • the inverting amplifier 404 is an amplification circuit that amplifies the pixel signal of the corresponding vertical signal line 105.
  • FIG. 14 is a diagram illustrating an example of the inverting amplifier 404.
  • the inverting amplifier 404 illustrated in FIG. 14 is a common source amplifier including an NMOS transistor and a PMOS transistor. This is the simplest circuit example of the inverting amplifier 404. In general, a cascode is added to this circuit configuration in order to increase the gain. Further, the inverting amplifier 404 may take the configuration of a differential transistor, and is not limited to the configuration of FIG.
  • the amplifier reset switch 403 When reading out the pixel reset signal, the amplifier reset switch 403 is turned on by setting the amplifier reset control signal ⁇ AMPCL to the H level. The pixel reset signal is read with the reset voltage clamped in this way. Thereafter, the amplifier reset switch 403 is turned off by setting the amplifier reset control signal ⁇ AMPCL to the L level, and then the pixel signal is read out.
  • the amplifier gain is determined by these capacitance ratios. That is, when the amplifier gain switching control signal ⁇ CGSW is at the H level, the amplifier gain is set to a low gain setting C2 / (C3 + C4), and when the amplifier gain switching control signal ⁇ CGSW is at the L level, the amplifier gain is set to C2 / C3. Gain setting.
  • the column amplifier circuit 110 switches the gain in two stages, but may have a switching function of two or more stages.
  • the pixel signal is amplified by the column amplifier circuit 110 in accordance with the amplifier gain, and the amplified pixel signal is output to the column signal processing circuit 107 in the subsequent stage.
  • FIG. 15 is a diagram illustrating an example of the timing of each control signal in the solid-state imaging device 200.
  • the voltage Vfd of the FD 206 is initialized to the FD reset voltage Vfdrst.
  • the voltage Vsf of the vertical signal line 105 is as shown in (Equation 1) above. This voltage Vsf is input to the column amplifier circuit 110 as a pixel reset signal.
  • the signal charge accumulated in the PD 201 is transferred to the FD 206 according to the amount of light, and the voltage Vfd decreases by the voltage Vfdsig corresponding to this signal charge amount.
  • the voltage Vfdsig is as shown in (Equation 2) shown in the first embodiment.
  • the voltage Vsf of the vertical signal line 105 is as shown in (Equation 3) and is input to the amplifier input capacitor 401 of the column amplifier circuit 110.
  • the amplifier reset control signal ⁇ AMPCL is at the L level
  • the signal input to the amplifier input capacitor 401 is inverted and amplified by the column amplifier circuit 110 according to the amplifier gain.
  • the output voltage Vca of the column amplifier circuit 110 at this time is as shown in (Equation 25).
  • A represents the gain of the column amplifier circuit 110
  • Vcasig represents Vsig multiplied by the gain of the column amplifier circuit 110.
  • the clamp control signal ⁇ CLIP is at the L level
  • the terminal voltage 305 on the output side of the clamp capacitor 301, the voltage Vsh1 of the sample hold capacitor 302, and the voltage Vsh2 of the sample hold capacitor 303 correspond to the voltage increase Vcasig of the output voltage Vca. And rises from the voltage VCLIP.
  • Vcasig includes a signal component Vsig ′ and a noise component Vn ′, and can be expressed as (Equation 26).
  • the noise component Vn ′ indicates a random noise component having irregular fluctuation in a time series.
  • Vcasig Vsig '+ Vn' (Equation 26)
  • the signal charge is held in the sample and hold capacitor 302 by setting the sample and hold control signal ⁇ SH1 to the L level.
  • the voltage Vsh1 of the sample-and-hold capacitor 302 is represented by (Equation 28) from the law of conservation of charge.
  • Vn1 ' represents a noise component Vn' at timing t5.
  • Vsh1 VCLIP + ⁇ x / (x + 2) ⁇ Vsig ′ + x / (x + 2) ⁇ Vn1 ′ ⁇ (Equation 28)
  • the signal held in the sample hold capacitor 302 includes a signal component of x / (x + 2) ⁇ Vsig ′ and a noise component of x / (x + 2) ⁇ Vn1 ′.
  • the signal charge is held in the sample hold capacitor 303 by setting the sample hold control signal ⁇ SH2 to the L level.
  • the sample and hold control signal ⁇ SH1 is already at the L level, and the voltage Vsh2 of the sample and hold capacitor 303 is expressed by (Equation 29) from the charge conservation law.
  • Vn2 ' represents a noise component Vn' at timing t6.
  • Vsh2 VCLIP + [x / (x + 2) ⁇ Vsig ′ + x / (x + 1) ⁇ Vn2′ ⁇ x / ⁇ (x + 1) (x + 2) ⁇ ⁇ Vn1 ′] (Equation 29)
  • the signal held in the sample-and-hold capacitor 303 includes a signal component of x / (x + 2) ⁇ Vsig ′ and x / (x + 1) ⁇ Vn2′ ⁇ x / ⁇ (x + 1) (x + 2) ⁇ ⁇ Vn1 ′. Noise component.
  • the signals held in the sample hold capacitors 302 and 303 are Vsig_sh1 and Vsig_sh2, the signals Vsig_sh1 and Vsig_sh2 are expressed as (Equation 30) and (Equation 31) from (Equation 28) and (Equation 29).
  • Vsig_sh1 x / (x + 2) ⁇ Vsig ′ + x / (x + 2) ⁇ Vn1 ′ (Equation 30)
  • Vsig_sh2 x / (x + 2) ⁇ Vsig ′ + x / (x + 1) ⁇ Vn2′ ⁇ x / ⁇ (x + 1) (x + 2) ⁇ ⁇ Vn1 ′ (Formula 31)
  • the signals Vsig_sh1 and Vsig_sh2 held in the two sample hold capacitors 302 and 303 provided for each pixel column are mixed and then sequentially read out to the horizontal signal line 111 by setting the output control signal ⁇ HSW to the H level. It is.
  • the signal read out to the horizontal signal line 111 can be expressed as (Expression 32) from (Expression 30) and (Expression 31).
  • Vsig_sh1 + Vsig_sh2 2x / (x + 2) ⁇ Vsig ′ + x / (x + 1) ⁇ Vn2 ′ + x 2 / ⁇ (x + 1) (x + 2) ⁇ ⁇ Vn1 ′ (Expression 32)
  • the SNR between the case where the same pixel signal is held in the sample hold capacitors 302 and 303 at different timings and the case where the same pixel signals are held at the same timing are compared.
  • the signal component is S_diff ′ and the noise component is N_diff ′
  • the signal component S_diff ′ and the noise component are N_diff ′ from (Equation 32). They can be expressed as (Equation 33) and (Equation 34), respectively.
  • the signal component is S_same ′ and the noise component is N_same ′.
  • the SNR Can be expressed as (Equation 36).
  • the SNR is ⁇ [2 (x + 1) 2 / ⁇ (x + 1) 2 +1 ⁇ ] compared to the case where the same pixel signals are held at the same timing.
  • the column amplifier circuit 110 in the previous stage of the column signal processing circuit 107, the pixel signal (both signal component and noise component) of the vertical signal line 105 can be amplified. As a result, the influence of noise generated at a stage subsequent to the column amplifier circuit 110 can be reduced, so that the random noise reduction effect in the column signal processing circuit 107 can be further enhanced.
  • each control signal supplied to the pixel cell 102, the column amplifier circuit 110, and the column signal processing circuit 107 is as long as it can hold uncorrelated noise components in different sample and hold capacitors in time series. It is not limited to what was shown by 15.
  • the gain setting of the column amplifier circuit 110 is either a low gain setting when the amplifier gain switching control signal ⁇ CGSW is at an H level or a high gain setting when the amplifier gain switching control signal ⁇ CGSW is at an L level. Also good.
  • the column amplifier circuit 110 is set to a high gain setting when imaging a low-illuminance subject, and the column amplifier circuit 110 is set to a low gain setting when imaging a medium-high illuminance subject.
  • random noise has a large effect on image quality when imaging low-light subjects. For this reason, when the column amplifier circuit 110 is set to a high gain, the same pixel signal is held in the sample hold capacitors 302 and 303 at different timings. When the column amplifier circuit 110 is set to a low gain, the same pixel signal is The operation may be switched according to the imaging mode so that the sample hold capacitors 302 and 303 are held at the same timing. Random noise can be reduced by operating the same pixel signal in the sample hold capacitors 302 and 303 so as to be held at different timings.
  • the same pixel signal is operated so as to be held in the sample hold capacitors 302 and 303 at the same timing, the period of the timings t5 to t6 shown in FIG. 15 can be reduced and the reading speed can be improved. .
  • Embodiment 3 a solid-state imaging device according to Embodiment 3 of the present invention and an imaging device (camera) incorporating the solid-state imaging device will be described in detail with reference to the drawings.
  • FIG. 16 is a block diagram showing a configuration of the imaging apparatus according to the present embodiment.
  • This imaging device includes a solid-state imaging device 300, ADCs (Analog Digital Converters) 112A and 112B, and DSPs (Digital Signal Processors) 113 arranged in the subsequent stage.
  • the ADCs 112 ⁇ / b> A and 112 ⁇ / b> B and the DSP 113 are formed as separate ICs from the solid-state imaging device 300.
  • the solid-state imaging device 300 is different from the solid-state imaging device 100 described in Embodiment 1 in the configuration of the column signal processing circuit 107A and the column selection circuit 108A.
  • the solid-state imaging device 300 includes two output amplifiers 109A and 109B.
  • the two output amplifiers 109A and 109B each output the same pixel signal.
  • the ADC 112A is an analog-digital converter that converts the pixel signal (first mixed signal) output from the output amplifier 109A into digital data.
  • the ADC 112B is an analog-digital converter that converts the pixel signal (second mixed signal) output from the output amplifier 109B into digital data.
  • the DSP 113 is a mixing unit that mixes two pixel signals converted into digital data by the ADCs 112A and 112B.
  • the same pixel signal can be mixed in the column signal processing circuit 107A, and further the pixel signal can be mixed in the DSP 113 in the subsequent stage, so that the effect of reducing random noise can be further enhanced. .
  • FIG. 17 is a circuit diagram showing an example of the configuration of the column circuit 115B included in the column signal processing circuit 107A.
  • the column circuit 115B includes a CDS circuit 116 and sample hold circuits 117 and 117A. Note that the CDS circuit 116 and the sample hold circuit 117 have the same configuration as shown in FIG.
  • the sample hold circuit 117A includes sample hold capacitors 310 and 311, sample hold switches 312 and 313, and output selection switches 314 and 315. Further, the connection relationship of the components included in the sample hold circuit 117A is the same as the connection relationship of the components included in the sample hold circuit 117.
  • the output selection switches 308 and 309 are connected to the horizontal signal line 111A, and the output selection switches 314 and 315 are connected to the horizontal signal line 111B. That is, the output selection switches 314 and 315 are output selection circuits for outputting a second mixed signal obtained by mixing a part or all of two signals held in the sample hold capacitors 310 and 311.
  • the column signal processing circuit 107A has four sample and hold capacitors 302, 303, 310, and 311 and four sample and hold switches 306, 307, 312 and 313 are provided.
  • Sample hold switches 306, 307, 312 and 313 are independently controlled by sample hold control signals ⁇ SH1, ⁇ SH2, ⁇ SH3 and ⁇ SH4.
  • the same pixel signal can be held in four different sample hold capacitors 302, 303, 310, and 311.
  • the output selection switches 308, 309, 314, and 315 are controlled by the output control signal ⁇ HSW.
  • the output control signal ⁇ HSW By setting the output control signal ⁇ HSW to the H level, the signals held in the sample hold capacitors 302 and 303 are mixed and then output to the horizontal signal line 111A. Further, the signals held in the sample hold capacitors 310 and 311 are mixed and then output to the horizontal signal line 111B.
  • FIG. 18 is a diagram illustrating an example of the configuration of the column selection circuit 108A and the like that controls the output control signal ⁇ HSW.
  • FIG. 19 is a diagram showing an example of timing for controlling the output control signal ⁇ HSW for each pixel column from the column selection circuit 108A.
  • the signals held in the sample hold capacitors 302 and 303 are mixed by setting the output control signal ⁇ HSW to the H level, and then sequentially read out to the horizontal signal line 111A. Further, the signals held in the sample hold capacitors 310 and 311 are mixed by setting the output control signal ⁇ HSW to the H level, and then sequentially read out to the horizontal signal line 111B.
  • the same pixel signal in which random noise is reduced by the column signal processing circuit 107A is output to each of the horizontal signal lines 111A and 111B.
  • the pixel signal read out to the horizontal signal line 111A is amplified by the output amplifier 109A and then converted into digital data by the ADC 112A.
  • the pixel signal read out to the horizontal signal line 111B is amplified by the output amplifier 109B and then converted into digital data by the ADC 112B. Then, the two converted digital data are mixed by the DSP 113.
  • FIG. 20 is a diagram illustrating an example of the timing of each control signal when the same pixel signal is held in the sample hold capacitors 302, 303, 310, and 311 at different timings.
  • Timings t1 to t6 are the same as those shown in FIG. 5 of the first embodiment.
  • the signal is held in the sample and hold capacitor 310 by setting the sample and hold control signal ⁇ SH3 to the L level.
  • the signal is held in the sample and hold capacitor 311 by setting the sample and hold control signal ⁇ SH4 to the L level.
  • the same pixel signal can be held in the sample hold capacitors 302, 303, 310 and 311 at different timings, and uncorrelated noise components can be sampled in time series. Since the random noise reduction effect in the column signal processing circuit 107A is the same as that described in the first and second embodiments, the description thereof is omitted here.
  • each control signal supplied to the pixel cell 102 and the column signal processing circuit 107A is the timing shown in FIG. 20 as long as the uncorrelated noise components can be held in different sample hold capacitors in time series. It is not limited to.
  • the same pixel signal may be held at different timings in the sample hold capacitors 302 and 303, and may be held at the same timing in the sample hold capacitors 310 and 311.
  • the DSP 113 can further increase the random noise reduction effect by further mixing the same pixel signals.
  • a column amplifier circuit 110 may be provided between the current source circuit 106 and the column signal processing circuit 107A as in the solid-state imaging device 400 illustrated in FIG.
  • column circuit 115C includes a column circuit 115B shown in FIG. 17 and a column amplifier 110A shown in FIG.
  • the pixel signal (both signal component and noise component) on the vertical signal line 105 is amplified, and the influence of noise generated at the subsequent stage of the column amplifier circuit 110 can be reduced. Therefore, the random noise reduction effect in the column signal processing circuit 107A and the DSP 113 can be further enhanced.
  • the solid-state imaging devices 300 and 400 according to the present embodiment read out the same pixel signal using the same clamp capacitor as in the first and second embodiments described above. Capacitance variation can be reduced. As a result, it is possible to effectively reduce random noise without generating vertical line noise, which was a problem in the prior art.
  • the solid-state imaging devices 300 and 400 according to the present embodiment can reduce the circuit scale and reduce random noise compared to the conventional technology.
  • each functional block described in FIG. 16 and FIG. 21 is configured as a combination of individual components. However, all or a part of the functional blocks may be integrated in the same IC. When configured as a combination of individual parts, it is advantageous for reducing the cost of the device of the camera. On the other hand, the integration is advantageous for speeding up the device.
  • the configurations of the solid-state imaging device and the camera according to the first to third embodiments are not limited to the above-described embodiments, and may be other configurations.
  • a configuration in which the configurations of the current source circuit, the column amplifier circuit, the row selection circuit, and the column selection circuit, and combinations thereof are changed may be used.
  • the solid-state imaging device according to the present invention includes another embodiment realized by combining arbitrary components in the above-described embodiments, and a range that does not depart from the gist of the present invention with respect to the embodiments. Modifications obtained by applying various modifications conceivable by those skilled in the art are also included. Furthermore, various devices including the solid-state imaging device according to the present invention are also included in the present invention.
  • Embodiment 4 The solid-state imaging devices according to Embodiments 1 to 3 described above are used as imaging devices (image input devices) in imaging devices such as video cameras, digital still cameras, and camera modules for mobile devices such as mobile phones. Is preferred.
  • FIG. 22 is a block diagram showing an example of the configuration of the imaging apparatus 500 according to Embodiment 4 of the present invention.
  • An imaging apparatus 500 illustrated in FIG. 22 includes an optical system including a lens 561, an imaging device 562, a camera signal processing circuit 563, and a system controller 564.
  • the lens 561 forms image light from the subject on the imaging surface of the imaging device 562.
  • the imaging device 562 outputs an image signal obtained by converting the image light imaged on the imaging surface by the lens 561 into an electrical signal in units of pixels.
  • the imaging device 562 the solid-state imaging device according to any of Embodiments 1 to 3 is used.
  • the camera signal processing circuit 563 performs various signal processing on the image signal output from the imaging device 562.
  • the system controller 564 controls the imaging device 562 and the camera signal processing circuit 563.
  • the present invention is not limited to this embodiment.
  • the solid-state imaging device according to the above-described embodiment and each processing unit included in the imaging device are typically realized as an LSI that is an integrated circuit. These may be individually made into one chip, or may be made into one chip so as to include a part or all of them.
  • circuits are not limited to LSI, and may be realized by a dedicated circuit or a general-purpose processor.
  • An FPGA Field Programmable Gate Array
  • reconfigurable processor that can reconfigure the connection and setting of circuit cells inside the LSI may be used.
  • a part of the functions of the solid-state imaging device and the imaging device according to the embodiment of the present invention may be realized by a processor such as a CPU executing a program.
  • the present invention may be the above program or a non-transitory computer-readable recording medium on which the above program is recorded.
  • the program can be distributed via a transmission medium such as the Internet.
  • division of functional blocks in the block diagram is an example, and a plurality of functional blocks can be realized as one functional block, a single functional block can be divided into a plurality of functions, or some functions can be transferred to other functional blocks. May be.
  • functions of a plurality of functional blocks having similar functions may be processed in parallel or time-division by a single hardware or software.
  • MOS transistors In the above description, an example using MOS transistors is shown, but other transistors may be used.
  • the circuit configuration shown in the circuit diagram is an example, and the present invention is not limited to the circuit configuration. That is, like the above circuit configuration, a circuit that can realize a characteristic function of the present invention is also included in the present invention.
  • the present invention includes a device in which a device such as a switching device (transistor), a resistor, or a capacitor is connected in series or in parallel to a certain device within a range in which a function similar to the above circuit configuration can be realized. It is.
  • the term “connected” in the above embodiment is not limited to the case where two terminals (nodes) are directly connected, and the two terminals ( Node) is connected through an element.
  • the present invention can be applied to a solid-state imaging device and an imaging device.
  • the present invention is useful for image sensors for imaging devices that require high image quality and high functionality, such as digital single-lens cameras, high-end compact cameras, in-vehicle cameras, surveillance cameras, and medical cameras.
  • Solid-state imaging device 102 102A Pixel cell 103 Pixel array 104 Row selection circuit 105 Vertical signal line 106 Current source circuit 107, 107A Column signal processing circuit 108, 108A Column selection circuit 109, 109A, 109B Output amplifier 110 Column amplifier circuit 110A Column amplifier 111, 111A, 111B Horizontal signal line 112A, 112B ADC 113 DSP 114 Timing control unit 115, 115A, 115B, 115C Column circuit 116 CDS circuit 117, 117A Sample hold circuit 118 Column ADC 201 Photodiode (PD) 202 Transfer transistor 203, 213 Amplification transistor 204, 214 Reset transistor 205, 215 Selection transistor 206, 216 Floating diffusion (FD) 207 Current source transistor 211 Photoelectric conversion element 221 Power supply wiring 222 Reset signal line 223 Reset voltage line 224 Address signal line 301 Clamp capacitance 302, 303, 310, 311 Sample hold capacitance 304

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Abstract

L'invention porte sur un dispositif de prise de vue à semi-conducteurs (100) qui comprend : une pluralité de cellules de pixel (102) ; une pluralité de lignes de signal verticales (105) ; et une pluralité de circuits de rangée (115). La pluralité de circuits de rangée (115) comprennent respectivement : un circuit CDS (116) qui génère un premier signal par traitement de signal analogique du signal de pixel de la ligne de signal perpendiculaire correspondante (105) ; des première et seconde capacités d'échantillonnage-maintien (302 et 303) pour maintenir le premier signal, des premier et second interrupteurs d'échantillonnage-maintien (306 et 307) qui commandent le maintien du premier signal par les première et seconde capacités d'échantillonnage-maintien (302 et 303) ; et des interrupteurs de sélection de sortie (308 et 309) pour délivrer un premier signal mélangé obtenu par mélange de certains ou de la totalité des signaux maintenus dans les première et seconde capacités d'échantillonnage-maintien (302 et 303).
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WO2023063024A1 (fr) * 2021-10-15 2023-04-20 ソニーセミコンダクタソリューションズ株式会社 Élément d'imagerie à semi-conducteurs, dispositif d'imagerie, et procédé de commande d'élément d'imagerie à semi-conducteurs

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