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WO2012118177A1 - Dispositif de synchronisation, procédé de gestion de l'heure et programme d'ordinateur - Google Patents

Dispositif de synchronisation, procédé de gestion de l'heure et programme d'ordinateur Download PDF

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Publication number
WO2012118177A1
WO2012118177A1 PCT/JP2012/055371 JP2012055371W WO2012118177A1 WO 2012118177 A1 WO2012118177 A1 WO 2012118177A1 JP 2012055371 W JP2012055371 W JP 2012055371W WO 2012118177 A1 WO2012118177 A1 WO 2012118177A1
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WO
WIPO (PCT)
Prior art keywords
time
synchronization
clock signal
clock
slave
Prior art date
Application number
PCT/JP2012/055371
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English (en)
Japanese (ja)
Inventor
鎌田　慎也
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Publication of WO2012118177A1 publication Critical patent/WO2012118177A1/fr

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    • G—PHYSICS
    • G04—HOROLOGY
    • G04R—RADIO-CONTROLLED TIME-PIECES
    • G04R40/00—Correcting the clock frequency
    • G04R40/06—Correcting the clock frequency by computing the time value implied by the radio signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0073—Services, e.g. multimedia, GOS, QOS
    • H04J2203/0082—Interaction of SDH with non-ATM protocols
    • H04J2203/0085—Support of Ethernet
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays

Definitions

  • the present invention relates to a technique for synchronizing time between devices that perform communication.
  • FIG. 7 is a diagram illustrating a configuration example of the time synchronization apparatus 90 related to the above technique.
  • the time synchronization apparatus 90 includes a synchronization packet transmission / reception unit 901, a synchronization control unit 902, a clock oscillator 904, and a time management unit 905.
  • the time synchronization device 90 keeps the time counted by the time management unit 905 with a certain accuracy by the clock oscillator 904 provided in the time synchronization device 90. That is, the time synchronization is maintained only by the clock signal of the clock oscillator 904 during the interval (time synchronization interval) at which the phase signal is generated in response to reception of the synchronization packet.
  • an object of the present invention is to provide a technique that can increase the accuracy of time synchronization between communication devices without significantly increasing the device cost and the communication frequency of synchronization packets.
  • One aspect of the present invention is a synchronization device that synchronizes time with the other device by transmitting and receiving a synchronization packet according to a synchronization protocol with another device, and a transmission and reception unit that transmits and receives the synchronization packet; Based on the clock signal acquisition unit that acquires the clock signal flowing through the communication path, the synchronization control unit that acquires the difference between the time of its own device and the time of the other device, based on the synchronization packet, and the difference A time management unit that corrects the time of the own device and manages the time of the own device based on the corrected time and the clock signal.
  • One aspect of the present invention is a time management method performed by a synchronization device that synchronizes time with another device by transmitting and receiving a synchronization packet with the other device according to a synchronization protocol, and transmits and receives the synchronization packet.
  • a transmission / reception step a clock signal acquisition step of acquiring a clock signal flowing through the communication path, a synchronization control step of acquiring a difference between the time of the own device and the time of the other device based on the synchronization packet, A time management step of correcting the time of the own device based on the difference and managing the time of the own device based on the corrected time and the clock signal.
  • One aspect of the present invention is a computer program for operating a computer as a synchronization device that synchronizes time with the other device by transmitting and receiving a synchronization packet with the other device according to a synchronization protocol.
  • FIG. 3 is a sequence diagram showing a communication sequence by an IEEE 1588 time synchronization algorithm. It is a functional block diagram showing the structure of a time synchronous slave apparatus. It is a flowchart showing the flow of operation
  • FIG. 1 is a system configuration diagram showing a system configuration of the first embodiment (synchronization system 100) of the synchronization system.
  • the synchronization system 100 includes a clock generator 10, a time synchronization master device 20 (corresponding to “another device” of the present invention), a relay device 30, and a time synchronization slave device 40 (corresponding to “a synchronization device” of the present invention).
  • the synchronization system 100 includes one device, but the number of devices included in the synchronization system 100 is not limited to one. Further, the number of relay devices 30 provided between the time synchronization master device 20 and the time synchronization slave device 40 is not limited to one, and may be two or more.
  • the time synchronization master device 20 and the time synchronization slave device 40 transmit and receive synchronization packets according to a predetermined protocol.
  • the time synchronization master device 20 and the time synchronization slave device 40 perform time synchronization by transmitting and receiving synchronization packets.
  • the predetermined protocol may be any protocol as long as time synchronization is possible. Specific examples of the predetermined protocol include IEEE 1588, IEEE 1588 version 2, and the like.
  • the time synchronization slave device 40 counts the time based on the clock signal between the time synchronization and the next time synchronization.
  • the time synchronization slave device 40 outputs a time synchronization signal every time a predetermined time is reached.
  • the clock signal used by the time synchronization slave device 40 to count the time is a clock signal that flows through the communication path between the relay device 30 and the time synchronization slave device 40. Therefore, the time synchronization slave device 40 does not need to include a clock signal generation device (for example, a clock oscillator) that outputs a clock signal for generating a time synchronization signal, and can maintain high time accuracy.
  • a clock signal generation device for example, a clock oscillator
  • FIG. 2 is a sequence diagram showing a communication sequence based on the IEEE 1588 time synchronization algorithm.
  • a clock master (corresponding to a time synchronization master device) and a clock slave (corresponding to a time synchronization slave device) perform bidirectional communication, and the clock slave periodically synchronizes the time with the clock master.
  • each message (Sync message, Follow_up message, Delay_Request message, Delay_Response message) transmitted from the clock master or clock slave corresponds to a synchronization packet.
  • the clock master periodically sends a Sync message to the clock slave (step S900).
  • the clock master records the transmission time of the Sync message (hereinafter referred to as “Sync transmission time”) Tm (0) (step S901).
  • the clock master transmits a Follow_up message to the clock slave (step S903).
  • the clock master stores the Sync transmission time Tm (0) in the Follow_up message.
  • the clock slave Upon receiving the Sync message, the clock slave records the reception time of the Sync message (hereinafter referred to as “Sync reception time”) Ts (0) using this reception process as a trigger (step S902). Next, the clock slave receives the Follow_up message and extracts and records the Sync transmission time Tm (0) stored in the Follow_up message. Next, the clock slave transmits a Delay_Request message to the clock master (step S904). Then, the clock slave records the transmission time of the Delay_Request message (hereinafter referred to as “Delay transmission time”) Ts (1) (step S905).
  • Delay transmission time the transmission time of the Delay_Request message
  • the clock master Upon receiving the Delay_Request message, the clock master records the reception time of the Delay_Request message (hereinafter referred to as “Delay reception time”) Tm (1) using this reception process as a trigger (step S906). Next, the clock master transmits a Delay_Response message to the clock slave (step S907). At this time, the clock master stores the Delay reception time Tm (1) in the Delay_Response message.
  • the clock slave obtains the difference between the slave time and the master time from the following equation 2 based on the Delay transmission time Ts (1) and the Delay reception time Tm (1).
  • MS_Delay represents the transmission delay from the clock master to the clock slave
  • SM_Delay represents the transmission delay from the clock slave to the clock master
  • Offset represents the time offset (advance) of the clock slave with respect to the clock master.
  • the transmission delays MS_Delay and SM_Delay are composed of a propagation delay between the clock master and the clock slave and a queuing delay that occurs at a relay node on the network between the clock master and the clock slave.
  • the clock slave calculates the offset based on Equation 5 and corrects the slave time based on the offset to synchronize the slave time with the master time.
  • the above is the time synchronization algorithm defined in IEEE1588.
  • the clock generator 10 supplies a clock signal to the time synchronization master device 20 and the relay device 30.
  • the clock generator 10 is preferably a high-accuracy clock generator that generates a clock signal with high accuracy.
  • the clock generator 10 may be a GPS (Global Positioning System) receiver, for example, or may be configured using a high-performance oscillator.
  • the time synchronization master device 20 operates in synchronization with the clock signal output from the clock generator 10.
  • the time synchronization master device 20 operates according to a predetermined protocol, and performs time synchronization with the time synchronization slave device 40 by transmitting and receiving synchronization packets.
  • the time synchronization processing synchronizes the time in the time synchronization master device 20 (hereinafter referred to as “master device time”) and the time in the time synchronization slave device 40 (hereinafter referred to as “slave device time”). .
  • the relay device 30 is a clock synchronous communication device, and performs packet relay processing in synchronization with the clock signal output from the clock generator 10. For example, the relay device 30 relays packets according to a synchronous communication method such as SDH (Synchronous Digital Hierarchy) or Synchronous Ethernet (registered trademark). More specifically, the relay device 30 synchronizes its own clock with the clock signal received from the communication path, and transmits the signal to the communication path at the same frequency.
  • the communication path between the relay device 30 and the time synchronization slave device 40 is clock-synchronized according to the clock signal output by the clock generator 10, and a clock signal having a predetermined cycle is propagated.
  • a clock signal flows through the communication path at 125 MHz.
  • the relay device 30 relays the synchronization packet received from the time synchronization master device 20 to the time synchronization slave device 40.
  • the relay device 30 relays the synchronization packet received from the time synchronization slave device 40 to the time synchronization master device 20.
  • the time synchronization slave device 40 transmits / receives a synchronization packet to / from the time synchronization master device 20 via the relay device 30 and performs time synchronization with the time synchronization master device 20.
  • the time synchronization slave device 40 acquires a synchronized clock signal from the communication path with the relay device 30.
  • the time synchronization slave device 40 outputs a time synchronization signal synchronized with the time synchronization master device 20 based on the result of the time synchronization and the clock signal acquired from the communication path.
  • the destination to which the time synchronization slave device 40 outputs the time synchronization signal may be a network to which the time synchronization slave device 40 is connected, or may be a device to which the time synchronization slave device 40 is connected.
  • the time synchronization slave device 40 may be incorporated in the device as one component. In this case, the time synchronization slave device 40 outputs a time synchronization signal to other parts of the device in which the device is incorporated.
  • FIG. 3 is a functional block diagram showing the configuration of the time synchronization slave device 40.
  • the time synchronization slave device 40 includes a CPU (Central Processing Unit) connected via a bus, a memory, an auxiliary storage device, and the like, and executes a time synchronization program.
  • the time synchronization slave device 40 includes a synchronization packet transmission / reception unit 401 (corresponding to “transmission / reception unit” of the present invention), a synchronization control unit 402, a first clock signal extraction unit 403 (“clock signal of the present invention” It corresponds to an apparatus provided with a second clock signal generation unit 404 and a time management unit 405.
  • a synchronization packet transmission / reception unit 401 corresponding to “transmission / reception unit” of the present invention
  • a synchronization control unit 402 a first clock signal extraction unit 403 (“clock signal of the present invention” It corresponds to an apparatus provided with a second clock signal generation unit 404 and a time management unit 405.
  • the time synchronization slave device 40 may be realized using hardware such as ASIC (Application Specific Integrated Circuit), PLD (Programmable Logic Device), and FPGA (Field Programmable Gate Array). good.
  • the time synchronization program may be recorded on a computer-readable recording medium.
  • the computer-readable recording medium is, for example, a portable medium such as a flexible disk, a magneto-optical disk, a ROM, a CD-ROM, or a storage device such as a hard disk built in the computer system.
  • the synchronization packet transmission / reception unit 401 receives the synchronization packet from the communication path with the relay device 30 and transfers the synchronization packet to the synchronization control unit 402. In addition, the synchronization packet transmission / reception unit 401 sends the synchronization packet received from the synchronization control unit 402 to the communication path.
  • the synchronization packet sent to the communication path by the synchronization packet transmitting / receiving unit 401 is relayed by the relay device 30 and received by the time synchronization master device 20.
  • the synchronization control unit 402 synchronizes the slave device time with the master device time by exchanging synchronization packets with the time synchronization master device 20 at the end of the communication path.
  • the synchronization control unit 402 outputs a phase signal representing the difference between the slave device time before synchronization and the master device time to the time management unit 405 as a result of the time synchronization.
  • the first clock signal extraction unit 403 extracts a clock signal from the physical layer signal received from the communication path.
  • the first clock signal extraction unit 403 outputs the extracted clock signal to the second clock signal generation unit 404 as the first clock signal.
  • the second clock signal generation unit 404 generates a second clock signal synchronized with the first clock signal output from the first clock signal extraction unit 403.
  • the second clock signal generation unit 404 generates the second clock signal by multiplying or dividing the first clock signal.
  • the second clock signal is a clock signal used by the time management unit 405 to count the slave device time.
  • the time management unit 405 manages the slave device time. Specifically, the time management unit 405 counts the slave device time based on the second clock signal received from the second clock signal generation unit 404. The time management unit 405 generates and outputs a time synchronization signal at a predetermined time. When receiving the phase signal from the synchronization control unit 402, the time management unit 405 corrects the slave device time based on the received phase signal. By correcting the slave device time, the output timing of the time synchronization signal is corrected. The time management unit 405 corrects the slave device time based on the phase signal, and then receives the phase signal until the next time the phase signal is received, the slave device based on the second clock signal received from the second clock signal generation unit 404 Count the time. For this reason, if a shift occurs in the second clock signal, the slave device time being counted also shifts, and the timing at which the time synchronization signal is output shifts. This deviation is corrected based on the next phase signal.
  • FIG. 4 is a flowchart showing an operation flow of the time synchronization slave device 40.
  • the synchronization control unit 402 performs time synchronization by transmitting and receiving a synchronization packet to and from the time synchronization master device 20 at a predetermined timing.
  • the synchronization control unit 402 outputs a phase signal representing a difference between the slave device time and the master device time to the time management unit 405 as a result of the time synchronization (step S101).
  • the time management unit 405 corrects the slave device time based on the phase signal (step S102).
  • the second clock signal generation unit 404 continues to output the second clock signal to the time management unit 405 (steps S103, S105, S109).
  • the time management unit 405 determines the output timing of the time synchronization signal based on the corrected slave device time and the second clock signal. Then, the time management unit 405 outputs a time synchronization signal at the determined output timing (steps S104, S106, S110).
  • step S107 When a new phase signal is output from the synchronization control unit 402 (step S107), the time management unit 405 performs time correction based on the new phase signal (step S108). Thereafter, the time management unit 405 counts the slave device time based on the slave device time corrected in step S108 and the second clock signal (step S109) output from the second clock signal generation unit 404. When a predetermined time comes, a time synchronization signal is output (step S110).
  • the second clock signal used by the time management unit 405 to count the slave device time is synchronized with the clock signal (first clock signal) extracted from the communication path. Therefore, by making the clock signal flowing in the communication path into a high-accuracy clock signal, each time synchronization slave device 40 does not have a high-accuracy clock signal generator, and the slave is based on the high-accuracy clock signal. The device time can be counted. Therefore, in order to maintain highly accurate time synchronization, it is not necessary to shorten the interval between transmission and reception of synchronization packets.
  • the clock signal flowing in the communication path is synchronized with the clock signal input to the time synchronization master device 20. Therefore, once the time synchronization by the transmission / reception of the synchronization packet is performed once, the time synchronization master device 20 and the time synchronization slave device are not newly transmitted / received unless the clock signal flowing through the communication path is shifted. It is possible to maintain a synchronization state with 40.
  • the clock signal flowing through the communication path need not be limited to a clock signal as a synchronization signal used for transmission / reception of the relay device 30.
  • the relay device 30 may be configured so that a clock signal flows through the communication path. Therefore, in this case, the relay device 30 is not necessarily a clock synchronous communication device.
  • FIG. 5 is a system configuration diagram showing a system configuration of the second embodiment (synchronization system 100a) of the synchronization system.
  • the clock signal used by the time synchronization slave device 40a is not the clock signal extracted from the communication path between the relay device 30 and the time synchronization slave device 40a, but the clock synchronization to which the clock generator 10 is connected. It differs from the synchronization system 100 of the first embodiment in that it is extracted from the network 50.
  • the synchronization system 100a of the second embodiment will be described in detail.
  • the clock generator 10 is connected to the clock synchronization network 50 and supplies a clock signal to the clock synchronization network 50.
  • the relay device 30a is a general packet transmission device, and relays synchronous packets without clock synchronization.
  • FIG. 6 is a functional block diagram showing the configuration of the time synchronization slave device 40a in the second embodiment.
  • the time synchronization slave device 40a is different from the time synchronization slave device 40 of the first embodiment in that a first clock signal extraction unit 403a is provided instead of the first clock signal extraction unit 403.
  • the remaining configuration of the time synchronization slave device 40a is the same as that of the time synchronization slave device 40 of the first embodiment.
  • the first clock signal extraction unit 403a extracts the first clock signal based on the signal received from the clock synchronization network 50, not the communication path through which the synchronization packet is transmitted and received.
  • the first clock signal for generating the second clock signal is extracted from the clock synchronization network 50 instead of the communication path through which the synchronization packet is transmitted and received. Therefore, even when a failure occurs in the communication path through which the synchronization packet is transmitted and received, the time synchronization slave device 40 is counted by counting the time based on the first clock signal extracted from the clock synchronization network 50. It is possible to prevent the time of the time from deviating significantly.
  • the clock synchronization network 50 may be configured by a clock synchronization type transmission network that can operate in synchronization with the clock generator 10.
  • the relay device 30a of the second embodiment may perform synchronization packet relay by clock synchronization.
  • the present invention can be applied to a system or a device that synchronizes time between devices that perform communication.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

L'invention porte sur un dispositif de synchronisation qui synchronise l'heure avec un autre dispositif par transmission d'un paquet de synchronisation à l'autre dispositif et réception d'un paquet de synchronisation en provenance de ce dernier, conformément à un protocole de synchronisation, le du de synchronisation comprenant : une unité de transmission/réception qui transmet et reçoit le paquet de synchronisation ; une unité d'acquisition de signal d'horloge qui acquiert un signal d'horloge circulant sur un canal de communication ; une unité de commande de synchronisation qui acquiert la différence entre l'heure du dispositif lui-même et l'heure de l'autre dispositif sur la base du paquet de synchronisation ; et une unité de gestion de l'heure qui corrige l'heure du dispositif lui-même sur la base de ladite différence, et qui gère l'heure du dispositif lui-même sur la base de l'heure corrigée et du signal d'horloge.
PCT/JP2012/055371 2011-03-03 2012-03-02 Dispositif de synchronisation, procédé de gestion de l'heure et programme d'ordinateur WO2012118177A1 (fr)

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JP2011046155 2011-03-03

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105652655A (zh) * 2016-04-01 2016-06-08 湖南述泰信息技术有限公司 手持式卫星授时同步终端

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63106252U (fr) * 1986-12-26 1988-07-09
JPH08191301A (ja) * 1995-01-10 1996-07-23 Anritsu Corp 測定システム及び測定器の時刻設定方法
JP2000314788A (ja) * 1999-05-07 2000-11-14 Kanda Tsushin Kogyo Co Ltd ディジタル網からの同期信号に同期した時計
JP2001036538A (ja) * 1999-07-19 2001-02-09 Nippon Telegr & Teleph Corp <Ntt> 時刻同期方法及びその装置
JP2001054152A (ja) * 1999-08-17 2001-02-23 Nec Shizuoka Ltd ボタン電話装置の時刻修正方式および方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63106252U (fr) * 1986-12-26 1988-07-09
JPH08191301A (ja) * 1995-01-10 1996-07-23 Anritsu Corp 測定システム及び測定器の時刻設定方法
JP2000314788A (ja) * 1999-05-07 2000-11-14 Kanda Tsushin Kogyo Co Ltd ディジタル網からの同期信号に同期した時計
JP2001036538A (ja) * 1999-07-19 2001-02-09 Nippon Telegr & Teleph Corp <Ntt> 時刻同期方法及びその装置
JP2001054152A (ja) * 1999-08-17 2001-02-23 Nec Shizuoka Ltd ボタン電話装置の時刻修正方式および方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105652655A (zh) * 2016-04-01 2016-06-08 湖南述泰信息技术有限公司 手持式卫星授时同步终端

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